Waveguide integrated photodetector

Abstract

The application discloses a waveguide integrated photoelectric detector, which comprises a photoelectric chip, an optical receiving array, an on-chip waveguide network, a photoelectric conversion module and a signal processing circuit. The photoelectric chip has a first region and a second region horizontally spaced apart; the optical receiving array is arranged on the first region and comprises a plurality of optical receiving units for receiving and converging spatial light signals; the on-chip waveguide network is arranged in the photoelectric chip and is coupled with the optical receiving units to transmit the converged spatial light signals to the second region; the photoelectric conversion module is arranged in the second region and is coupled with the on-chip waveguide network to convert the light signals into electric signals; and the signal processing circuit is connected with the photoelectric conversion module to receive and process the electric signals. The spatial light receiving and photoelectric conversion functions are decoupled in space, the parasitic parameters of the photoelectric conversion module are effectively reduced, and the photoelectric detection bandwidth and system integration are effectively improved.

Description

Technical Field

[0001] This invention relates to the field of photodetector technology, and in particular to a waveguide-integrated photodetector. Background Technology

[0002] With the continuous expansion of AI computing clusters and data centers, increasingly higher demands are being placed on high-speed, low-latency, and low-power optical interconnect technologies. As a core component in optical interconnect systems, the bandwidth and integration of photodetectors directly determine the transmission rate of the entire system.

[0003] Currently, most existing photodetectors employ a traditional front-incident structure. In this type of device structure, the light absorption region is highly coupled to the metal electrode, and the functions of light signal reception and photoelectric conversion are tightly intertwined. Because this structural design requires close contact between the light absorption region and the electrode, the device has a large parasitic capacitance, and RC delay becomes the main physical bottleneck limiting its electrical bandwidth. When the data rate increases to hundreds of gigabits per second and above, this type of structure struggles to simultaneously achieve high responsivity and high bandwidth, and is gradually becoming insufficient to meet the demands of next-generation optical interconnect technologies.

[0004] Therefore, how to effectively overcome the RC delay limitation of existing front-incident structures to meet the needs of high-speed photoelectric detection is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The embodiments of the present invention provide a waveguide integrated photodetector, which aims to solve the technical problems of large RC delay and limited bandwidth caused by the high coupling between the light absorption region and the electrode in existing front-incident photodetectors.

[0006] This invention provides a waveguide-integrated photodetector, comprising: a photoelectric chip having a first region and a second region spaced apart in a horizontal direction; an optical receiving array disposed in the first region, the optical receiving array including a plurality of optical receiving units for receiving and converging spatial optical signals; an on-chip waveguide network disposed inside the photoelectric chip and coupled to the optical receiving units, for transmitting the converged spatial optical signals from the first region to the second region; a photoelectric conversion module disposed in the second region and coupled to the on-chip waveguide network, for converting the optical signals output by the on-chip waveguide network into electrical signals; and a signal processing circuit electrically connected to the photoelectric conversion module, for receiving and processing the electrical signals output by the photoelectric conversion module.

[0007] In the waveguide integrated photodetector provided in the embodiments of the present invention, the on-chip waveguide network includes a plurality of waveguide lines corresponding to the optical receiving unit. Each waveguide line is coupled to the corresponding optical receiving unit and is used to transmit the spatial optical signal converged by the corresponding optical receiving unit from the first region to the second region.

[0008] In the waveguide integrated photodetector provided in the embodiments of the present invention, the plurality of waveguide lines include silicon waveguide lines and silicon nitride waveguide lines, wherein at least one silicon waveguide line and at least one silicon nitride waveguide line are disposed in different layers within the photodetector chip.

[0009] In the waveguide integrated photodetector provided in the embodiments of the present invention, both the silicon waveguide circuit and the silicon nitride waveguide circuit have a curved section, which is an arc-shaped bend and / or an Euler bend.

[0010] In the waveguide integrated photodetector provided in the embodiments of the present invention, the photoelectric conversion module includes a plurality of photoelectric detection units corresponding to the optical receiving unit. Each photoelectric detection unit is coupled to the corresponding waveguide circuit and is used to convert the optical signal output by the corresponding waveguide circuit into an electrical signal.

[0011] In the waveguide integrated photodetector provided in this embodiment of the invention, the signal processing circuit includes a dedicated integrated circuit chip, a transimpedance amplifier, and a digital signal processing chip. The transimpedance amplifier is electrically connected to the photoelectric conversion module and is used to amplify the electrical signal. The dedicated integrated circuit chip is electrically connected to the transimpedance amplifier, and the digital signal processing chip is electrically connected to the dedicated integrated circuit chip.

[0012] In the waveguide integrated photodetector provided in this embodiment of the invention, the signal processing circuit is disposed on the back side of the photoelectric chip, and the photoelectric chip has a through-hole in the second region. The output terminal of the photoelectric conversion module is led to the back side of the photoelectric chip through the through-hole and is electrically connected to the signal processing circuit.

[0013] In the waveguide integrated photodetector provided in the embodiments of the present invention, the optical receiving unit has an input port, an output port, and a light guide channel connecting the input port and the output port. The output port is coupled to the on-chip waveguide network, and the aperture of the light guide channel gradually narrows from the input port to the output port.

[0014] In the waveguide integrated photodetector provided in the embodiments of the present invention, a light-guiding gradient coupling section is provided between the light-emitting port and the input end of the on-chip waveguide network, and the gradient coupling section gradually expands from the light-emitting port to the on-chip waveguide network.

[0015] In the waveguide integrated photodetector provided in the embodiments of the present invention, all the optical receiving units are regularly arranged in a polygonal array, and the center-to-center distance between adjacent optical receiving units is equal.

[0016] Compared with existing technologies, the waveguide-integrated photodetector of this invention completely decouples spatial light reception and photoelectric conversion functions in space, constructing a high-speed photoelectric detection architecture based on waveguide integration. Utilizing horizontally spaced first and second regions on the photoelectric chip, an optical receiving array is positioned in the first region to receive spatial light signals. The converged light signals are then transmitted to the second region at the chip edge for photoelectric conversion and signal processing via an on-chip waveguide network. This design fundamentally breaks through the physical limitation of high coupling between the light absorption region and electrodes in traditional front-incident detectors. By arranging the photoelectric conversion module at the chip edge, the electrode length is significantly shortened, parasitic capacitance and inductance are reduced, and the limitation of RC delay on electrical bandwidth is weakened, providing a physical basis for achieving high-speed detection of hundreds of gigabits per second and above. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0018] Figure 1 A perspective view of a waveguide-integrated photodetector provided in an embodiment of the present invention; Figure 2 This is a top view of a waveguide-integrated photodetector provided in an embodiment of the present invention; Figure 3 This is a side view of a waveguide-integrated photodetector provided in an embodiment of the present invention; Figure 4 This is a wiring diagram of a waveguide-integrated photodetector provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the waveguide network on-chip provided in an embodiment of the present invention; Figure 6 A schematic structural diagram of a waveguide-integrated photodetector provided in an embodiment of the present invention; Figure 7 A schematic cross-sectional view of the waveguide integrated photodetector provided in an embodiment of the present invention; Explanation of reference numerals in the attached figures: 10. Optoelectronic chip; 101. First region; 102. Second region; 11. Via; 20. Optical receiving array; 21. Optical receiving unit; 211. Light inlet; 212. Light outlet; 213. Light guide channel; 201. Gradient coupling section; 30. On-chip waveguide network; 31. Waveguide circuit; 31a. Silicon waveguide circuit; 31b. Silicon nitride waveguide circuit; 301. Bending section; 40. Optoelectronic conversion module; 41. Optoelectronic detection unit; 50. Signal processing circuit; 51. Integrated circuit chip; 52. Transimpedance amplifier; 53. Digital signal processing chip. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0021] Please see Figures 1 to 3 This invention provides a waveguide-integrated photodetector, comprising a photodetector chip 10, an optical receiving array 20, an on-chip waveguide network 30, a photoelectric conversion module 40, and a signal processing circuit 50. The photodetector chip 10 has a first region 101 and a second region 102 spaced apart in a horizontal direction. The optical receiving array 20 is disposed in the first region 101 and includes a plurality of optical receiving units 21 for receiving and converging spatial optical signals. The on-chip waveguide network 30 is disposed inside the photodetector chip 10 and coupled to the optical receiving units 21, for transmitting the converged spatial optical signal from the first region 101 to the second region 102. The photoelectric conversion module 40 is disposed in the second region 102 and coupled to the on-chip waveguide network 30, for converting the optical signal output by the on-chip waveguide network 30 into an electrical signal. The signal processing circuit 50 is electrically connected to the photoelectric conversion module 40 and for receiving and processing the electrical signal output by the photoelectric conversion module 40.

[0022] In specific implementation, the optoelectronic chip 10 serves as the physical carrier of the entire detector. Its first region 101 and second region 102 are horizontally spaced apart, thus completely separating the two functional areas of "spatial light reception" and "photoelectric conversion" in spatial layout. For example, in a preferred embodiment, the first region 101 can be located at the center of the upper side of the optoelectronic chip 10 for concentrated reception of incident spatial light signals; the second region 102 can be located at the edge of the upper side of the optoelectronic chip 10, such as the peripheral area of ​​the chip or a side close to the chip edge. Placing the second region 102 at the edge facilitates subsequent signal transmission and system integration with external electronic circuits through interconnect structures at the chip edge (such as vias 11, leads, flip-chip bonding, etc.). Of course, the specific positions of the first region 101 and the second region 102 can be adjusted according to the actual application scenario, as long as they remain horizontally spaced apart. This spatial decoupling provides a physical basis for reducing the parasitic parameters of subsequent photoelectric conversion components and also leaves flexible layout space for efficient integration with external circuits.

[0023] The optical receiving array 20 is disposed in the first region 101 and consists of a plurality of optical receiving units 21 arranged in an array. For example, the array size of the optical receiving array 20 can be 4×4 optical receiving units 21, 8×8 optical receiving units 21, 16×16 optical receiving units 21, or larger, to adapt to different spatial light reception throughput and system parallelism requirements. Each optical receiving unit 21 is used to receive spatial light signals incident on the front side of the chip and converge them. In practical applications, the optical receiving unit 21 can adopt a microlens structure, a funnel-shaped tapered structure, or other types of three-dimensional spatial light collection structure. It captures spatial light through its large-aperture receiving end at the top, and after gradually narrowing through the internal light guide channel 213, it is output from the small-aperture output end at the bottom. The microlens is combined with the grating coupler to achieve efficient coupling of spatial light to the on-chip waveguide fundamental mode.

[0024] The on-chip waveguide network 30 is embedded within the optoelectronic chip 10 and is coupled to each optical receiving unit 21 in the optical receiving array 20. The spatial optical signal converged by each optical receiving unit 21 is transmitted from the first region 101 to the second region 102 through the corresponding on-chip waveguide path 31. The on-chip waveguide network 30 uses the refractive index difference between the waveguide core layer and the cladding layer of the optoelectronic chip 10 to constrain the light field, enabling the optical signal to be transmitted over long distances along the waveguide path in a low-loss manner. This efficiently guides the arrayed spatial optical signal to the chip edge or other designated areas for centralized photoelectric conversion.

[0025] The photoelectric conversion module 40 is disposed in the second region 102 and coupled to the output of the on-chip waveguide network 30. When the on-chip waveguide network 30 transmits an optical signal to the second region 102, the photoelectric conversion module 40 receives the optical signal and converts it into an electrical signal. In practical applications, the photoelectric conversion module 40 can be designed using high-speed photoelectric conversion devices such as III-V group semiconductor photodetectors or silicon-germanium photodetectors to achieve high-speed detection requirements of hundreds of gigabits per second or higher. Because the photoelectric conversion module 40 is disposed in the second region 102, which is spatially isolated from the optical receiving array 20, its electrode design is no longer limited by the physical location of the light absorption region, thereby effectively reducing electrode length, lowering parasitic capacitance and inductance, and fundamentally weakening the limitation of RC delay on detection bandwidth.

[0026] The signal processing circuit 50 is electrically connected to the photoelectric conversion module 40, and is used to receive the electrical signal output by the photoelectric conversion module 40, and perform operations such as amplification, filtering, analog-to-digital conversion, or digital signal processing on the electrical signal. In practical applications, the signal processing circuit 50 can be integrated on the back side of the same optoelectronic chip 10, or it can be connected to the photoelectric conversion module 40 through external interconnection. Through the above structure, the entire detector realizes the integrated function of spatial optical signal reception, on-chip optical transmission, high-speed photoelectric conversion, and electrical signal processing, which significantly improves the system's integration and scalability while ensuring bandwidth and response speed.

[0027] In one embodiment, see Figure 2 , Figure 4 and Figure 5 The on-chip waveguide network 30 includes a plurality of waveguide paths 31 corresponding to the optical receiving unit 21. Each waveguide path 31 is coupled to the corresponding optical receiving unit 21 and is used to transmit the spatial optical signal converged by the corresponding optical receiving unit 21 from the first region 101 to the second region 102.

[0028] In practice, the on-chip waveguide network 30 does not employ a single waveguide carrying the converged transmission structure of all optical receiving units 21. Instead, it constructs a system of waveguide paths 31 that correspond one-to-one with each optical receiving unit 21 in the optical receiving array 20. Specifically, the optical receiving array 20 has several optical receiving units 21, and correspondingly, the on-chip waveguide network 30 also has the same number of waveguide paths 31. The input end of each waveguide path 31 is aligned and coupled to the output end of only one specific optical receiving unit 21, thereby forming an independent optical signal transmission channel.

[0029] In practical implementation, this one-to-one coupling relationship means that the spatial optical signal gathered by each optical receiving unit 21 is transmitted individually to the second region 102 through its dedicated waveguide path 31. Each waveguide path 31 starts from the position of the optical receiving unit 21 in the first region 101 and extends along its own preset path to the designated position in the second region 102. Since each waveguide path 31 is independent of each other, the optical signals received by each optical receiving unit 21 will not interfere with or mix with each other during transmission, thus ensuring the independence and integrity of the optical signal of each channel in the array during transmission. This is particularly important for signal quality in multi-channel parallel detection scenarios. In specific wiring, each waveguide path 31 can be led out in a fan-shaped or serpentine manner inside the optoelectronic chip 10 according to the array layout of the first region 101, in order to avoid possible optical path crossings, and finally converge to the corresponding optoelectronic conversion module 40 in the second region 102. Each waveguide path 31 can employ the same or different bending path designs. Its specific length and shape can be optimized based on the relative positional relationship between the first region 101 and the second region 102, as well as the overall chip layout, to reduce transmission loss and ensure phase consistency of each channel. Through this independent waveguide path 31 design, the on-chip waveguide network 30 can effectively support the parallel transmission and routing requirements of multi-channel, large-scale arrayed spatial optical signals, providing stable and reliable optical signal input for high-speed photoelectric conversion in subsequent edge regions.

[0030] Further, see Figure 4 and Figure 5 The plurality of waveguide lines 31 include silicon waveguide lines 31a and silicon nitride waveguide lines 31b, wherein at least one silicon waveguide line 31a and at least one silicon nitride waveguide line 31b are disposed in different layers within the optoelectronic chip 10.

[0031] In specific implementations, the on-chip waveguide network 30 employs two different waveguide circuits 31 made of different materials, namely silicon waveguide circuit 31a and silicon nitride waveguide circuit 31b, to meet different optical transmission requirements and chip wiring density requirements. Silicon waveguide circuit 31a has a high refractive index contrast, with a large refractive index difference between its waveguide core and cladding. Therefore, it can maintain low optical signal leakage with a small bending radius, making it suitable for applications requiring compact bending, high-density integration, and direct coupling with photodetectors. Silicon nitride waveguide circuit 31b, on the other hand, has lower propagation loss and a wider transparency window. Its material itself has low absorption loss of optical signals, making it suitable for long-distance transmission at the array level, complex optical path routing, and multi-layer waveguide wiring. It also helps ensure signal strength consistency between multiple channels.

[0032] Since the optical receiving array 20 of the first region 101 on the optoelectronic chip 10 is usually densely arranged in a two-dimensional array, and a large number of waveguide lines 31 need to be uniformly led from the central first region 101 to the edge second region 102, if all waveguide lines 31 are arranged on the same planar layer, a large number of optical path intersections will inevitably occur. To solve this problem, the silicon waveguide lines 31a and silicon nitride waveguide lines 31b are arranged in different layers within the optoelectronic chip 10. Specifically, some waveguide lines 31 (e.g., silicon waveguide lines 31a) are located on the upper layer of the optoelectronic chip 10, while other waveguide lines 31 (e.g., silicon nitride waveguide lines 31b) are located on the lower layer. By forming waveguide networks of different heights in the vertical direction, when the waveguide lines 31 of the upper and lower layers intersect in the horizontal projection, they do not actually form a direct lateral intersection in physical space, thereby effectively avoiding the radiation loss and crosstalk introduced by optical path intersections in the same planar layer.

[0033] As a specific size implementation, for an operating wavelength of 1550 nm, the on-chip waveguide network 30 can adopt the following cross-sectional dimensions: the silicon nitride waveguide has a width of 0.6 μm to 1.2 μm and a thickness of 0.2 μm to 0.4 μm. In a specific preferred example, the silicon nitride waveguide can adopt a cross-sectional structure with a width of 0.8 μm and a thickness of 0.3 μm; the silicon waveguide can adopt a cross-sectional structure with a width of 0.45 μm to 0.50 μm and a thickness of 0.22 μm. The specific dimensions of the waveguide cross-section are not arbitrarily chosen, but are determined comprehensively based on the operating wavelength, polarization state, single-mode conditions, and mode matching requirements with the upstream optical receiving unit 21 or the downstream photodetector unit 41. In practical design, the fundamental mode optical field distribution of the target waveguide can be obtained through eigensimlation simulation, and the bottom output end size of the spatial light collection structure can be set according to this optical field distribution to achieve low-loss docking between the waveguide and the optical receiving unit 21.

[0034] In a multilayer waveguide structure, when an optical signal needs to switch from one waveguide layer to another, a low-loss transition between the upper and lower waveguide layers can be achieved through tapered coupling structures, tapered directional couplers, or other interlayer optical path conversion structures located between the layers. By employing this layered wiring design of silicon waveguides and silicon nitride waveguides, coupled with cross-sectional size optimization for specific wavelengths and mode matching, the on-chip waveguide network 30 not only meets the complex routing paths required for large-area array wiring but also maintains low loss and low crosstalk during the transmission of multi-channel optical signals.

[0035] In one embodiment, see Figure 5Both the silicon waveguide circuit 31a and the silicon nitride waveguide circuit 31b have a curved section 301, which is an arc-shaped bend or an Euler bend; the radius of curvature of the curved section 301 of the silicon waveguide circuit 31a is not less than 5 μm, and the radius of curvature of the curved section 301 of the silicon nitride waveguide circuit 31b is not less than 50 μm.

[0036] In practice, since the optical receiving array 20 of the first region 101 is usually arranged in a two-dimensional regular pattern, while the second region 102 is usually located at a specific position on the edge of the chip, the silicon waveguide lines 31a and silicon nitride waveguide lines 31b in the on-chip waveguide network 30 inevitably need to bend and turn to avoid obstacles, cross other waveguides, or adapt to the wiring constraints of the chip as they extend from the first region 101 to the second region 102. In order to achieve low-loss transmission of optical signals, the waveguide lines 31 need to be provided with bending sections 301 at their bends.

[0037] In practical design, the bending section 301 can be either an arc bend or an Euler bend, depending on the specific wiring space and loss requirements. Alternatively, a combination of arc bends and Euler bends can be used on different bending sections 301 of the same waveguide 31, or even combined within the same bending section 301. An arc bend is a conventional bending structure with a constant radius of curvature. It is simple in structure, easy to model and fabricate, and suitable for scenarios with ample space and fixed bending angles. An Euler bend, on the other hand, is a bending structure with curvature that continuously changes along the propagation direction. Its curvature gradually increases from zero at the straight waveguide end to its maximum value at the midpoint, and then gradually decreases back to zero. Because the curvature change is continuous and smooth, the Euler bend can effectively avoid additional radiation loss caused by mode abrupt changes at the connection between the straight and bent waveguides, significantly reducing the overall transmission loss of the bending section 301. Therefore, it is a preferred choice in high-density wiring or arrayed transmission scenarios with extremely stringent loss requirements. In actual wiring, designers can flexibly choose to use arc bending, Euler bending, or a combination of both, depending on different optical path detour requirements and chip area limitations, in order to achieve the best balance between bending loss and wiring density.

[0038] To ensure that the waveguide circuit 31 maintains a high optical field confinement capability in the curved section 301 while also considering the chip's area, the bending dimensions of the two waveguide materials are differentiated. Silicon waveguides, due to their high refractive index contrast, possess extremely strong lateral confinement capability for the optical field; therefore, the radius of curvature of its curved section 301 can be designed to be no less than 5 μm. With a radius of curvature of 5 μm or greater, silicon waveguides can maintain low bending radiation loss within a compact turning radius, thus meeting the wiring requirements of high-density integration. Silicon nitride waveguides, with their relatively low refractive index contrast, have weaker optical field confinement capability. If the radius of curvature is too small, the optical field is prone to leakage to the outside of the bend, resulting in significant radiation loss. Therefore, the radius of curvature of the curved section 301 of the silicon nitride waveguide must be greater than or equal to 50 μm to ensure low-loss transmission characteristics during long-distance transmission and multi-layer routing.

[0039] In one embodiment, see Figure 1 , Figure 2 as well as Figure 4 The photoelectric conversion module 40 includes a plurality of photoelectric detection units 41 corresponding to the optical receiving unit 21. Each photoelectric detection unit 41 is coupled to the corresponding waveguide circuit 31 and is used to convert the optical signal output by the corresponding waveguide circuit 31 into an electrical signal.

[0040] In practical implementation, the photoelectric conversion module 40, as the core functional unit for realizing photoelectric signal conversion, has an internal structure that strictly matches the waveguide circuit 31 layout of the on-chip waveguide network 30. Specifically, the photoelectric conversion module 40 contains several photoelectric detection units 41, the number of which is exactly the same as the number of optical receiving units 21 in the optical receiving array 20, forming a one-to-one mapping relationship. The input end of each photoelectric detection unit 41 is aligned and coupled only to the output end of a specific waveguide circuit 31, thereby ensuring that the spatial optical signal transmitted by that waveguide circuit 31 can be accurately sent to the corresponding photoelectric detection unit 41 for photoelectric conversion.

[0041] In practical implementation, the photodetector unit 41 can be a high-speed optoelectronic device with fast response speed and high quantum efficiency, such as a silicon-germanium photodetector or a III-V semiconductor photodetector. After receiving the guided light signal output from the corresponding waveguide circuit 31, each photodetector unit 41 uses its internal light absorption layer to convert photons into electron-hole pairs, and extracts photogenerated carriers through the built-in electrode structure, thereby forming an electrical signal output proportional to the light signal intensity. Since the photoelectric conversion module 40 is located in the second region 102 (e.g., the chip edge region), the electrode arrangement of the photodetector unit 41 is not limited by the physical location of the light absorption region, which can significantly shorten the electrode length and optimize the electrode layout, thereby effectively reducing parasitic capacitance and parasitic inductance, and reducing the impact of RC delay on signal bandwidth. Through the independent channel architecture of one-to-one correspondence between the light receiving unit and the waveguide circuit 31, and one-to-one correspondence between the waveguide circuit 31 and the photodetector unit 41, the light signals of each channel remain completely isolated and do not interfere with each other during the process of receiving from space and photoelectric conversion. This structure ensures that the signal quality and response speed of each channel are not affected by adjacent channels in multi-channel array detection, which is beneficial to improving the overall parallel detection capability and signal consistency of the system, and provides a reliable structural foundation for large-scale integrated high-speed photoelectric detection.

[0042] In one embodiment, see Figure 6 The signal processing circuit 50 includes a dedicated integrated circuit chip 51, a transimpedance amplifier 52, and a digital signal processing chip. The transimpedance amplifier 52 is electrically connected to the photoelectric conversion module 40 and is used to amplify the electrical signal. The dedicated integrated circuit chip 51 is electrically connected to the transimpedance amplifier 52, and the digital signal processing chip is electrically connected to the dedicated integrated circuit chip 51.

[0043] In practical implementation, the signal processing circuit 50, as a key module for amplifying, conditioning, and digitally processing the weak electrical signal output from the photoelectric conversion module 40, is composed of a cascaded transimpedance amplifier 52, a dedicated integrated circuit chip 51, and a digital signal processing chip. In practical applications, the electrical signal output by the photoelectric conversion module 40 is usually an extremely weak current signal, which is difficult to directly drive subsequent digital logic circuits. Therefore, the transimpedance amplifier 52 (TIA) is first electrically connected to the output terminal of the photoelectric conversion module 40. Its core function is to convert the weak current signal into a voltage signal with a certain voltage amplitude, and then perform preliminary linear amplification and low-pass filtering to eliminate some high-frequency noise, so that the signal can meet the processing requirements of subsequent circuits.

[0044] The application-specific integrated circuit (ASIC) chip 51 is electrically connected to the output of the transimpedance amplifier 52. In practical implementations, the ASIC chip can integrate functional modules such as multi-channel signal conditioning, clock synchronization, data buffering, and high-speed serial / parallel interfaces. It receives the amplified analog electrical signal output from the transimpedance amplifier 52 and executes corresponding signal conditioning and control tasks according to system instructions, providing a standardized signal interface and data format conversion for subsequent digital processing. The digital signal processing (DSP) chip is electrically connected to the ASIC chip 51. Based on its internal high-speed computing unit and dedicated algorithm engine, the DSP chip performs further high-speed digital processing on the digital signal output by the ASIC chip, including digital filtering, equalization, clock data recovery, and forward error correction, ultimately outputting a high-quality digital electrical signal that meets communication or computing requirements.

[0045] Through the aforementioned three-stage cascaded architecture, the signal processing circuit 50 achieves a complete conditioning and processing path from the weak analog current signal output by the photoelectric conversion module 40 to a high-quality digital electrical signal. The clear division of labor and collaborative work among the chips effectively ensures the reliable output of electrical signals from the waveguide integrated photodetector described in this application at rates of hundreds of gigabits per second and above, and the efficient integration with subsequent systems.

[0046] In one embodiment, see Figure 1 , Figure 3 as well as Figure 6 The signal processing circuit 50 is located on the back side of the optoelectronic chip 10. The optoelectronic chip 10 has a through hole 11 in the second region 102. The output terminal of the optoelectronic conversion module 40 is led to the back side of the optoelectronic chip 10 through the through hole 11 and is electrically connected to the signal processing circuit 50.

[0047] In specific implementation, to achieve high-density three-dimensional integration of the photoelectric detection system and effectively shorten the electrical signal interconnection path, the signal processing circuit 50 is arranged on the back side of the photoelectric chip 10 (i.e., the side opposite to the front side where the photoelectric chip 10 and the optical receiving array 20 are located). Simultaneously, the photoelectric chip 10 has vias 11 penetrating both the top and bottom sides of the photoelectric chip 10 at the position corresponding to the second region 102. These vias 11 are through-silicon vias (TSVs) in semiconductor technology, meaning that vias 11 are formed on the silicon substrate of the photoelectric chip 10 using TSV penetration technology. The output terminal of the photoelectric conversion module 40 is aligned and connected to one end of the via 11, allowing the electrical signal output by the photoelectric conversion module 40 to be transmitted directly from the front side of the chip through the inside of the photoelectric chip 10 to the back side of the chip via the via 11, thereby electrically connecting the photoelectric conversion module 40 to the signal processing circuit 50 integrated on the back side of the chip.

[0048] In practical implementation, the via 11 is filled with a conductive material (such as copper or other metals) to achieve a low-impedance electrical connection between the output of the photoelectric conversion module 40 and the back-side signal processing circuit 50 of the chip. An insulating layer may also be provided inside the via 11 to prevent short circuits or parasitic coupling between the signal and the silicon substrate, ensuring the integrity of high-frequency signal transmission. Through this structure, the electrical signal output by the photoelectric conversion module 40 can be guided to the input of the back-side signal processing circuit 50 within a very short transmission path. By placing the signal processing circuit 50 on the back side of the optoelectronic chip 10 and leading the output terminal of the optoelectronic conversion module 40 to the back side through the via 11, on the one hand, this three-dimensional integrated structure significantly shortens the physical interconnection distance between the optoelectronic conversion module 40 and the signal processing circuit 50, which can effectively reduce parasitic resistance, capacitance and inductance on the interconnection path, which is extremely beneficial to improving signal transmission bandwidth and reducing power consumption; on the other hand, this integration method allows the front area of ​​the optoelectronic chip 10 to be fully used for the layout of the optical receiving array 20, and the signal processing circuit 50 no longer occupies the front planar space, which is conducive to increasing the scale of the optical receiving array 20 or reducing the overall size of the chip.

[0049] Through the above-mentioned three-dimensional integrated structure, a high-efficiency electrical connection between the photoelectric conversion module 40 and the signal processing circuit 50 is realized, providing key structural support for the improvement of the overall system bandwidth and large-scale integration. It is especially suitable for high-speed optical interconnect, optical computing and microwave photonic radar and other application scenarios with extremely high requirements for speed and integration.

[0050] In one embodiment, see Figure 7 The optical receiving unit 21 has an inlet port 211, an outlet port 212, and a light guide channel 213 that connects the inlet port 211 and the outlet port 212. The outlet port 212 is coupled to the on-chip waveguide network 30. The aperture of the light guide channel 213 gradually narrows from the inlet port 211 to the outlet port 212.

[0051] In specific implementation, the optical receiving unit 21 serves as the front-end interface for converting spatial optical signals into on-chip waveguide optical signals. Physically, it consists of an inlet port 211, an outlet port 212, and a light guide channel 213 connecting the two. The inlet port 211, located at the top of the optical receiving unit 21, has a relatively large aperture to cover the main energy region of the incident spatial beam, capturing as much spatial optical signal as possible. The outlet port 212, located at the bottom of the optical receiving unit 21, is precisely aligned with the input end of the on-chip waveguide network 30, achieving physical and optical coupling to ensure that the compressed and converged optical signal can be efficiently introduced into the on-chip waveguide network 30 for subsequent transmission. The light guide channel 213 connects the inlet port 211 and the outlet port 212, forming a continuous optical transmission path within the optical receiving unit 21.

[0052] In the actual structural design, the aperture of the light guide channel 213 gradually narrows from the light inlet 211 to the light outlet 212. This tapered structure causes the cross-sectional size of the spatial optical signal entering from the light inlet 211 to be gradually compressed as it propagates downward along the light guide channel 213, ultimately forming a convergent optical field at the light outlet 212 that highly matches the on-chip waveguide fundamental mode field distribution. Since the light outlet 212 is directly coupled to the on-chip waveguide network 30, this tapered optical field compression process effectively reduces optical coupling loss caused by abrupt changes in mode size, enabling the spatial optical signal to be efficiently injected into the on-chip waveguide network 30 with low loss. The coupling between the light outlet 212 and the on-chip waveguide network 30 can be achieved by aligning the end faces of the light outlet 212 with the input end of the on-chip waveguide. The cross-sectional size, refractive index distribution, and optical field mode of both are matched to ensure low reflection and low scattering at the coupling interface. The optical receiving unit 21 can adopt different three-dimensional optical forms such as funnel shape, microlens shape, cone shape, or freeform tapered structure. Through the tapering of the aperture from the light inlet 211 to the light outlet 212, combined with the light outlet 212, and through a combination of microlenses and grating couplers, it achieves precise coupling with the on-chip waveguide, realizing efficient and low-loss conversion from large-aperture spatial light reception to small-aperture guided wave light transmission. This structural design helps to relax the system's tolerance to spatial light incident angle and position deviations, effectively improving the coupling stability and reliability of the photodetector in practical applications.

[0053] The coupling between the light exit port 212 and the on-chip waveguide network 30 can be achieved by aligning the light exit port 212 with the input end of the on-chip waveguide. The cross-sectional dimensions, refractive index distribution, and optical field modes of both are matched to ensure low reflection and low scattering at the coupling interface. The optical receiving unit 21 can adopt different three-dimensional optical forms such as funnel shape, microlens shape, cone shape, or freeform tapered structure. Through the tapering of the aperture from the light inlet port 211 to the light exit port 212, combined with the light exit port 212, and through a combination of microlenses and grating couplers, it achieves precise coupling with the on-chip waveguide, realizing efficient and low-loss conversion from large-aperture spatial light reception to small-aperture guided wave light transmission. This structural design helps to relax the system's tolerance to spatial light incident angle and position deviation, effectively improving the coupling stability and reliability of the photodetector in practical applications.

[0054] Preferably, the aperture of the light inlet 211 is 5 μm to 20 μm, the aperture of the light outlet 212 is 0.6 μm to 2.0 μm, and the axial distance (i.e., structural height) between the light inlet 211 and the light outlet 212 is 8 μm to 30 μm. These dimensional parameters are determined based on the operating wavelength, the fundamental mode optical field distribution of the on-chip waveguide, and the spatial light incident conditions.

[0055] In one specific implementation, the optical receiving array 20 is a 4×4 array. The aperture of the light inlet 211 of the optical receiving unit 21 is 10 μm, the aperture of the light outlet 212 is 1.0 μm, and the axial distance between the light inlet 211 and the light outlet 212 is 15 μm. The optical receiving units 21 are arranged according to a square array rule, with an array period of 20 μm, meaning the distance between the centers of adjacent optical receiving units 21 is 20 μm. This spacing configuration maintains an approximately 10 μm gap between the edges of adjacent light receiving apertures. This spacing effectively reduces optical crosstalk between adjacent optical receiving units 21, avoiding signal interference caused by light field overlap. Furthermore, this spacing provides ample physical space for the bending, crossing, and interlayer routing of the on-chip waveguide network 30, contributing to improved flexibility and integration density of optical path wiring.

[0056] Further, see Figure 7 A light-guiding gradient coupling section 201 is provided between the light output port 212 and the input end of the on-chip waveguide network 30, and the gradient coupling section 201 gradually expands from the light output port 212 toward the on-chip waveguide network 30.

[0057] In specific implementation, a light-guiding gradient coupling section 201 is added between the light output port 212 of the optical receiving unit 21 and the input end of the on-chip waveguide network 30. Since there is still a certain difference between the compressed light field output from the light output port 212 and the fundamental mode size of the on-chip waveguide, direct coupling can easily cause mode mismatch and radiation loss. The gradient coupling section 201 gradually expands radially from the small aperture of the light output port 212 to the input end of the on-chip waveguide network 30, so that the mode size and field distribution of the light field can undergo a smooth and continuous adiabatic evolution during the propagation of the light field along the gradient coupling section 201, thereby completing a smooth transition from the output mode of the light output port 212 to the fundamental mode of the on-chip waveguide before entering the on-chip waveguide network 30. The gradient coupling section 201 effectively reduces coupling loss caused by mode abrupt changes, further improving the coupling efficiency of spatial optical signals to the on-chip waveguide network 30. This ensures that the optical signal maintains good mode matching when entering the on-chip waveguide network 30, which is particularly important for low-loss optical transmission in large-scale array detection. In actual fabrication, the gradient coupling section 201 can be formed during the fabrication of the spatial light collection structure or fabricated through independent photolithography and etching processes.

[0058] In one embodiment, see Figure 2 All the optical receiving units 21 are regularly arranged in a polygonal array, and the center-to-center distance between adjacent optical receiving units 21 is equal.

[0059] In specific implementation, the optical receiving array 20 adopts a regular polygonal array arrangement on the first region 101 of the optoelectronic chip 10. The polygonal array can be selected with different geometric shapes according to specific application requirements, such as square array, rectangular array, hexagonal close-packed array, or staggered array. The square array facilitates the regular outlining of waveguides in the horizontal and vertical directions, which is beneficial to the wiring symmetry and modular design of the on-chip waveguide network 30; the hexagonal close-packed array can achieve a higher spatial light filling rate per unit area, which is beneficial to improving the spatial light collection efficiency of the receiving array; the staggered array can increase the wiring spacing between adjacent waveguides and reduce the risk of optical crosstalk between waveguides when high-density wiring is used.

[0060] In the array design, the center-to-center spacing between adjacent optical receiving units 21 remains equal, meaning the array period remains consistent throughout the entire array. This equal-spacing design ensures channel consistency for each receiving unit during spatial light reception, resulting in a uniform distribution of spatial light signal intensity and incident angle received by each unit, thus avoiding differences in reception efficiency caused by uneven spacing between units. Simultaneously, the equal-spacing design also facilitates that waveguide paths 31 extending from the first region 101 have the same initial spacing when entering the on-chip waveguide network 30, which is beneficial for spacing planning and optical path symmetry design during waveguide wiring.

[0061] Preferably, the array period can be determined based on the spatial light collection aperture and channel isolation spacing, with the array period set within the range of 10μm to 50μm. A period that is too small may increase optical crosstalk between adjacent units, while a period that is too large will reduce the receiving unit density per unit area, thus reducing the number of channels that can be integrated. By combining regular arrangement with equal spacing design, a stable and reliable spatial light receiving foundation can be provided for large-scale arrayed photoelectric detection while ensuring channel consistency, meeting the dual requirements of channel uniformity and high density for multi-channel parallel detection.

[0062] In summary, the waveguide-integrated photodetector of this invention completely decouples spatial light reception and photoelectric conversion functions in space, constructing a high-speed photoelectric detection architecture based on waveguide integration. Utilizing horizontally spaced first and second regions on the photoelectric chip, an optical receiving array is positioned in the first region to receive spatial light signals. The converged light signals are then transmitted to the second region at the chip edge for photoelectric conversion and signal processing via an on-chip waveguide network. This design fundamentally breaks through the physical limitation of high coupling between the light absorption region and electrodes in traditional front-incident detectors. By arranging the photoelectric conversion module at the chip edge, the electrode length is significantly shortened, parasitic capacitance and inductance are reduced, and the limitation of RC delay on electrical bandwidth is weakened, providing a physical basis for achieving high-speed detection of hundreds of gigabits per second and above.

[0063] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A waveguide-integrated photodetector, characterized in that, include: A photoelectric chip having a first region and a second region spaced apart in the horizontal direction; An optical receiving array is disposed in the first region, and the optical receiving array includes a plurality of optical receiving units for receiving and converging spatial light signals; An on-chip waveguide network, disposed inside the optoelectronic chip and coupled to the optical receiving unit, is used to transmit the converged spatial light signal from the first region to the second region. A photoelectric conversion module is disposed in the second region and coupled to the on-chip waveguide network, and is used to convert the optical signal output by the on-chip waveguide network into an electrical signal. The signal processing circuit is electrically connected to the photoelectric conversion module and is used to receive and process the electrical signals output by the photoelectric conversion module.

2. The waveguide integrated photodetector according to claim 1, characterized in that, The on-chip waveguide network includes several waveguide paths corresponding to the optical receiving unit. Each waveguide path is coupled to the corresponding optical receiving unit and is used to transmit the spatial optical signal converged by the corresponding optical receiving unit from the first region to the second region.

3. The waveguide integrated photodetector according to claim 2, characterized in that, The plurality of waveguide lines include silicon waveguide lines and silicon nitride waveguide lines, wherein at least one silicon waveguide line and at least one silicon nitride waveguide line are disposed in different layers within the optoelectronic chip.

4. The waveguide integrated photodetector according to claim 3, characterized in that, Both the silicon waveguide and the silicon nitride waveguide have curved sections, which are arc-shaped bends and / or Euler bends.

5. The waveguide integrated photodetector according to claim 2, characterized in that, The photoelectric conversion module includes a plurality of photoelectric detection units corresponding to the optical receiving unit. Each photoelectric detection unit is coupled to the corresponding waveguide circuit and is used to convert the optical signal output by the corresponding waveguide circuit into an electrical signal.

6. The waveguide integrated photodetector according to any one of claims 1-5, characterized in that, The signal processing circuit includes a dedicated integrated circuit chip, a transimpedance amplifier, and a digital signal processing chip. The transimpedance amplifier is electrically connected to the photoelectric conversion module and is used to amplify the electrical signal. The dedicated integrated circuit chip is electrically connected to the transimpedance amplifier, and the digital signal processing chip is electrically connected to the dedicated integrated circuit chip.

7. The waveguide integrated photodetector according to any one of claims 1-5, characterized in that, The signal processing circuit is located on the back side of the optoelectronic chip. The optoelectronic chip has a through-hole in the second region. The output terminal of the optoelectronic conversion module is led to the back side of the optoelectronic chip through the through-hole and is electrically connected to the signal processing circuit.

8. The waveguide integrated photodetector according to any one of claims 1-5, characterized in that, The optical receiving unit has an inlet port, an outlet port, and a light guide channel connecting the inlet port and the outlet port. The outlet port is coupled to the on-chip waveguide network, and the diameter of the light guide channel gradually narrows from the inlet port to the outlet port.

9. The waveguide integrated photodetector according to claim 8, characterized in that, A light-guiding gradient coupling section is provided between the light-emitting port and the input end of the on-chip waveguide network, and the gradient coupling section gradually expands from the light-emitting port to the on-chip waveguide network.

10. The waveguide integrated photodetector according to any one of claims 1-5, characterized in that, All the optical receiving units are arranged regularly in a polygonal array, and the center-to-center distance between adjacent optical receiving units is equal.

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