A solar cell and a method of manufacturing the same

Abstract

The present disclosure relates to the technical field of solar cells, and discloses a solar cell and a preparation method thereof. The solar cell comprises a base layer including a front surface and a back surface arranged oppositely; the back surface includes contact areas and interval areas arranged alternately and at intervals; a first semiconductor layer is located at the contact areas of the back surface of the base layer; a composite tower base structure is located at the interval areas of the back surface of the base layer; the composite tower base structure includes a plurality of first tower bases and a plurality of second tower bases; the size of the second tower base is smaller than that of the first tower base; and a first passivation layer is located on the surface of the composite tower base structure of the interval areas. The present disclosure can improve the passivation effect of the first passivation layer on the surface of the interval areas of the solar cell.

Description

Technical Field

[0001] This disclosure relates to the field of solar cell technology, specifically to a solar cell and its fabrication method. Background Technology

[0002] In TOPCon (Tunneling Oxide Passivated Contact) cells, the N-polyfinger (N-type polycrystalline silicon finger contact) process typically requires the deposition of an aluminum oxide passivation film on the back side to compensate for the loss of chemical and field passivation after the removal of tunneling oxygen and doped polycrystalline silicon in the non-metallic region. The thickness of the aluminum oxide film in the non-metallic region plays an important role in the hydrogen passivation of the cell.

[0003] In related technologies, the non-metallic region (also known as the spacer region) on the back side of the N-type polyfinger process is typically formed as a single, relatively large tower-like structure with low surface roughness. While this ensures the uniformity of the passivation film subsequently formed in the non-metallic region, it hinders the suspension of hydrogen atoms in the passivation film, thus reducing the passivation effect of the final solar cell. Furthermore, fewer hydrogen atom suspension sites during the deposition of the passivation film result in a lower thickness of the stably deposited alumina passivation film, leading to poor passivation performance. Even if a thick alumina passivation film is forcibly deposited, hydrogen accumulation and overflow, film bursting, pinholes, and decreased adhesion can occur, resulting in poor integrity and passivation performance of the entire film.

[0004] Therefore, a solution is needed that can increase the thickness and passivation performance of the passivation film while maintaining its uniformity and integrity. Summary of the Invention

[0005] This disclosure provides a solar cell and its fabrication method to solve the problem in related technologies where the surface of the spacer region on the back of the solar cell is a large-sized single tower base structure with low surface roughness, resulting in a low thickness of the passivation film layer formed in the non-metallic region and poor passivation effect.

[0006] In a first aspect, this disclosure provides a solar cell, comprising: The base layer includes a front side and a back side that are arranged opposite to each other; the back side includes contact areas and interval areas that are alternately spaced. The first semiconductor layer is located in the contact area on the back side of the substrate layer; A composite tower base structure is located in the spacer region on the back side of the base layer; the composite tower base structure includes multiple first tower bases and multiple second tower bases; the size of the second tower base is smaller than the size of the first tower base; The first passivation layer is located on the surface of the composite tower base structure in the interval zone.

[0007] The solar cell disclosed herein has a composite base structure on the surface of the spacer region on the back side of the substrate, which is composed of a larger first base and a smaller second base. Compared with a single-sized base structure, the composite base structure can increase the roughness and specific surface area of ​​the spacer region without affecting the uniformity of the first passivation layer, thereby providing more suspension sites for hydrogen atoms in the first passivation layer, improving the passivation effect of the first passivation layer, and increasing the thickness of the first passivation layer on the surface of the spacer region while ensuring the quality of the first passivation layer, thus improving the passivation effect of the solar cell.

[0008] In one alternative implementation, the second tower base is located on the surface of the first tower base, and / or the second tower base is located between two adjacent first tower bases; The dimensions of the first tower base are 15μm~25μm, and the dimensions of the second tower base are 4μm~8μm; The material of the first passivation layer includes aluminum oxide; the thickness of the first passivation layer is 4nm~6nm.

[0009] The solar cell disclosed herein utilizes a composite tower base structure with significant size differences on the surface of the spacer region. The first tower base has a size of 15μm to 25μm, and the second tower base has a size of 4μm to 8μm. This structure increases the surface roughness and specific surface area of ​​the spacer region and provides more suspension sites for hydrogen atoms in the first passivation layer. While ensuring the film quality and passivation performance of the first passivation layer, it also increases the thickness of the first passivation layer on the surface of the spacer region, thereby improving the passivation effect of the solar cell. The second tower base is located on the surface of the first tower base, and / or between two adjacent first tower bases. It superimposes finer micro-undulations on the micro-undulations formed by the first tower base, further increasing the surface roughness and specific surface area of ​​the spacer region and increasing the suspension sites for hydrogen atoms on the substrate surface of the spacer region. This stabilizes the deposition of a first passivation layer with a thickness of 4nm to 6nm, improves the hydrogen passivation effect of the first passivation layer, and thus enhances the passivation effect of the solar cell.

[0010] In one alternative embodiment, the solar cell further includes a second semiconductor layer located on the front side of the substrate; the first semiconductor layer and the second semiconductor layer have opposite conductivity types; the first passivation layer also covers the surface of the first semiconductor layer away from the substrate and the surface of the second semiconductor layer away from the substrate in the contact area. The solar cell also includes: a second passivation layer located on the surface of the first passivation layer facing away from the substrate; the second passivation layer is located on both the front and back sides of the substrate. The first electrode is located on the surface of the second passivation layer corresponding to the contact area. The first electrode penetrates the first passivation layer and the second passivation layer and contacts the side of the first semiconductor layer opposite to the contact area.

[0011] The solar cell disclosed herein features a second semiconductor layer that covers the entire front side, which improves the cell's light absorption efficiency and photoelectric conversion efficiency. By setting a spacer region in the first semiconductor layer on the back side, parasitic absorption of light by the spacer region can be reduced, thus improving cell performance. The first passivation layer and the second passivation layer are stacked on both the front and back sides of the substrate layer, providing passivation and anti-reflection protection for both the front and back sides. The first electrode penetrates the first and second passivation layers and contacts the first semiconductor layer, enabling the back electrode to be led out while ensuring passivation performance.

[0012] In one optional embodiment, a tunneling oxide layer is further disposed between the contact area of ​​the substrate layer and the first semiconductor layer, and the tunneling oxide layer and the first semiconductor layer form a passivation contact structure. The substrate is an N-type silicon substrate, the first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer.

[0013] The solar cell disclosed herein comprises a tunneling oxide layer in the contact region and a first semiconductor layer forming a passivation contact structure. This reduces surface recombination of the substrate layer and metal contact recombination of the first electrode in the contact region, thereby improving the passivation effect of the contact region on the back of the cell. Simultaneously, the first semiconductor layer is an N-type semiconductor layer. By setting an N-type semiconductor layer and a tunneling oxide layer in the contact region on the back of the substrate layer, an N-type polyfinger structure can be formed. This reduces the parasitic absorption of light by the tunneling oxide layer and the N-type doped polycrystalline silicon layer without affecting the passivation formation in the contact region, thereby improving the passivation performance of the passivation contact structure.

[0014] Secondly, this disclosure provides a method for preparing a solar cell, the method comprising: A base layer is provided, the base layer including a front side and a back side disposed opposite to each other; the back side includes a contact area and a spacing area alternately disposed along a first direction; A first semiconductor layer is formed on the back side of the substrate; The spacer region is wet-cleaned using a target alkaline solution containing anti-plating additives to remove the first semiconductor layer of the spacer region while retaining the first semiconductor layer of the contact region, and a composite tower base structure is formed on the substrate surface of the spacer region; the composite tower base structure includes multiple first tower bases and multiple second tower bases; the size of the second tower bases is smaller than the size of the first tower bases. A first passivation layer is formed on the surface of the composite tower base structure in the interval zone.

[0015] The solar cell fabrication method disclosed herein, in the step of wet cleaning the spacer region using a target alkaline solution containing a de-coating additive, can utilize the de-coating additive in the target alkaline solution to adjust the longitudinal corrosion rate of the substrate surface of the spacer region. This allows for the simultaneous wet cleaning of the spacer region and removal of the first semiconductor layer, while simultaneously etching a composite tower structure containing a first tower base and a second tower base on the substrate surface of the spacer region. This achieves a high-roughness and uniformly distributed spacer region surface without additional processing, providing more suspension sites for the subsequent hydrogen passivation of the first passivation layer. This increases the thickness of the first passivation layer that can be stably deposited on the spacer region surface, enhances the passivation effect of the first passivation layer formed in the spacer region, and ultimately improves the passivation effect of the solar cell.

[0016] In one optional embodiment, the concentration of the de-coating additive in the target alkaline solution is 0.2% to 0.3%, the size of the first tower base is 15 μm to 25 μm, the size of the second tower base is 4 μm to 8 μm, and the thickness of the first passivation layer is 4 nm to 6 nm.

[0017] The solar cell fabrication method disclosed herein, when the concentration of the de-coating additive in the target alkaline solution is 0.2%~0.3%, can stably form a first substrate and a second substrate with sizes of 15μm~25μm and 4μm~8μm respectively on the surface of the spacer region of the substrate layer, thereby stably depositing a first passivation layer with a thickness of 4nm~6nm and high film quality, which can increase the thickness of the first passivation layer on the surface of the spacer region, thereby improving the passivation effect of the first passivation layer.

[0018] In one alternative implementation, a first semiconductor layer is formed on the back side of the substrate, comprising: A tunneling oxide layer, a first semiconductor layer, and a first surface layer are sequentially formed on the back side of the substrate layer; Before wet cleaning the spacer area with a target alkaline solution containing anti-plating additives, the method further includes: laser patterning the first surface layer to vaporize or loosen the first surface layer corresponding to the spacer area. In the step of wet cleaning the spacer region with a target alkaline solution containing anti-plating additives, the first semiconductor layer and tunneling oxide layer of the spacer region are removed, while the first surface layer, tunneling oxide layer and first semiconductor layer of the contact region are retained, and a composite tower base structure is formed on the substrate surface of the spacer region.

[0019] The solar cell fabrication method disclosed herein pre-vaporizes or loosens the first surface layer corresponding to the spacer region through laser patterning. This allows for selective removal of the tunneling oxide layer and the first semiconductor layer in the spacer region during the wet cleaning step, forming a composite tower structure on the substrate surface of the spacer region. The contact region, protected by the first surface layer, is retained, achieving patterned separation between the contact region and the spacer region. Furthermore, the tunneling oxide layer retained in the contact region and the first semiconductor layer ultimately form a passivated contact structure, reducing surface recombination and metal-to-metal contact recombination, thereby improving the performance of the solar cell.

[0020] In one alternative implementation, before forming the first semiconductor layer on the back side of the substrate, the method further includes forming a second semiconductor layer on the front side of the substrate. Forming a second semiconductor layer on the front side of the substrate includes: The substrate is textured on both sides; the substrate is a silicon wafer. A second diffusion process is performed on the double-textured substrate layer to form a second semiconductor layer and a second surface layer; Remove the second surface layer on the back side of the substrate and perform alkaline washing and polishing on the back side of the substrate to remove the second semiconductor layer on the back side of the substrate; retain the second semiconductor layer and the second surface layer on the front side of the substrate.

[0021] The method for fabricating a solar cell disclosed herein first involves double-sided texturing and forming a second semiconductor layer and a second surface layer on both sides. Then, an alkaline washing and polishing process is used to remove the second semiconductor layer and the second surface layer on the back side. This process can form a textured surface and a second semiconductor layer on the front side of the substrate, improving the light trapping performance and light utilization efficiency of the cell. Furthermore, during the alkaline washing and polishing process to remove the second semiconductor layer and the second surface layer on the back side, a polished surface can be formed on the back side of the substrate, improving the bonding force between the back side of the substrate and the subsequently formed tunneling oxide layer and the first semiconductor layer, as well as the film quality of the tunneling oxide layer and the first semiconductor layer. This reduces the difficulty of the process, improves the passivation effect and contact performance of the passivation contact structure, and thus improves the performance of the solar cell.

[0022] In one alternative embodiment, after alkaline washing and polishing, a third tower base is formed on the back side of the substrate layer. The size of the third tower base is smaller than that of the first tower base and larger than that of the second tower base. The size of the third tower base is 8~12μm.

[0023] The solar cell fabrication method disclosed herein removes the second semiconductor layer on the back side during alkaline washing and polishing, while simultaneously forming a third substrate with a size between the first and second substrates on the back side. This facilitates the subsequent formation of a tunneling oxide layer and a first semiconductor layer on the back side of the substrate layer, improves the film quality of the tunneling oxide layer and the first semiconductor layer, reduces process difficulty, enhances the passivation effect and contact performance of the passivation contact structure, and thus improves the performance of the solar cell.

[0024] In one optional embodiment, a tunneling oxide layer, a first semiconductor layer, and a first surface layer are sequentially formed on the back side of the substrate, including: An initial tunneling oxide layer and an intrinsic amorphous silicon layer are formed on the back side of the substrate after alkaline washing and polishing. A first diffusion process is performed on the initial tunneling oxide layer and the intrinsic amorphous silicon layer to obtain a tunneling oxide layer based on the initial tunneling oxide layer, and to form a first semiconductor layer and a first surface layer based on the intrinsic amorphous silicon layer, respectively. The first surface layer is located on the surface of the first semiconductor layer on the side opposite to the tunneling oxide layer. The material of the first semiconductor layer includes first doped polycrystalline silicon.

[0025] The method for fabricating solar cells disclosed herein first deposits an initial tunneling oxide layer and an intrinsic amorphous silicon layer, and then forms a tunneling oxide layer, a first semiconductor layer and a first surface layer on the outside through a first diffusion process, thereby realizing the fabrication of a back passivation contact structure and a surface protective layer. At the same time, it can improve the passivation effect and contact performance of the passivation contact structure, thereby improving the performance of the solar cell.

[0026] In one optional embodiment, the first diffusion process is a phosphorus diffusion process; the first semiconductor layer is an N-type semiconductor layer, and the first surface layer is a phosphorus silicon glass layer; The second diffusion process is a boron diffusion process; the second semiconductor layer is a P-type semiconductor layer, and the second surface layer is a borosilicate glass layer.

[0027] The solar cell fabrication method disclosed herein involves forming an N-type semiconductor layer and a phosphosilicate glass layer on the back side of a substrate using a phosphorus diffusion process, and forming a P-type semiconductor layer and a borosilicate glass layer on the front side of the substrate using a boron diffusion process, resulting in a solar cell structure with opposite conductivity types on the front and back sides. Simultaneously, by patterning the N-type semiconductor layer and tunneling oxide layer on the back side to form an N-type polyfinger structure, the parasitic absorption of light by the tunneling oxide layer and the N-type doped polycrystalline silicon layer can be reduced without affecting the passivation formation of the contact area, thereby improving the passivation performance of the passivation contact structure.

[0028] In one alternative embodiment, a first passivation layer is formed on the surface of the composite tower base structure in the interval region, comprising: A first passivation layer is formed simultaneously on the front and back sides of the substrate. The first passivation layer covers the surface of the composite tower base structure in the spacer region, and also covers the surface of the first semiconductor layer away from the substrate layer in the contact region, as well as the surface of the second semiconductor layer away from the substrate layer. After forming the first passivation layer on the surface of the composite tower base structure in the interval zone, the process also includes: A second passivation layer is formed on the surface of the first passivation layer facing away from the substrate layer; the second passivation layer is located on both the front and back sides of the substrate layer. A first electrode is formed on the surface of the second passivation layer corresponding to the contact area. The first electrode penetrates the first passivation layer and the second passivation layer and contacts the side of the first semiconductor layer opposite to the contact area.

[0029] The solar cell fabrication method disclosed herein involves forming a first passivation layer simultaneously on the front and back sides of the substrate layer, which can provide passivation and anti-reflection protection for the composite tower structure in the spacer region, the first semiconductor layer in the contact region, and the second semiconductor layer on the front side. A second passivation layer is stacked outside the first passivation layer to further enhance the passivation and anti-reflection effects on the front and back sides of the cell. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of a solar cell according to an embodiment of the present disclosure; Figure 2 This is a schematic flowchart of a method for preparing a solar cell according to an embodiment of the present disclosure; Figure 3 This is a schematic flowchart illustrating a method for preparing a solar cell according to an embodiment of the present disclosure. Figure 4 This is a schematic diagram of the structure for forming a second semiconductor layer in a method for preparing a solar cell according to an embodiment of the present disclosure; Figure 5 This is a schematic diagram of the structure in which a first semiconductor layer and a first surface layer are formed in a method for preparing a solar cell according to an embodiment of the present disclosure; Figure 6 This is a schematic diagram of the structure of a solar cell fabrication method according to an embodiment of the present disclosure, in which the first surface is laser patterned. Figure 7This is a schematic diagram of a structure in which a first surface layer is retained in the contact area after laser patterning processing in a method for preparing a solar cell according to an embodiment of the present disclosure. Figure 8 This is a schematic diagram of a method for preparing a solar cell according to an embodiment of the present disclosure, in which the first semiconductor layer of the spacer region is removed and a composite tower base structure is formed on the surface of the spacer region. Figure 9A This is a schematic diagram of the structure of removing the first surface layer of the contact area in a method for preparing a solar cell according to an embodiment of the present disclosure; Figure 9B This is a top view of the structure on one side of the spacer region on the back side in a method for fabricating a solar cell according to an embodiment of the present disclosure; Figure 10 This is a schematic diagram of the structure for forming the first passivation layer in a method for preparing a solar cell according to an embodiment of the present disclosure; Figure 11 This is a schematic diagram of the structure of forming the first electrode and the second electrode in a method for preparing a solar cell according to an embodiment of the present disclosure.

[0032] Figure label: 10. Base layer; 101. Contact area; 102. Spacing area; 20. First semiconductor layer; 21. Tunneling oxide layer; 22. First surface layer; 30. Second semiconductor layer; 40. First passivation layer; 51. First electrode; 52. Second electrode; 60. Composite tower base structure; 61. First tower base; 62. Second tower base. Detailed Implementation

[0033] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present disclosure and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the drawings, not the entire structure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without inventive effort are within the scope of protection of the present disclosure.

[0034] In the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of this disclosure. Various structural schematic diagrams according to embodiments of this disclosure are shown in the accompanying drawings. These drawings are not to scale, and some details are enlarged for clarity and may be omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from actual practices due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0035] N-type tunneling oxide passivated contact (N-TOPCon) solar cell technology is one of the mainstream cell technologies in the photovoltaic industry. The core structure of an N-TOPCon cell involves fabricating an ultrathin silicon oxide layer as a tunneling oxide layer on the back of the cell, followed by the deposition of an N-type doped polycrystalline silicon thin layer on top of this tunneling oxide layer. Together, these two layers form a passivation contact structure, effectively reducing surface recombination and metal-to-metal recombination. However, while the N-type doped polycrystalline silicon thin layer on the back optimizes the passivation of the back metal region, it also causes parasitic absorption of incident light, thus affecting light utilization.

[0036] To address the aforementioned issues, related technologies employ an N-type polyfinger process to remove the tunneling oxide layer and doped polysilicon layer in the non-metallic region on the back side. This reduces parasitic light absorption in the non-metallic region due to the tunneling oxide layer and N-type doped polysilicon layer, without affecting the passivation of the metallic region. The removal of the tunneling oxide layer and doped polysilicon in the non-metallic region is typically achieved using a laser-assisted wet chemical process. After removing the tunneling oxide layer and doped polysilicon in the non-metallic region, the N-type polyfinger process usually requires depositing an aluminum oxide film on the back side to compensate for the loss of chemical and field passivation in the non-metallic region after the removal of the tunneling oxide layer and doped polysilicon. The thickness of the aluminum oxide film in the non-metallic region plays a crucial role in the hydrogen passivation of the battery.

[0037] In related technologies, the non-metallic region (also known as the spacer region) on the back side of the N-type polyfinger process is typically formed as a single, relatively large tower-like structure with low surface roughness. While this ensures the uniformity of the passivation film subsequently formed in the non-metallic region, it hinders the suspension of hydrogen atoms in the passivation film, thus reducing the passivation effect of the final solar cell. Furthermore, fewer hydrogen atom suspension sites during the deposition of the passivation film result in a lower thickness of the stably deposited alumina passivation film, leading to poor passivation performance. Even if a thick alumina passivation film is forcibly deposited, hydrogen accumulation and overflow, film bursting, pinholes, and decreased adhesion can occur, resulting in poor integrity and passivation performance of the entire film.

[0038] Therefore, a solution is needed that can increase the thickness and passivation performance of the passivation film while maintaining its uniformity and integrity.

[0039] like Figure 1 As shown, this embodiment provides a solar cell, including: a substrate layer 10, including a front side and a back side disposed opposite to each other; the back side includes contact areas 101 and spacer areas 102 disposed alternately; a first semiconductor layer 20 located in the contact areas 101 on the back side of the substrate layer 10; a composite tower base structure 60 located in the spacer areas 102 on the back side of the substrate layer 10; the composite tower base structure 60 includes a plurality of first tower bases 61 and a plurality of second tower bases 62; the size of the second tower bases 62 is smaller than the size of the first tower bases 61; and a first passivation layer 40 located on the surface of the composite tower base structure 60 in the spacer areas 102.

[0040] The solar cell provided in this embodiment has a composite base structure 60 formed by a larger first base 61 and a smaller second base 62 on the surface of the spacer region 102 on the back of the substrate layer 10. Compared with a single-sized base structure, the composite base structure 60 can increase the roughness and specific surface area of ​​the spacer region 102 without affecting the uniformity of the first passivation layer 40, thereby providing more suspension sites for hydrogen atoms in the first passivation layer 40, improving the passivation effect of the first passivation layer 40, and increasing the thickness of the first passivation layer 40 on the surface of the spacer region 102 while ensuring the film quality of the first passivation layer 40, thereby improving the passivation effect of the solar cell and improving the electrical performance and photoelectric conversion efficiency of the solar cell.

[0041] In some alternative embodiments, the solar cell further includes a first electrode 51 located on the side of the first passivation layer 40 facing away from the first semiconductor layer 20 within the contact area 101, the first electrode 51 penetrating the first passivation layer 40 and contacting the first semiconductor layer 20.

[0042] In some alternative implementations, the second tower base 62 is located on the surface of the first tower base 61, and / or the second tower base 62 is located between two adjacent first tower bases 61.

[0043] In some alternative implementations, the size of the first base 61 is 1.5 times larger than the size of the second base 62. If the size of the first base 61 and the size of the second base 62 are too small, the roughness of the spacer region 102 will be reduced, and the thickness and passivation effect of the first passivation layer 40 cannot be effectively improved.

[0044] In some alternative embodiments, the size of the first tower base 61 is 15μm to 25μm, such as 15μm, 18μm, 20μm, 22μm or 25μm, and the size of the second tower base 62 is 4μm to 8μm, such as 4μm, 5μm, 6μm, 7μm or 8μm.

[0045] If the size of the first base 61 is too large, the roughness of the spacer region 102 will be reduced, which will not effectively improve the thickness and passivation effect of the first passivation layer 40. If the size of the first base 61 is too small, the deposition uniformity and film integrity of the first passivation layer 40 will be reduced, thereby reducing the passivation performance of the first passivation layer 40 and reducing the battery performance.

[0046] If the size of the second base 62 is too large, the roughness of the spacer region 102 will be reduced, which will not effectively improve the thickness and passivation effect of the first passivation layer 40. If the size of the second base 62 is too small, the deposition uniformity and film integrity of the first passivation layer 40 will be reduced, thereby reducing the passivation performance of the first passivation layer 40 and reducing the battery performance.

[0047] In some optional embodiments, the material of the first passivation layer 40 includes aluminum oxide; the thickness of the first passivation layer 40 is 4nm to 6nm, for example, 4nm, 4.2nm, 4.5nm, 5nm, 5.5nm, or 6nm. If the thickness of the first passivation layer 40 is too small, it will reduce the passivation performance of the battery; if the thickness of the first passivation layer 40 is too large, it will reduce the film quality and film integrity, and increase the difficulty of the process.

[0048] In specific implementation, the material of the first passivation layer 40 also includes hydrogen atoms, and the first passivation layer 40 is aluminum hydroxide.

[0049] The solar cell provided in this embodiment, by setting composite tower base structures 60 with large size differences on the surface of the spacer region 102, with the first tower base 61 having a size of 15μm~25μm and the second tower base 62 having a size of 4μm~8μm, can increase the surface roughness of the spacer region 102 and provide more suspension sites for hydrogen atoms in the first passivation layer 40. While ensuring the film quality and passivation performance of the first passivation layer 40, it also increases the thickness of the first passivation layer 40 on the surface of the spacer region 102, thereby improving the passivation effect of the solar cell; the second tower base 62... Located on the surface of the first base 61, and / or the second base 62 located between two adjacent first bases 61, a finer micro-undulation is superimposed on the micro-undulation formed by the first base 61, further increasing the surface roughness and specific surface area of ​​the spacer region 102, increasing the hydrogen atom suspension sites on the surface of the base layer 10 of the spacer region 102, thereby stably depositing a first passivation layer 40 with a thickness of 4nm~6nm, improving the hydrogen passivation effect of the first passivation layer 40, improving the passivation effect of the solar cell, and thus improving the electrical performance and photoelectric conversion efficiency of the solar cell.

[0050] In some alternative implementations, the first tower base 61 occupies 60% to 70% of the area of ​​the interval 102; the second tower base 62 occupies 30% to 40% of the area of ​​the interval 102.

[0051] In some alternative implementations, within the interval 102, the ratio of the number of first tower bases 61 to the number of second tower bases 62 is 1:2 to 1:6.

[0052] The solar cell provided in this embodiment has a first base 61 with a size of 15μm~25μm and a second base 62 with a size of 4μm~8μm. The first base 61 occupies 60%~70% of the area of ​​the spacer region 102, and the second base 62 occupies 30%~40% of the area of ​​the spacer region 102. At the same time, within the spacer region 102, the ratio of the number of first bases 61 to the number of second bases 62 is 1:2~1:6. This can further increase the surface roughness and specific surface area of ​​the spacer region 102, and provide more suspension sites for hydrogen atoms in the first passivation layer 40. While ensuring the film quality and passivation performance of the first passivation layer 40, the thickness of the first passivation layer 40 on the surface of the spacer region 102 is increased, thereby improving the passivation effect of the solar cell.

[0053] In some alternative embodiments, the solar cell further includes a second semiconductor layer 30 located on the front side of the substrate 10; the first semiconductor layer 20 and the second semiconductor layer 30 have opposite conductivity types; the first passivation layer 40 also covers the surface of the first semiconductor layer 20 facing away from the substrate 10 and the surface of the second semiconductor layer 30 facing away from the substrate 10 in the contact area 101.

[0054] The solar cell provided in this embodiment has a second semiconductor layer 30 on the front side that covers the entire surface, which can improve the light absorption efficiency and photoelectric conversion efficiency of the cell. By setting a spacer region 102 on the first semiconductor layer 20 on the back side, the parasitic absorption of light by the spacer region 102 can be reduced, thereby improving the performance of the cell.

[0055] In some alternative embodiments, the solar cell further includes a first electrode 51 located on the side of the first semiconductor layer 20 facing away from the contact region 101, the first electrode 51 being in contact with the first semiconductor layer 20 within the contact region 101.

[0056] In some alternative embodiments, the solar cell further includes a second electrode 52 located on the side of the second semiconductor layer 30 facing away from the front of the substrate layer 10, and the second electrode 52 is in contact with the second semiconductor layer 30.

[0057] The solar cell provided in this embodiment has a first electrode 51 formed on the side of the first semiconductor layer 20 facing away from the contact area 101, and a second electrode 52 formed on the side of the second semiconductor layer 30 facing away from the front of the substrate layer 10. This allows for the extraction of the front and back electrodes while ensuring passivation performance.

[0058] In some alternative embodiments, the solar cell further includes a second passivation layer located on the surface of the first passivation layer 40 facing away from the substrate layer 10; the second passivation layer is located on both the front and back sides of the substrate layer 10. A first electrode 51 is located on the surface of the second passivation layer corresponding to the contact area 101, the first electrode 51 penetrates the first passivation layer 40 and the second passivation layer, and contacts the side of the first semiconductor layer 20 facing away from the contact area 101.

[0059] In the solar cell provided in this embodiment, the first passivation layer 40 and the second passivation layer are stacked on both the front and back sides of the substrate layer 10, which can provide passivation and anti-reflection protection for both the front and back sides; the first electrode 51 penetrates the first passivation layer 40 and the second passivation layer and contacts the first semiconductor layer 20, which can achieve the output of the back electrode while ensuring passivation performance.

[0060] In some optional embodiments, a tunneling oxide layer 21 is further disposed between the contact area 101 of the substrate layer 10 and the first semiconductor layer 20, and the tunneling oxide layer 21 and the first semiconductor layer 20 form a passivation contact structure.

[0061] In specific implementation, the material of the tunneling oxide layer 21 includes silicon oxide, and the material of the first semiconductor layer 20 includes doped polycrystalline silicon.

[0062] In the solar cell provided in this embodiment, the tunneling oxide layer 21 of the contact area 101 and the first semiconductor layer 20 form a passivation contact structure, which reduces the surface recombination of the substrate layer 10 and the metal contact recombination of the first electrode 51 in the contact area 101, thereby improving the passivation effect of the back contact area 101 of the cell.

[0063] In some alternative embodiments, the substrate 10 is an N-type silicon substrate, the first semiconductor layer 20 is an N-type semiconductor layer, and the second semiconductor layer 30 is a P-type semiconductor layer.

[0064] In specific implementation, the first semiconductor layer 20 is an N-type doped polysilicon layer, and the second semiconductor layer 30 is a P-type doped silicon layer.

[0065] In the solar cell provided in this embodiment, the first semiconductor layer 20 is an N-type semiconductor layer. By providing an N-type semiconductor layer and a tunneling oxide layer 21 in the contact area 101 on the back side of the substrate layer 10, an N-type polyfinger structure can be formed. This reduces the parasitic absorption of light by the tunneling oxide layer 21 and the N-type doped polycrystalline silicon layer without affecting the passivation formation of the contact area 101, thereby improving the passivation performance of the passivation contact structure.

[0066] This disclosure provides a method for fabricating a solar cell, which will be discussed below. Figures 2 to 11 Please provide a detailed explanation.

[0067] like Figure 2 As shown, this embodiment provides a method for preparing a solar cell, which includes, but is not limited to, steps S101 to S104.

[0068] Step S101: Provide a substrate layer 10, the substrate layer 10 including a front side and a back side disposed opposite to each other; the back side includes contact areas 101 and spacer areas 102 alternately disposed along a first direction, such as... Figure 4 As shown.

[0069] Step S102: A first semiconductor layer 20 is formed on the back side of the substrate 10, such as... Figure 5 As shown.

[0070] Step S103: The spacer region 102 is wet-cleaned using a target alkaline solution containing anti-plating additives to remove the first semiconductor layer 20 of the spacer region 102, retaining the first semiconductor layer 20 of the contact region 101, and forming a composite tower base structure 60 on the surface of the substrate layer 10 of the spacer region 102; the composite tower base structure 60 includes a plurality of first tower bases 61 and a plurality of second tower bases 62; the size of the second tower bases 62 is smaller than the size of the first tower bases 61, such as... Figure 9A and Figure 9B As shown.

[0071] Step S104: A first passivation layer 40 is formed on the surface of the composite tower base structure 60 in the interval region 102, such as... Figure 10 As shown.

[0072] The solar cell fabrication method provided in this embodiment, in the step of wet cleaning the spacer region 102 using a target alkaline solution containing a de-coating additive, can utilize the de-coating additive in the target alkaline solution to adjust the longitudinal corrosion rate on the surface of the substrate layer 10 of the spacer region 102. This allows for the simultaneous wet cleaning of the spacer region 102 and removal of the first semiconductor layer 20, while simultaneously etching a composite base structure 60 containing a first base 61 and a second base 62 onto the surface of the substrate layer 10 of the spacer region 102. This achieves a high-roughness and uniformly distributed surface of the spacer region 102 without additional processing, providing more suspension sites for the subsequent hydrogen passivation of the first passivation layer 40. This increases the thickness of the first passivation layer 40 that can be stably deposited on the surface of the spacer region 102, enhances the passivation effect of the first passivation layer 40 formed in the spacer region 102, improves the passivation effect of the solar cell, and ultimately improves the electrical performance and photoelectric conversion efficiency of the solar cell.

[0073] In some alternative implementations, a first electrode 51 is formed on the side of the first semiconductor layer 20 opposite to the contact region 101.

[0074] In some optional embodiments, the concentration of the de-coating additive in the target alkaline solution is 0.2% to 0.3%, and in the composite tower base structure 60 formed, the size of the first tower base 61 is 15 μm to 25 μm, the size of the second tower base 62 is 4 μm to 8 μm, and the thickness of the first passivation layer 40 is 4 nm to 6 nm.

[0075] In practice, the concentration of the de-coating additive is 0.2% to 0.3%, such as 0.2%, 0.23%, 0.25%, 0.28%, or 0.3%. If the concentration of the de-coating additive is too low, the surface roughness of the spacer region 102 will be too low, thereby reducing the thickness of the first passivation layer 40 that can be stably deposited; if the concentration of the de-coating additive is too high, it will damage other film layers of the battery and reduce the reliability of the battery.

[0076] In some optional embodiments, the target alkaline solution has an alkaline concentration of 0.1% to 0.3%, the wet cleaning temperature is 55°C to 75°C, and the cleaning time is 300s to 400s.

[0077] The solar cell fabrication method provided in this embodiment, when the concentration of the de-coating additive in the target alkaline solution is 0.2%~0.3%, and in combination with the mass concentration of the alkali in the target alkaline solution and the temperature and time of wet cleaning, can stably form a first base 61 and a second base 62 with sizes of 15μm~25μm and 4μm~8μm respectively on the surface of the spacer region 102 of the substrate layer 10. This can stably deposit a first passivation layer 40 with a thickness of 4nm~6nm and high film quality, thereby increasing the thickness of the first passivation layer 40 on the surface of the spacer region 102 and improving the passivation effect of the first passivation layer 40.

[0078] In some alternative embodiments, during the step of forming the first semiconductor layer 20 on the back side of the substrate 10, a small amount of the first semiconductor layer 20 is also formed on the front and side sides of the substrate 10 by wire bonding. Therefore, during the wet cleaning of the spacer region 102 using a target alkaline solution containing a wire bonding removal additive, the first semiconductor layers 20 formed on the front and side sides of the substrate 10 are also removed.

[0079] In some alternative implementations, the components of the de-coating additive include surfactants and wetting agents.

[0080] In practice, while controlling the concentration of the de-coating additive to 0.2%~0.3%, the ratio of surfactant and wetting agent can be fine-tuned, thereby adjusting the ratio of the first tower base 61 and the second tower base 62 in the composite tower base structure 60.

[0081] In some optional embodiments, a first semiconductor layer 20 is formed on the back side of the substrate layer 10, including: sequentially forming a tunneling oxide layer 21, the first semiconductor layer 20, and a first surface layer 22 on the back side of the substrate layer 10, such as... Figure 5 As shown.

[0082] In some alternative embodiments, prior to wet cleaning of the spacer region 102 with a target alkaline solution containing anti-plating additives, the method further includes: laser patterning the first surface layer 22 to vaporize or loosen the first surface layer 22 corresponding to the spacer region 102, such as... Figure 6 and Figure 7 As shown; In some alternative embodiments, in the step of wet cleaning the spacer region 102 with a target alkaline solution containing a de-plating additive, the first semiconductor layer 20 and the tunneling oxide layer 21 of the spacer region 102 are removed, while the first surface layer 22, the tunneling oxide layer 21, and the first semiconductor layer 20 of the contact region 101 are retained, and a composite tower base structure 60 is formed on the surface of the base layer 10 of the spacer region 102, such as... Figure 8 As shown.

[0083] The solar cell fabrication method provided in this embodiment pre-vaporizes or loosens the first surface layer 22 corresponding to the spacer region 102 through laser patterning. This allows for selective removal of the tunneling oxide layer 21 and the first semiconductor layer 20 of the spacer region 102 during the wet cleaning step, forming a composite tower structure 60 on the surface of the substrate layer 10 of the spacer region 102. The contact region 101 is protected by the first surface layer 22 and thus retained, achieving a patterned separation between the contact region 101 and the spacer region 102. Furthermore, the tunneling oxide layer 21 and the first semiconductor layer 20 retained in the contact region 101 ultimately form a passivated contact structure, reducing surface recombination and metal-to-metal contact recombination, thereby improving the performance of the solar cell.

[0084] In some alternative embodiments, before forming the first semiconductor layer 20 on the back side of the substrate 10, the method further includes forming a second semiconductor layer 30 on the front side of the substrate 10, such as... Figure 4 As shown.

[0085] In practice, the front side of the base layer 10 is velvety.

[0086] In some optional embodiments, forming a second semiconductor layer 30 on the front side of the substrate 10 includes: texturing the substrate 10 on both sides; the substrate 10 is a silicon wafer; performing a second diffusion process on the textured substrate 10 to form a second semiconductor layer 30 and a second surface layer; removing the second surface layer on the back side of the substrate 10, and performing an alkaline washing and polishing process on the back side of the substrate 10 to remove the second semiconductor layer 30 on the back side of the substrate 10; retaining the second semiconductor layer 30 and the second surface layer on the front side of the substrate 10.

[0087] The method for fabricating a solar cell provided in this embodiment first involves double-sided texturing and forming a second semiconductor layer 30 and a second surface layer on both sides. Then, an alkaline washing and polishing process is used to remove the second semiconductor layer 30 and the second surface layer on the back side. This process can form a textured surface and a second semiconductor layer 30 on the front side of the substrate layer 10, improving the light trapping performance and light utilization efficiency of the cell. Furthermore, during the alkaline washing and polishing process to remove the second semiconductor layer 30 and the second surface layer on the back side, a polished surface can be formed on the back side of the substrate layer 10, improving the bonding force between the back side of the substrate layer 10 and the subsequently formed tunneling oxide layer 21 and the first semiconductor layer 20, as well as the film quality of the tunneling oxide layer 21 and the first semiconductor layer 20. This reduces the difficulty of the process, improves the passivation effect and contact performance of the passivation contact structure, and thus improves the performance of the solar cell.

[0088] In some alternative embodiments, after alkaline washing and polishing, a third tower base is formed on the back side of the substrate 10. The size of the third tower base is smaller than that of the first tower base 61 and larger than that of the second tower base 62. The size of the third tower base is 8~12μm.

[0089] The solar cell fabrication method provided in this embodiment removes the second semiconductor layer 30 on the back side during alkaline washing and polishing, while simultaneously forming a third base with a size between the first base 61 and the second base 62. This facilitates the subsequent formation of the tunneling oxide layer 21 and the first semiconductor layer 20 on the back side of the substrate layer 10, improves the film quality of the tunneling oxide layer 21 and the first semiconductor layer 20, reduces process difficulty, enhances the passivation effect and contact performance of the passivation contact structure, and thus improves the performance of the solar cell.

[0090] In some optional embodiments, a tunneling oxide layer 21, a first semiconductor layer 20, and a first surface layer 22 are sequentially formed on the back side of the substrate layer 10, including: forming an initial tunneling oxide layer and an intrinsic amorphous silicon layer on the back side of the substrate layer 10 after alkaline washing and polishing; performing a first diffusion process on the initial tunneling oxide layer and the intrinsic amorphous silicon layer to obtain the tunneling oxide layer 21 based on the initial tunneling oxide layer, and to obtain the first semiconductor layer 20 and the first surface layer 22 based on the intrinsic amorphous silicon layer, respectively, wherein the first surface layer 22 is located on the surface of the first semiconductor layer 20 facing away from the tunneling oxide layer 21; the material of the first semiconductor layer 20 includes first doped polycrystalline silicon.

[0091] The solar cell fabrication method provided in this embodiment first deposits an initial tunneling oxide layer and an intrinsic amorphous silicon layer, and then forms a tunneling oxide layer 21, a first semiconductor layer 20 and a first surface layer 22 on the outside through a first diffusion process, thereby realizing the fabrication of a back passivation contact structure and a surface protective layer. At the same time, it can improve the passivation effect and contact performance of the passivation contact structure, thereby improving the performance of the solar cell.

[0092] In some alternative implementations, the first diffusion process is a phosphorus diffusion process; the first semiconductor layer 20 is an N-type semiconductor layer, and the first surface layer 22 is a phosphosilicate glass layer.

[0093] In some alternative embodiments, the second diffusion process is a boron diffusion process; the second semiconductor layer 30 is a P-type semiconductor layer, and the second surface layer is a borosilicate glass layer.

[0094] The solar cell fabrication method provided in this embodiment forms an N-type semiconductor layer and a phosphosilicate glass layer on the back side of the substrate 10 through a phosphorus diffusion process, and forms a P-type semiconductor layer and a borosilicate glass layer on the front side of the substrate 10 through a boron diffusion process, resulting in a solar cell structure with opposite conductivity types on the front and back sides. At the same time, by patterning the N-type semiconductor layer and tunneling oxide layer 21 on the back side to form an N-type polyfinger structure, the parasitic absorption of light by the tunneling oxide layer 21 and the N-type doped polycrystalline silicon layer can be reduced without affecting the passivation formation of the contact area 101, thereby improving the passivation performance of the passivation contact structure.

[0095] In some optional embodiments, a first passivation layer 40 is formed on the surface of the composite tower base structure 60 in the spacer region 102, including: simultaneously forming the first passivation layer 40 on both the front and back sides of the base layer 10; the first passivation layer 40 covers the surface of the composite tower base structure 60 in the spacer region 102, and also covers the surface of the first semiconductor layer 20 in the contact region 101 facing away from the base layer 10, and the surface of the second semiconductor layer 30 facing away from the base layer 10, such as... Figure 10 As shown.

[0096] In some optional embodiments, the step of forming the first electrode 51 includes: forming the first electrode 51 on the side of the first passivation layer 40 opposite to the first semiconductor layer 20 corresponding to the contact region 101, wherein the first electrode 51 penetrates the first passivation layer 40 and contacts the side of the first semiconductor layer 20 opposite to the contact region 101, such as... Figure 11 As shown.

[0097] In some optional embodiments, the fabrication method further includes forming a second electrode 52 on the surface of the second semiconductor layer 30 on the front side of the substrate layer. The second electrode 52 penetrates the first passivation layer 40 and contacts the side of the second semiconductor layer 30 facing away from the substrate layer, such as... Figure 11 As shown.

[0098] In some alternative embodiments, after forming the first passivation layer 40 on the surface of the composite tower base structure 60 in the spacer region 102, the method further includes forming a second passivation layer on the surface of the first passivation layer 40 facing away from the base layer 10; the second passivation layer is located on both the front and back sides of the base layer 10, and the second passivation layer is shaped to cover the first passivation layer 40.

[0099] In some alternative embodiments, after forming the second passivation layer, the method further includes forming a first electrode 51 on the surface of the second passivation layer corresponding to the contact region 101. The first electrode 51 penetrates the first passivation layer 40 and the second passivation layer and contacts the side of the first semiconductor layer 20 opposite to the contact region 101.

[0100] The solar cell fabrication method provided in this embodiment involves forming a first passivation layer 40 on both the front and back sides of the substrate layer 10. This provides passivation and anti-reflection protection for the composite tower base structure 60 of the spacer region 102, the first semiconductor layer 20 of the contact region 101, and the second semiconductor layer 30 on the front side. The second passivation layer is stacked outside the first passivation layer 40 to further enhance the passivation and anti-reflection effects on both the front and back sides of the cell.

[0101] like Figure 3 As shown in the diagram, this embodiment also provides a detailed flowchart of a method for fabricating a solar cell, which includes, but is not limited to, steps S201 to S209. The solar cell is a TOPCon cell using the N-polyfinger process.

[0102] Step S201: Provide a substrate layer 10, the substrate layer 10 including a front side and a back side disposed opposite to each other; the back side includes contact areas 101 and spacer areas 102 alternately disposed along a first direction, such as... Figure 4 As shown.

[0103] In specific implementation, the back surface of the substrate 10 includes a plurality of contact areas 101 and a plurality of spacer areas 102 alternately spaced along a first direction; both the contact areas 101 and the spacer areas 102 extend along a second direction, such as... Figure 4 As shown.

[0104] Step S202: A second semiconductor layer 30 is formed on the front side of the substrate 10, such as... Figure 4 As shown.

[0105] Optionally, step S202 specifically includes: S202-1 to S202-3.

[0106] S202-1. Double-sided texturing of substrate 10; substrate 10 is a silicon wafer. Specifically, the silicon wafer is double-sided texturized to remove metallic impurities and organic contaminants from its surface. The double-sided texturing process takes 440±20 seconds, the reaction temperature is 80±10℃, and the texturing solution includes a target alkaline solution with a concentration of 0.5%±0.3% and texturing additives with a concentration of 0.1%±0.08%.

[0107] S202-2. A second diffusion process is performed on the double-textured substrate layer 10 to form a second semiconductor layer 30 and a second surface layer. Specifically, the second diffusion process is a boron diffusion process; the second semiconductor layer 30 is a P-type semiconductor layer, and the second surface layer is a borosilicate glass layer. In some examples, the deposition temperature is 450±20℃, the deposition time is 450±30s, the boron source flow rate is 240±20sccm, the oxygen flow rate is 620±20sccm, the nitrogen flow rate is 2000±20sccm, the advance temperature is 1000±20℃, the time is 1150±20s, and the oxidation temperature is 1050±20℃, the time is 3750±20s.

[0108] S202-3, remove the second surface layer on the back side of the substrate 10, and perform alkaline washing and polishing on the back side of the substrate 10 to remove the second semiconductor layer 30 on the back side of the substrate 10; retain the second semiconductor layer 30 and the second surface layer on the front side of the substrate 10, as shown in the image. Figure 4As shown. In specific implementation, firstly, a 10±3% hydrofluoric acid (HF) solution is used to perform a chain cleaning of the back side of the silicon wafer for 80±20 seconds to remove the second surface layer on the back side. Secondly, an alkaline washing and polishing process is performed on the back side of the substrate layer 10 to remove the second semiconductor layer 30 on the back side of the substrate layer 10, forming a polished surface on the back side of the substrate layer 10 and improving the back side reflectivity. The alkaline washing and polishing process takes 200±50 seconds, the reaction temperature is 60±10℃, and the solution used in the alkaline washing and polishing process includes a 0.2%±0.1% alkaline solution and a 0.1%±0.08% alkaline polishing additive. Finally, after the alkaline washing and polishing process, a third base is formed on the back side of the substrate layer 10. The size of the third base is smaller than that of the first base 61 and larger than that of the second base 62; the size of the third base is 8~12μm.

[0109] In step S203, a tunneling oxide layer 21, a first semiconductor layer 20, and a first surface layer 22 are sequentially formed on the back side of the substrate layer 10, such as... Figure 5 As shown.

[0110] Optionally, step S203 specifically includes: S203-1 to S203-2.

[0111] S203-1. An initial tunneling oxide layer and an intrinsic amorphous silicon layer are formed on the back side of the substrate layer 10 after alkaline washing and polishing.

[0112] In practice, the initial tunneling oxide layer deposition temperature is 600±50℃, the oxygenation time is 350±100s, the oxygenation time is 550±200s, the intrinsic amorphous silicon layer deposition temperature is 600±50℃, and the reaction time is 1800±200s.

[0113] S203-2, a first diffusion process is performed on the initial tunneling oxide layer and the intrinsic amorphous silicon layer to obtain a tunneling oxide layer 21 based on the initial tunneling oxide layer, and to form a first semiconductor layer 20 and a first surface layer 22 based on the intrinsic amorphous silicon layer, respectively. The first surface layer 22 is located on the surface of the first semiconductor layer 20 on the side opposite to the tunneling oxide layer 21. The material of the first semiconductor layer 20 includes first doped polycrystalline silicon.

[0114] In specific implementation, the first diffusion process is a phosphorus diffusion process; the first semiconductor layer 20 is an N-type semiconductor layer, and the first surface layer 22 is a phosphorus silicon glass layer. The deposition temperature of the phosphorus diffusion process is 790±200℃, the time is 800±200s, the phosphorus source flow rate is 1400±200sccm, the oxygen flow rate is 50±20sccm, the propagation temperature is 830±50℃, the time is 960±100s, and the oxidation temperature is 880℃, the time is 900±100s.

[0115] Step S204: Perform laser patterning processing on the first surface layer 22 to vaporize or loosen the first surface layer 22 corresponding to the interval region 102, such as... Figure 6 and Figure 7 As shown.

[0116] In practice, a green laser is used to pattern the first surface layer 22 within the spacer region 102 on the back of the silicon wafer, vaporizing or loosening it. The laser spot width used is 150±50μm. A large rectangular light spot of 150±50μm is overlapped by 50±40% in both the X and Y axes.

[0117] In step S205, the spacer region 102 is wet-cleaned using a target alkaline solution containing anti-plating additives to remove the first semiconductor layer 20 and tunneling oxide layer 21 from the spacer region 102, while retaining the first surface layer 22, tunneling oxide layer 21, and first semiconductor layer 20 of the contact region 101. A composite tower base structure 60 is then formed on the surface of the base layer 10 of the spacer region 102. The composite tower base structure 60 includes a plurality of first tower bases 61 and a plurality of second tower bases 62; the size of the second tower bases 62 is smaller than the size of the first tower bases 61.

[0118] In specific implementation, the concentration of the plating additive in the target alkaline solution is 0.2%~0.3%, and the mass concentration of the alkali is 0.1%~0.3%. The wet cleaning temperature is 55℃~75℃, and the cleaning time is 300s~400s. In the final composite tower base structure 60, the size of the first tower base 61 is 15μm~25μm, and the size of the second tower base 62 is 4μm~8μm.

[0119] Step S206: Remove the first surface layer 22 of the contact area 101 and remove the second surface layer on the front side of the base layer 10, as shown below. Figure 9A and Figure 9B As shown.

[0120] In a specific implementation, after removing the first surface layer 22, a composite tower base structure 60 is formed on the surface of the exposed base layer 10 in the spacer region 102. The first tower base 61 in the composite tower base structure 60 has a size of 15μm~25μm, and the second tower base 62 has a size of 4μm~8μm.

[0121] In step S207, a first passivation layer 40 is simultaneously formed on both the front and back sides of the substrate layer 10. The first passivation layer 40 covers the surface of the composite tower base structure 60 of the spacer region 102, and also covers the surface of the first semiconductor layer 20 of the contact region 101 facing away from the substrate layer 10, and the surface of the second semiconductor layer 30 facing away from the substrate layer 10, as shown below. Figure 10 As shown.

[0122] In specific implementation, the material of the first passivation layer 40 includes aluminum oxide. Alumina is deposited on both sides as the first passivation layer 40 to form a good passivation layer. The thickness of the first passivation layer 40 in the spacer region 102 is 4 nm to 6 nm.

[0123] In step S208, a second passivation layer (not shown in the figure) is formed on the surface of the first passivation layer 40 facing away from the base layer 10; the second passivation layer is located on both the front and back sides of the base layer 10, and the second passivation layer covers the first passivation layer 40 in the same shape.

[0124] In a specific implementation, a second passivation layer is formed on both sides, with a thickness of 80±20 nm. The material of the second passivation layer includes silicon nitride. Optionally, the second passivation layer can be a silicon nitride composite layer.

[0125] In step S209, a first electrode 51 is formed on the surface of the second passivation layer corresponding to the contact region 101, and a second electrode 52 is formed on the surface of the second passivation layer corresponding to the second semiconductor layer 30. The first electrode 51 penetrates the first passivation layer 40 and the second passivation layer, and contacts the side of the first semiconductor layer 20 opposite to the contact region 101. The second electrode 52 penetrates the first passivation layer 40 and the second passivation layer, and contacts the side of the second semiconductor layer 30 opposite to the substrate layer 10. Figure 11 As shown.

[0126] In a specific implementation, a second electrode 52 is formed on the front side of the substrate layer 10 using silver-aluminum paste as the raw material, and a first electrode 51 is formed on the contact area 101 on the back side using silver paste as the raw material. Then, with the help of laser-assisted sintering technology, a reliable connection is achieved between the first electrode 51 and the first semiconductor layer 20, and a reliable connection is achieved between the second electrode 52 and the second semiconductor layer 30.

[0127] To verify the effectiveness of the solar cell fabrication method provided in this embodiment, this disclosure provides solar cell fabrication methods of Example 1, Comparative Example 1, and Comparative Example 2 for comparison.

[0128] Example 1 is based on, for example Figure 2 The preparation method shown is used. In step S205, the concentration of the de-coating additive in the target alkaline solution is 0.25%. In the final composite tower base structure 60, the size of the first tower base 61 is 15μm~25μm, and the size of the second tower base 62 is 4μm~8μm. After step S207, the thickness of the first passivation layer 40 (material including alumina) formed in the spacer region 102 is 4.2nm.

[0129] The difference between Comparative Example 1 and Example 1 is that, in step S205, the concentration of the de-coating additive in the target alkaline solution is 0.1%, and the final surface of the spacer region 102 in Comparative Example 1 only includes a relatively large (15μm~25μm) tower base. The thickness of the first passivation layer 40 (material including alumina) formed in the spacer region 102 after step S207 is 3.8nm.

[0130] The difference between Comparative Example 2 and Example 1 is that, in step S205, the concentration of the de-coating additive in the target alkaline solution is 0.1%, and the final spacer surface formed in Comparative Example 2 only includes a relatively large (15μm~25μm) tower base. In step S207, the thickness of the first passivation layer of alumina is directly increased to 4.2nm by increasing the process time, etc.

[0131] The electrical performance of the solar cells formed in Example 1, Comparative Example 1, and Comparative Example 2 was tested respectively, and the specific data are shown in the table below.

[0132]

[0133] As can be seen, although Comparative Example 2 directly increased the thickness of the alumina compared to Comparative Example 1, the film quality was poor, resulting in a decrease in all aspects of the battery's performance. The solar cell formed in Example 1, compared to Comparative Example 1, showed a 0.06%+ improvement in electrical performance, thus increasing the photoelectric conversion efficiency of the solar cell. This demonstrates that the composite tower base structure provided in this embodiment can bring a more than 0.06% improvement in electrical performance in the N-type polyfinger process of TOPCon cells.

[0134] Therefore, this application increases the roughness and specific surface area of ​​the spacer region by forming a composite tower base structure, thereby increasing the thickness of the first passivation layer that can be stably deposited on the surface of the spacer region, thus improving the passivation performance of the first passivation layer in the spacer region, thereby improving the electrical performance of the cell and increasing the photoelectric conversion efficiency of the solar cell.

[0135] In the description of this specification, the references to terms such as "this embodiment," "an embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0136] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0137] The above description is merely a preferred embodiment and the technical principles employed in this disclosure. Those skilled in the art will understand that this disclosure is not limited to the specific embodiments described above, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of this disclosure. Therefore, although this disclosure has been described in detail through the above embodiments, it is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of this disclosure, and the scope of protection of this disclosure is determined by the scope of the appended claims.

Claims

1. A solar cell, characterized in that, include: The base layer includes a front side and a back side disposed opposite to each other; the back side includes contact areas and spacing areas disposed alternately at intervals. The first semiconductor layer is located in the contact area on the back side of the substrate layer; A composite tower base structure is located in the spacer region on the back side of the base layer; the composite tower base structure includes a plurality of first tower bases and a plurality of second tower bases; the size of the second tower base is smaller than the size of the first tower base; The first passivation layer is located on the surface of the composite tower base structure in the interval region.

2. The solar cell according to claim 1, characterized in that, The second tower base is located on the surface of the first tower base, and / or the second tower base is located between two adjacent first tower bases; The dimensions of the first tower base are 15μm to 25μm, and the dimensions of the second tower base are 4μm to 8μm; The material of the first passivation layer includes aluminum oxide; the thickness of the first passivation layer is 4nm~6nm.

3. The solar cell according to claim 1, characterized in that, The solar cell further includes a second semiconductor layer located on the front side of the substrate; the first semiconductor layer and the second semiconductor layer have opposite conductivity types; the first passivation layer also covers the surface of the first semiconductor layer away from the substrate layer and the surface of the second semiconductor layer away from the substrate layer in the contact area; The solar cell also includes: The second passivation layer is located on the surface of the first passivation layer facing away from the substrate layer; the second passivation layer is located on both the front and back sides of the substrate layer. The first electrode is located on the surface of the second passivation layer corresponding to the contact area. The first electrode penetrates the first passivation layer and the second passivation layer and contacts the side of the first semiconductor layer opposite to the contact area.

4. The solar cell according to claim 3, characterized in that, A tunneling oxide layer is further disposed between the contact area of ​​the substrate layer and the first semiconductor layer, and the tunneling oxide layer and the first semiconductor layer form a passivation contact structure; The substrate is an N-type silicon substrate, the first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer.

5. A method for preparing a solar cell, characterized in that, include: A substrate layer is provided, the substrate layer including a front side and a back side disposed opposite to each other; the back side includes contact areas and spacing areas alternately disposed along a first direction; A first semiconductor layer is formed on the back side of the substrate layer; The spacer region is wet-cleaned using a target alkaline solution containing anti-plating additives to remove the first semiconductor layer in the spacer region, while retaining the first semiconductor layer in the contact region, and a composite tower base structure is formed on the surface of the substrate layer in the spacer region; the composite tower base structure includes a plurality of first tower bases and a plurality of second tower bases; the size of the second tower bases is smaller than the size of the first tower bases. A first passivation layer is formed on the surface of the composite tower base structure in the interval region.

6. The method for preparing a solar cell according to claim 5, characterized in that, In the target alkaline solution, the concentration of the de-coating additive is 0.2%~0.3%, the size of the first tower base is 15μm~25μm, the size of the second tower base is 4μm~8μm, and the thickness of the first passivation layer is 4nm~6nm.

7. The method for preparing a solar cell according to claim 5, characterized in that, The formation of a first semiconductor layer on the back side of the substrate includes: A tunneling oxide layer, a first semiconductor layer, and a first surface layer are sequentially formed on the back side of the substrate layer; Before performing wet cleaning of the spacer area using a target alkaline solution containing anti-plating additives, the method further includes: performing laser patterning on the first surface layer to vaporize or loosen the first surface layer corresponding to the spacer area. In the step of wet cleaning the spacer region with a target alkaline solution containing anti-plating additives, the first semiconductor layer and the tunneling oxide layer of the spacer region are removed, while the first surface layer, the tunneling oxide layer and the first semiconductor layer of the contact region are retained, and a composite tower base structure is formed on the surface of the base layer of the spacer region.

8. The method for preparing a solar cell according to claim 7, characterized in that, Before forming the first semiconductor layer on the back side of the substrate, the method further includes forming a second semiconductor layer on the front side of the substrate; Forming a second semiconductor layer on the front side of the substrate includes: The substrate layer is textured on both sides; the substrate layer is a silicon wafer. A second diffusion process is performed on the double-textured substrate layer to form a second semiconductor layer and a second surface layer; Remove the second surface layer on the back side of the substrate layer, and perform alkaline washing and polishing on the back side of the substrate layer to remove the second semiconductor layer on the back side of the substrate layer; retain the second semiconductor layer and the second surface layer on the front side of the substrate layer.

9. The method for preparing a solar cell according to claim 8, characterized in that, After the alkaline washing and polishing treatment, a third tower base is formed on the back side of the substrate layer. The size of the third tower base is smaller than that of the first tower base and larger than that of the second tower base. The size of the third tower base is 8nm~12nm.

10. The method for preparing a solar cell according to claim 8, characterized in that, The process of sequentially forming a tunneling oxide layer, a first semiconductor layer, and a first surface layer on the back side of the substrate includes: An initial tunneling oxide layer and an intrinsic amorphous silicon layer are formed on the back side of the substrate after the alkaline washing and polishing treatment; A first diffusion process is performed on the initial tunneling oxide layer and the intrinsic amorphous silicon layer to obtain a tunneling oxide layer based on the initial tunneling oxide layer, and to form a first semiconductor layer and a first surface layer based on the intrinsic amorphous silicon layer, wherein the first surface layer is located on the surface of the first semiconductor layer facing away from the tunneling oxide layer; the material of the first semiconductor layer includes first doped polycrystalline silicon.

11. The method for preparing a solar cell according to claim 10, characterized in that, The first diffusion process is a phosphorus diffusion process; the first semiconductor layer is an N-type semiconductor layer; and the first surface layer is a phosphorus silicon glass layer. The second diffusion process is a boron diffusion process; The second semiconductor layer is a P-type semiconductor layer, and the second surface layer is a borosilicate glass layer.

12. The method for preparing a solar cell according to claim 8, characterized in that, The formation of a first passivation layer on the surface of the composite tower base structure in the interval region includes: A first passivation layer is formed simultaneously on the front and back sides of the substrate layer. The first passivation layer covers the surface of the composite tower base structure in the spacer region, and also covers the surface of the first semiconductor layer away from the substrate layer and the surface of the second semiconductor layer away from the substrate layer in the contact region. After the first passivation layer is formed on the surface of the composite tower base structure in the interval region, the method further includes: A second passivation layer is formed on the surface of the first passivation layer facing away from the substrate layer; the second passivation layer is located on both the front and back sides of the substrate layer; A first electrode is formed on the surface of the second passivation layer corresponding to the contact area. The first electrode penetrates the first passivation layer and the second passivation layer and contacts the side of the first semiconductor layer opposite to the contact area.

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