A solar cell, a method for manufacturing the same, a stacked cell, and a photovoltaic module

Abstract

The application discloses a solar cell and a preparation method thereof, a laminated cell and a photovoltaic module, and belongs to the technical field of photovoltaic cells. The solar cell is characterized in that at least one main surface of a semiconductor substrate is formed with a pyramid base, the main surface is provided with a doped region, and the doped region comprises a metal printing region for printing a metal grid line and a non-printing region without the metal grid line; wherein the pyramid base corresponding to the metal printing region comprises a plurality of stacked composite base structures, and the pyramid base corresponding to the non-printing region is basically composed of uniformly distributed single-layer base structures. The application optimizes the design of the base structure on the surface of the semiconductor substrate, that is, the base structure is designed differently according to different regions on the surface of the semiconductor substrate, so that the adhesion between the grid line electrode and the semiconductor substrate can be effectively improved, and the problems of easy delamination, broken grid and virtual welding of the grid line in the prior art are solved.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cell technology, and more specifically, to a solar cell and its preparation method, a tandem cell, and a photovoltaic module. Background Technology

[0002] Currently, the metallization process of crystalline silicon photovoltaic cells is mainly divided into two categories: screen printing silver paste process and copper electroplating process. It is the core link of cell photoelectric conversion and current output. The adhesion strength between the grid line and the silicon substrate directly determines the service life and power generation reliability of the cell and module.

[0003] In current mass production processes, solar cells typically employ a uniform alkaline textured pyramid structure throughout, resulting in pyramids with uniform size, height, and morphology. This structure only meets basic optical anti-reflection requirements and has significant drawbacks when used for grid line attachment. 1. Conventional velvet pyramids are small and uniform in size, with relatively high surface flatness. However, they lack sufficient physical anchoring points, and the grid slurry can only adhere to the surface layer, failing to form a deep interlock, resulting in relatively weak mechanical adhesion. Second, the line width of the fine grid lines continues to narrow to reduce light shading loss, and the substrate area is further reduced. At the same time, the copper electroplated fine grid lines and HJT low temperature silver paste grid lines have poor adhesion, so they are very prone to local delamination and peeling problems. Third, the surface energy of conventional uniform textured surfaces is limited, and the slurry is not sufficiently wetted and spread, which makes it easy for micro-gaps to exist between the grid lines and the substrate. This not only reduces mechanical adhesion but also increases interfacial contact resistance, affecting the battery conversion efficiency.

[0004] Due to the above defects, during module lamination, transportation and installation, outdoor high and low temperature alternation, and damp heat aging, the grid lines are subjected to tensile stress and thermal expansion and contraction, generating shear stress. The traditional single-textured surface attachment structure cannot offset the stress, and defects such as grid breakage, grid line detachment, and poor soldering delamination are prone to occur frequently, leading to module power decay and microcrack failure. This is a key pain point that restricts the yield of cells and the long-term reliability of modules.

[0005] Existing technologies for improving grid line adhesion are mostly limited to slurry formulation modification, adding transition metal seed layers, and annealing process optimization. However, these methods usually suffer from high costs, complex processes, easy introduction of metal diffusion and recombination defects, and limited improvement effects. Therefore, it is of great significance to effectively improve the adhesion between grid lines and solar cells and avoid the above-mentioned problems. Summary of the Invention The first objective of this invention is to provide a solar cell that, by optimizing the tower structure on the surface of a semiconductor substrate, i.e., by designing a differentiated tower structure according to different regions of the semiconductor substrate surface, can effectively improve the adhesion between the grid line electrodes and the semiconductor substrate, thereby solving the problems of easy delamination, grid breakage, and poor soldering in the prior art. The present invention also provides a method for preparing the above-mentioned solar cell; The present invention also provides a stacked battery, wherein the bottom cell of the stacked battery adopts the above-mentioned solar cell; The present invention also provides a photovoltaic module comprising the above-described solar cells or tandem cells.

[0006] To achieve the above objectives, the technical solution provided by the present invention is as follows: The first aspect of the present invention provides a solar cell, comprising: A semiconductor substrate, wherein at least one main surface of the semiconductor substrate is formed with a pyramid base, the main surface being provided with a doped region, the doped region including a metal printing region for printing metal gate lines and a non-printed region for not printing metal gate lines; The pyramid base corresponding to the metal printing area includes several stacked composite base structures, and each stacked composite base structure is formed by stacking multiple base units along the thickness direction of the main surface of the semiconductor substrate.

[0007] A second aspect of the present invention provides a method for preparing a solar cell, comprising the following steps: Provide semiconductor substrates; The semiconductor substrate is wet-cleaned to obtain a semiconductor substrate with a pyramid base structure formed on its surface. The pyramid base includes several stacked composite base structures. Each stacked composite base structure is formed by stacking multiple base units basically along the thickness direction of the main surface of the semiconductor substrate. The mask printing process is used to cover and block the metal printing area on the surface of the semiconductor substrate corresponding to the metal gate line to be printed, thereby exposing the pyramid base of other areas on the surface. Alkali polishing is performed on the non-mask area on the surface of the semiconductor substrate where the printed metal gate lines are located to form a basically uniformly distributed single-layer tower base structure in the non-mask area, and the mask of the metal printing area is removed, while the stacked composite tower base structure of the metal printing area is retained. Semiconductor-doped functional stacks are formed in the doped regions on the surface of a semiconductor substrate after alkaline polishing. Metal gate lines are formed in the metal printing area on the surface of a semiconductor substrate.

[0008] A third aspect of the present invention provides a stacked battery, including a top battery and a bottom battery, wherein the top battery is located on one side of the bottom battery and is electrically connected to the bottom battery, and the bottom battery employs the solar cell described in the first aspect above.

[0009] A fourth aspect of the present invention provides a photovoltaic module, including the solar cell described in the first aspect above, or the tandem cell described in the third aspect above.

[0010] Compared with the prior art, the technical solution provided by this invention has the following advantages: (1) The present invention provides a solar cell by partitioning and differentiating the pyramid base structure on the surface of the semiconductor substrate, so that the pyramid base corresponding to the metal printing area includes several stacked composite base structures. The effective contact area between the metal grid line and the semiconductor substrate can be effectively increased by utilizing the three-dimensional physical anchoring effect of the three-dimensional base. At the same time, the surface energy is optimized to improve the wetting and spreading effect of the paste. The adhesion of the grid line is greatly improved from the dual dimensions of physical anchoring and interface bonding, solving the problems of easy peeling and falling off of traditional single textured grid lines, grid breakage, cold solder joints, high contact resistance, and poor long-term reliability of the module.

[0011] (2) The present invention performs a partitioned and differentiated reconstruction design of the pyramid base on the surface of the semiconductor substrate. The pyramid base corresponding to the metal grid line printing area includes a stacked composite base structure, while the non-printed area basically retains the conventional pyramid base structure. That is, the area is basically composed of a single-layer base structure, which can effectively balance the optical performance of the battery and the grid line adhesion performance, and also slightly improve the battery fill factor and conversion efficiency. (3) The top layer of the stacked composite tower base structure in this application includes a tower base body with a horizontal cross-sectional profile of a near-circular or polygonal shape. The corners of the polygons are preferably rounded transition angles, which can improve the inherent defects of traditional regular rectangular tower base structures such as stress concentration, excessive corrosion of corners, and carrier recombination concentration, and reduce the interface state density and mechanical stress of the tower base.

[0012] (4) When the solar cell is a back contact cell, a pyramid base is formed on the light-facing surface of the semiconductor substrate. The pyramid base is a single-layer base structure, or a combination of a single-layer base structure and a stacked composite base structure. The pyramid texture size on the surface of the stacked composite base is smaller than the pyramid texture size on the surface of the single-layer base structure, which is beneficial to improving the short-wavelength light absorption rate and making the passivation film deposition quality better.

[0013] (5) The battery manufacturing process of the present invention is compatible with all mainstream battery mass production lines such as TOPCon, HJT and PERC. No new complex equipment is required. The modification cost is low and the mass production capability is strong. It can stably increase the welding tensile strength of the grid line by more than 30%, and significantly reduce the risk of module microcracks, grid breakage and power decay.

[0014] (6) In this invention, the adjacent stacked composite tower base structure is arranged continuously or intermittently. By the differentiated arrangement of the adjacent stacked composite tower base structure in the metal printing area, the electrode warping, local grid detachment, poor soldering, etc. that are prone to occur during the sintering, lamination, and cold and hot cycle testing of the battery cells can be effectively avoided, thereby improving the stability of the electrode interface bonding under long-term outdoor conditions and reducing the risk of series failure after encapsulation. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the tower base structure on the back side of the silicon substrate in Example 1; Figure 2 This is a schematic diagram of the pyramidal textured surface structure on the front side of the silicon substrate in Example 1; Figure 3 This is a schematic diagram of the tower base distribution structure on the back side of the silicon substrate in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a conventional single-layer tower base in Comparative Example 1; Figure 5 This is a schematic diagram of the pyramidal textured surface structure on the front side of the silicon substrate in Example 2.

[0016] Explanation of the labels in the diagram: 1. First metal grid line; 2. Second metal grid line; A1, First doped region; A2, Second doped region; B1, First metal printed region; B2, Second metal printed region; C1, First non-printed region; C2, Second non-printed region. Detailed Implementation

[0017] To further understand the present invention, it will now be described in detail with reference to the accompanying drawings and specific embodiments. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of this disclosure.

[0018] It should be noted that the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate for the embodiments of this application described herein.

[0019] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to be constructed and operated in a specific orientation. Furthermore, some of the above terms may be used to indicate other meanings besides orientation or positional relationship; for example, the term "upper" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application according to the specific circumstances.

[0020] Furthermore, all terms used herein (including technical and scientific terms) shall have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein shall be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid manner.

[0021] Furthermore, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. For example, the terms "comprising," "including," etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0022] It should also be understood that the numerical range of the process parameters involved in this application refers to the protection scope of the process parameter, which includes both any point value within the numerical range and any range of values ​​within the numerical range. For example, the total height of a single stacked composite tower base structure is 2-10μm, which means that the total height of a single stacked composite tower base structure can take specific values ​​such as 2μm, 3μm, 5μm, 7μm, 8.5μm, 10μm, or range values ​​such as 2~4μm, 3~5μm, 6~8μm, 7~10μm.

[0023] This invention provides a solar cell, comprising: A semiconductor substrate, the semiconductor substrate including a first main surface and a second main surface disposed opposite to each other, at least one of the first main surface and the second main surface being formed with a pyramid base, the main surface being provided with a doped region, the doped region including a metal printing region for printing metal gate lines and a non-printed region for not printing metal gate lines. The pyramid base corresponding to the metal printing area includes several stacked composite base structures, while the pyramid base corresponding to the non-printing area is basically composed of a single-layer base structure.

[0024] Addressing the technical challenges and industry pain points of existing solar cells, such as relatively low mechanical adhesion between metal grid lines and semiconductor substrates, leading to defects like grid breakage, grid line detachment, and poor solder joints, and particularly the inability to effectively meet the application requirements of continuously narrowing grid line widths, as well as the high interfacial contact resistance between the metal grid line electrodes and the semiconductor substrate, thus affecting cell conversion efficiency, this invention addresses these issues by reconstructing a differentiated microstructure on the semiconductor substrate surface. Specifically, it involves designing a differentiated surface base morphology in different zones. The pyramid base in the pre-deposited metal grid area (i.e., the metal printing area) is designed to include several stacked composite base structures, while the non-printed area primarily retains a conventional single-layer base structure. This effectively improves the adhesion performance between the metal grid lines and the semiconductor substrate while ensuring the optical performance requirements of the solar cell, thus solving the aforementioned technical problems in the prior art.

[0025] Furthermore, the single stacked composite tower base structure is formed by stacking multiple tower base units substantially along a direction perpendicular to the main surface of the semiconductor substrate (i.e., substantially along the thickness direction of the semiconductor substrate). The interlocking and anchoring effect of this three-dimensional stacked tower base can significantly increase the effective contact area between the metal gate line and the semiconductor substrate, while optimizing the surface energy to improve the slurry wetting and spreading effect. Therefore, the adhesion of the metal gate line is greatly improved from the dual dimensions of physical anchoring and interface bonding.

[0026] Furthermore, the pyramid base corresponding to the metal printing area may also include a conventional single-layer base structure, but preferably it is mainly composed of a stacked composite base structure, that is, in the pyramid base corresponding to the metal printing area, the distribution area of ​​the stacked composite base structure is greater than the distribution area of ​​the single-layer base structure. For example, the distribution area of ​​the stacked composite base structure in the metal printing area is greater than 40%, more preferably greater than 50%, even more preferably greater than 60%, even more preferably greater than 70%, even more preferably greater than 80%, even more preferably greater than 90%, and even more preferably greater than 95%.

[0027] Meanwhile, the statement that the pyramid base corresponding to the non-printed area is primarily composed of a single-layer base structure means that the pyramid base corresponding to the non-printed area can be composed of a single-layer base structure, or it can include a few stacked composite base structures, that is, a combination of single-layer base structures and stacked composite base structures, and the distribution area ratio of the single-layer base structure is greater than the distribution area ratio of the stacked composite base structure. Preferably, the distribution area ratio of the single-layer base structure in the non-printed area is greater than 60%, more preferably greater than 70%, more preferably greater than 80%, more preferably greater than 90%, and even more preferably greater than 95%.

[0028] It should also be emphasized that each layer of the stacked composite tower base structure may contain only one tower base or multiple tower bases. More preferably, the surfaces of multiple tower substrates located on the same layer that are far from the semiconductor substrate are substantially on the same plane.

[0029] Furthermore, the stacking overlap rate between two adjacent tower base units of the stacked composite tower base structure is not less than 70%, more preferably not less than 80%, more preferably not less than 90%, and even more preferably not less than 95%. The higher the stacking overlap rate between two adjacent tower base units, the larger the effective contact area between the metal gate line and the semiconductor substrate, which is beneficial to further improve the adhesion of the gate line.

[0030] More preferably, the tower base units of the same stacked composite tower base structure are arranged approximately concentrically, that is, the geometric centers of each tower base unit coincide or there is a slight horizontal offset, so as to further improve the bonding force between the metal gate line and the semiconductor substrate.

[0031] In some specific embodiments, the stacked composite tower base structure is formed by nesting multiple layers of tower base units, and the overall outline size of each layer of tower base units gradually decreases along the surface direction away from the semiconductor substrate. Here, the overall outline size of the tower base unit refers to the projected area of ​​the top of the tower base unit (the surface away from the semiconductor substrate) on the semiconductor substrate.

[0032] Furthermore, the number of stacked layers in the stacked composite tower base structure can be 2, 3, 4, or 5 layers, preferably more than 3 layers, more preferably not less than 5 layers, and even more preferably not less than 7 layers. The more stacked layers, the better the adhesion of the metal grid lines and the lower the interfacial contact resistance.

[0033] Furthermore, the total height of a single stacked composite tower base structure is 2~10μm, the maximum feature width of its outer contour is 10~70μm, the angle between the sidewall of the stacked composite tower base and the main surface of the semiconductor substrate is 35°~90°, and the height of a single-layer tower base unit is 0.8~6μm.

[0034] The maximum characteristic width of the outer contour of the aforementioned stacked composite tower base structure refers to the maximum lateral contour dimension of the orthographic projection of the entire stacked composite tower base onto the semiconductor substrate plane. For example, if the orthographic projection of the entire stacked composite tower base onto the semiconductor substrate plane is a square or rectangle, it refers to the maximum side length of its projection; if the orthographic projection of the entire stacked composite tower base onto the semiconductor substrate plane is approximately a circle or a polygon, it refers to the maximum circumscribed diameter of its projection.

[0035] Furthermore, the adjacent stacked composite tower base structures can be arranged continuously or intermittently, preferably corresponding to the metal printing area. The arrangement of the adjacent stacked composite tower base structures includes both continuous and intermittent arrangements, that is, some areas are arranged continuously and some areas are arranged intermittently. Through the differentiated design of the arrangement of the adjacent stacked composite tower base structures, electrode warping, local grid detachment, and poor soldering that are prone to occur during cell sintering, lamination, and thermal cycling tests can be effectively avoided, thereby improving the stability of the electrode interface bonding under long-term outdoor conditions and reducing the risk of series failure after encapsulation.

[0036] More preferably, the topmost tower base unit of the partially stacked composite tower base structure includes a tower base body with a horizontal cross-sectional profile that is approximately circular or polygonal, and the edges of the polygon are rounded transition angles. The polygon has 3 to 16 sides, more preferably 6 to 8.

[0037] Existing tower bases are typically regular rectangular structures, meaning their surfaces furthest from the semiconductor substrate are regular rectangles. Due to the sharp angles of these rectangles, even after polishing, there remains a problem of concentrated interface state density, which becomes a recombination center for photogenerated carriers. This easily leads to stress concentration and high recombination loss. This invention designs a portion of the tower base in the topmost tower base unit as a near-circular or polygonal shape, with rounded corners on the polygonal edges. This structurally eliminates right-angled angles, thereby further reducing the interface state density and mechanical stress of the tower base, achieving uniform stress distribution, reducing recombination loss, and improving optical absorption and passivation effects.

[0038] It should also be understood that this application does not specifically limit the material and conductivity type of the semiconductor substrate. The material can be a silicon substrate (monocrystalline silicon or polycrystalline silicon), or a cadmium telluride, copper indium gallium selenide, or perovskite substrate, etc. Optionally, the conductivity type of the semiconductor substrate can be an N-type semiconductor substrate (e.g., an N-type monocrystalline silicon substrate) or a P-type semiconductor substrate (e.g., a P-type monocrystalline silicon substrate). This application also does not have special requirements for the type of solar cell; for example, it can be applied to different types of cells such as TOPCon, HJT, and PERC.

[0039] In some of these embodiments, such as Figure 3 As shown, the doped region includes a first doped region A1 and a second doped region A2, which are alternately arranged along a first direction on the first main surface (i.e., the backlight surface) of the semiconductor substrate. An isolation region A3 is provided between the first doped region A1 and the second doped region A2, meaning that the solar cell is a back-contact solar cell. The first doped region A1 is divided into a first metal printing region B1 for printing the first metal grid line 1 and a first non-printing region C1. The first doped region A2 is divided into a second metal printing region B2 for printing the second metal grid line 2 and a second non-printing region C2.

[0040] Furthermore, the pyramid base corresponding to at least one of the first metal printing area B1 and the second metal printing area B2 includes the above-mentioned stacked composite base structure, preferably both the pyramid bases corresponding to the first metal printing area B1 and the second metal printing area B2 include the above-mentioned stacked composite base structure.

[0041] Furthermore, the pyramid bases corresponding to the first non-printed area C1 and the second non-printed area C2 are mainly composed of conventional single-layer pyramid base structures.

[0042] Furthermore, the first doped region is provided with a first functional layer, which includes a first doped semiconductor layer, and the second doped region is provided with a second functional layer, which includes a second doped semiconductor layer, and the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types.

[0043] The first doped semiconductor layer can be either a P-type doped semiconductor layer or an N-type doped semiconductor layer. The P-type doped semiconductor layer can be a doped silicon-containing film layer, specifically including one or more stacked structures of polycrystalline silicon thin films, intrinsic amorphous silicon thin films, microcrystalline silicon thin films, and silicon-based composite materials (such as SiC, SiO2-doped silicon, etc.). The doping element can be one or more of boron, aluminum, gallium, and indium; for example, boron is the P-type doping element. The N-type doped semiconductor layer can be an N-type doped polycrystalline silicon layer or an N-type doped silicon-containing film layer, and the doping element can be one or more of phosphorus, arsenic, antimony, and bismuth; for example, phosphorus is the N-type doping element.

[0044] Optionally, a dielectric layer (corresponding to the first dielectric layer and the second dielectric layer, respectively) is provided between at least one of the first doped semiconductor layer and the semiconductor substrate. The dielectric layer and the first or second doped semiconductor layer together form a passivation contact structure, thereby effectively reducing carrier recombination and improving the performance of the back-contact solar cell. The dielectric layer may include at least one of various dielectric materials, such as silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. For example, both the first and second dielectric layers are silicon oxide layers containing silicon oxide.

[0045] Optionally, both the first doped semiconductor layer and the second doped semiconductor layer have a passivation layer and / or an antireflection layer on the side facing away from the semiconductor substrate. The passivation layer can passivate the defect structure on the back surface, further reducing carrier recombination and improving the photoelectric conversion efficiency of the solar cell; while the antireflection layer can reduce the reflection of incident light, which is beneficial to further improve the light utilization rate of the solar cell.

[0046] Furthermore, a pyramid base is also formed on the second main surface (i.e., the light-facing surface) of the semiconductor substrate, which is disposed opposite to the first main surface, and a pyramid textured surface is formed on the surface of the pyramid base away from the semiconductor substrate.

[0047] As one alternative, the pyramid base of the second main surface of the semiconductor substrate is a single-layer pyramid base structure, and the surface of the single-layer pyramid base structure is formed with a pyramid velvet structure.

[0048] As an alternative, the pyramid base of the second main surface of the semiconductor substrate includes the above-mentioned stacked composite base structure, or includes both the above-mentioned stacked composite base structure and the conventional single-layer base structure, wherein the pyramid textured surface dimensions (width and height dimensions) of the single-layer base structure surface are larger than the pyramid textured surface dimensions of the stacked composite base structure surface.

[0049] Furthermore, the pyramid width of the single-layer tower base structure surface is 1.8~2.5μm, and the pyramid height is 1.6~2.2μm; the pyramid width of the stacked composite tower base structure surface is 1~1.5μm, and the pyramid height is 0.3~1μm.

[0050] In addition, according to other embodiments of the present invention, the doped region includes a first doped region located on the first main surface of the semiconductor substrate and a second doped region located on the second main surface of the semiconductor substrate, that is, the solar cell is a bifacial cell.

[0051] Furthermore, in this embodiment, the tower base structure of the semiconductor substrate metal printing area corresponding to the first doped region and / or the second doped region includes the stacked composite tower base structure described above.

[0052] This invention also provides a method for preparing a solar cell, comprising the following steps: Provide semiconductor substrates; The semiconductor substrate is wet-cleaned to obtain a semiconductor substrate with a pyramid base structure formed on its surface. The pyramid base includes several stacked composite base structures. Each stacked composite base structure is formed by stacking multiple base units basically along the thickness direction of the main surface of the semiconductor substrate. The mask printing process is used to cover and block the metal printing area on the surface of the semiconductor substrate corresponding to the metal gate line to be printed, thereby exposing the pyramid base of other areas on the surface. Alkali polishing is performed on the non-mask area on the surface of the semiconductor substrate where the printed metal gate lines are located to form a basically uniformly distributed single-layer tower base structure in the non-mask area, and the mask of the metal printing area is removed, while the stacked composite tower base structure of the metal printing area is retained. A doped semiconductor layer is formed in the doped region on the surface of a semiconductor substrate after alkaline polishing. Metal gate lines are formed in the metal printing area on the surface of a semiconductor substrate.

[0053] Further, the wet cleaning of the semiconductor substrate to obtain a semiconductor substrate with a pyramidal base structure formed on its surface specifically includes: First, the semiconductor substrate is acid-washed with an acid polishing solution to remove the cutting damage layer and surface dirt on the tower base surface; Then, an alkaline polishing solution is used for polishing to obtain a semiconductor substrate with a pyramidal base structure on its surface.

[0054] In one implementation, the mass concentration of HF in the acidic polishing solution is 1%~5%, such as 1%, 2%, 3%, 4%, 5%, etc., and the mass concentration of HNO3 is 5%~25%, such as 5%, 10%, 13%, 18%, 25%, etc.; the pickling is carried out at room temperature for 10~200s, such as 10s, 20s, 50s, 100s, 120s, 150s, 200s, etc.

[0055] The alkaline polishing solution contains 5% to 10% NaOH by mass, such as 5%, 6%, 7%, 9%, 10%, etc., and ADD1 (battery alkaline polishing auxiliary additive) by mass concentration of 2% to 6%, such as 2%, 3%, 4%, 5%, 6%, etc., and the alkaline solution temperature is 50 to 80℃, such as 50℃, 60℃, 70℃, 75℃, 80℃, etc., and the polishing time is 30 to 600s, such as 50s, 100s, 200s, 250s, 300s, 400s, 550s, 600s, etc.

[0056] The specific type and composition of the battery alkaline polishing auxiliary additive are not limited, and existing polishing auxiliary additives can be used directly. Optionally, for example, the battery alkaline polishing auxiliary additive includes the following components: 3.0-4.0% surfactant, 7.0-8.0% catalyst, and 1.0-2.0% sodium benzoate. Other chemical components may also be added as needed, with the other chemical components accounting for 7.0-8.0% by mass.

[0057] Furthermore, the doped region includes a first doped region and a second doped region located on the first main surface of the semiconductor substrate and alternately spaced along a first direction, with an isolation region provided between the first doped region and the second doped region; When the metal printing area corresponding to the metal gate line to be printed is covered and blocked on the first main surface using the mask printing process, the second main surface of the semiconductor substrate opposite to the first main surface is simultaneously covered with a mask. The mask on the second main surface is removed by alkaline polishing, while the stacked composite tower base structure of the second main surface of the semiconductor substrate is retained.

[0058] This invention also provides a stacked battery, including a top battery and a bottom battery, wherein the top battery is located on one side of the bottom battery and is electrically connected to the bottom battery, and the bottom battery uses the aforementioned solar cell.

[0059] This invention also provides a photovoltaic module, including the above-described solar cell or the above-described tandem cell.

[0060] Example 1 This embodiment uses a back-contact solar cell as an example for illustration. The fabrication method of the solar cell in this embodiment includes the following steps: S1. Using an N-type single-crystal silicon wafer as a substrate, wet cleaning is performed to obtain a silicon substrate with a stacked composite tower base structure on both the first and second main surfaces (front and back sides). A single stacked composite tower base structure is formed by stacking multiple tower base units basically along the thickness direction of the main surface of the semiconductor substrate, and the number of stacked layers is greater than 3.

[0061] Specifically, in this embodiment, the mixture of HF with a mass concentration of 2%, HNO3 with a mass concentration of 10%, and 460L of H2O is reacted at room temperature for 100s to remove the cutting damage layer and surface dirt on the tower base surface. Then, in a mixed solution of 6% NaOH, 4% ADD1, and 460L H2O, it is polished at 80℃ for 200s to form a silicon substrate with a stacked composite tower structure.

[0062] S2. Using a mask printing process, the gate line printing areas corresponding to the first and second doped regions on the back side of the silicon substrate (i.e., the first main surface or the backlight surface) as well as the entire front side of the silicon substrate (i.e., the second main surface or the light-facing surface) are covered and masked to accurately expose all non-main gate and non-fine gate printing areas on the back side of the silicon substrate. The mask edge accuracy is ±0.1μm, avoiding etching damage to non-processed areas and ensuring that the optical performance of the battery is not affected.

[0063] S3. Control the process by using an alkaline solution to finely polish the non-mask area, thereby forming a tower base structure of basically uniform size in the non-mask area, while removing the printed masks on the front and back of the silicon substrate. Then, the surface is thoroughly cleaned by rinsing with deionized water, ultrasonic cleaning, and hot air drying to ensure the cleanliness of the silicon substrate surface and avoid impurities affecting the bonding performance of the metal gate lines.

[0064] like Figure 1 As shown, the back of the polished silicon substrate forms a partitioned morphology: the gate line printing area forms several stacked composite tower base structures, while the non-printed area mainly consists of conventional single-layer tower base structures.

[0065] S4. First deposition: On the back side of the silicon substrate, a first tunnel oxide layer and a first polysilicon layer are deposited by LPCVD. S5. First diffusion: Diffusion doping of a first type of impurity (boron in this embodiment) is carried out on the back side of the silicon substrate to form an integral first doped semiconductor layer and a first mask layer (specifically a borosilicate glass layer BSG in this embodiment). S6. First laser engraving: Laser patterning process is used to define the pattern of the second doped region (N region) and the gap isolation region on the back side; S7. Wet alkaline etching: The back side of the silicon substrate is etched using an alkaline solution to form a polished surface in the N-region. S8. Second deposition: On the back side of the silicon substrate, a second tunnel oxide layer and a second polycrystalline silicon layer are deposited by LPCVD. S9. Second diffusion: Diffusion doping of a second type of impurity (group V element, phosphorus in this embodiment) on the back side of the silicon substrate to form an integral second doped semiconductor layer and a second mask layer (specifically a silicon phosphide glass layer PSG in this embodiment). S10, Second laser engraving: Laser patterning process is used to define the pattern of the first doped region (P region) and the gap isolation region on the back side; S11, Acid etching and texturing: Chain acid etching is performed on the front side of the silicon substrate to remove the mask and polysilicon layer of the front edge wrapping; then wet polishing is performed on the second laser area; then texturing is performed on the entire front side and the back gap area of ​​the silicon substrate to obtain a differentiated textured surface structure; then acid etching is used to remove the remaining first and second mask layers on the front side. like Figure 2 As shown, after texturing, a finer textured surface is formed on the surface of the stacked composite pyramid structure on the front side of the silicon substrate (the surface away from the silicon substrate). The average width of the pyramids on the surface of the stacked composite pyramid structure is approximately 1.432 μm, the average height of the pyramids is approximately 0.582 μm, and the number of pyramids is approximately 254,882 / mm. 2 The specific surface area of ​​the pyramid is approximately 1.144.

[0066] S12, Preparation of AlO₂ on the front and back sides of the silicon substrate x passivation layer; S13, Preparation of SiO₂ on the front and back sides of the silicon substrate y N x Passivation anti-reflection layer; S14. Prepare first and second doped metal gate electrodes on a tower base structure with differentiated back side.

[0067] Comparative Example 1 The method for preparing the solar cell in this comparative example includes the following steps: S1. Using an N-type single-crystal silicon wafer as a substrate, wet cleaning is performed to obtain a silicon substrate with a conventional uniform single-layer tower base structure on both the first and second main surfaces (front and back sides). Figure 4 (as shown) Specifically, the wet cleaning process in this comparative example is as follows: first, react in a mixed solution of NaOH with a mass concentration of 0.5%, H2O2 with a mass concentration of 5%, and 460L H2O at 70℃ for 300s to remove the cutting damage layer and surface dirt on the tower base surface; Then, in a mixed solution of NaOH concentration of 0.6%, ADD1 content of 0.55%, and 460 L H2O, it was polished at 80 °C for 500 s to form a silicon substrate with a conventional uniform single-layer tower base structure.

[0068] S2, First deposition: On the back side of the silicon substrate, a first tunnel oxide layer and a first polycrystalline silicon layer are deposited by LPCVD. S3. First diffusion: Diffusion doping of a first type of impurity (boron in this embodiment) is carried out on the back side of the silicon substrate to form an integral first doped semiconductor layer and a first mask layer (specifically a borosilicate glass layer BSG in this embodiment). S4. First laser engraving: Laser patterning process is used to define the pattern of the second doped region (N region) and the gap isolation region on the back side; S5. Wet alkaline etching: The back side of the silicon substrate is etched using an alkaline solution to form a polished surface in the N-region. S6. Second deposition: On the back side of the silicon substrate, a second tunnel oxide layer and a second polycrystalline silicon layer are deposited by LPCVD. S7. Second diffusion: Diffusion doping of a second type of impurity (group V element, phosphorus in this embodiment) on the back side of the silicon substrate to form an integral second doped semiconductor layer and a second mask layer (specifically a silicon phosphide glass layer PSG in this embodiment). S8. Second laser engraving: Laser patterning process is used to define the pattern of the first doped region (P region) and the gap isolation region on the back side; S9, Acid etching and texturing: Chain acid etching is performed on the front side of the silicon substrate to remove the mask and polysilicon layer of the front edge wrapping; then wet polishing is performed on the second laser area; then texturing is performed on the entire front side and the back gap area of ​​the silicon substrate, and then acid etching is used to remove the remaining first and second mask layers on the back side. After texturing, a basically uniformly distributed textured surface structure is formed on the front side of the silicon substrate.

[0069] S12: Fabrication of AlO₂ on the front and back sides of a silicon substrate x passivation layer; S13: Fabrication of SiO₂ on the front and back sides of a silicon substrate y N x Passivation anti-reflection layer; S14: Fabricate the first and second doped metal gate electrodes on the back side.

[0070] According to the comparative structure, the present invention, through the optimized design of the tower base structure in the grid line printing area, utilizes the dual effects of three-dimensional physical anchoring and chemical interface to increase the grid line welding tensile force from the traditional 1~2N / cm to more than 3N / cm. After damp heat aging and cold and heat alternation tests, the adhesion attenuation rate is less than 5%. At the same time, the contact area between the tower base and the grid line in the grid line printing area is increased, and the contact resistance can be reduced by 3~8mΩ.

[0071] Example 2 The method for fabricating the solar cell in this embodiment is basically the same as that in Embodiment 1, with the main difference being that: in S2 of this embodiment, the front side of the semiconductor substrate is not covered by a mask. Therefore, after the alkaline polishing treatment in S3, a basically uniform single-layer pyramidal structure is formed on the front side of the semiconductor substrate, thereby forming a basically uniform pyramidal textured surface in the subsequent texturing process in S11. Figure 5 As shown, its pyramid width is 2.003 μm, pyramid height is 1.774 μm, and number of pyramids is 150,654 / mm. 2 The specific surface area of ​​the pyramid is 1.509.

Claims

1. A solar cell, characterized in that, include: A semiconductor substrate, wherein at least one main surface of the semiconductor substrate is formed with a pyramid base, the main surface being provided with a doped region, the doped region including a metal printing region for printing metal gate lines and a non-printed region for not printing metal gate lines; The pyramid base corresponding to the metal printing area includes several stacked composite base structures, and each stacked composite base structure is formed by stacking multiple base units along the thickness direction of the main surface of the semiconductor substrate.

2. The solar cell according to claim 1, characterized in that, In the pyramid base corresponding to the metal printing area, the distribution area of ​​the stacked composite base structure is greater than that of the single-layer base structure.

3. The solar cell according to claim 1, characterized in that, The overlap rate of the stacked area between two adjacent layers of the stacked composite tower base structure shall not be less than 70%, or not less than 80%, or not less than 90%, or not less than 95%.

4. The solar cell according to claim 1, characterized in that, The stacked composite tower base structure is formed by nesting multiple layers of tower base units, and the overall outline size of each layer of tower base units gradually decreases along the surface direction away from the semiconductor substrate.

5. The solar cell according to any one of claims 1-4, characterized in that, The total height of a single stacked composite tower base structure is 2~10μm, and the maximum characteristic width of its outer contour is 10~70μm; the height of a single-layer tower base unit is 0.8~6μm.

6. The solar cell according to any one of claims 1-4, characterized in that, The pyramid base corresponding to the non-printed area is a single-layer base structure; Alternatively, the pyramid base corresponding to the non-printed area is a combination of a single-layer base structure and a stacked composite base structure, and the distribution area of ​​the single-layer base structure is greater than that of the stacked composite base structure.

7. The solar cell according to any one of claims 1-4, characterized in that, The topmost tower base unit of a partially stacked composite tower base structure includes a tower base with a horizontal cross-sectional profile that is roughly circular or polygonal, and the edges of the polygon are rounded transition angles.

8. The solar cell according to any one of claims 1-4, characterized in that, Adjacent stacked composite tower base structures are arranged continuously or intermittently.

9. The solar cell according to any one of claims 1-4, characterized in that, The doping region includes a first doping region and a second doping region located on the first main surface of the semiconductor substrate and alternately spaced along a first direction. An isolation region is provided between the first doping region and the second doping region. The pyramid base corresponding to the metal printing area of ​​at least one of the first doping region and the second doping region includes the stacked composite base structure.

10. The solar cell according to claim 9, characterized in that, The surface of the first doped region is provided with a first doped semiconductor layer, and the surface of the second doped region is provided with a second doped semiconductor layer, wherein the doping type of the first doped semiconductor layer is opposite to that of the second doped semiconductor layer.

11. The solar cell according to claim 9, characterized in that, A pyramid base is also formed on the second main surface of the semiconductor substrate, which is disposed opposite to the first main surface, and a pyramid textured surface is formed on the surface of the pyramid base away from the semiconductor substrate.

12. The solar cell according to claim 10, characterized in that, The pyramid base on the second main surface of the semiconductor substrate is a single-layer pyramid base structure, and the surface of the single-layer pyramid base structure is formed with a pyramid velvet structure.

13. The solar cell according to claim 10, characterized in that, The pyramid base on the second main surface of the semiconductor substrate is a combination of a single-layer base structure and the stacked composite base structure. Both the single-layer base structure and the stacked composite base structure have a pyramid textured surface, and the pyramid textured surface size of the single-layer base structure is larger than that of the stacked composite base structure.

14. A method for preparing a solar cell, characterized in that, Includes the following steps: Provide semiconductor substrates; The semiconductor substrate is wet-cleaned to obtain a semiconductor substrate with a pyramid base structure formed on its surface. The pyramid base includes several stacked composite base structures. Each stacked composite base structure is formed by stacking multiple base units along the thickness direction of the main surface of the semiconductor substrate. The mask printing process is used to cover and block the metal printing area on the surface of the semiconductor substrate corresponding to the metal gate line to be printed, thereby exposing the pyramid base of other areas on the surface. Alkali polishing is performed on the non-mask area on the surface of the semiconductor substrate where the printed metal gate lines are located to form a basically uniformly distributed single-layer tower base structure in the non-mask area, and the mask of the metal printing area is removed, while the stacked composite tower base structure of the metal printing area is retained. Semiconductor-doped functional stacks are formed in the doped regions on the surface of a semiconductor substrate after alkaline polishing. Metal gate lines are formed in the metal printing area on the surface of a semiconductor substrate.

15. The method for preparing a solar cell according to claim 14, characterized in that, The doped region includes a first doped region and a second doped region located on the first main surface of the semiconductor substrate and alternately spaced along a first direction, with an isolation region provided between the first doped region and the second doped region; When the metal printing area corresponding to the metal gate line to be printed is covered and blocked on the first main surface using the mask printing process, the second main surface of the semiconductor substrate opposite to the first main surface is simultaneously covered with a mask. The mask on the second main surface is removed by alkaline polishing, while the stacked composite tower base structure of the second main surface of the semiconductor substrate is retained.

16. The method for preparing a solar cell according to claim 14 or 15, characterized in that, The wet cleaning of the semiconductor substrate to obtain a semiconductor substrate with a pyramidal base structure formed on its surface specifically includes: First, the semiconductor substrate is acid-washed with an acid polishing solution to remove the cutting damage layer and surface dirt on the tower base surface; Then, an alkaline polishing solution is used for polishing to obtain a semiconductor substrate with a pyramidal base structure on its surface.

17. The method for preparing a solar cell according to claim 16, characterized in that, The acidic polishing solution contains HF at a mass concentration of 1% to 5% and HNO3 at a mass concentration of 5% to 25%; the acid pickling is carried out at room temperature for 10 to 200 seconds. The alkaline polishing solution has a NaOH mass concentration of 5%~10%, an alkaline solution temperature of 50~80℃, and a polishing time of 30~600s.

18. A stacked battery, comprising a top battery and a bottom battery, wherein the top battery is located on one side of the bottom battery and is electrically connected to the bottom battery, characterized in that, The bottom battery is a solar cell according to any one of claims 1-13.

19. A photovoltaic module, characterized in that, Includes the solar cell according to any one of claims 1-13, or the tandem cell according to claim 18.

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