Segmented slanted grating patterned sapphire substrate and method of making the same

Abstract

The application discloses a segmented slanting grid patterned sapphire substrate and a preparation method thereof. The substrate comprises a surface sapphire substrate and a segmented slanting grid array on the substrate, the slanting grid is periodically interrupted by gaps along the length direction to form multiple independent slanting grid segments, and the gaps simultaneously serve as etching byproduct discharge channels, penetrating dislocation termination zones and chip cutting channels. The application optimizes etching uniformity, dislocation control and chip cutting process through the segmented structure design, and is suitable for manufacturing of 4-6 inch large-size substrate-based semi-polar or non-polar GaN-based light-emitting diodes, laser diodes and vertical cavity surface emitting lasers.

Description

Technical Field

[0001] This invention relates to the field of third-generation semiconductor material manufacturing technology, specifically to a patterned sapphire substrate and its fabrication method for semi-polar or non-polar gallium nitride (GaN)-based light-emitting diodes (LEDs), lasers (LDs), and vertical-cavity surface-emitting lasers (VCSELs). Background Technology

[0002] Semi-polar GaN (e.g.) (Surface) and non-polar GaN (such as) GaN (semi-polar / non-polar) is widely recognized as the best material system for laser diodes and high-end Micro LEDs due to its low polarization ratio, high wavelength stability, and significant quantum efficiency advantage in the green band. However, when semi-polar / non-polar GaN is epitaxially grown on substrates other than c-plane sapphire, there are two core challenges: (1) high dislocation density, typically greater than 102. 9 cm -2 (2) When the oblique grating stripes are continuously infinitely long, severe grain boundaries are generated in the center of the stripes when GaN merges laterally along the oblique grating sidewall.

[0003] In the prior art, Chinese patent application CN110335924A discloses a slanted gate PSS structure on r-plane sapphire, where the slanted gate is a continuous infinite stripe without segmentation gaps. The continuous slanted gate causes the grain boundary to span the entire stripe length during GaN lateral epitaxial merging, making it impossible to localize to a specific point. Chinese patent application CN120857727A discloses a trench array plus dislocation localization structure, but its trenches are continuous in length without segmentation design. None of these solutions solve the problems of etching uniformity and lateral defect conduction in large-size substrates.

[0004] Furthermore, existing technologies primarily target small-sized 2-inch sapphire substrates. When the substrate size increases to 4-6 inches, the high chemical stability and etching difficulty of sapphire (Al2O3) become more pronounced. Loading effects lead to significant differences in sidewall angles and pattern structure dimensions across different regions, easily resulting in non-target sidewalls that severely impact epitaxial layer quality and can even cause epitaxial failure. Existing slanted gate structures can only achieve vertical defect enrichment, resulting in a high dislocation ratio at the vertical epitaxial layer grain boundaries between two patterns. The lack of lateral defect channeling and stress release pathways expands the defect-rich area and reduces the area of ​​low-defect regions. Moreover, the technology does not consider the ease of subsequent chip dicing, making it prone to generating additional defects during dicing due to stress release. Summary of the Invention

[0005] The technical problems to be solved by this invention include: First, how to prepare a sapphire patterned substrate with precisely pre-defined sidewall crystallographic orientation, so as to simultaneously achieve low dislocation density and weak built-in polarization electric field in the GaN epitaxial layer through a unified structural design. Second, in the patterning and etching process of large-size sapphire substrates, how to improve the efficiency of reactant transport and by-product removal during the etching process by optimizing the pattern layout, obtain steep, precisely oriented C-plane sidewalls, and improve the uniformity of microstructure pattern etching and the consistency of sidewall quality at various locations.

[0006] In a first aspect, the present invention provides a large-size patterned sapphire substrate, comprising: a sapphire substrate having a surface that is... The sapphire substrate has a crystal face and a size of 4 inches or more; and a segmented slanted gate array located on the sapphire substrate, the segmented slanted gate array being composed of multiple slanted gate segments arranged parallel along the length direction; wherein each slanted gate segment is periodically spaced apart along its length direction to form multiple independent slanted gate units; the gaps also serve as lateral discharge channels for etching byproducts, dislocation termination regions, and chip cutting positioning grooves; the gap width G between adjacent slanted gate segments is 0.2μm~2μm; one side of the sidewall of the slanted gate is a sapphire C-plane crystal family, the tilt angle of which matches the sapphire crystal face, for guiding semi-polar or non-polar gallium nitride epitaxial growth.

[0007] Preferably, the length Ls of the oblique gate segment is 1μm to 500μm, more preferably 50μm to 150μm; the gap width G is preferably 0.5μm to 1.0μm.

[0008] Preferably, the depth Dg of the gap and the depth Ds of the inclined gate trench satisfy the relationship: Dg≥Ds, preferably Dg=Ds.

[0009] Preferably, the sidewall tilt angle θ of the slanted gate is 75°±5°, corresponding to the c-plane family of sapphire crystal planes, guiding the semi-polarity. Gallium nitride is grown in a planar pattern; the extension direction of the slanted gate is parallel to the m-axis direction of the sapphire. .

[0010] Preferably, the bottom shape of the gap is U-shaped or V-shaped, and the bottom chamfer radius R is 0.1μm~0.5μm.

[0011] Preferably, the sidewall of the gap has a roughened surface formed by O2 plasma treatment, and the surface roughness Ra≥30nm.

[0012] Preferably, the segment period Ps=Ls+G is 1.2-502μm.

[0013] Secondly, the present invention provides a method for preparing the above-mentioned patterned sapphire substrate, comprising the following steps: Step S1: Provide Sapphire wafers are surface-cleaned and then subjected to standard cleaning processes. Step S2: Coat the surface of the cleaned sapphire wafer with photoresist and perform step-through exposure using a mask containing a segmented gap pattern; the mask is designed with a slant gate period P'=10~250μm, a segment length Ls'=5-2500μm, and a gap width G'=1~10μm. Step S3: Develop the exposed photoresist to form a photoresist mask; Step S4: Pattern transfer is performed using inductively coupled plasma dry etching, with the etching gas being a mixture of BCl3 and Ar. Step S5: Remove residual photoresist to obtain a segmented oblique gate patterned sapphire substrate.

[0014] Preferably, the etching process parameters in step S4 are: BCl3 flow rate of 60~80 sccm, Ar flow rate of 20~40 sccm, reaction chamber pressure of 2~4 mTorr, ICP power of 1000~1500W, bias power of 400~800W, and etching time of 7~15 minutes; in step S5, the gap sidewalls of the obtained segmented oblique gate patterned sapphire substrate are roughened with O2 plasma at a power of 100W for 10~30 seconds.

[0015] Thirdly, the present invention provides a semiconductor device comprising the patterned sapphire substrate described above and a gallium nitride-based epitaxial layer located on the patterned sapphire substrate, wherein the semiconductor device is a light-emitting diode, a laser diode, or a vertical-cavity surface-emitting laser.

[0016] Compared with the prior art, the present invention has the following beneficial effects: (1) Advantages of large-size substrate adaptation: It solves the load effect problem of etching 4-6 inch sapphire substrates, and optimizes the sidewall angle control and pattern uniformity by discharging etching byproducts in segments.

[0017] (2) Defect control upgrade: There is a lack of nucleation substrate at the segment gap. When the penetrating dislocation reaches the gap, it naturally terminates, realizing the horizontal and vertical collaborative control of defects.

[0018] (3) Improved process convenience: The segmented intervals can be directly used as chip cutting channels, which simplifies the processing flow and reduces the risk of cutting defects.

[0019] (4) The amount of etching byproducts is significantly reduced: the byproduct accumulation factor is reduced by more than two orders of magnitude compared with the continuous slant gate structure. Attached Figure Description

[0020] Figure 1 For the purposes of this invention A schematic diagram of the crystal orientation of a sapphire substrate with a crystal facet.

[0021] Figure 2 This is a partially enlarged schematic diagram of the photolithography plate for the segmented oblique grating pattern structure of the present invention.

[0022] Figure 3 This is a partial SEM top view of the oblique grid structure of the present invention.

[0023] Figure 4 This is a partial SEM cross-sectional view of the oblique grid structure of the present invention.

[0024] Figure 5 This is a flowchart illustrating the fabrication process of the segmented oblique gate patterned sapphire substrate according to the present invention.

[0025] Figure 6 This is a schematic diagram showing how byproducts deposited on the sidewalls of a pattern during the etching process form a secondary mask.

[0026] Figure 7 This is a schematic diagram of GaN surface anomalies caused by the deviation of the C-plane sidewall angle.

[0027] Figure 8 This is a schematic diagram of the GaN growth process in the transition region between the sidewall and the top surface of the slanted gate pattern structure. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention in any way. It should be noted that, unless otherwise specified, the following embodiments and features can be combined with each other. It should also be understood that the terminology used in the embodiments of this invention is for describing specific implementation schemes and not for limiting the scope of protection of this invention.

[0029] When a range of values ​​is given, it should be understood that, unless otherwise stated in this invention, the two endpoints of each range and any value between the two endpoints may be selected.

[0030] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly used in the field to which this invention pertains. The terminology used to describe this invention is intended only to describe a particular implementation and is not intended to limit the scope of the teachings. This invention can be implemented using any prior art methods, apparatus, and materials similar to or equivalent to those described, used, or made in the embodiments of this invention.

[0031] The term “and / or” as used herein should be understood to mean any one of the options or any combination of two or more of the options.

[0032] As used herein, the term "about" indicates a range of ±20% of the following value. In some embodiments, the term "about" indicates a range of ±10% of the following value. In some embodiments, the term "about" indicates a range of ±5% of the following value.

[0033] The main innovation of this invention, which provides a large-size patterned sapphire substrate, lies in transforming the traditional continuous, infinitely long oblique gate stripes into an oblique gate array interrupted by periodic gaps. The width, depth, and distribution density of the gaps are three independently adjustable parameters that can be adaptively adjusted according to the chip size.

[0034] In one specific embodiment, a large-size (4-inch or 6-inch) patterned sapphire substrate includes... A sapphire substrate and a segmented oblique gate array located on the substrate, which meet the following requirements: (1) The oblique gate is periodically broken along its length direction to form multiple independent oblique gate segments. (2) The length Ls of each oblique gate segment satisfies: 1μm ≤ Ls ≤ 500μm; As a preferred embodiment, 50μm ≤ Ls ≤ 150μm. (3) The gap width G between adjacent oblique grid segments satisfies: 0.2μm ≤ G ≤ 2μm; As a preferred embodiment, 0.5μm ≤ G ≤ 1μm. (4) The gap depth Dg and the skew gate trench depth Ds satisfy the relationship: Dg ≥ Ds, the gap penetrates the entire trench depth; As a preferred implementation, Dg = Ds. (5) The segmented period Ps = Ls + G, satisfying: 1.2μm ≤ Ps ≤ 502μm.

[0035] In a preferred embodiment, 50.2μm ≤ Ps ≤ 150μm.

[0036] In a preferred embodiment, the sidewall tilt angle θ of the slanted gate matches the sapphire crystal plane: for Sapphire substrate with θ = 75°±3°, corresponding to a c-plane group of crystal planes, guiding half-polarity. GaN growth; the extension direction of the slanted gate is parallel to the m-axis of the sapphire. This ensures the crystal orientation consistency of GaN lateral epitaxy.

[0037] In a preferred embodiment, the bottom shape of the gap is U-shaped or V-shaped, more preferably U-shaped, with a bottom chamfer radius R = 0.1~0.5μm to avoid stress concentration. In another preferred embodiment, the gap sidewalls can be selectively roughened to Ra ≥ 30nm to further promote dislocation termination at the gap.

[0038] The following is a quantitative analysis of the mechanism by which the segmented slanted gate structure improves the uniformity of ICP etching from the perspective of by-product transport.

[0039] During ICP dry etching, etching byproducts (mainly AlCl3, etc.) accumulate inside the trenches. When these byproducts cannot be removed in time, they deposit on the sidewalls, forming a secondary mask, causing the sidewall angle to deviate from the preset value and become uneven. The following uses a diffusion model to quantitatively illustrate the improvement effect of the segmented structure.

[0040] 1. Accumulation of byproducts In a continuous slanted grid structure, the byproduct concentration C(z) within the trench satisfies a one-dimensional steady-state diffusion equation along the trench length: Where C(z) is the byproduct concentration at x (unit: mol / m³); D is the effective diffusion coefficient of byproducts in the trench (unit: m² / s), which is subject to Knudsen diffusion limitation; S0 is the byproduct generation rate per unit volume per unit time (unit: mol / (m³·s)), which is proportional to the etching rate; and the total trench length is L (unit: μm or mm). bulk The concentration of byproducts in the cavity (background concentration far from the etched surface, unit: mol / m³).

[0041] Solving the above diffusion equation and combining it with boundary conditions, we obtain the parabolic distribution of byproduct concentration along the trench: As can be seen from the above formula, the concentration of byproducts is highest at the center of the trench (x=L / 2).

[0042] Define cumulative factor Let represent the multiple by which the highest concentration in the trench of a continuous slanted grid structure exceeds the background concentration. in Cmax is a dimensionless quantity representing the byproduct accumulation factor of a continuous slanted grid structure, indicating the multiple by which the highest concentration in the trench exceeds the background concentration; Cmax is the highest byproduct concentration at the center of the trench (unit: mol / m³).

[0043] As shown in the above formula, the amount of accumulated byproducts is directly proportional to the square of the trench length L. In continuous oblique grid structures, the trench length L can reach the centimeter level, resulting in severe byproduct accumulation.

[0044] 2. Improvement Mechanism of Segmented Slanted Grid Structure In the segmented slanted grid structure, the length Ls of each slanted grid segment is much smaller than the total length L of the continuous structure, and each slanted grid segment has gaps (width G on the submicron scale) at both ends. These gaps provide lateral discharge channels for byproducts, allowing them to diffuse not only longitudinally along the trenches but also laterally through the gaps.

[0045] The byproduct accumulation factor of a segmented slanted grid structure can be expressed as: in: The byproduct accumulation factor representing the segmented slanted grid structure; The representative will be in the continuous structure formula Replace with The value after; The length (μm) of each slanted grid segment is preferred to be 50-150μm. The width (μm) representing the gap between adjacent oblique grid segments is preferably 0.5~1.0 μm; The transverse diffusion coefficient (m² / s) of byproducts at the gaps is not limited by the trench walls and is much larger than .

[0046] The ratio of the two: Take the maximum length L of the segmented slanted gate s / L is 0.5mm / 10cm = 10 -3 The cumulative amount of byproducts in segmented structures is reduced by more than three orders of magnitude compared to continuous structures.

[0047] 3. Improved angular uniformity Sidewall angle deviation proportional to the spatial variation rate of by-product concentration ,in: Represents the sidewall angle relative to the preset value Deviation (°); This represents the spatial gradient of byproduct concentration along the trench direction.

[0048] In continuous structures The gradient distribution along the trenches exhibits a parabolic pattern, with the sidewall angles shifting systematically along the stripe direction. Within the segmented structure, the concentration gradient is minimal, and the sidewall angles at all locations are highly consistent. Simultaneously, timely removal of byproducts ensures the cleanliness of the sidewall surfaces, resulting in more precise C-plane crystal orientation and effective elimination of radial concentration gradients on large-size substrates.

[0049] In summary, by transforming the traditional continuous slanted gate into a segmented slanted gate structure and utilizing the lateral discharge channel provided by the gap, the accumulation of etching byproducts is reduced by more than two orders of magnitude, effectively solving the problem of poor sidewall angle consistency in patterned etching of large-size substrates.

[0050] The present invention also provides a method for preparing the above-mentioned large-size patterned sapphire substrate, comprising the following steps: Step 1: Provide Sapphire wafers, standard cleaning; Step 2: Coat photoresist and expose using a mask with a segmented gap pattern; Mask design: slant gate period P' = 10~250μm, segment length Ls' = 5~2500μm, gap width G' = 1~10μm; The stepper lithography mask and substrate projection size used in this method are 5:1; Step 3: Develop to form a photoresist mask, which is retained in the slant gate region and removed in the gap region; Step 4: ICP dry etching, conditions: BCl3 / Ar = 60~80 / 20~40 sccm, pressure 2~4 mTorr, ICP power 1000~1500W, bias power 400~800W; Etching time: adjusted according to the required pattern depth and corresponding etching process, usually 7~15 minutes; Step 5: Remove residual photoresist; Step 6 (optional post-processing): Roughen the gap sidewalls with O2 plasma, power 100W, time 10~30 seconds.

[0051] In the aforementioned fabrication method, precise adjustment of etching process parameters can control the etching rate and anisotropy to a certain extent. However, to ensure precise control of the sidewalls within 75°±3°, a higher etching rate and BRF are required to improve anisotropy, resulting in a larger amount of etching byproducts. Furthermore, a single longitudinal channel is not entirely aligned with the cavity flow field direction, causing byproducts to adhere to the etched pattern sidewalls. As etching progresses downwards, the angle of the newly etched sidewalls differs from that of the sidewalls protected by byproducts, leading to multi-segmented sidewalls with inconsistent tilt angles. Simultaneously, the amount of byproducts discharged varies at different locations on the substrate, further contributing to differences in the sidewall angles of the pattern within the wafer. In contrast, adding lateral channels to the pattern design optimizes the removal mechanism of etching byproducts, ensuring consistency in pattern size and sidewall angles at different locations on the substrate. Additionally, timely removal of byproducts improves the cleanliness of the etched pattern sidewalls, resulting in steeper sidewalls and more precise crystal orientation. Figure 3 A magnified schematic diagram of a segmented oblique grid pattern structure photomask is shown, in which the mask pattern is 1 / 5 of the photomask pattern.

[0052] Example 1 This embodiment provides a structural design for a segmented, oblique-gate patterned sapphire substrate. (Selection) The substrate material is 4-inch sapphire with crystal facet orientation. Figure 1 This illustrates the crystal orientation and plane relationships of the sapphire substrate with a specific crystal orientation used in this invention, where the c-axis and m-axis are shown. The orientation relationship with the a-axis determines the extension direction and sidewall crystal orientation of the subsequent slanted grating structure.

[0053] Figure 2 This is a partially enlarged schematic diagram of the segmented oblique grating pattern structure photomask of the present invention. The rectangular blocks represent the oblique grating areas covered by the photoresist mask, and the blank areas between adjacent rectangular blocks are gaps. The figure labels three key structural parameters: segment length Ls, gap width G, and segment period Ps. Specifically, in this embodiment, the oblique grating period P is 30 μm, the oblique grating segment length Ls is 500 μm (corresponding to an actual size of 100 μm after step-type 5:1 projection), and the gap width G is 5 μm (corresponding to an actual size of 1 μm after projection).

[0054] like Figure 3 and 4 As shown, the sidewalls of the slanted gate structure obtained after ICP dry etching are C-planes with a sidewall tilt angle of 75°, corresponding to the c-plane family of crystal planes in sapphire. This specific crystal plane selection guides the semi-polarity of subsequent MOCVD epitaxial growth. Planar GaN. The direction of the slanted gate extension is parallel to the m-axis of the sapphire. This orientation ensures the consistency of the crystal orientation during GaN lateral epitaxy. The bottom of the gap is U-shaped with a bottom chamfer radius R of 0.3 μm to reduce stress concentration. The gap depth is equal to the depth of the skew gate trench, both being 1 μm, allowing the gap to penetrate the entire depth of the skew gate trench.

[0055] Example 2 This embodiment provides a specific process method for preparing the patterned sapphire substrate described in Example 1. For example... Figure 5 As shown, the fabrication process of the segmented oblique gate patterned sapphire substrate of the present invention includes the following steps: Step S1: Provide The sapphire wafers are subjected to standard wet cleaning to remove surface contaminants.

[0056] Step S2: Coat the cleaned sapphire wafer surface with photoresist, with a photoresist thickness of 6 μm. Perform step-through exposure using a mask containing a segmented gap pattern, with a mask-to-substrate projection ratio of 5:1. The mask design parameters are: slant gate period P' = 30 μm, slant gate segment length Ls' = 500 μm, and gap width G' = 5 μm.

[0057] Step S3: Develop the exposed photoresist to form a photoresist mask. The photoresist mask is retained in the angled gate region and removed in the gap region. The resulting photoresist mask has a thickness of 6 μm, a segment length of 100 μm, and a gap width of 1 μm.

[0058] Step S4: Perform ICP dry etching using the developed photoresist mask. The etching gas is a mixture of BCl3 and Ar with a flow rate ratio of BCl3:Ar = 80:20 sccm. The reaction chamber pressure is 2 mTorr, the ICP power is 1000 W, and the bias power is 700 W. The etching time is 12.5 minutes, and the resulting slanted gate trench depth is 1 μm.

[0059] Step S5: Remove residual photoresist to obtain a segmented oblique gate patterned sapphire substrate.

[0060] Step S6 (optional): Roughen the gap sidewall with O2 plasma at a power of 100W for 15 seconds to achieve a surface roughness Ra ≥ 30nm.

[0061] Example 3 This embodiment provides a segmented slanted gate structure suitable for 6-inch large-size sapphire substrates, and analyzes the mechanism by which the segmented structure improves etching uniformity.

[0062] like Figure 6 As shown, in the traditional continuous slanted gate structure ICP dry etching process, etching byproducts (mainly AlCl3, B2O3, etc.) accumulate inside the trenches. When these byproducts cannot be removed in time, they deposit on the sidewalls, forming a secondary mask. This secondary mask alters the local etching rate and anisotropy during the etching process, causing the sidewall angle to deviate from the preset value. The byproduct concentration exhibits a parabolic distribution along the trench direction, with the highest concentration at the center of the trench, resulting in a systematic drift of the sidewall angle along the stripe length direction.

[0063] This invention employs a segmented oblique grid structure, with the length Ls of the oblique grid segment preferably ranging from 50 μm to 150 μm, and the gap width G preferably ranging from 0.5 μm to 1.0 μm. In this structure, gaps are provided at both ends of each oblique grid segment, forming a lateral discharge channel for byproducts, significantly reducing the cumulative concentration of byproducts within the trench. Theoretical calculations show that the byproduct accumulation factor of the segmented structure is reduced by more than two orders of magnitude compared to the continuous oblique grid structure. Timely discharge of byproducts ensures the cleanliness of the sidewall surface, resulting in more precise C-plane crystal orientation and consistent sidewall angles at all locations.

[0064] Figure 7 This demonstrates that the deposition of etching byproducts leads to a non-target tilt angle at the top of the sidewall, resulting in the formation of non-oriented GaN in the top region after epitaxy, forming cavities or amorphous GaN.

[0065] Example 4 This embodiment provides a semiconductor device and its epitaxial structure comprising the above-described patterned sapphire substrate. For example... Figure 8 As shown, semi-polar sapphire crystals are epitaxially grown on a segmented, oblique-gate patterned sapphire substrate via MOCVD. GaN-based epitaxial layer. During epitaxial growth, GaN preferentially nucleates and grows on the C-plane sidewalls. Since the C-plane is a patterned sidewall and has a certain angle with the substrate plane, the stress in the longitudinal direction of the grown GaN is weakened, effectively modulating the polarization field distribution and reducing the quantum confinement Stark effect (QCSE).

[0066] At the healed grain boundary, two adjacent epitaxial layers form a dislocation defect-rich region, while between two adjacent patterns, the lateral epitaxy guides dislocations to the grain boundary, forming a low dislocation density region. Simultaneously, the lack of a nucleation substrate at the segment gaps causes penetrating dislocations extending along the slanted gate segment to terminate naturally upon reaching the gap, preventing them from continuing upwards into the active region. This results in a material channel with extremely low dislocation density within the epitaxial layer region corresponding to the active region of the device.

[0067] The semiconductor device can be a light-emitting diode, a laser diode, or a vertical-cavity surface-emitting laser, and is particularly suitable for Micro LED and laser applications that require high crystal quality.

[0068] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the appended claims.

Claims

1. A large-size patterned sapphire substrate, characterized in that, include: Sapphire substrate, its surface is The sapphire substrate has a crystal face and a size of 4 inches or more; and a segmented slanted gate array located on the sapphire substrate, the segmented slanted gate array being composed of multiple slanted gate segments arranged parallel along the length direction; wherein each slanted gate segment is periodically spaced apart along its length direction to form multiple independent slanted gate units; the gaps also serve as lateral discharge channels for etching byproducts, dislocation termination regions, and chip cutting positioning grooves; the gap width G between adjacent slanted gate segments is 0.2μm~2μm; one side of the sidewall of the slanted gate is a sapphire C-plane crystal family, the tilt angle of which matches the sapphire crystal face, for guiding semi-polar or non-polar gallium nitride epitaxial growth.

2. The large-size patterned sapphire substrate according to claim 1, characterized in that, The length Ls of the oblique gate segment is 1μm to 500μm, preferably 50μm to 150μm, and the gap width G is 0.5μm to 1.0μm.

3. The large-size patterned sapphire substrate according to claim 1, characterized in that, The gap depth Dg and the slanted gate trench depth Ds satisfy the relationship: Dg≥Ds, preferably Dg=Ds.

4. The large-size patterned sapphire substrate according to claim 1, characterized in that, The sidewall tilt angle θ of the slanted gate is 75°±5°, corresponding to the c-plane family of sapphire crystal planes, guiding the semi-polarity. Gallium nitride is grown in a planar pattern; the extension direction of the slanted gate is parallel to the m-axis direction of the sapphire. .

5. The large-size patterned sapphire substrate according to claim 1, characterized in that, The bottom shape of the gap is U-shaped or V-shaped, and the bottom chamfer radius R is 0.1μm~0.5μm.

6. The large-size patterned sapphire substrate according to claim 1, characterized in that, The sidewalls of the gap have a roughened surface formed by O2 plasma treatment, with a surface roughness Ra≥30nm.

7. The large-size patterned sapphire substrate according to claim 1, characterized in that, The segmented period Ps = Ls + G is 1.2-502 μm.

8. A method for preparing a large-size patterned sapphire substrate as described in any one of claims 1 to 7, characterized in that, Includes the following steps: Step S1: Provide Sapphire wafers are surface-cleaned and then subjected to standard cleaning processes. Step S2: Coat the surface of the cleaned sapphire wafer with photoresist and perform step-through exposure using a mask containing a segmented gap pattern; the mask is designed with a slant gate period P'=10~250μm, a segment length Ls'=5-2500μm, and a gap width G'=1~10μm. Step S3: Develop the exposed photoresist to form a photoresist mask; Step S4: Pattern transfer is performed using inductively coupled plasma dry etching, with the etching gas being a mixture of BCl3 and Ar; Step S5: Residual photoresist is removed to obtain a segmented oblique gate patterned sapphire substrate.

9. The method according to claim 8, characterized in that, In step S4, the etching process parameters are as follows: BCl3 flow rate is 60~80 sccm, Ar flow rate is 20~40 sccm, reaction chamber pressure is 2~4 mTorr, ICP power is 1000~1500W, bias power is 400~800W, and etching time is 7~15 minutes. In step S5, the gap sidewalls of the obtained segmented oblique gate patterned sapphire substrate are roughened with O2 plasma at a power of 100W for 10~30 seconds.

10. A semiconductor device, characterized in that, The semiconductor device includes a large-size patterned sapphire substrate as described in any one of claims 1 to 6, and a gallium nitride-based epitaxial layer located on the patterned sapphire substrate, wherein the semiconductor device is a light-emitting diode, a laser diode, or a vertical-cavity surface-emitting laser.

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