Semiconductor device

Abstract

A semiconductor device is disclosed. The semiconductor device includes a substrate and a support layer disposed on the substrate. In a cross section, the support layer has a first support pillar and a second support pillar separated from each other. The semiconductor device also includes one or more semiconductor elements. The semiconductor element includes a semiconductor stack and an insulating structure disposed on the semiconductor stack. The insulating structure has a main portion covering the semiconductor stack and a first extension portion and a second extension portion separated from each other. The first extension portion and the second extension portion extend outwardly from the main portion to the first support pillar and the second support pillar, respectively. A thickness of the first extension portion is less than a thickness of the main portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device comprising one or more extensions. Background Technology

[0002] Micro LEDs have immense application potential in the display technology field due to their high brightness, high energy efficiency, and miniaturization. However, the extremely small size of micro LED chips (bare dies) necessitates highly efficient mass transfer technologies for large-scale manufacturing. Currently, the main mass transfer technologies include laser transfer, stamp transfer, and monolithic bonding.

[0003] While current mainstream technologies (such as laser transfer) offer precision, their equipment costs are high and they can easily damage the micro-LED chips. Single-crystal bonding offers high integration but is not suitable for all applications. Transfer printing technology, due to its cost-effectiveness and applicability, has become a worthwhile technology to develop. Summary of the Invention

[0004] Some embodiments of the present invention are semiconductor devices. The semiconductor device includes a substrate and a support layer disposed on the substrate. In a cross-section, the support layer has a first support pillar and a second support pillar separated from each other. The semiconductor device also includes one or more semiconductor elements, each semiconductor element comprising a semiconductor stack and an insulating structure disposed on the semiconductor stack. The insulating structure has a main body portion and a first extension portion and a second extension portion separated from each other. The main body portion covers the semiconductor stack, and the first extension portion and the second extension portion extend outward from the main body portion to the first support pillar and the second support pillar, respectively. The thickness of the first extension portion is less than the thickness of the main body portion. Attached Figure Description

[0005] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, according to industry standard practice, the various feature components are not drawn to scale. In fact, the dimensions of the various feature components may be enlarged or reduced to clearly demonstrate the technical features of the embodiments of the present invention.

[0006] Figure 1A This is a partial cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0007] Figure 1B This is a partial top view of a semiconductor device according to some embodiments of the present invention;

[0008] Figure 1C This is a partial perspective view of a semiconductor device according to some embodiments of the present invention;

[0009] Figures 2A to 2C This is a schematic diagram illustrating the structure in the insulation structure according to some embodiments of the present invention;

[0010] Figures 3A to 3H These are partial cross-sectional views illustrating various stages of manufacturing a semiconductor device according to some embodiments of the present invention;

[0011] Figure 4A and Figure 4B This is a partial top view of a semiconductor device according to some embodiments of the present invention;

[0012] Figure 5 This is a partial top view of a semiconductor device according to some embodiments of the present invention;

[0013] Figure 6 This is a partially enlarged view of a semiconductor device according to some embodiments of the present invention;

[0014] Figures 7A to 7F This is a schematic diagram illustrating the relative relationships between semiconductor elements, insulating structures, and support layers in a top view, based on different embodiments;

[0015] Figure 8 This is a partial cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0016] Figures 9A to 9H These are partial cross-sectional views illustrating various stages of manufacturing a semiconductor device according to some embodiments of the present invention;

[0017] Figure 10 This is a partial cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0018] Figure 11A , Figure 11B and Figure 11C This is a partial cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0019] Figure 12A This is a partial cross-sectional view of a semiconductor device according to some embodiments of the present invention;

[0020] Figure 12B This is a partial top view of a semiconductor device according to some embodiments of the present invention;

[0021] Figure 13 This is a schematic cross-sectional view of a semiconductor component illustrated according to some embodiments of the present invention.

[0022] Symbol explanation:

[0023] 1,2,3,100,102,104,106: Semiconductor devices

[0024] 4: Semiconductor components

[0025] 10: Growth substrate 11: Temporary carrier

[0026] 12: Substrate 20, 20', 20”: Semiconductor element

[0027] 201: First semiconductor element; 202: Second semiconductor element

[0028] 21: Semiconductor stack 22: Semiconductor layer

[0029] 23: First Semiconductor Structure

[0030] 23S1, 23S2, 24S, 25S, 30S, 32S, 61S, 62S: Sidewall

[0031] 24: Active region 25: Second semiconductor structure

[0032] 27: Insulation structure 27C: Main body

[0033] 27H, 70H: Openings 271: First extension

[0034] 271V, 272V: Void; 272: Second Extension

[0035] 273: Third extension 274: Fourth extension

[0036] 30, 32: Conductive bonding layer; 30T: Top surface

[0037] 32B: Bottom surface 50, 52: Electrodes

[0038] 60: Support layer; 60': Dielectric layer

[0039] 60C: Cavity; 60S1: First surface

[0040] 60S2: Second surface; 61: First support column

[0041] 611, 621: Upper surface; 62: Second support column

[0042] 70: Protective layer; 701: First opening

[0043] 702: Second opening; 80: Substrate

[0044] 82: Supporting components; 82C, 82C1, 82C2: Cavities

[0045] 820: Prominent part 821: First prominent part

[0046] 822: Second protruding part; 84: Connecting layer

[0047] 86: Alignment mark; 90: Semiconductor substrate

[0048] 92: Conductive pad; 94: Filler material

[0049] E: Dashed line M, M': Platform area

[0050] O: Geometric center; PL1, PL2, PL3: Second sub-layer

[0051] PR1: Sacrificial layer; PR2: Mask layer

[0052] SL1, SL2, SL3: First sublayer T27C, T271, T272: Thickness

[0053] TP1, TS1, TS2: Thickness A-A', B-B': Line Detailed Implementation

[0054] To provide a more detailed and complete description of the present invention, the following will be done in conjunction with the accompanying drawings. It should be noted that the following illustrations are examples of semiconductor elements used to illustrate the present invention and are not intended to limit the invention to these embodiments. In the drawings and descriptions, similar or identical components will be described using similar or identical reference numerals, and unless otherwise specified, the shapes or dimensions of the elements in the drawings are merely illustrative and are not actually limited thereto. It should be particularly noted that elements not depicted in the figures may be in forms known to those skilled in the art.

[0055] The semiconductor device of this invention is, for example, a semiconductor optoelectronic device or a non-light-emitting device. The semiconductor optoelectronic device includes a light-emitting element (e.g., a light-emitting diode, a laser diode) or a light-absorbing element (e.g., a photodetector). The composition of each layer and the dopant in the semiconductor device of this invention can be analyzed by any suitable method, such as secondary ion mass spectrometry (SIMS) or electrochemical capacitance-voltage (ECV) measurement, and the thickness of each layer can also be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscopy (SEM).

[0056] A person of ordinary skill in the art should understand that other components may be added on the basis of the various embodiments described below. For example, unless otherwise specified, descriptions similar to "the first layer (structure) is located on the second layer (structure)" may include embodiments where the first layer (structure) is in direct contact with the second layer (structure), and may also include embodiments where there are other structures between the first layer (structure) and the second layer (structure) such that they are not in direct contact with each other. In addition, it should be understood that the positional relationship between the top and bottom of each layer (structure) and the like may be changed depending on the observation from different orientations. In the method, some steps may be replaced or omitted.

[0057] Unless otherwise specified, the general formula InGaP represents In x0 Ga 1-x0 P, where 0<x0<1; the general formula AlInP represents A lx1 In 1-x1 P, where 0<x1<1; the general formula InGaN represents In x2 Ga 1-x2 N, where 0<x2<1; the general formula AlGaN represents Al x3 Ga 1- x3 N, where 0<x3<1; the general formula AlGaInP represents Al x4 Ga x5 In 1-x4-x5 P, where 0<x4<1 and 0<x5<1; the general formula InGaAsP represents In x6 Ga 1-x6 As x7 P 1-x7 , where 0<x6<1, 0<x7<1; the general formula AlGaInAs represents Al x8 Ga x9 In 1-x8-x9 As, where 0<x8<1, 0<x9<1; the general formula InGaAs represents In x10 Ga 1-x10 As, where 0<x10<1; the general formula AlGaAs represents Al x11 Ga 1-x11 As, where 0<x11<1; the general formula AlGaAsP represents Al x12 Ga 1-x12 As x13 P 1-x13 , where 0<x12<1, 0<x13<1; the general formula InGaNAs represents In x14 Ga 1-x14 N x15 As 1-x15 , where 0<x14<1, 0<x15<1; the general formula AlInGaN represents Al x16 Inx16 Ga 1-x16-x17 N, where 0 <x16<1,0<x17<1。

[0058] Figure 1A This is a partial cross-sectional view of a semiconductor device 100 according to some embodiments of the present invention. (Refer to...) Figure 1A In some embodiments, the semiconductor device 100 includes a substrate 12. For example, the substrate 12 may include a sapphire substrate, a plastic substrate, a ceramic substrate, or a glass substrate. In some embodiments, the semiconductor device 100 further includes a support layer 60 disposed on the substrate 12. Figure 1A As shown in a cross-section, the support layer 60 may have a first support pillar 61 and a second support pillar 62 separated from each other. The first support pillar 61 and the second support pillar 62 are located on the left and right sides of the support layer 60, respectively. The first support pillar 61 has an upper surface 611, and the second support pillar 62 has an upper surface 621. The support layer 60 may contain a dielectric material, such as a polymer material like benzocyclobutene (BCB), epoxy resin, polyimide, or silicone resin, alumina (Al2O3), silicon oxide (SiO2), etc.

[0059] Semiconductor device 100 further includes semiconductor element 20. For example... Figure 1A As shown, a cavity 60C can be formed between the first support pillar 61 and the second support pillar 62. The semiconductor element 20 may include a semiconductor stack 21 and an insulating structure 27. The semiconductor stack 21 may include a first semiconductor structure 23, an active region 24, and a second semiconductor structure 25. The insulating structure 27 is connected to the semiconductor stack 21. Figure 1A As shown, the semiconductor stack 21 in the semiconductor element 20 is, for example, suspended on the support layer 60. The semiconductor stack 21 does not directly contact the support layer 60. The insulating structure 27 may include oxides, nitrides, or fluorides, such as titanium oxide (TiO2), silicon oxide (SiO2), aluminum nitride (AlN), aluminum oxide (Al2O3), magnesium fluoride (MgF2), or thallium oxide (Ta2O5).

[0060] The first semiconductor structure 23, the active region 24, and the second semiconductor structure 25 may each comprise a single layer or multiple layers. The first semiconductor structure 23 and the second semiconductor structure 25 located on either side of the active region 24 have asymmetrical appearances. For example... Figure 1AAs shown, the minimum width of the second semiconductor structure 25 is smaller than the minimum width of the first semiconductor structure 23. The first semiconductor structure 23 has a first conductivity type, and the second semiconductor structure 25 has a second conductivity type different from the first conductivity type. The first semiconductor structure 23 and the second semiconductor structure 25 can respectively provide electrons and holes (or holes and electrons). For example, the first conductivity type is n-type and the second conductivity type is p-type, or the first conductivity type is p-type and the second conductivity type is n-type. Each layer in the first semiconductor structure 23, the active region 24, and the second semiconductor structure 25 can contain binary III-V semiconductor materials (such as GaN, GaAs, or GaP), ternary III-V semiconductor materials (such as InGaN, AlGaN, InGaAs, AlGaAs, InGaP, or AlInP), or quaternary III-V semiconductor materials (such as AlInGaN, AlGaInAs, AlGaInP, InGaAsP, or AlGaAsP). The conductivity types of the first semiconductor structure 23 and the second semiconductor structure 25 can be adjusted by adding different dopants. For example, the first semiconductor structure 23 includes a first dopant, and the second semiconductor structure 25 includes a second dopant different from the first dopant. The first and second dopants can be elements from Group II, Group IV, or Group VI of the periodic table, such as magnesium (Mg), zinc (Zn), carbon (C), silicon (Si), germanium (Ge), or tellurium (Te). In some embodiments, the first dopant is silicon (Si) or germanium (Ge), and the second dopant is magnesium (Mg) or carbon (C).

[0061] The active region 24 is located between the first semiconductor structure 23 and the second semiconductor structure 25. For example, the active region 24 may include a quantum well (QW) layer, such as indium gallium nitride (InGaN) or gallium nitride (GaN). In some embodiments, the active region 24 includes a multiple quantum well (MQW) structure. Electrons and holes can combine in the active region 24 to emit light with a peak wavelength. This light can be visible or invisible, and can be incoherent or coherent. Specifically, the peak wavelength may depend on the material composition of the active region 24. When the material of the active region 24 contains AlGaN, it can emit ultraviolet light with a peak wavelength of 250 nm to 400 nm, for example; when the material of the active region 24 contains InGaN, it can emit deep blue or blue light with a peak wavelength of 400 nm to 490 nm, or green or yellow light with a peak wavelength of 490 nm to 550 nm, or red light with a peak wavelength of 560 nm to 650 nm, for example; when the material of the active region 24 contains InGaP or AlGaInP, it can emit yellow, orange, or red light with a peak wavelength of 530 nm to 700 nm, for example; when the material of the active region 24 contains InGaAs, InGaAsP, AlGaAs, or AlGaInAs, it can emit infrared light with a peak wavelength of 700 nm to 1700 nm, for example.

[0062] like Figure 1A As shown, in some embodiments, the insulating structure 27 has a main body 27C and a first extension 271 and a second extension 272 separated from each other. The main body 27C covers the semiconductor stack 21. The first extension 271 and the second extension 272 extend outward from the main body 27C to the first support post 61 and the second support post 62, respectively, and are connected to the first support post 61 and the second support post 62, respectively. Figure 1A As shown, the first extension 271 and the second extension 272 may not overlap with the semiconductor stack 21 in the vertical direction. The first extension 271 has a thickness T271, the second extension 272 has a thickness T272, and the main body 27C has a thickness T27C. The thickness T271 or the thickness T272 may be different from the thickness T27C.

[0063] In this embodiment, the thickness T271 of the first extension 271 is less than the thickness T27C of the main body 27C. The thickness T272 of the second extension 272 may be less than the thickness T27C of the main body 27C. In some embodiments, the thickness T271 may be less than or equal to 400 nm, for example, in the range of 50 nm to 200 nm. In some embodiments, the thickness T272 may be less than or equal to 400 nm, for example, in the range of 50 nm to 200 nm. In some embodiments, the thickness T27C may be greater than or equal to 200 nm, for example, in the range of 300 nm to 3000 nm. In some embodiments, the ratio of thickness T271 or thickness T272 to thickness T27C is, for example, in the range of 1:4 to 1:60. According to some embodiments, when the thicknesses T271, T272, and / or T27C fall within the above-mentioned thickness ranges, it helps to maintain the structural stability of the semiconductor device 100 and can improve the success rate of subsequent transfer of the semiconductor element 20.

[0064] Figure 1B This is a partial top view of a semiconductor device 100 according to some embodiments of the present invention. Figure 1C This is a partial perspective view of a semiconductor device 100 according to some embodiments of the present invention, for example, along... Figure 1B A three-dimensional cross-sectional view of line A-A' in the diagram. For ease of understanding, Figure 1B The structure of semiconductor element 20 is omitted. For example... Figure 1B As shown, from a top view, the first extension 271 and the second extension 272 are symmetrically arranged relative to the geometric center O of the semiconductor element 20, thereby maintaining the position of the semiconductor element 20 and keeping it balanced. The support layer 60 may surround the semiconductor element 20, and the semiconductor element 20 is connected to the support layer 60 through the first extension 271 and the second extension 272.

[0065] like Figure 1B As shown, in some embodiments, the first extension 271 may selectively have one or more cavities 271V, and the second extension 272 may selectively have one or more cavities 272V. By providing cavities 271V and 272V, the semiconductor element 20 can be more easily broken in subsequent transfer fabrication processes, and the breakage location can be better controlled. In this embodiment, the semiconductor stack 21 may be inverted trapezoidal. Figure 1C As shown, the width of the semiconductor stack 21 gradually decreases from the first semiconductor structure 23 towards the second semiconductor structure 25. In some embodiments, the first support pillar 61 and the second support pillar 62 may also have roughened sidewalls.

[0066] Figures 2A to 2C The structure of the insulating structure 27 is illustrated according to some embodiments of the present invention. Figures 2A to 2C The description focuses on the main body 27C; however, the first extension 271 and / or the second extension 272 may also have... Figures 2A to 2C The structure of any one of them, or its partial structure. For example... Figures 2A to 2B As shown, the main body 27C may include one or more first sublayers (SL1 / SL2 / SL3…) and one or more second sublayers (PL1 / PL2 / PL3…). The first sublayers and the second sublayers have different Mohs scales. The Mohs scale of the first sublayer may be greater than that of the second sublayer. The first sublayer may serve as an etch stop layer, for example, and the second sublayer may serve as a passivation layer, for example. In some embodiments, each first sublayer comprises aluminum oxide (Al2O3) with a Mohs scale of approximately 9, while each second sublayer comprises silicon dioxide (SiO2) or titanium dioxide (TiO2) with a Mohs scale of approximately 6 to 7.

[0067] like Figure 2A As shown, the main body 27C includes two first sublayers SL1 and SL2 and a second sublayer PL1 disposed between the first sublayers SL1 and SL2. The thickness TS1 of the first sublayer SL1 and the thickness TS2 of the first sublayer SL2 can be in the range of 400 Å to 1500 Å. The first sublayers SL1 and SL2 can have substantially the same thickness. The thickness TP1 of the second sublayer PL1 can be in the range of 8000 Å to 12000 Å. In some embodiments, thickness TP1 > thickness TS1 > thickness TS2, for example, thickness TS1 is in the range of 1000 Å to 3000 Å, thickness TP1 is in the range of 6000 Å to 10000 Å, and thickness TS2 is in the range of 400 Å to 1500 Å.

[0068] like Figure 2B As shown, in this embodiment, the main body 27C includes three first sublayers SL1, SL2, and SL3, and two second sublayers PL1 and PL2 disposed between the first sublayers SL1, SL2, and SL3. In this embodiment, the first sublayers SL1, SL2, and SL3 have different thicknesses. For example, the thickness TS3 of the first sublayer SL3 may be greater than or equal to the thickness TS1 of the first sublayer SL1 and the thickness TS2 of the first sublayer SL2.

[0069] like Figure 2CAs shown, in this embodiment, the main body 27C may include a structure similar to a distributed Bragg reflector (DBR). The main body 27C includes multiple layers of staggered first sublayers (SL1, SL2, SL3…) and multiple layers of second sublayers (PL1, PL2, PL3…). The number of first and second sublayers can be adjusted according to actual needs. The main body 27C may, for example, include 3 to 20 pairs of first and second sublayers. The first and second sublayers have different refractive indices. Specifically, the first and second sublayers may include oxides or nitrides, such as: aluminum oxide (Al2O3), silicon oxide (SiO2), titanium oxide (TiO2), silicon nitride (Si3N4), tantalum oxide (Ta2O5), or niobium oxide (Nb2O5). According to some embodiments, the combination of the first and second sublayers is, for example, SiO2 / TiO2 or SiO2 / Nb2O5. According to some embodiments, Figures 2A to 2C The structures shown can also be combined or substituted. For example, Figure 2A or Figure 2B The structure shown may further include, for example: Figure 2C The DBR structure shown; or, Figure 2A or Figure 2B One or more layers in the structure shown (e.g., the second sublayer PL1 or PL2) can be replaced with, for example... Figure 2C The DBR structure shown.

[0070] According to some embodiments, the main body 27C, the first extension 271, and / or the second extension 272 may have Figures 2A to 2C The structure of any one of them, or a portion thereof. In some embodiments, the main body 27C and the first extension 271 have different compositions, and / or the main body 27C and the second extension 272 have different compositions. For example, in one embodiment, the main body 27C may have the following structure: Figure 2A , Figure 2B or Figure 2C The structure shown may have a first extension 271 and a second extension 272 having a first sublayer (SL1 / SL2 / SL3…) and / or a second sublayer (PL1 / PL2 / PL3…) with a portion of the structure removed. For example, the first extension 271 and / or the second extension 272 may be formed with a different composition from the main body 27C by a thinning process on a portion of the insulating structure 27.

[0071] In some embodiments, the first extension 271 and / or the second extension 272 may be a structure consisting of the remaining first sublayer SL1. Since the Mohs hardness of the first sublayer (e.g., Al2O3, with a Mohs hardness of approximately 9) is greater than that of the second sublayer (e.g., SiO2 or TiO2, with a Mohs hardness of approximately 6-7), the first sublayer is more brittle, increasing the probability of breakage at the first extension 271 or the second extension 272 during subsequent transfer of the semiconductor device 20. In some embodiments, the first extension 271 or the second extension 272 after locally thinning the insulating structure 27 may include the first sublayer SL1 and the second sublayer PL1 (or include the first sublayer SL1, the second sublayer PL1, and the first sublayer SL2). Specifically, by using the first sublayer (SL1 / SL2…) in the insulating structure 27 as an etch barrier layer, the thickness of the first extension 271 and the second extension 272 can be easily controlled, improving thickness uniformity and contributing to increased structural stability. In some embodiments, when the first extension 271 and / or the second extension 272 includes a DBR structure, the probability of breakage at the first extension 271 or the second extension 272 during subsequent transfer of the semiconductor element 20 can be increased due to the multi-layer interface in the DBR structure.

[0072] Reference Figure 1A , Figure 1B and Figure 1C The semiconductor element 20 may optionally further include conductive connection layers 30 and 32, which are respectively disposed on the second semiconductor structure 25 and the first semiconductor structure 23. For example, the conductive connection layers 30 and 32 may comprise transparent conductive oxides, such as indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (ITZO), antimony tin oxide (ATO), or antimony zinc oxide (AZO). The conductive connection layers 30 and 32, for example, facilitate current diffusion in the semiconductor element 20 and / or form good contact (such as ohmic contact) with the semiconductor stack 21.

[0073] Reference Figure 1A , Figure 1B and Figure 1CThe semiconductor element 20 may further include electrodes 50 and 52. Electrode 50 may be electrically connected to the second semiconductor structure 25, and electrode 52 may be electrically connected to the first semiconductor structure 23. Electrodes 50 and 52 may comprise, for example, metals or alloys, or combinations thereof. For example, metals may include germanium (Ge), beryllium (Be), zinc (Zn), gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), or copper (Cu). Alloys may comprise at least two of the above metals, such as germanium-gold-nickel (GeAuNi), beryllium-gold (BeAu), germanium-gold (GeAu), zinc-gold (ZnAu), etc.

[0074] like Figure 1A As shown, in this embodiment, for example, through the material combination of the main body 27C, the first extension 271 and the second extension 272, and / or the relative relationship between the thickness T271, the thickness T27C and the thickness T272, the first extension 271 and the second extension 272 can be easily disconnected in the subsequent semiconductor element 20 manufacturing process, thereby improving the success rate of transferring the semiconductor element 20.

[0075] like Figure 1A As shown, a portion of the semiconductor element 20 is disposed within the cavity 60C. Another portion of the semiconductor element 20 may extend vertically beyond the upper surface 611 of the first support pillar 61 or the upper surface 621 of the second support pillar 62. Specifically, a portion of the second semiconductor structure 25, the conductive connection layer 30, the electrode 50, and a portion of the insulating structure 27 of the semiconductor element 20 may be disposed within the cavity 60C, while other portions of the semiconductor element 20 extend upward beyond the upper surface 611 (or upper surface 621). The insulating structure 27 covers the sidewalls of the second semiconductor structure 25, a portion of the sidewalls of the first semiconductor structure 23, and the sidewalls and a portion of the bottom surface of the conductive connection layer 30. Figure 1A As shown, the sidewall 61S of the first support post 61 may selectively have a roughened structure (not shown) facing the semiconductor stack 21. Similarly, in some embodiments, the sidewall 62S of the second support post 62 may selectively have a roughened structure (not shown), and the sidewall 62S faces the semiconductor stack 21.

[0076] Figures 3A to 3H These are partial cross-sectional views illustrating various stages of manufacturing a semiconductor device 100 according to some embodiments of the present invention. Similarly, for the sake of brevity, Figures 3A to 3H Some components of the semiconductor device 100 are omitted. For example... Figure 3AAs shown, in some embodiments, a semiconductor layer 22, a first semiconductor structure 23, an active region 24, and a second semiconductor structure 25 are sequentially formed on a growth substrate 10. For example, the growth substrate 10 is sapphire (PSS), gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), or gallium nitride (GaN). The growth substrate 10 may optionally include a patterned surface, and the semiconductor layer 22 is formed directly on the patterned surface.

[0077] Semiconductor layer 22 can be an undoped semiconductor layer or a lightly doped semiconductor layer (e.g., dopant concentration less than 1 × 10⁻⁶). 17 cm -3 Semiconductor layer 22, first semiconductor structure 23, active region 24, and second semiconductor structure 25 are sequentially formed on growth substrate 10 using epitaxial growth processes. For example, the epitaxial growth process may include metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), or a combination thereof. Next, a conductive interconnect layer 30 is formed on the second semiconductor structure 25. For example, the conductive interconnect layer 30 can be formed using deposition processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, evaporation, sputtering, or a combination thereof.

[0078] Next, as Figure 3BAs shown, in some embodiments, a portion of the first semiconductor structure 23, the active region 24, the second semiconductor structure 25, and the conductive interconnect layer 30 is removed to form a platform region M on the first semiconductor structure 23. Specifically, this can be accomplished by forming a mask layer (not shown) on the conductive interconnect layer 30 through a deposition process, and performing a patterning process (e.g., an etching process) on the mask layer. The aforementioned deposition process includes, for example, spin-on coating, chemical vapor deposition, or atomic layer deposition, or a combination thereof. The aforementioned etching process may include dry etching, wet etching, or a combination thereof. For example, a dry etching process may include reactive ion etching (RIE), inductively coupled plasma (ICP) etching, neutron beam etching (NBE), electron cyclotron resonance (ERC) etching, or a combination thereof. For example, a wet etching process may use, for example, hydrofluoric acid (HF), ammonium hydroxide (NH4OH), or any suitable etchant.

[0079] like Figure 3C As shown, in some embodiments, an insulating structure 27 is formed on the platform region M. The insulating structure 27 can be formed by a deposition process and a patterning process. Then, an opening 27H is formed in the insulating structure 27 to expose a portion of the surface of the conductive interconnect layer 30.

[0080] like Figure 3D As shown, in some embodiments, an electrode 50 is formed on the conductive interconnect layer 30 and the insulating structure 27. The electrode 50 fills the opening 27H. Next, a sacrificial layer PR1 is formed on the electrode 50 and the insulating structure 27. The electrode 50 and the sacrificial layer PR1 can be formed by the aforementioned deposition process.

[0081] like Figure 3E As shown, a bonding fabrication process is performed, in which the sacrificial layer PR1 and the like are bonded to the substrate 12 via the support layer 60. The support layer 60 can directly contact the sacrificial layer PR1 and the insulating structure 27. Figure 3F As shown, an electrode 52 and a conductive connection layer 32 are formed on the first semiconductor structure 23. Similarly, the electrode 52 and the conductive connection layer 32 can be formed by the aforementioned deposition process.

[0082] like Figure 3GAs shown, a portion of the conductive interconnect layer 32 and the first semiconductor structure 23 is removed to expose the insulating structure 27. Next, in some embodiments, a mask layer PR2 is formed over the conductive interconnect layer 32, the first semiconductor structure 23, and a portion of the insulating structure 27. Then, the insulating structure 27 is patterned using the mask layer PR2 as an etching mask to give the insulating structure 27 one or more extensions (see reference). Figure 1B ).

[0083] like Figure 3H As shown, the mask layer PR2 is removed, and the sacrificial layer PR1 may be further removed to form a cavity 60C between the electrode 50 and the support layer 60. In some embodiments, the insulating structure 27 may be selectively further thinned so that the thickness of the first extension 271 and the second extension 272 is less than the thickness T27C of the main body 27C (see reference). Figure 1A The thinning step described above can be performed, for example, by the aforementioned etching process (such as ICP). The roughened structures of sidewalls 61S and 62S are formed, for example, during the thinning step described above. According to some embodiments, the volume of cavity 60C can be further increased through the thinning step described above, which also helps to improve the transfer success rate of semiconductor device 20.

[0084] In the foregoing embodiment, the example is that the insulating structure 27 of the semiconductor device 100 has two extensions (e.g., a first extension 271 and a second extension 272). Figure 4A and Figure 4B This is a partial top view of a semiconductor device 100 according to some embodiments of the present invention. Figure 4A and Figure 4B As shown, in some embodiments, the insulating structure 27 further includes a third extension 273 and a fourth extension 274. Figure 4A In the top view shown, the semiconductor element 20 is a quadrilateral (e.g., a rectangle, a square), and the first extension 271, the second extension 272, the third extension 273, and the fourth extension 274 extend outward from the center of the four sides of the quadrilateral and connect to the support layer 60. Figure 4B In the top view shown, the semiconductor element 20 is a quadrilateral (e.g., a rectangle or a square), and the first extension 271, the second extension 272, the third extension 273, and the fourth extension 274 extend outward from the four corners of the quadrilateral and connect to the support layer 60. The number and shape of the extensions of the insulating structure 27 can be adjusted according to actual needs.

[0085] Figure 5This is a partial top view of a semiconductor device 100 according to some embodiments of the present invention, obtained by scanning electron microscopy (SEM) analysis. Figure 5 As shown, multiple semiconductor elements 20 can be arranged in an array. There are gaps between semiconductor elements 20 in the same row, and semiconductor elements 20 in different rows are separated by a support layer 60. For clarity of the structure below, the first and third semiconductor elements 20 in the third row are removed. Figure 5 As shown, in some embodiments, the support layer 60 has a first surface 60S1 and a second surface 60S2. Specifically, the first surface 60S1 corresponds to the position below each semiconductor element 20, and the second surface 60S2 corresponds to the gap position between semiconductor elements 20 in the same row. The first surface 60S1 and the second surface 60S2 are not flush. That is, the first surface 60S1 may be located below the semiconductor element 20, the second surface 60S2 may not be covered by the semiconductor element 20, and the first surface 60S1 is higher than the second surface 60S2 in the vertical direction. In detail, in such embodiments... Figure 3G , Figure 3H In the process, because a portion of the support layer 60 is protected by the semiconductor element 20 and the mask layer PR2 above it, the first surface 60S1 is higher than the second surface 60S2, which is not protected, after the sacrificial layer PR1 is removed.

[0086] Figure 6 This is a partially enlarged view of a semiconductor device 100 according to some embodiments of the present invention, obtained by SEM analysis, showing the connection between the insulating structure 27 and the semiconductor element 20. Figure 6 As shown, in some embodiments, the first extension 271 of the insulating structure 27 may have one or more voids 271V. During the subsequent fabrication process of transferring the semiconductor element 20, the voids 271V can make it easier for the semiconductor element 20 to break off from the first extension 271. Similarly, the second extension 272 of the insulating structure 27 may also have one or more voids (not shown), which will not be described in detail here.

[0087] Figures 7A to 7F The diagram illustrates the relative positions of the semiconductor element 20, the insulating structure 27 (which may include one or more first extensions 271 and one or more second extensions 272), and the support layer 60 (which may include first support pillars 61 and second support pillars 62) in a top view, according to different embodiments.

[0088] like Figure 7A , Figure 7B and Figure 7CAs shown in the top view, in some embodiments, the first extension 271 and the second extension 272 of the insulating structure 27 are located on opposite sides of the semiconductor element 20. Specifically, Figure 7A The first extension 271 and the second extension 272 are located at the center of both sides of the semiconductor element 20, respectively. Figure 7B and Figure 7C The first extension 271 is located on the upper left side of the semiconductor element 20, while the second extension 272 is located on the lower right side of the semiconductor element 20.

[0089] exist Figure 7A , Figure 7B and Figure 7C In the illustrated embodiment, the width of the first extension 271 gradually increases from the semiconductor element 20 to the first support post 61, and the width of the second extension 272 gradually increases from the semiconductor element 20 to the second support post 62, thereby making it easier for the semiconductor element 20 to be disconnected from the narrower side of the first extension 271 and the second extension 272 during subsequent transfer fabrication processes (e.g., transfer printing).

[0090] like Figure 7D , Figure 7E and Figure 7F As shown in the top view, in some embodiments, a plurality of (e.g., four) semiconductor elements 20 are arranged in an array. Figure 7D and Figure 7E The first extension 271 and the second extension 272 of the insulating structure 27 are located on both sides of each individual semiconductor element 20. Specifically, Figure 7D The first extension 271 and the second extension 272 are respectively located at the center of both sides of the corresponding semiconductor element 20; Figure 7E The first extension 271 is located on the upper left side of the corresponding semiconductor element 20, while the second extension 272 is located on the lower right side of the corresponding semiconductor element 20. Figure 7F The semiconductor element 20 has a first extension 271, a second extension 272, a third extension 273, and a fourth extension 274. The first extension 271 is located at the upper left corner of the corresponding semiconductor element 20, the second extension 272 is located at the upper right corner of the corresponding semiconductor element 20, the third extension 273 is located at the lower right corner of the corresponding semiconductor element 20, and the fourth extension 274 is located at the lower left corner of the corresponding semiconductor element 20. The number and position of the extensions of the insulating structure 27 can be adjusted according to actual needs.

[0091] Similarly, in Figure 7D , Figure 7E and Figure 7FIn the illustrated embodiment, the width of each extension (first extension 271, second extension 272, third extension 273, and fourth extension 274) can gradually widen from the direction closest to the semiconductor element 20 to the direction furthest away from the semiconductor element 20. This makes it easier for the semiconductor element 20 to be transferred from the side closest to the semiconductor element 20 during subsequent transfer fabrication processes (e.g., transfer printing). Figure 7D , Figure 7E and Figure 7F The multiple dashed lines (E) in the diagram are broken. In some embodiments, this design helps to reduce the extensions remaining on the semiconductor element 20 after transfer.

[0092] Figure 8 This is a partial cross-sectional view of a semiconductor device 102 according to some embodiments of the present invention. Similarly, for the sake of brevity, Figure 8 Some components of the semiconductor device 102 have been omitted.

[0093] like Figure 8 As shown, the semiconductor device 102 includes one or more semiconductor elements 20'. Each semiconductor element 20' includes a semiconductor stack 21 and an insulating structure 27. In this embodiment, the insulating structure 27 is disposed on the semiconductor stack 21. Figure 8 As shown, the main body 27C covers the semiconductor stack 21. Sidewalls 61S and 62S may be inclined surfaces. More specifically, in this embodiment, the semiconductor stack 21 includes a first semiconductor structure 23, an active region 24, and a second semiconductor structure 25. In this embodiment, the first semiconductor structure 23 is closer to the substrate 12 than the second semiconductor structure 25. The semiconductor element 20' may also include conductive connection layers 30 and 32, which are respectively disposed on the second semiconductor structure 25 and the first semiconductor structure 23. The semiconductor element 20' may also include an electrode 50. The electrode 50 may be electrically connected to the first semiconductor structure 23. Optionally, the semiconductor element 20' may further include, for example,... Figure 1A The electrode 52 (not shown) is disposed, for example, on the conductive connection layer 30. In some embodiments, when the electrode 50 can form good contact (such as an ohmic contact) directly with the first semiconductor structure 23, the conductive connection layer 32 may be omitted from the semiconductor element 20'.

[0094] like Figure 8As shown, a portion of the first semiconductor structure 23, the conductive connection layer 32, and the electrode 50 are disposed in the cavity 60C, while other portions of the semiconductor element 20 extend upward beyond the upper surface 611 of the first support pillar 61 (or the upper surface 621 of the first support pillar 62). The insulating structure 27 is also disposed to extend beyond the upper surface 611 (or the upper surface 621) and cover the sidewalls 25S of the second semiconductor structure 25, the sidewalls 24S of the active region 24, a portion of the sidewalls 23S1 of the first semiconductor structure 23, and the sidewalls 30S and a portion of the top surface 30T of the conductive connection layer 30.

[0095] In this embodiment, the semiconductor element 20' further selectively includes a protective layer 70. The protective layer 70 is disposed in the cavity 60C. The protective layer 70 covers another portion of the sidewall 23S2 of the first semiconductor structure 23 and the sidewall 32S and a portion of the bottom surface 32B of the conductive connection layer 32. In other words, a portion of the protective layer 70 may be located between the conductive connection layer 32 and the electrode 50. The protective layer 70 has an opening 70H. The electrode 50 may be filled into the opening 70H to achieve electrical connection with the conductive connection layer 32 and the first semiconductor structure 23. The positions, relative relationships, material compositions, and structural variations of each layer or structure in this embodiment have been described in detail in previous embodiments and will not be repeated here.

[0096] Figures 9A to 9H These are partial cross-sectional views illustrating various stages of manufacturing the semiconductor device 102 according to some embodiments of the present invention. Similarly, for the sake of brevity, Figures 9A to 9H Some components of the semiconductor device 102 are omitted.

[0097] like Figure 9A As shown, in some embodiments, a semiconductor layer 22, a first semiconductor structure 23, an active region 24, and a second semiconductor structure 25 are sequentially formed on a growth substrate 10. Next, a conductive interconnect layer 30 is formed on the second semiconductor structure 25, and a portion of the first semiconductor structure 23, the active region 24, the second semiconductor structure 25, and the conductive interconnect layer 30 is removed to form a platform region M on the first semiconductor structure 23. Then, an insulating structure 27 is formed on the first semiconductor structure 23, the second semiconductor structure 25, and the conductive interconnect layer 30. An opening 27H is formed in the insulating structure 27 to expose a portion of the top surface of the conductive interconnect layer 30.

[0098] Then, as Figure 9BAs shown, in some embodiments, the insulating structure 27 and the conductive connection layer 30 are bonded to the temporary carrier 11 via a dielectric layer 60'. The dielectric layer 60' may comprise a polymer material, such as benzocyclobutene (BCB), epoxy resin, polyimide, or silicone resin, alumina (Al2O3), silicon oxide (SiO2), etc. The temporary carrier 11 may comprise a sapphire substrate or a glass substrate.

[0099] like Figure 9C As shown, in some embodiments, the growth substrate 10 and the semiconductor layer 22 are removed. For example, a laser lift-off (LLO) fabrication process can be performed to remove the growth substrate 10 and the semiconductor layer 22. Then, as... Figure 9D As shown, a conductive connection layer 32 may be formed on the first semiconductor structure 23. The conductive connection layer 32 is formed, for example, by the aforementioned deposition process. In some embodiments, the conductive connection layer 32 and a portion of the first semiconductor structure 23 are removed to expose the insulating structure 27 and form a platform region M'. Optionally, after forming the conductive connection layer 32, a protective layer 70 covering the first semiconductor structure 23 and the conductive connection layer 32 may be formed, for example, by the aforementioned deposition process.

[0100] After that, as Figure 9E As shown, an electrode 50 and a sacrificial layer PR1 can be sequentially formed on the conductive connection layer 32 and the first semiconductor structure 23, and the electrode 50 can be electrically connected to the first semiconductor structure 23. The electrode 50 and the sacrificial layer PR1 can be formed by the aforementioned deposition process.

[0101] like Figure 9F As shown, a bonding fabrication process is performed, in which the sacrificial layer PR1 and the like are bonded to the substrate 12 via the support layer 60. The support layer 60 can directly contact the sacrificial layer PR1 and the insulating structure 27. Then, as... Figure 9G As shown, the dielectric layer 60' and the temporary carrier plate 11 are removed. Then, as... Figure 9H As shown, the sacrificial layer PR1 is removed. According to some embodiments, before removing the sacrificial layer PR1, a mask layer PR2 may be formed over the conductive interconnect layer 30, the second semiconductor structure 25, and a portion of the insulating structure 27 (see the aforementioned embodiments). Then, the insulating structure 27 is patterned using the mask layer PR2 as an etching mask to give the insulating structure 27 one or more extensions (see...). Figure 1B Then remove the mask layer PR2.

[0102] In some embodiments, the insulating structure 27 may be selectively further thinned to form, as... Figure 8The semiconductor device 102 shown above. The thinning step described above can be performed, for example, by the aforementioned etching process (such as ICP). The roughened structures of sidewalls 61S and 62S are formed, for example, during the thinning step described above. According to some embodiments, the volume of cavity 60C can be further increased through the thinning step described above, which also helps to improve the transfer success rate of semiconductor element 20'. The positions, relative relationships, material compositions, and structural variations of each layer or structure in this embodiment have been described in detail in the previous embodiments and will not be repeated here.

[0103] Figure 10 This is a partial cross-sectional view of a semiconductor device 104 according to some embodiments of the present invention. Similarly, for the sake of brevity, Figure 10 Some components of the semiconductor device 104 are omitted.

[0104] Figure 10 The semiconductor device 104 shown has a similar Figure 8 The semiconductor device 102 shown has a similar structure. Figure 10 As shown, semiconductor device 104 includes at least one semiconductor element 20". Semiconductor element 20" includes a semiconductor stack 21 and an insulating structure 27. The difference between semiconductor device 104 and semiconductor device 102 lies in the appearance of the semiconductor stack 21 and the configuration of the protective layer 70 and the insulating structure 27. In semiconductor device 104, the insulating structure 27 is disposed in cavity 60C and covers a portion of the sidewall 23S1 of the first semiconductor structure 23, the sidewall 32S of the conductive connection layer 32, and a portion of the bottom surface 32B. In other words, a portion of the insulating structure 27 may be located between the conductive connection layer 32 and the electrode 50. The insulating structure 27 exposes a portion of the conductive connection layer 32 so that the electrode 50 can be electrically connected to the first semiconductor structure 23. In this embodiment, the protective layer 70 covers the sidewall 25S of the second semiconductor structure 25, the sidewall 24S of the active region 24, another portion of the sidewall 23S2 of the first semiconductor structure 23, and the sidewall 30S and a portion of the top surface 30T of the conductive connection layer 30. The positions, relative relationships, material composition, and structural variations of each layer or structure in this embodiment have been described in detail in previous embodiments and will not be repeated here.

[0105] Figure 11A , Figure 11B and Figure 11C These are partial cross-sectional views of semiconductor devices 1, 2, and 3 according to some embodiments of the present invention. Similarly, for the sake of brevity, ... Figure 11A , Figure 11B and Figure 11C Some components of semiconductor devices 1, 2, and 3 have been omitted. Figure 11A , Figure 11B and Figure 11CProvide another type of semiconductor device, for example, applicable to transfer technology.

[0106] like Figure 11A As shown, in this embodiment, the semiconductor device 1 includes a substrate 80 and a support member 82, with the support member 82 disposed on the substrate 80. The semiconductor device 1 includes a first semiconductor element 201 and a second semiconductor element 202. In this embodiment, the first semiconductor element 201 and the second semiconductor element 202 may not have the aforementioned insulating structure 27. The material of the substrate 80 can refer to the aforementioned substrate 12. The material of the support member 82 can refer to the aforementioned support layer 60. In the first semiconductor element 201 and the second semiconductor element 202, a protective layer 70 covers the semiconductor stack 21 and has a first opening 701 and a second opening 702. The conductive connection layer 30 can be exposed through the first opening 701, and the conductive connection layer 32 and the electrode 50 can be exposed through the second opening 702. Figure 11A In the illustrated embodiment, the support member 82 has a protruding portion 820, and a first semiconductor element 201 and a second semiconductor element 202 are respectively connected to both sides of the protruding portion 820 of the support member 82. Figure 11A As shown, the first semiconductor element 201 and the second semiconductor element 202 are in direct contact with the protrusion 820, thereby maintaining the position of the first semiconductor element 201 and the second semiconductor element 202 and improving the success rate of the first semiconductor element 201 and the second semiconductor element 202 in subsequent transfer.

[0107] like Figure 11B As shown, in this embodiment, the semiconductor device 2 includes a substrate 80 and a support member 82, with the support member 82 disposed on the substrate 80. Figure 11B In the illustrated embodiment, the support member 82 includes a first protrusion 821 and a second protrusion 822. The first protrusion 821 and the second protrusion 822 are spaced apart and do not directly contact each other. A first semiconductor element 201 and a second semiconductor element 202 are respectively connected to the first protrusion 821 and the second protrusion 822.

[0108] like Figure 11C As shown, in this embodiment, the semiconductor device 3 includes a substrate 80 and a support member 82, with the support member 82 disposed on the substrate 80. Figure 11C In the illustrated embodiment, the support member 82 includes cavities 82C1 and 82C2. A first semiconductor element 201 and a second semiconductor element 202 can be respectively disposed corresponding to cavities 82C1 and 82C2. In the first semiconductor element 201 and the second semiconductor element 202, since both side surfaces are in direct contact with the support member 82, compared to… Figure 11A , Figure 11BThe embodiments may have a more stable connection. Regarding Figure 11A , Figure 11B and Figure 11C The positions, relative relationships, material composition, and structural variations of each layer or structure in the embodiments have been described in detail in the previous embodiments and will not be repeated here.

[0109] Figure 12A This is a partial cross-sectional view of a semiconductor device 106 according to some embodiments of the present invention. Figure 12B This is a partial top view of a semiconductor device 106 according to some other embodiments of the present invention. Figure 12A The cross-sectional view shown is Figure 12B The top view shown is not a perfect correspondence. Specifically, Figure 12A For example is Figure 12B A schematic cross-sectional view along line B-B'. For simplicity, in... Figure 12A and Figure 12B Some components of the semiconductor device 106 have been omitted (for example, the cross-section along line B-B' passes through 6 semiconductor elements 20, but...). Figure 12A Only three semiconductor elements 20 are shown.

[0110] like Figure 12A As shown, in some embodiments, the semiconductor device 106 includes a substrate 12 and a support layer 60 disposed on the substrate 12. In a cross-section, the support layer 60 has a first support pillar 61 and a second support pillar 62 separated from each other. The semiconductor device 102 also includes a plurality of semiconductor elements 20, each semiconductor element including a semiconductor stack 21 and an insulating structure 27 disposed on the semiconductor stack 21. The insulating structure 27 has a main body portion 27C and a first extension portion 271 and a second extension portion 272 separated from each other. The main body portion 27C is covered by the semiconductor stack 21. The first extension portion 271 and the second extension portion 272 extend outward from the main body portion 27C to the first support pillar 61 and the second support pillar 62, respectively, and are respectively connected to the first support pillar 61 and the second support pillar 62. The thickness of the first extension portion 271 (and the thickness of the second extension portion 272) is less than the thickness of the main body portion 27C.

[0111] In this embodiment, the semiconductor device 106 further includes a connection layer 84. The connection layer 84 is, for example, a semiconductor layer. In some embodiments, the connection layer 84 may comprise a binary III-V semiconductor material (such as GaN, GaAs, or GaP). Figure 12A As shown, the interconnect layer 84 is disposed on a plurality of semiconductor elements 20 and connects these semiconductor elements 20 together. That is, the interconnect layer 84 covers and directly contacts the semiconductor stack 21 in each semiconductor element 20. Figure 12AAs shown, multiple semiconductor elements 20 can be connected to each other through the interconnect layer 84, and multiple semiconductor elements 20 can share the first extension 271 and the second extension 272.

[0112] like Figure 12B As shown, in this embodiment, each interconnect layer 84 in the semiconductor device 106 can correspond to twenty semiconductor elements 20. If one interconnect layer 84 and the multiple semiconductor elements 20 connected to it are considered as a group, in... Figure 12B The image shows four groups of semiconductor elements 20. Each group of semiconductor elements 20 can be connected to the support layer 60 through its own insulating structure 27. In this embodiment, the semiconductor device 106 may further include alignment marks 86. Figure 12B As shown, alignment marks 86 can be located on the interconnect layer 84. For example, from a top view, an alignment mark 86 can be provided at each corner of each group of semiconductor elements 20. With this arrangement, during the subsequent transfer of semiconductor elements 20, multiple semiconductor elements 20 can be transferred simultaneously as a group, and the alignment marks 86 can be used to align the semiconductor elements 20 to specific positions at the transfer destination. This further improves transfer efficiency. On the other hand, since multiple semiconductor elements 20 in the same group can be connected to each other through the insulating structure 27 and the interconnect layer 84, aisle space can be saved compared to multiple separate semiconductor elements 20, which is beneficial for applications that require further reduction in element spacing.

[0113] Figure 13 This is a schematic cross-sectional view of a semiconductor component 4 according to some embodiments of the present invention, for example, a partial cross-sectional view of the aforementioned semiconductor device 106 transferred into a semiconductor substrate 90 (e.g., a CMOS backplane). Similarly, for the sake of brevity, Figure 13 Some components of semiconductor component 4 are omitted.

[0114] like Figure 13As shown, in some embodiments, semiconductor component 4 includes a semiconductor substrate 90. The semiconductor substrate 90 may be a bulk semiconductor substrate or a composite substrate formed of different materials. For example, the semiconductor substrate 90 may be formed of elemental semiconductors (e.g., silicon or germanium), compound semiconductors (e.g., silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)), alloy semiconductors (e.g., SiGe, SiGeC, GaAsP, or GaInP), or combinations thereof. The semiconductor substrate 90 may be a semiconductor-on-insulator (SOI) substrate. The aforementioned SOI substrate may include a substrate, a buried oxide layer disposed on the substrate, and a semiconductor layer disposed on the buried oxide layer. Alternatively, the semiconductor substrate 90 may be a semiconductor wafer (e.g., a silicon wafer or other suitable semiconductor wafer).

[0115] The semiconductor substrate 90 may also include various p-type and / or n-type doped regions formed by processes such as ion implantation and / or diffusion. For example, the aforementioned doped regions may be configured to form transistors, photodiodes, and / or light-emitting diodes. The semiconductor substrate 90 may include various isolation features, such as, but not limited to, shallow trench isolation (STI) components, to separate different device regions within the semiconductor substrate 90. The step of forming shallow trench isolation may include etching trenches in the semiconductor substrate 90 and filling the trenches with an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride). The filled trenches may have a multilayer structure (e.g., a thermally oxidized substrate and silicon nitride filling the trenches). A chemical mechanical polishing (CMP) process may be performed to remove excess insulating material and planarize the upper surface of the isolation components.

[0116] The semiconductor substrate 90 may include various conductive components (e.g., conductive lines or vias). For example, the aforementioned conductive components may be formed of aluminum (Al), copper (Cu), tungsten (W), their respective alloys, or combinations thereof. In this embodiment, the semiconductor substrate 90 includes a plurality of conductive pads 92, and a plurality of semiconductor elements 20 connected by a connection layer 84 can be transferred over the semiconductor substrate 90 and connected to the corresponding conductive pads 92 via electrodes of the semiconductor elements 20, thereby electrically connecting the semiconductor elements 20 to the semiconductor substrate 90.

[0117] like Figure 13As shown, in some embodiments, the semiconductor component 4 further includes an underfill material 94. The underfill material 94 is located between the semiconductor substrate 90 and the semiconductor element 20 (or the interconnect layer 84) to fill the gap between the semiconductor substrate 90 and the semiconductor element 20, thereby preventing moisture or dust from entering the semiconductor element 20, protecting the semiconductor component 4 and improving the overall yield.

[0118] In summary, embodiments of the present invention provide a semiconductor device that can improve transfer success rate and structural stability through fabrication processes and structural design. The semiconductor device according to embodiments of the present invention is suitable for mass transfer of miniature light-emitting diode (LED) chips and can improve stress distribution during the transfer process, reducing the risk of structural deformation, thereby improving manufacturing efficiency and product yield. According to some embodiments of the present invention, the semiconductor device may include an extension. The extension can be part of the insulating structure in the semiconductor element, eliminating the need for additional components, effectively reducing costs and simplifying fabrication steps.

[0119] The semiconductor element described in this invention can be applied to products in the fields of lighting, display, communication, and power systems, such as lamps, monitors, automotive dashboards, televisions, computers, traffic lights, and outdoor displays.

[0120] Although the present invention has been disclosed above with reference to embodiments, some modifications or changes may be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. The above embodiments can be combined or substituted with each other where appropriate, and are not limited to the specific embodiments described. For example, the relevant parameters of specific components or the connection relationships between specific components and other components disclosed in some embodiments can also be applied to other embodiments, and all fall within the scope of protection of the present invention.

Claims

1. A semiconductor device, comprising: substrate; A support layer is disposed on the substrate, wherein, in cross-section, the support layer has a first support pillar and a second support pillar that are separated from each other; as well as At least one semiconductor element, comprising: Semiconductor stacking; and An insulating structure is disposed on the semiconductor stack, wherein the insulating structure has a main body and a first extension and a second extension separated from each other, the main body covers the semiconductor stack, the first extension and the second extension extend outward from the main body to the first support post and the second support post respectively, and the thickness of the first extension is less than the thickness of the main body.

2. The semiconductor device of claim 1, wherein the main body and the first extension have different compositions.

3. The semiconductor device of claim 2, wherein the cover layer comprises at least two first sublayers and at least one second sublayer disposed between the first sublayers.

4. The semiconductor device of claim 3, wherein the thicknesses of the first sublayers are different.

5. The semiconductor device of claim 3, wherein the first sublayer comprises Al2O3 and the second sublayer comprises SiO2 or TiO2.

6. The semiconductor device of claim 1, wherein the first support pillar has a roughened sidewall facing the semiconductor stack.

7. The semiconductor device of claim 1, wherein the support layer has a first surface and a second surface, the first surface being located below the semiconductor element, the second surface being not covered by the semiconductor element, and the first surface being higher than the second surface.

8. The semiconductor device of claim 1, wherein the first extension has a cavity.

9. The semiconductor device of claim 1, wherein, in a top view, the first extension and the second extension are respectively located on both sides or at two corners of the semiconductor element.

10. The semiconductor device of claim 1, wherein, in a top view, the width of the first extension gradually increases from the semiconductor element to the first support post.

Images