Panel structure and light emitting device using the same

Abstract

A board structure includes a substrate and an insulating layer disposed on the substrate and having a plurality of recesses. The board structure also includes a conductive layer disposed on the insulating layer. The conductive layer has a reserved space that exposes a portion of the insulating layer, and the recesses are located within the reserved space.

Description

Technical Field

[0001] This disclosure relates to a plate structure and a light-emitting device using the same, and more particularly to a plate structure that can increase the adhesion between a wafer and a substrate and a light-emitting device using the same. Background Technology

[0002] The combination of light-emitting diodes (LEDs) and lenses has been widely used in backlight modules. With technological advancements, the requirements for local dimming have increased, leading to the emergence of new backlight modules that combine chips on board (COB) packages with lenses using adhesive bonding. COB LED strip chips can be directly mounted on printed circuit boards, and a highly transparent adhesive is applied over these chips. After high-temperature curing, a lens-like structure is formed to widen the light divergence angle.

[0003] However, while this method simplifies the production process and reduces costs, it may result in insufficient adhesion between the adhesive and the printed circuit board. Especially during the transportation or assembly of the light strip, the adhesive is prone to detachment, affecting the product's reliability and lifespan. Summary of the Invention

[0004] This disclosure provides a sheet material structure that includes an insulating layer with multiple recesses, which enables the adhesive to have stronger adhesion when glue is subsequently applied to the sheet material structure, thereby increasing the reliability of the light-emitting device using this sheet material structure.

[0005] According to some embodiments of this disclosure, a sheet metal structure is provided. The sheet metal structure includes a substrate and an insulating layer, the insulating layer being disposed on the substrate and having a plurality of recesses. The sheet metal structure further includes a conductive layer, the conductive layer being disposed on the insulating layer. The conductive layer has a reserved space, the reserved space exposing a portion of the insulating layer, and the recesses are located within the reserved space.

[0006] According to some embodiments of this disclosure, a light-emitting device is provided. The light-emitting device includes a substrate and an insulating layer, the insulating layer being disposed on the substrate and having a plurality of recesses. The light-emitting device also includes a conductive layer disposed on the insulating layer. The conductive layer has a reserved space that exposes a portion of the insulating layer, and the recesses are located within the reserved space. The light-emitting device further includes a light-emitting chip disposed within the reserved space and electrically connected to the conductive layer. Furthermore, the light-emitting device includes a reflective layer disposed on the insulating layer and the conductive layer and filling the recesses. The reflective layer exposes the light-emitting chip. Attached Figure Description

[0007] Figure 1 This is a partial top view illustrating a plate structure according to some embodiments of the present disclosure.

[0008] Figure 2 This is a partial cross-sectional view of a plate structure according to some embodiments of the present disclosure.

[0009] Figure 3 This is a partial top view of a light-emitting device according to some embodiments of the present disclosure.

[0010] Figure 4 This is a partial cross-sectional view of a light-emitting device according to some embodiments of the present disclosure.

[0011] The attached figures are labeled as follows:

[0012] 1: Light-emitting device

[0013] 100: Panel Structure

[0014] 10:Substrate

[0015] 20: Insulation layer

[0016] 20R: concave part

[0017] 20S: Solder mask layer

[0018] 20T: Top surface

[0019] 30: Conductive layer

[0020] 30C: Reserved space

[0021] 30E: Conductive connection part

[0022] 30P: Conductive pad

[0023] 301: Area 1

[0024] 302: Second Zone

[0025] 40: Light-emitting chip

[0026] 50: Reflective layer

[0027] 60: Lens structure

[0028] D20R: Depth of recess

[0029] S: Axis of symmetry

[0030] T20: Thickness of the insulation layer

[0031] T30: Thickness of the conductive layer

[0032] A-A': line Detailed Implementation

[0033] Figure 1 This is a partial top view of a plate structure 100 according to some embodiments of the present disclosure. Figure 2This is a partial cross-sectional view of a plate structure 100 according to some embodiments of the present disclosure. For example, Figure 2 For example, along Figure 1 The cross-sectional view shown by line A-A' is not limited to the embodiments disclosed herein. It should be noted that, for simplicity, Figure 1 and Figure 2 The components in the document may not correspond exactly, and Figure 1 and Figure 2 Some components of the plate structure 100 have been omitted.

[0034] Reference Figure 1 and Figure 2 In some embodiments, the substrate structure 100 includes a substrate 10 and an insulating layer 20 disposed on the substrate 10 and having a plurality of recesses 20R. For example, the substrate 10 may be a rigid circuit substrate, which may contain elemental semiconductors (e.g., silicon or germanium), compound semiconductors (e.g., silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)), alloy semiconductors (e.g., SiGe, SiGeC, GaAsP, or GaInP), other suitable semiconductors, or combinations thereof. Alternatively, the substrate 10 may also be a flexible circuit substrate, a semiconductor-on-insulator (SOI) substrate, or a glass substrate, etc. The substrate 10 may contain various conductive components (e.g., conductive lines or vias) (not shown). For example, the aforementioned conductive components may contain aluminum (Al), copper (Cu), tungsten (W), their respective alloys, other suitable conductive materials, or combinations thereof.

[0035] The insulating layer 20 may comprise an insulating material, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), similar materials, or combinations thereof, but this disclosure is not limited thereto. The insulating material may be formed on the substrate 10 by, for example, metal-organic chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, similar processes, or combinations thereof, but this disclosure is not limited thereto. A mask layer (not shown) may be disposed on the insulating layer 20, and then the mask layer may be used as an etching mask for an etching process to etch a plurality of recesses 20R into the insulating layer 20. The mask layer may comprise a photoresist, such as a negative photoresist or a positive photoresist. For example, the mask layer may comprise a hard mask and may be formed from silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbide nitride (SiCN), similar materials, or combinations thereof. The mask layer may be a single-layer or multi-layer structure.

[0036] The pattern of the mask layer can be adjusted according to actual needs and can be formed by spraying or printing processes. Alternatively, the mask layer can be formed by deposition, photolithography, other suitable processes, or combinations thereof. For example, deposition processes include spin-on coating, chemical vapor deposition, atomic layer deposition, similar processes, or combinations thereof; photolithography processes may include photoresist coating (e.g., spin coating), soft baking, mask aligning, exposure, post-exposure baking (PEB), developing, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. Etching processes may include dry etching, wet etching, or combinations thereof. For example, dry etching processes can include reactive ion etching (RIE), inductively coupled plasma (ICP) etching, neutron beam etching (NBE), electron cyclotron resonance (ERC) etching, similar etching processes, or combinations thereof, while wet etching processes can use, for example, hydrofluoric acid (HF), ammonium hydroxide (NH4OH), or any suitable etchant.

[0037] Before etching the insulating layer 20 to create multiple recesses 20R, the insulating layer 20 can be subjected to plasma treatment to remove surface contaminants and increase its surface energy. For example... Figure 2 As shown, in some embodiments, the thickness T20 of the insulating layer 20 is between about 30 μm and about 35 μm. In some embodiments, the depth D20R of the recess 20R of the insulating layer 20 is between about 10 μm and about 15 μm. Here, the depth D20R of the recess 20R can be defined as the vertical distance from the bottom of the recess 20R to the top surface 20T of the insulating layer 20.

[0038] In this embodiment, in the top view (e.g.) Figure 1 In the top view shown, the recess 20R of the insulating layer 20 is circular, but this embodiment is not limited to this. In some other embodiments, the recess 20R of the insulating layer 20 is elliptical, rectangular, trapezoidal, arbitrary polygonal, or other suitable shape, and the shape of the recess 20R can be changed according to process or other requirements.

[0039] Reference Figure 1 and Figure 2 In some embodiments, the board structure 100 includes a conductive layer 30 disposed on the insulating layer 20. For example... Figure 2 As shown, the conductive layer 30 has a reserved space 30C, which exposes a portion of the insulating layer 20 (e.g., the central portion), and the recess 20R of the insulating layer 20 is located within the reserved space 30C. For example, the conductive layer 30 comprises a conductive material, such as a metal, a metal silicide, similar materials, or a combination thereof. The metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, alloys thereof, or combinations thereof. The conductive layer 30 can be formed on the insulating layer 20 by physical vapor deposition, chemical vapor deposition, atomic layer deposition, evaporation, sputtering, similar processes, or combinations thereof. Furthermore, a mask layer (not shown) may be provided on the conductive layer 30, and then the mask layer may be used as an etching mask for an etching process to etch the reserved space 30C into the conductive layer 30. This will not be repeated here, but the embodiments disclosed herein are not limited thereto.

[0040] like Figure 2 As shown, in some embodiments, the thickness T30 of the conductive layer 30 is between about 30 μm and about 35 μm. Furthermore, as... Figure 1 and Figure 2As shown, the conductive layer 30 includes a conductive pad 30P and a conductive connection portion 30E. The conductive pad 30P is substantially located in (or adjacent to) the center of the conductive layer 30, while the conductive connection portion 30E is located on both sides of the conductive pad 30P. It can be used to electrically connect with the light-emitting chip 40 subsequently formed thereon, but the embodiments disclosed herein are not limited thereto.

[0041] like Figure 1 As shown, in some embodiments, the conductive layer 30 includes a conductive connection portion 30E, which divides the reserved space 30C into a first region 301 and a second region 302. In this embodiment, the first region 301 and the second region 302 are, for example, two vertically arranged rectangular regions. However, the embodiments disclosed herein are not limited to this, and the shape and size of the first region 301 and the second region 302 can be adjusted according to actual needs (e.g., electrical properties, circuit arrangement).

[0042] like Figure 1 As shown, in this embodiment, the plurality of recesses 20R located in the first region 301 and the plurality of recesses 20R located in the second region 302 are arranged symmetrically with respect to the conductive connection portion 30E as the axis of symmetry S. Furthermore, in this embodiment, the number of recesses 20R located in the first region 301 is the same as the number of recesses 20R located in the second region 302, but this embodiment is not limited thereto. The recesses 20R can effectively improve the surface roughness of the insulating layer 20, making the subsequently formed reflective layer 50 (and / or lens structure 60) (see...) more... Figure 3 and Figure 4 The adhesion of the reflective layer 50 (and / or lens structure 60) to the insulating layer 20 is stronger. Furthermore, the arrangement and number of the aforementioned recesses 20R can be adjusted to improve the adhesion of the subsequently formed reflective layer 50 (and / or lens structure 60) (see...). Figure 3 and Figure 4 The adhesion of the insulation layer 20 is more uniform.

[0043] Figure 3 This is a partial top view of the light-emitting device 1 according to some embodiments of the present disclosure. Figure 4 This is a partial cross-sectional view of the light-emitting device 1 according to some embodiments of the present disclosure. For example, Figure 4 For example, along Figure 3 The cross-sectional view shown by line B-B' is not limited to the embodiments disclosed herein. It should be noted that, for simplicity, Figure 3 and Figure 4 The components in the document may not correspond exactly, and Figure 3 and Figure 4 Some components of the light-emitting device 1 have been omitted from the text.

[0044] Reference Figure 3 and Figure 4 In some embodiments, the light-emitting device 1 includes, for example, Figure 1 and Figure 2 The illustrated board structure 100. More specifically, the light-emitting device 1 includes a substrate 10 and an insulating layer 20, the insulating layer 20 being disposed on the substrate 10 and having a plurality of recesses 20R. The light-emitting device 1 also includes a conductive layer 30, the conductive layer 30 being disposed on the insulating layer 20 and having a reserved space 30C. The reserved space 30C exposes a portion of the insulating layer 20, and the recesses 20R are located within the reserved space 30C. Furthermore, the light-emitting device 1 also includes a light-emitting chip 40 and a reflective layer 50. The light-emitting chip 40 is disposed within the reserved space 30C and electrically connected to the conductive layer 30, while the reflective layer 50 is disposed on the insulating layer 20 and the conductive layer 30 and fills the recesses 20R. The reflective layer 50 exposes the light-emitting chip 40.

[0045] The light-emitting chip 40 is, for example, a sub-millimeter light-emitting diode (mini LED) or a micro LED, which may include an N-type semiconductor layer, an active layer, and a P-type semiconductor layer (none shown in detail), with the active layer disposed between the N-type and P-type semiconductor layers. The light emitted by the light-emitting chip 40 is determined by the light-emitting layer. Figure 3 and Figure 4 As shown, in some embodiments, the light-emitting chip 40 is electrically connected to the conductive layer 30 via a conductive connection portion 30E (and / or a conductive pad 30P).

[0046] The N-type semiconductor layer may contain group II-VI materials (e.g., zinc selenide (ZnSe)) or group III-V materials (e.g., gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN)), and the N-type semiconductor layer may contain dopants such as silicon (Si) or germanium (Ge), but the embodiments disclosed herein are not limited thereto.

[0047] The active layer may comprise at least one undoped semiconductor layer or at least one lightly doped layer. For example, the active layer may be a quantum well (QW) layer, which may comprise indium gallium nitride (InGaN). x Ga 1-x The active layer can be gallium nitride (GaN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN). Alternatively, the active layer can also be a multiple quantum well (MQW) layer, but this disclosure is not limited to these embodiments.

[0048] The P-type semiconductor layer may contain group II-VI materials (e.g., zinc selenide (ZnSe)) or group III-V materials (e.g., gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), or aluminum indium gallium nitride (AlInGaN)), and may contain dopants such as magnesium (Mg) and carbon (C), but the embodiments disclosed herein are not limited thereto. Furthermore, the N-type and P-type semiconductor layers may be single-layer or multi-layer structures.

[0049] The reflective layer 50 may comprise a reflective material and a semi-cured (B-stage) adhesive (e.g., a thermosetting resin). The reflective material may comprise, for example, titanium dioxide (TiO2) or silicon dioxide (SiO2). x However, the embodiments disclosed herein are not limited thereto. For example, the reflective layer 50 may be a white semi-cured (B-stage) adhesive. Here, the B-stage adhesive is a two-stage thermosetting adhesive that requires two baking cycles to fully cure. B-stage refers to the reaction between the resin and the curing agent to form a semi-cured solid, which can be fully cured after further heating.

[0050] like Figure 4 As shown, since the reflective layer 50 covers the insulating layer 20, the reflective layer 50 may also include a shape corresponding to the recess 20R. The recess 20R can effectively improve the surface roughness of the insulating layer 20, making the adhesion of the reflective layer 50 on the insulating layer 20 stronger.

[0051] like Figure 3 and Figure 4 As shown, in some embodiments, the light-emitting device 1 further includes a solder resist layer 20S, which is located around the light-emitting chip. The solder resist layer 20S may comprise epoxy resin, photoimageable polymer, polyimide, acrylic resin, silicone resin, fluoropolymer, phenolic resin, other similar materials, or combinations thereof, but this disclosure is not limited to these embodiments. Figure 4 As shown, the reflective layer 50 does not cover the solder mask layer 20S.

[0052] like Figure 3 and Figure 4 As shown, in some embodiments, the light-emitting device 1 further includes a lens structure 60, which is disposed on the light-emitting chip 40 and the reflective layer 50, and covers the recess 20R of the light-emitting chip 40 and the insulating layer 20. Furthermore, as... Figure 3 As shown, in this embodiment, the arrangement of the recesses 20R corresponds to the lens structure 60. Specifically, in this embodiment, the projection of the outermost recess 20R onto the substrate 10 partially overlaps with the projection of the lens structure 60 onto the substrate 10, while the projections of the other recesses 20R onto the substrate 10 completely overlap with the projections of the lens structure 60 onto the substrate 10. However, this embodiment is not limited to this. In some other examples, the lens structure 60 may cover all the recesses 20R. Furthermore, as... Figure 4 As shown, the lens structure 60 can fill the space above the solder resist layer 20S that is not covered by the reflective layer 50.

[0053] For example, the material of the lens structure 60 may include glass, epoxy resin, silicone resin, polyurethane, other suitable materials, or combinations thereof, but this disclosure is not limited thereto. In some embodiments, the lens structure 60 may be formed using a photoresist reflow method, a hot embossing method, other suitable methods, or combinations thereof. The steps of forming the lens structure 60 may include spin coating, lithography, etching, other suitable processes, or combinations thereof.

[0054] A push-force test was conducted on the light-emitting device 1 of the present disclosure embodiment and the light-emitting device of the comparative example (whose insulating layer does not include the recess), and the pushing force required to destroy the reflective layer 50 and the lens structure 60 was recorded. The experimental results show that the average pushing force required to destroy the reflective layer 50 and the lens structure 60 of the light-emitting device 1 of the present disclosure embodiment is 1.42 kg, while the average pushing force required to destroy the reflective layer and lens structure of the light-emitting device of the comparative example is 1.278 kg. In other words, the adhesive adhesion of the light-emitting device 1 of the present disclosure embodiment is improved by approximately 11.1% (1.42-1.278) / 1.278×100%) compared with the adhesive adhesion of the light-emitting device of the comparative example.

[0055] As described above, the plate structure of this embodiment includes an insulating layer with multiple recesses, which makes the adhesive have stronger adhesion when glue is subsequently applied to this plate structure (e.g., to form a reflective layer 50), thereby increasing the reliability of the light-emitting device using this plate structure.

[0056] The components of several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments of this disclosure. Those skilled in the art should understand that other processes and structures can be designed or modified based on the embodiments of this disclosure to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure. Furthermore, although this disclosure has been described above with reference to several preferred embodiments, it is not intended to limit this disclosure.

Claims

1. A plate structure, comprising: One substrate; An insulating layer is disposed on the substrate and has multiple recesses; as well as A conductive layer is disposed on the insulating layer, wherein the conductive layer has a reserved space that exposes a portion of the insulating layer, and the plurality of said recesses are located within the reserved space.

2. The plate structure as described in claim 1, wherein the conductive layer includes a conductive connection portion, the conductive connection portion dividing the reserved space into a first region and a second region.

3. The plate structure as claimed in claim 2, wherein some of the plurality of recesses located in the first region and others of the plurality of recesses located in the second region are arranged symmetrically with respect to the conductive connection portion as the axis of symmetry.

4. The sheet metal structure as claimed in claim 2, wherein the number of the plurality of recesses located in the first region is the same as the number of the plurality of recesses located in the second region.

5. The plate structure as claimed in claim 1, wherein in a top view, the shape of the plurality of recesses is circular, elliptical, rectangular or trapezoidal.

6. A light-emitting device, comprising: One substrate; An insulating layer is disposed on the substrate and has multiple recesses; A conductive layer is disposed on the insulating layer, wherein the conductive layer has a reserved space that exposes a portion of the insulating layer, and the plurality of said recesses are located within the reserved space; A light-emitting chip is disposed in the reserved space and electrically connected to the conductive layer; as well as A reflective layer is disposed on the insulating layer and the conductive layer and filled into the plurality of said recesses, wherein the reflective layer exposes the light-emitting wafer.

7. The light-emitting device as claimed in claim 6, further comprising: A lens structure is disposed on the light-emitting wafer and the reflective layer, wherein the lens structure covers the light-emitting wafer and the plurality of recesses.

8. The light-emitting device of claim 7, wherein the arrangement of the plurality of said recesses corresponds to the lens structure.

9. The light-emitting device of claim 8, wherein the projections of the outermost plurality of recesses onto the substrate partially overlap with the projection of the lens structure onto the substrate, while the projections of the other plurality of recesses onto the substrate completely overlap with the projection of the lens structure onto the substrate.

10. The light-emitting device of claim 6, wherein the conductive layer includes a conductive connection portion, and the light-emitting chip is electrically connected to the conductive layer through the conductive connection portion.

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