Wafer package substrate with thickness-reduced region and electronic device thereof

Abstract

The present application provides a kind of wafer package substrate with thickness reduction area and its electronic device, the substrate includes: a substrate; A circuit and a connecting pad are formed on the substrate, the connecting pad is electrically connected with the circuit, the connecting pad is configured to be electrically connected with the wafer, and an insulating layer is arranged on the circuit and the connecting pad, wherein the connecting pad is formed with a thickness reduction area in the corresponding area electrically connected with the wafer, and the insulating layer has an opening, the opening is arranged relative to the thickness reduction area, so that the wafer is connected with the thickness reduction area through the opening, and the thickness of the thickness reduction area is 20% to 80% relative to the thickness of the circuit.

Description

Technical Field

[0001] This invention relates to substrates for wafer packaging and electronic devices thereof. More specifically, this invention relates to substrates for light-emitting diode (LED) wafers, particularly for co-packaged optics (CPO), and electronic devices thereof. Background Technology

[0002] With the rapid development of high-performance computing (HPC), artificial intelligence (AI), and data center applications, the demand for high-speed, high-bandwidth, and low-loss interconnects is increasing. To meet this demand, co-packaged optics (CPO) technology is gradually becoming mainstream. CPO significantly shortens the electrical signal transmission distance, reduces latency and signal loss, and improves overall system energy efficiency and bandwidth density by directly packaging the optical engine and computing chip (such as ASIC and GPU) on the same substrate. Since CPO systems need to maintain stability at high frequencies, the substrate design must also consider low impedance to avoid resistive-capacitive loading (RC loading) interference and ensure signal integrity.

[0003] However, due to the need for high-frequency operation, existing designs often employ thick copper (for example, approximately 5 μm) to reduce line impedance. While copper has low electrical resistance, it also possesses extremely high thermal conductivity (approximately 401 W / m·K). The increased copper thickness leads to a larger thermally conductive volume, resulting in insufficient laser heating energy accumulation efficiency during light-emitting diode (LED) chip bonding, thus causing poor chip loading rates. This problem demonstrates that existing substrate structures, while balancing high-frequency, low-impedance design, face a contradiction: excessive thermal conductivity leads to insufficient laser heating efficiency.

[0004] Therefore, how to meet the requirements of high-frequency optical operation in co-packaged products while taking into account low impedance and low loss design, and at the same time improve the efficiency of laser heating and heat storage and the yield of wafer bonding, has become a technical challenge that needs to be solved in the substrate structure for wafer packaging. Summary of the Invention

[0005] The purpose of this invention is to provide a substrate structure for chip packaging, which improves the heat storage efficiency of the chip during laser heating bonding by adjusting the copper film thickness in a thinned region formed on the bonding pad. This design effectively increases the chip loading rate and avoids heat loss problems caused by the high thermal conductivity and high film thickness of the bonding pad metal.

[0006] The purpose of this invention is to further consider the electrical requirements under high-frequency operation by maintaining a high film thickness in the circuit area to reduce circuit impedance and avoid signal attenuation or drive failure caused by resistive-capacitive load interference. Simultaneously, the copper film thickness in the connection pad area is reduced to improve the heat storage characteristics of laser heating. Through the differentiated design of the circuit area and the connection pad area, this invention can improve chip packaging yield and reliability while ensuring high-speed signal integrity.

[0007] In view of this, the present invention provides a substrate for a chip package, comprising: a substrate; a circuit and a connection pad formed on the substrate, the connection pad being electrically connected to the circuit and configured to be electrically connected to the chip; and an insulating layer disposed on the circuit and the connection pad, wherein the connection pad has a thickness reduction region formed in the corresponding region electrically connected to the chip, and the insulating layer has an opening disposed relative to the thickness reduction region so that the chip can be connected to the thickness reduction region through the opening, the thickness reduction region being 20% ​​to 80% of the thickness of the circuit.

[0008] In some embodiments, the thickness reduction region is located below the opening and a portion below the insulating layer, and the connecting pad forms a lateral etched region at the boundary of the thickness reduction region, the lateral etched region extending along the boundary of the thickness reduction region and constituting a part of the thickness reduction region.

[0009] In some embodiments, the non-thickness-reduced area of ​​the connector pad is 5 micrometers ± 15% of the thickness of the line.

[0010] In some embodiments, the thickness of the thinned region is less than or equal to 4 micrometers ± 15%.

[0011] In some embodiments, the thickness reduction region is a recessed region located on a portion of the connecting pad below the opening.

[0012] In some embodiments, the thickness reduction region is disposed at a central portion of the connecting pad, and a metal retention portion is formed on each side of the thickness reduction region, the metal retention portion extending circumferentially along the boundary of the thickness reduction region.

[0013] In some embodiments, the thickness reduction region is disposed on one side of the connector pad and located below the opening for electrical connection with the wafer, and the connector pad forms a metal retention portion on the opposite side of the thickness reduction region.

[0014] In some embodiments, a first metal layer is disposed on the connection pad, the first metal layer covers the upper surface of the thickness reduction region and extends along the sidewall of the thickness reduction region, and a second metal layer is disposed on the first metal layer for electrical connection with the wafer.

[0015] In some embodiments, the area of ​​the thickness reduction region accounts for more than 80% of the total area of ​​the connecting pad.

[0016] The present invention also provides an electronic device, comprising: a chip; and a substrate as described above, wherein the chip is electrically connected to the bonding pad of the thickness reduction region through the opening. Attached Figure Description

[0017] Figure 1 This is a top view schematic diagram of a substrate for chip packaging according to a first embodiment of the present invention.

[0018] Figure 2 Show Figure 1 Schematic diagram of the cross section along section line A-A'.

[0019] Figure 3 Show Figure 1 Schematic diagram of the cross section along section line B-B'.

[0020] Figure 4 This diagram illustrates a wafer being bonded to a substrate according to a first embodiment of the present invention.

[0021] Figure 5 This is a top view schematic diagram of a substrate for a chip package according to a second embodiment of the present invention.

[0022] Figure 6 Show Figure 5 Schematic diagram of the cross section along section line A-A'.

[0023] Figure 7 This diagram illustrates a second embodiment of the present invention, showing the bonding of a wafer to a substrate.

[0024] In the attached figures, the following labels are used:

[0025] 1: Substrate

[0026] 2: Chip

[0027] 10: Base

[0028] 11: Route

[0029] 12: Connecting pad

[0030] 121: Thickness Reduction Area

[0031] 122: Lateral erosion area

[0032] 123: Metal Retention Section

[0033] 13: Insulation layer

[0034] 131: Opening

[0035] 17: First metal layer

[0036] 18: Second metal layer Detailed Implementation

[0037] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can understand other advantages and effects of the present invention from the content disclosed in this specification. However, the exemplary embodiments disclosed in this invention are for illustrative purposes only and should not be considered as limiting the scope of the invention. In other words, the present invention can also be implemented or applied through other different embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] Unless otherwise stated herein, the singular forms “a” and “the” used in the specification and the appended claims include the plural individuals. Unless otherwise stated herein, the term “or” used in the specification and the appended claims includes the meaning of “and / or”.

[0039] Please refer to Figures 1 to 3 As shown, Figure 1 This is a top view schematic diagram of a substrate 1 for a chip package according to a first embodiment of the present invention; Figure 2 Show Figure 1 Schematic diagram of cross section along section line A-A'; Figure 3 Show Figure 1 A schematic sectional view along section line B-B'. (See diagram.) Figure 1As shown, the present invention provides a substrate 1 for chip packaging, which includes a substrate 10, circuitry 11, connector pads 12, and an insulating layer 13. The circuitry 11 and connector pads 12 are formed on the substrate 10 and electrically connected to each other for transmitting high-frequency signals. The insulating layer 13 covers the circuitry 11 and connector pads 12, forming an opening 131. The connector pads 12 have a thickness reduction region 121 relative to the opening 131, the thickness of which is 20% to 80% of the thickness relative to the circuitry 11. Specifically, the thickness reduction region is a recessed region located on a portion of the connector pad below the opening. The substrate 10 can be made of glass, or other common substrate materials such as silicon, ceramic, epoxy resin substrate, or FR-4 fiberglass reinforced epoxy. Furthermore, the area between line 11, connecting pad 12, and substrate 10 may include a multi-layer interconnect structure, such as alternating conductive and dielectric layers, to support higher-density signal transmission and power distribution. Vertical interconnection can be achieved through through holes and blind vias, further enhancing the substrate's integration and design flexibility. Those skilled in the art can adjust the number, arrangement, and material selection of the multi-layer interconnects according to different application requirements without departing from the spirit and scope of this invention.

[0040] like Figure 2 and Figure 3 As shown, the thickness reduction region 121 is located below the opening 131 and the portion of the insulating layer 13, and a lateral undercut region 122 is formed at its boundary. The lateral undercut region 122 is a lateral undercut (undercut) generated during the etching process due to the covering of the insulating layer 13, extending along the boundary of the thickness reduction region 121 and constituting a part of the thickness reduction region 121. In a specific embodiment, the thickness reduction region 121 and the lateral undercut region 122 can be formed by the following steps: forming the circuit 11 and the connecting pad 12 on the substrate 10; covering the circuit 11 and the connecting pad 12 with the insulating layer 13; forming the opening 131 on the insulating layer 13; using the insulating layer 13 as an etching mask, isotropically etching the connecting pad 12; after etching, the thickness reduction region 121 is formed below the opening 131, and the lateral undercut region 122 is generated at its boundary. Optionally, the thermal conductivity of the metal material of the connecting pad 12 can be 200 to 450 W / m·K (room temperature) or higher. Alternatively, the connecting pad 12 can be formed from a highly thermally conductive metal such as aluminum, silver, or copper to improve heat dissipation and electrical conductivity.

[0041] A first metal layer 17 (e.g., nickel) may be formed on the thickness-reduced region 121 and in the opening 131 to fill and cover the laterally etched region 122. A second metal layer 18 (e.g., gold) may be formed on the first metal layer 17 as a bonding bump between the wafer and the substrate 1. Optionally, the first metal layer 17 and the second metal layer 18 may be formed by electroless nickel immersion gold (ENIG). Alternatively, the materials of the first metal layer 17 and the second metal layer 18 may be selected from tin (Sn), nickel (Ni), copper (Cu), silver (Ag), gold (Au), aluminum (Al), or alloys thereof.

[0042] In this embodiment, the thickness reduction region 121 is located in the central part of the connector pad 12, with metal retention portions 123 formed on both sides to provide a symmetrical structure. If the connector pad 12 is large and the insulating layer opening 131 is relatively small, the metal retention portion 123 will still be retained at the edge of the opening after etching, forming a stable sidewall structure. This helps to strengthen the mechanical support of the connector pad, maintain conductive continuity, and improve thermal conductivity, further enhancing the reliability of the wafer 2 after bonding with the substrate 1. Optionally, the width of the metal retention portion 123 can be 1 to 2 micrometers, and the area of ​​the thickness reduction region 121 can account for more than 80% of the total area of ​​the connector pad 12. Alternatively, the length L2 of the thickness reduction region 121 can be more than 80% of the length L1 of the connector pad 12 (for example, the length L2 of the thickness reduction region 121 can be 26 to 48 micrometers, and the length L1 of the connector pad 12 can be 30 to 50 micrometers).

[0043] Please refer to Figure 4 As shown, Figure 4 This diagram illustrates the bonding of a wafer 2 to a substrate 1 according to a first embodiment of the present invention. Figure 4As shown, the chip 2 is disposed on the substrate 1 and electrically connected through a first metal layer 17 disposed in the thickness reduction region 121 between the opening 131 and the connecting pad 12, and a second metal layer 18 disposed on the first metal layer 17. The first metal layer 17 and the second metal layer 18 serve as the bonding interface between the chip 2 and the substrate 1. In a specific embodiment, the chip 2 can be an LED chip. The above structural design can improve the bonding yield and electrical performance between the LED chip and the substrate 1. The package formed after packaging can be used in co-packaged optical systems to support high-frequency operation and ensure the stability of photoelectric signal transmission. In addition, other electronic components or photoelectric components, such as resistors, capacitors, driving circuits, or optical coupling elements, can also be disposed on the substrate 1 to further improve system integration and functionality. In a co-packaged optical system, a variety of functional components can be integrated on the substrate, such as optical transceivers, optical modulators, photodetectors (PDs), driver ICs, controller / ASICs, and thermal dissipation structures. Through the integration of these components, substrate 1 not only supports efficient bonding between the chip and the substrate but also provides a complete optoelectronic integration platform, further enhancing the reliability and performance of the CPO system in high-speed computing and data center applications.

[0044] The wafer 2 can be bonded via laser heating. Due to the low thickness of the thinned region 121 (e.g., less than or equal to 4 micrometers ± 15%), heat energy can be effectively stored, improving the efficiency of laser heating bonding and thus improving the wafer 2's assembly yield. The non-thickened areas of the connector pads and the lines 11 maintain a high film thickness (e.g., 5 micrometers ± 15%), reducing line impedance and avoiding resistive-capacitive load interference during high-frequency operation. This ensures that the substrate 1 can still avoid problems such as signal delay, waveform distortion, signal attenuation, bandwidth limitation, and increased power consumption under high-speed operation. Therefore, by forming a thinned region 121 and a lateral etched region 122 on the connector pad 12, and forming a first metal layer 17 and a second metal layer 18 thereon, the present invention enables the wafer 2 to be stably and efficiently bonded to the substrate 1, balancing high-frequency signal transmission and packaging yield.

[0045] Please refer to Figures 5 to 6 As shown, Figure 5 A top view schematic diagram of a substrate for a chip package according to a second embodiment of the present invention is shown; Figure 6 Show Figure 5 The cross-sectional view along section line A-A' shows the number of elements only as an example and is not intended to limit the invention. Figure 6As shown, substrate 1 includes a base 10, a circuit 11, two adjacent connector pads 12, and an insulating layer 13. The insulating layer 13 covers the circuit 11 and the connector pads 12, forming an opening 131 such that a portion of each of the two adjacent connector pads 12 is exposed in the opening 131, and at least one sidewall of the connector pad 12 is exposed in the opening 131. At least one side of the connector pad 12 has a thickness reduction region 121 below the opening 131, the thickness of which is 20% to 80% of the thickness of the circuit 11. In one specific embodiment, the thickness of the circuit 11 can be 4 to 6 micrometers, the thickness of the insulating layer 13 can be 8 to 10 micrometers, and the thickness of the thickness reduction region 121 can be less than 4 micrometers (i.e., at least 1 micrometer thinner relative to the thickness of the circuit and the connector pads 12).

[0046] Additionally, on the other side of the connector pad 12, opposite to the side exposed by the opening 131, a lateral undercut region 122 is formed along the boundary of the thickness reduction region 121 below the insulating layer 13. The lateral undercut region 122 is an undercut created during the etching process due to the covering of the insulating layer 13, extending along the boundary of the thickness reduction region 121 and forming part of the thickness reduction region 121. The dimension from the sidewall of the insulating layer 13 to the boundary of the lateral undercut region 122 can range from 1 to 2 micrometers. Optionally, a metal retention portion can also be formed on the opposite side of the thickness reduction region 121 of the connector pad 12.

[0047] A first metal layer 17 (e.g., nickel) may be formed in the thickness reduction region 121 within the opening 131 and fills the lateral etched region 122. A second metal layer 18 (e.g., gold) may be formed on top of the first metal layer 17 for bonding between the wafer and the substrate 1. Optionally, the first metal layer 17 and the second metal layer 18 may also be formed using an electroless nickel immersion gold process. In one specific embodiment, the thickness of the first metal layer 17 in the thickness reduction region 121 may be 2 to 5 micrometers, and the lateral dimension of the sidewall of the thickness reduction region 121 may be 1.7 to 2 micrometers; the thickness of the second metal layer 18 may be 0.05 to 0.07 micrometers. After the first metal layer 17 and the second metal layer 18 are formed on two adjacent bonding pads 12, the lateral distance between two adjacent second metal layers 18 (e.g., the distance between the sidewalls of the second metal layers 18 on two adjacent bonding pads 12) may be 10 to 15 micrometers.

[0048] Please refer to Figure 7 As shown, Figure 7 This diagram illustrates the bonding of the wafer 2 to the substrate 1 according to a second embodiment of the present invention. Figure 7As shown, unlike the first embodiment, in the second embodiment, the opening 131 is formed between two adjacent connector pads 12, and a portion of each of the two adjacent connector pads 12 is exposed in the opening 131, such that at least one sidewall of the connector pad 12 is exposed in the opening 131. At least one side of the connector pad 12 has a thickness reduction region 121 below the opening 131, and a first metal layer 17 is formed in the thickness reduction region 121, filling the lateral etched region 122. A second metal layer 18 is also formed on the first metal layer 17, and the first metal layer 17 and the second metal layer 18 serve as the bonding interface between the wafer 2 and the substrate 1. After the formation of the first metal layer 17 and the second metal layer 18, the two adjacent connector pads 12 have a gap between them. With this structural design, the second embodiment of the present invention can support stable bonding between the wafer and the substrate, while also ensuring the reliability of high-frequency signal transmission and packaging yield.

[0049] To verify the technical effects of the present invention, Table 1 shows the test results of non-attachment rate and illumination rate of several comparative examples and embodiments of the present invention. After the substrate of the present invention has a thickness reduction region on the connector pads, laser heating bonding tests of the wafers are performed. In the comparative examples, the copper thickness of the connector pads is maintained at 5.0 micrometers without thinning. The results show that both the non-attachment rate and illumination rate are poor. Even with the laser heating power increased to 100%, there is still a significant non-attachment rate, and the illumination rate is low, indicating insufficient bonding efficiency. In contrast, the embodiments of this application design the thickness reduction region of the connector pads to 3.9 micrometers. The results show that only about 25% of the laser heating power is needed to achieve a 100% attachment rate, and the illumination rate also reaches 100%.

[0050] Connecting pad copper thickness Unsold rate (%) Lighting rate (%) Comparative Example 1 5 um 83% 0% Comparative Example 2 5 um 50% 25% Comparative Example 3 5 um 16% 10% Example 1 3.9 um 0% 100% Example 2 3.9 um 0% 100%

[0051] As can be seen from the above data, the present invention can significantly improve the bonding efficiency between the wafer and the substrate by setting a thinned region in the bonding pad. Compared with the unthinned comparative example, the present invention can not only achieve a qualified loading rate under low power conditions, but also ensure a wafer illumination rate of 100%, showing that it has significant improvements in both optoelectronic performance and packaging reliability.

[0052] This invention is not something that could be easily accomplished by someone skilled in the art based on existing technology. Existing designs reduce circuit impedance simply by adding or maintaining a thick copper layer, resulting in difficulty in accumulating laser heating energy and insufficient chip bonding efficiency. This invention selectively removes a portion of the metal from the connection pads below the opening in the insulating layer to form a thinner region, thereby reducing the local heat conduction volume and improving heat storage efficiency, allowing the laser heating energy to achieve the desired bonding effect. While reducing the overall circuit thickness can improve local heat storage efficiency, it increases the overall circuit resistance, thus affecting the quality of high-frequency signal transmission. This invention preferably achieves this by forming a thinner region only in the connection area, simultaneously considering both local heat accumulation and the low resistance requirements of the circuit area. Furthermore, this invention allows for etching of the connection pads using the insulating layer as an etching mask after the insulating layer is formed, simplifying the process and allowing precise control of the position and depth of the thinner region. Through this structural design, this invention significantly improves chip bonding yield and illumination rate while simultaneously ensuring the low resistance and signal integrity required for high-frequency operation in the circuit area, providing an integrated solution that combines electrical and thermal properties. Compared to existing methods that rely solely on increasing laser power or simply adjusting the overall copper thickness, the differentiated thickness design proposed in this invention is an innovation that breaks through existing thinking and possesses non-obviousness and significant progress.

[0053] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A substrate for wafer packaging, characterized in that, include: One base; A circuit and a connection pad are formed on the substrate, the connection pad being electrically connected to the circuit and configured to be electrically connected to the chip. An insulating layer is disposed on the circuit and the connecting pad. The connecting pad has a thickness reduction region in the corresponding area that is electrically connected to the chip, and the insulating layer has an opening that is disposed relative to the thickness reduction region so that the chip can be connected to the thickness reduction region through the opening. The thickness of the thickness reduction region is 20% to 80% of the thickness of the line.

2. The substrate as described in claim 1, characterized in that, The thickness reduction area is located below the opening and part of the insulating layer. The connecting pad forms a lateral etched area at the boundary of the thickness reduction area. The lateral etched area extends along the boundary of the thickness reduction area and constitutes part of the thickness reduction area.

3. The substrate as described in claim 1, characterized in that, The area of ​​the connection pad that is not thinned is 5 micrometers ± 15% of the thickness of the line.

4. The substrate as claimed in claim 1, characterized in that, The thickness of the thinned region is less than or equal to 4 micrometers ± 15%.

5. The substrate as claimed in claim 1, characterized in that, The area where the thickness is reduced is a recessed area, located on the portion of the connecting pad below the opening.

6. The substrate as claimed in claim 5, characterized in that, The thickness reduction area is located in the center of the connecting pad, and a metal retention portion is formed on both sides of the thickness reduction area. The metal retention portion extends circumferentially along the boundary of the thickness reduction area.

7. The substrate as claimed in claim 1, characterized in that, The thickness reduction area is located on one side of the connector pad and below the opening for electrical connection with the wafer. A metal retention portion is formed on the opposite side of the thickness reduction area of ​​the connector pad.

8. The substrate as claimed in claim 7, characterized in that, A first metal layer is disposed on the connecting pad, the first metal layer covers the upper surface of the thickness reduction area and extends along the sidewall of the thickness reduction area, and a second metal layer is disposed on the first metal layer for electrical connection with the wafer.

9. The substrate as claimed in claim 1, characterized in that, The area of ​​the thinned region accounts for more than 80% of the total area of ​​the connecting pad.

10. An electronic device, characterized in that, include: One chip; and The substrate as claimed in any one of claims 1 to 9, wherein the wafer is electrically connected to the bonding pad of the thickness reduction region through the opening.

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