A high-power LED device and a manufacturing method thereof

Abstract

The present application relates to a kind of high-power LED devices and its manufacturing method, wherein the device includes substrate and the light-emitting chip arranged on substrate;Substrate includes metal base, the first surface of metal base is provided with integrally formed first boss, first surface is covered with first insulating layer, first insulating layer is provided with first opening, for first boss to penetrate;The surface of first insulating layer is provided with first circuit layer;The second surface of metal base is provided with integrally formed second boss, second surface is covered with second insulating layer, second insulating layer is provided with second opening, for second boss to penetrate;The surface of second insulating layer is provided with second circuit layer;Substrate is provided with via structure penetrating first insulating layer, metal base and second insulating layer, the A pole of first circuit layer, B pole pad is respectively connected with the A pole of second circuit layer, B pole pin by a via structure electrically;Light-emitting chip is fixed in first boss, the A pole of light-emitting chip is connected with the A pole pad electrically, and B pole is connected with the B pole pad electrically.

Description

Technical Field

[0001] This invention relates to the field of semiconductor lighting technology, and in particular to a high-power LED device and its manufacturing method. Background Technology

[0002] Light-emitting diodes (LEDs), as a new type of solid-state lighting source, have been widely used in general lighting, automotive lighting, display backlighting, and special lighting due to their advantages such as high efficiency, low energy consumption, long lifespan, fast response, and environmental friendliness. With the continuous increase in LED output power, the market demands increasingly higher requirements for low thermal resistance, high current density, low warpage, and long-term reliability in high-power and ultra-high-power LED packaging. High-power LED devices refer to light-emitting diode devices that operate at higher currents and voltages, generating higher light output and corresponding heat. The junction temperature of an LED directly affects its luminous efficiency, wavelength stability, and lifespan. Excessively high junction temperatures will lead to accelerated light decay, increased color drift, and even device failure. Therefore, the packaging substrate, as the core component that carries the LED chip and realizes electrical interconnection and heat dissipation, has become one of the key factors restricting the performance of high-power LED devices due to its heat dissipation capacity and structural reliability.

[0003] Currently, high-power LED packaging commonly uses metal or ceramic substrates to carry the chip. Conventional metal substrates typically consist of a metal base, a thermally conductive insulating layer, and a copper foil circuit layer, generally manufactured through processes such as cutting, drilling, lamination, and circuit etching. In this structure, the LED chip is usually mounted on the copper foil circuit layer via a solder layer. The heat generated by the chip must sequentially pass through the solder layer, the copper foil circuit layer, and the insulating dielectric layer before being conducted to the metal substrate, and then from the metal substrate to the external heat sink. However, the insulating dielectric layer must meet both electrical insulation requirements and the function of heat transfer; its thermal conductivity is significantly lower than that of copper, and the numerous interfaces along the entire heat conduction path create a thermal resistance bottleneck, making it difficult to meet the heat dissipation requirements under high power density conditions. In high power density applications, the shortcomings of the conventional structure mentioned above become even more apparent: on the one hand, heat tends to accumulate in the substrate area directly below the chip, forming localized heat buildup, which leads to increased chip junction temperature and degraded device performance; on the other hand, there are differences in the coefficients of thermal expansion between the metal substrate and the insulating layer and copper foil circuit layer, which can cause the board to warp under temperature cycling, affecting subsequent mounting accuracy; in addition, during the lamination and molding process, defects such as interlayer bubbles or delamination, insulating layer residue or excess adhesive, and uneven height of bumps and circuit surfaces are also prone to occur. These problems will directly affect die bonding reliability, wire bonding stability, and the long-term temperature cycling life of the device.

[0004] To address the aforementioned issues, existing technologies have proposed several improvement measures, such as using copper substrates, adding thermally conductive fillers to the insulating layer, and incorporating copper vias or pillars in the substrate, to improve heat dissipation and current carrying capacity to some extent. However, these measures still have limitations: if the LED chip is still separated from the insulating layer directly below it, it is difficult to form a direct, low-thermal-resistance channel from the chip's heat source to the metal substrate, and the fundamental bottleneck of heat dissipation cannot be eliminated; if copper pillars or heat sinks are used, the matching accuracy between them and the insulating layer and circuit layer is difficult to control, which can easily introduce manufacturing risks such as bonding voids, excess adhesive contamination, and uneven assembly, affecting device reliability. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to overcome the defects or deficiencies of the prior art. On the one hand, it provides a high-power LED device with excellent heat dissipation performance, which can improve the reliability of the device.

[0006] A high-power LED device includes a substrate and a light-emitting chip disposed on the substrate, wherein the light-emitting chip has an A pole and a B pole with opposite polarities; The substrate includes a metal substrate, the metal substrate having a first surface and a second surface disposed opposite to each other along the thickness direction, the first surface having an integrally formed first boss, the first surface being covered with a first insulating layer, the first insulating layer having a first opening at a position corresponding to the first boss for the first boss to pass through; the surface of the first insulating layer facing away from the metal substrate having a first circuit layer, the first circuit layer including A-pole pads and B-pole pads that do not contact each other. The second surface is provided with an integrally formed second protrusion, and the second surface is covered with a second insulating layer. The second insulating layer is provided with a second opening at the position corresponding to the second protrusion for the second protrusion to extend out. The surface of the second insulating layer facing away from the metal substrate is provided with a second circuit layer, and the second circuit layer includes A-pole pins and B-pole pins that do not contact each other. The substrate is provided with at least two via structures. The A-pole pad is electrically connected to the A-pole pin through one via structure, and the B-pole pad is electrically connected to the B-pole pin through another via structure. The light-emitting chip is die-bonded on the first boss, and the A-pole of the light-emitting chip is electrically connected to the A-pole pad, and the B-pole is electrically connected to the B-pole pad.

[0007] On the other hand, the present invention also provides a method for manufacturing a high-power LED device, comprising the following steps: S1: Prepare a metal substrate, wherein the first surface of the metal substrate has an integrally formed first boss, the second surface of the metal substrate has an integrally formed second boss, and the second surface and the first surface are disposed opposite to each other along the thickness direction of the metal substrate; Prepare a first insulating layer and a second insulating layer. Form a first circuit layer including an A-pole pad and a B-pole pad on the surface of the first insulating layer according to a preset pattern. Open a first opening in the first insulating layer at the position corresponding to the first boss so that the first boss can pass through. A second circuit layer including A-pole pins and B-pole pins is formed on the surface of the second insulating layer according to a preset pattern, and a second opening is made at the position of the second boss in the second insulating layer for the second boss to pass through. S2: The first insulating layer with the first circuit layer, the metal substrate, and the second insulating layer with the second circuit layer are sequentially stacked along the thickness direction to form a laminate. Then, the laminate is vacuum hot-pressed to form a substrate. S3: Form at least two via structures on the substrate, the via structures penetrating the first insulating layer, the metal substrate and the second insulating layer, so that the A-pole pad is electrically connected to the A-pole pin through one via structure and the B-pole pad is electrically connected to the B-pole pin through another via structure; S4: A light-emitting chip with opposite polarities, A and B, is die-bonded to the first boss, and the A terminal of the light-emitting chip is electrically connected to the A terminal pad, and the B terminal is electrically connected to the B terminal pad.

[0008] Compared to existing technologies, the high-power LED device and its manufacturing method described in this invention feature integrally formed first and second protrusions on the first and second surfaces of a metal substrate, respectively. A light-emitting chip is then placed on the first protrusion, allowing the chip to directly contact the metal substrate and form a heat-conducting path perpendicular to the metal substrate's protective line. Simultaneously, a conductive path is formed through a first circuit layer, a via structure, and a second circuit layer, providing electrical connection. This completely separates "conductivity" from "heat conduction," bypassing the thermal resistance bottleneck caused by the insulating layer in traditional packaging. This effectively improves heat conduction efficiency and avoids device reliability issues caused by long heat transfer paths and excessive thermal resistance under high power density operation. It can be used in high-power lighting, automotive lighting, UV curing, stage / projection light sources, and other high heat flux density applications.

[0009] To better understand and implement this invention, the following detailed description is provided in conjunction with the accompanying drawings. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the substrate structure in the high-power LED device of Embodiment 1 of the present invention; Figure 2 The following are schematic diagrams of the structure of the metal substrate in the high-power LED device of Embodiment 1 of the present invention: 2(a) is a schematic diagram of the structure of the first surface of the metal substrate; 2(b) is a schematic diagram of the structure of the second surface of the metal substrate; Figure 3 This is a schematic diagram of the structure of the first insulating layer and the first circuit layer in the high-power LED device of Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the structure of the second insulating layer and the second circuit layer in the high-power LED device of Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the high-power LED device structure in Embodiment 1 of the present invention; Figure 6 This is a cross-sectional view of the conductive structure in the high-power LED device of Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the structure of the high-power LED device in Embodiment 2 of the present invention; Figure 8 This is a schematic diagram of the structure of the high-power LED device in Embodiment 3 of the present invention; Figure 9 This is a schematic flowchart of the manufacturing method of a high-power LED device according to Embodiment 1 of the present invention; Figure 10 This is a schematic flowchart of the manufacturing method of a high-power LED device according to Embodiment 2 of the present invention; Figure 11 This is a schematic flowchart of the manufacturing method of a high-power LED device according to Embodiment 3 of the present invention; Figure label: 10. Substrate; 100. Metal substrate; 1001. First boss; 1002. Second boss; 101. First insulating layer; 1010. First opening; 102. Second insulating layer; 1020. Second opening; 103. First circuit layer; 1031. A-pole pad; 1032. B-pole pad; 104. Second circuit layer; 1041. A-pole pin; 1042. B-pole pin; 105. First conductive layer; 106. Second conductive layer; 110. Composite conductive component; 1101. Conductive pillar; 1102. Insulating wall; 20. Light-emitting chip; 202. Conductive lead; 30. Supporting structure; 40. Zener tube. Detailed Implementation

[0011] In traditional high-power LED packaging, the heat generated by the LED chip must pass through the solder layer, copper foil circuit layer, and thermally conductive insulating layer before being conducted to the metal substrate. However, because the thermal conductivity of the thermally conductive insulating layer is lower than that of copper and multiple interfaces introduce additional thermal resistance, the heat transfer path from the chip to the heat dissipation substrate is lengthy and the thermal resistance is too high. This leads to a series of reliability problems under high power density operation, such as heat accumulation, substrate warping, interlayer bubbles, and inconsistencies in the height between the die bond surface and the circuit surface.

[0012] Through long-term practice, the inventors discovered that the root cause of the aforementioned problems lies in the fact that existing technologies consistently treat "electrical isolation" and "thermal conduction" as opposing functions that must be achieved through layering different materials, thus adhering to the structural setting that "the insulating layer must be located between the light-emitting chip and the metal substrate." While this design logic ensures electrical insulation, it artificially creates a physical barrier to thermal conduction. Even with auxiliary methods such as high thermal conductivity fillers, copper pillars, or copper vias, the thermal conductivity of these methods cannot overcome the fundamental limitation of the "thermal resistance bottleneck." More importantly, the multilayer structure stacked to achieve electrothermal separation is highly susceptible to manufacturing defects during the lamination process due to misalignment, uneven thickness, and differences in material expansion coefficients between the copper foil, insulating layer, and metal substrate. These defects further exacerbate the instability of thermal conduction and the risk of encapsulation failure.

[0013] Based on this, the present invention provides a high-power LED device with a structure designed to optimize thermal management and electrical interconnection. The high-power LED device includes a substrate and a light-emitting chip disposed on the substrate. The core of the substrate is a metal base. A first protrusion is integrally formed on the first surface of the metal base, and the light-emitting chip is disposed on the first protrusion, allowing the light-emitting chip to directly contact the metal base, forming a heat-conducting path perpendicular to the metal base. Simultaneously, a first circuit layer, via structures, and a second circuit layer constitute a conductive path, undertaking the electrical connection function, thus completely separating "conductivity" from "thermal conduction." In this way, by using the integrally formed metal base as the main heat-conducting channel, the thermal resistance bottleneck caused by the insulating layer in traditional packaging is bypassed, effectively improving thermal conductivity and avoiding device reliability issues caused by long heat transfer paths and excessive thermal resistance under high power density operation.

[0014] The present invention will now be described in detail with reference to the accompanying drawings.

[0015] Example 1 Figure 1-6 The specific structure of Embodiment 1 of the high-power LED device of the present invention is shown. For example... Figure 1-6 As shown, the high-power LED device of this embodiment includes a substrate 10 and a light-emitting chip 20 disposed on the substrate 10. The light-emitting chip 20 has A and B poles with opposite polarities, which are the electrical characteristics required for the normal operation of the light-emitting chip 20.

[0016] Specifically, such as Figure 2As shown in (a), the substrate 10 includes a metal substrate 100, specifically made of copper, preferably pure copper with better thermal conductivity. The metal substrate 100 includes a first surface and a second surface disposed opposite each other along the thickness direction. The first surface has a first boss 1001. This first boss 1001 can be formed directly by CNC controlled depth milling, controlled depth etching, post-positioned controlled depth groove, or stamping / roll forming, forming an integral part with the metal substrate 100. The first surface of the metal substrate 100 is covered with a first insulating layer 101. For example... Figure 3 As shown, the first insulating layer 101 has a first opening 1010 at a position corresponding to the first protrusion 1001, through which the first protrusion 1001 passes. A first circuit layer 103 is provided on the surface of the first insulating layer 101 facing away from the metal substrate 100. The first circuit layer 103 is specifically a copper foil layer, which is formed with non-contact A-pole pads 1031 and B-pole pads 1032 through a photolithography etching process. These pads are used for subsequent electrical connection with the light-emitting chip 20.

[0017] like Figure 2 As shown in (b), a second boss 1002 is provided on the second surface of the metal substrate 100, and this second surface is disposed opposite to the first surface along the thickness direction. Similar to the first boss 1001, the second boss 1002 is formed integrally with the metal substrate 100. The second surface of the metal substrate 100 is covered with a second insulating layer 102. Figure 4 As shown, the second insulating layer 102 has a second opening 1020 at a position corresponding to the second protrusion 1002 for the second protrusion 1002 to extend out. A second circuit layer 104 is provided on the surface of the second insulating layer 102 facing away from the metal substrate 100. The second circuit layer 104 is specifically a copper foil layer, which is also formed with non-contact A-pole pins 1041 and B-pole pins 1042 through photolithography etching. These pins are used for connecting the device to external circuits.

[0018] To achieve electrical connections between A-pole pad 1031 and A-pole pin 1041, and between B-pole pad 1032 and B-pole pin 1042, the substrate 10 is provided with two via structures. Each via structure penetrates at least the first insulating layer 101, the metal substrate 100, and the second insulating layer 102. A-pole pad 1031 is electrically connected to A-pole pin 1041 through one via structure, and B-pole pad 1032 is electrically connected to B-pole pin 1042 through the other via structure.

[0019] Furthermore, to form the shortest conductive path, the orthographic projection of A-pin 1041 on the reference plane at least partially overlaps with the orthographic projection of A-pad 1031 on the same reference plane, forming a first overlapping region; the orthographic projection of B-pin 1042 on the reference plane at least partially overlaps with the orthographic projection of B-pad 1032 on the same reference plane, forming a second overlapping region. Here, "reference plane" refers to a plane perpendicular to the thickness direction of the metal substrate 100, and "orthographic projection of A-pin 1041 on the reference plane" refers to the two-dimensional shape projection of A-pin 1041 on the plane perpendicular to the thickness direction of the metal substrate 100, which serves to define the position and range of A-pin 1041 in the horizontal direction. Similarly, "orthographic projection of B-pin 1042 on the reference plane" refers to the two-dimensional shape projection of B-pin 1042 on the plane perpendicular to the thickness direction of the metal substrate 100, which serves to define the position and range of B-pin 1042 in the horizontal direction. The phrase "at least partially overlap" means that the orthographic projection of pin 1041 and the orthographic projection of pad 1031 on the reference plane share a common area, the area of ​​which is greater than zero. This overlap design can achieve complete overlap, where the orthographic projection of a pin is completely contained within the orthographic projection of its corresponding pad, or the two orthographic projections are completely identical; or it can be partial overlap, for example, where the edges of the orthographic projections of the two pins and their corresponding pads partially intersect.

[0020] like Figure 3-4 As shown, in this embodiment, the orthographic projection of the A-pole pin 1041 on the reference plane is completely contained within the orthographic projection of the A-pole pad 1031 on the same reference plane, forming a first overlapping area; the B-pole pin 1042 forms a second overlapping area within the edge contour range of the orthographic projection of the reference plane and the orthographic projection of the B-pole pad 1032 on the same reference plane. One via structure is disposed in the first overlapping area, and the other via structure is disposed in the second overlapping area. The via structure located in the first overlapping area sequentially penetrates the A-pole pad 1031, the first insulating layer 101, the metal substrate 100, the second insulating layer 102, and the A-pole pin 1041; the via structure located in the second overlapping area sequentially penetrates the B-pole pad 1032, the first insulating layer 101, the metal substrate 100, the second insulating layer 102, and the B-pole pin 1042. By setting the A-pole pin 1041 and the A-pole pad 1031, and the B-pole pin 1042 and the B-pole pad 1032 to at least partially overlap, first and second overlap areas are formed respectively, and via structures are set in the first and second overlap areas respectively, thereby forming the shortest conductive path perpendicular to the substrate 10.

[0021] The light-emitting chip 20 is die-bonded onto the first protrusion 1001. The A-terminal of the light-emitting chip 20 is electrically connected to the A-terminal pad 1031 via a conductive lead 202, and its B-terminal is electrically connected to the B-terminal pad 1032 via a conductive lead 202. In this way, a conductive path separate from the heat conduction path of the light-emitting chip 20 is constructed.

[0022] The aforementioned high-power LED device employs a "thermoelectric separation" structure. When the high-power LED device is operating, the heat generated by the light-emitting chip 20 can be directly conducted to the integrally formed first protrusion 1001, and then rapidly diffused throughout the entire metal substrate 100. Since the first protrusion 1001 is integrally formed with the metal substrate 100, and the light-emitting chip 20 is directly die-bonded onto it, the obstruction of the heat conduction path by the insulating layer in traditional solutions is avoided, significantly reducing thermal resistance. Simultaneously, the electrical energy of the light-emitting chip 20 is transmitted through the A-pole pads 1031 and B-pole pads 1032 of the first circuit layer, via a via structure, and ultimately connected to the A-pole pins 1041 and B-pole pins 1042 of the second circuit layer 104, achieving reliable electrical interconnection. Furthermore, the integrally formed metal substrate 100 structure also enhances the mechanical strength and thermal cycling reliability of the entire substrate 10, reducing the risk of stress concentration and delamination caused by differences in the thermal expansion coefficients of different materials.

[0023] Compared to existing LED packaging substrates where a thermally conductive insulating layer between the light-emitting chip and the metal substrate creates a thermal resistance bottleneck in the heat conduction path, leading to increased chip junction temperature and decreased device performance, this invention effectively eliminates the barrier of the insulating layer between the chip heat source and the metal substrate by providing an integrally formed first protrusion 1001 on the first surface of the metal substrate 100 and directly die-bonding the light-emitting chip 20 onto this first protrusion 1001. This direct contact die-bonding method establishes a low thermal resistance channel from the light-emitting chip 20 to the metal substrate 100, significantly improving heat conduction efficiency, thereby effectively reducing the operating junction temperature of the light-emitting chip 20 and extending the device's lifespan.

[0024] Furthermore, in traditional multilayer lamination structures, differences in the coefficients of thermal expansion exist between the metal substrate, insulating layer, and circuit layer, which can easily lead to structural reliability issues such as board warping, interlayer delamination, or bubbles under temperature cycling. This invention employs an integrally formed first boss 1001 and second boss 1002, making the metal substrate 100 and the first and second bosses 1001 a single unit, reducing the number and complexity of interlayer interfaces. This integrated structure enhances the overall mechanical strength and thermal stability of the substrate 10, effectively alleviating stress caused by mismatched coefficients of thermal expansion, thereby improving the structural reliability of the device under long-term operation and temperature cycling conditions. Simultaneously, the integral molding process simplifies the manufacturing process, reduces the risk of manufacturing defects such as lamination voids and adhesive overflow, and helps improve product yield. The vertical electrical connection between the first circuit layer 103 and the second circuit layer 104 is achieved through a via structure, further optimizing the wiring space of the substrate 10 and ensuring stable transmission of electrical signals.

[0025] The aforementioned high-power LED device utilizes an integrally formed boss structure on the metal substrate 100 to achieve direct heat conduction between the light-emitting chip 20 and the metal substrate 100. However, in actual manufacturing and application, if the positional relationship between the first boss 1001 and the second boss 1002 in the thickness direction lacks effective constraint, stress concentration can easily occur in the metal substrate 100 when heated or compressed, leading to warping of the substrate 10 or a decrease in structural stability, making it difficult to ensure the flatness of the die-bonding position of the light-emitting chip 20 and the continuity of the heat conduction path.

[0026] Based on this, in the structure of the aforementioned high-power LED device, the orthographic projection of the first protrusion 1001 on the reference plane and the orthographic projection of the second protrusion 1002 on the same reference plane at least partially overlap.

[0027] The meanings of "orthographic projection" and "at least partially overlapping" here are the same as those mentioned earlier, and therefore will not be repeated here. For example... Figure 2 As shown, in this embodiment, the orthographic projection of the second boss 1002 on the reference plane is completely contained within the orthographic projection of the first boss 1001 on the same reference plane. By setting the orthographic projections of the first boss 1001 and the second boss 1002 on the reference plane perpendicular to the thickness direction to at least partially overlap, the first and second bosses 1001 and 1002 are geometrically aligned or partially aligned. The core contribution of this layout is the optimization of the stress distribution and heat flow conduction path of the metal substrate 100. Figure 1-6 In the high-power LED device shown, the heat generated by the light-emitting chip 20 is directly transferred to the first protrusion 1001, then through the metal substrate 100, and further conducted to the second protrusion 1002. By forming an overlapping region between the first protrusion 1001 and the second protrusion 1002 in the thickness direction, the structural rigidity on both sides of the metal substrate 100 can be effectively balanced, thereby reducing the risk of overall warping of the substrate 10 during thermal cycling. In terms of heat conduction, this overlapping design allows the heat generated by the light-emitting chip 20 to be transferred more directly to the metal substrate 100 through the first protrusion 1001, and then conducted along the thickness direction of the overlapping region to the second protrusion 1002 and the external heat dissipation structure, shortening the heat conduction path and reducing thermal resistance. Through this spatial constraint, not only is the structural stability of the substrate 10 improved, but the flatness of the die-bonding region is also ensured, providing a fundamental guarantee for the reliable operation of the high-power LED device at high power density.

[0028] Although direct heat conduction is achieved by setting the first protrusion 1001 and the second protrusion 1002, in practical applications, if the area of ​​the second protrusion 1002 is too small, the heat distribution on the metal substrate 100 will be uneven, making it impossible for heat to be efficiently transferred from the metal substrate 100 to the external heat sink, thus limiting the further improvement of the overall heat dissipation performance.

[0029] Preferably, the area of ​​the second protrusion 1002 is not less than half the area of ​​the second surface of the metal substrate 100. The second protrusion 1002 is part of the metal substrate 100, extending integrally from its second surface, and is primarily used for thermal contact with an external heat sink. Limiting its area to not less than half the area of ​​the second surface of the metal substrate 100 ensures that the thermal contact interface has sufficient dimensions for effective heat conduction. Specifically, this can be achieved in two ways: First, the second protrusion 1002 can be designed as an integral structure covering most of the second surface of the metal substrate 100. For example, its shape can be adapted to the outline of the second surface of the metal substrate 100, but its size can be slightly smaller to ensure its area proportion. Second, the second protrusion 1002 can be composed of multiple interconnected or closely arranged sub-regions, the total area of ​​which reaches or exceeds half the area of ​​the second surface of the metal substrate 100, thereby forming a large-area heat dissipation contact surface.

[0030] Thus, by increasing the area of ​​the second protrusion 1002, the heat transfer efficiency from the metal substrate 100 to the external heat sink is significantly improved. The heat generated by the light-emitting chip 20 is directly transferred to the first protrusion 1001, and then efficiently conducted from the first protrusion 1001 to the metal substrate 100. Since the orthographic projection of the first protrusion 1001 on the reference plane and the orthographic projection of the second protrusion 1002 on the same reference plane at least partially overlap, a direct and low-thermal-resistance heat transfer path is ensured between the chip heat source and the second protrusion 1002. Based on this, when the area of ​​the second protrusion 1002 is designed to be no less than 1 / 2 of the area of ​​the second surface of the metal substrate 100, the effective contact area between the metal substrate 100 and the external heat sink is greatly increased. This large-area contact design can effectively reduce the interfacial thermal resistance during heat conduction, allowing heat to diffuse more evenly and quickly from the entire surface of the second protrusion 1002 to the outside after it has diffused inside the metal substrate 100. This not only enhances the path width of heat conduction, but also increases the heat dissipation contact surface, enabling the metal substrate 100 to carry a higher power density of heat flow. Thus, while ensuring structural stability, it further improves the overall heat dissipation capacity and thermal management efficiency of the device.

[0031] In addition to constructing heat dissipation channels, high-power LED devices also form a via structure by introducing a composite conductive element 110 consisting of an insulating wall 1102 and a conductive pillar 1101 inside the vias penetrating the substrate 10, thereby achieving physical isolation and electrical insulation between the conductive path and the metal substrate 100.

[0032] Specifically, such as Figure 6As shown, the via structure includes a via penetrating at least the first insulating layer 101, the metal substrate 100, and the second insulating layer 102, and a composite conductive element 110 disposed within the via. The composite conductive element 110 includes a conductive post 1101 and an insulating wall 1102. The insulating wall 1102 is attached to the inner sidewall of the via to completely isolate the conductive post 1101 from the metal substrate 100. This ensures that the conductive post 1101 remains insulated from the metal substrate 100 throughout its penetration, effectively avoiding the risk of short circuits caused by direct contact between the conductive material and the metal substrate 100. The conductive post 1101 is encased within the insulating wall 1102, using the insulating wall 1102 as a barrier to enclose the conductive post 1101 in the central region. This not only ensures the continuity of current transmission but also enhances the structural strength of the via structure through this nested structure. Through the coordinated operation of the insulating wall 1102 and the conductive post 1101, this structural design achieves reliable electrical connection between the circuit layers on both sides of the metal substrate 100 while resolving the electrical interference problem that may arise from the metal substrate 100 acting as a conductive medium, thus improving the electrical safety and operational stability of the device in complex working environments. In the aforementioned high-power LED device, the A-pole of the light-emitting chip 20 is electrically connected to the A-pole pad 1031, and the B-pole is electrically connected to the B-pole pad 1032. The A-pole pad 1031 and the B-pole pad 1032 are respectively electrically connected to the A-pole pin 1041 and the B-pole pin 1042 through via structures. By setting the insulating wall 1102, the conductive post 1101 is effectively isolated from the metal substrate 100, thereby ensuring a complete and reliable electrical path from the light-emitting chip 20 to the pins and avoiding device failure due to short circuits.

[0033] Here, the insulating wall 1102 can penetrate only the first insulating layer 101, the metal substrate 100, and the second insulating layer 102, while the two ends of the conductive post 1101 protrude from the insulating wall 1102 in the axial direction and are in contact with the first circuit layer 103 and the second circuit layer 104, respectively. Alternatively, the insulating wall 1102 can penetrate the first circuit layer 103, the first insulating layer 101, the metal substrate 100, the second insulating layer 102, and the second circuit layer 104. In this case, a first conductive layer 105 needs to be added to the surface of the first circuit layer 103, and a second conductive layer 106 needs to be added to the surface of the second circuit layer 104, so that the end face of one end of the conductive post 1101 is electrically connected to the pad of the first circuit layer 103 through the first conductive layer 105, and the end face of the other end is electrically connected to the pin of the second circuit layer 104 through the second conductive layer 106.

[0034] Example 2 To achieve optimal heat dissipation, the A and B electrodes of the light-emitting chip 20 in the aforementioned high-power LED device are both located on its top surface. For example, the light-emitting chip 20 can be a vertically structured chip, with its A and B electrodes led out to the top surface of the chip body through a metallization layer. After the light-emitting chip 20 is die-bonded to the first protrusion 1001, its top surface A electrode is bonded to the A electrode pad 1031 via conductive leads 202, and its B electrode is bonded to the B electrode pad 1032 via conductive leads 202. These conductive leads 202 form a certain arc after bonding, and its highest point is the height of the arc of the conductive lead 202. Since the bottom of the light-emitting chip 20 is in direct contact with the first protrusion 1001, direct heat conduction between the light-emitting chip 20 and the substrate 10 can be achieved. However, the conductive leads 202 that realize electrical connection are easily squeezed or deformed during packaging or use, resulting in a decrease in the reliability of electrical connection.

[0035] In response, Figure 7 The specific structure of Embodiment 2 of the high-power LED device of the present invention is shown. The high-power LED device of Embodiment 2 has a similar structure to that of Embodiment 1, the difference being that the high-power LED device of Embodiment 2 further includes a support structure 30. For example... Figure 7 As shown, the support structure 30 is disposed on the surface of the first circuit layer 103 away from the first insulating layer 101 and surrounds the light-emitting chip 20, and the height of the support structure 30 is not less than the height of the arc of the conductive lead 202.

[0036] Specifically, the support structure 30 can be formed using various materials and processes. For example, it can be molded (using encapsulation materials such as epoxy resin or silicone) to form a dam structure around the light-emitting chip 20. The main function of the support structure 30 is to provide physical protection for the light-emitting chip 20. The support structure 30 enclosing the light-emitting chip 20 means that the support structure 30 surrounds the light-emitting chip 20 on a plane, forming a closed or semi-closed area. For example, the support structure 30 can be a... Figure 7The rectangular frame shown can also be a circular ring or a polygonal frame, with an appropriate gap between its inner wall and the outer surface of the light-emitting chip 20. This enclosure can be achieved through precision injection molding, adhesive curing, or prefabricated frame mounting. The enclosure design ensures that the support structure 30 can fully protect the light-emitting chip 20 and the conductive leads 202 above it, preventing external stress from acting on the light-emitting chip 20 and its conductive leads 202 from all directions. The height of the support structure 30 is not less than the height of the arc of the conductive lead 202, which means that the height of the support structure 30 extending upward from the surface of the substrate 10 must at least reach or exceed the highest point of the arc of the conductive lead 202 formed when the top surface of the light-emitting chip 20 is connected to the pad through the conductive lead 202. When the height of the support structure 30 is higher than or equal to the highest point of the arc of the conductive lead 202, the support structure 30 can form a physical barrier, completely covering the conductive lead 202 within the protection range, preventing the conductive lead 202 from being squeezed, scratched, or deformed during subsequent packaging and transportation, and can also serve as a support structure for other mounting components (such as lenses).

[0037] Example 3 Although the aforementioned high-power LED device achieves heat dissipation and electrical separation from the circuit layer through the protrusions on the metal substrate 100, in practical applications, high-power LED devices are susceptible to electrostatic discharge or surge voltage during operation, which can damage the internal structure of the light-emitting chip 20, thereby affecting the reliability and service life of the device.

[0038] In response, Figure 8 The specific structure of Embodiment 3 of the high-power LED device of the present invention is shown. The high-power LED device of Embodiment 3 has a similar structure to that of Embodiment 2, the difference being that the high-power LED device of Embodiment 3 also includes a Zener diode 40. The Zener diode 40 is a semiconductor device with a specific reverse breakdown voltage, having A and B terminals with opposite polarities, which is the electrical characteristic required for the normal operation of the Zener diode 40. When the voltage across the Zener diode 40 reaches or exceeds this breakdown voltage, the Zener diode 40 will quickly conduct, clamping the excessive voltage to a relatively stable level, thereby protecting other sensitive components in the circuit from overvoltage damage. Figure 8 As shown, the Zener diode 40 is die-bonded to the base plate 1032 of the first circuit layer 103. Its base plate (B-pole) at the bottom of the main body is in contact with the base plate 1032, and its base plate (A-pole) at the top of the main body is electrically connected to the base plate 1031 via a conductive lead 202. This electrical connection aims to connect the Zener diode 40 in parallel to the power supply circuit of the light-emitting chip 20, enabling it to monitor and respond to the voltage state across the light-emitting chip 20 in real time. Specifically, for... Figure 8The vertical Zener diode 40 shown is die-bonded to the B-type pad 1032. The B-type electrode located at the bottom of the Zener diode 40 body is directly electrically connected to the B-type pad 1032 through processes such as reflow soldering. The A-type electrode located at the top of the Zener diode 40 body is electrically connected to the A-type pad 1031 through conductive lead 202.

[0039] Thus, by integrating a Zener diode 40 onto the substrate 10 of the aforementioned high-power LED device and connecting it in parallel with the A and B terminals of the light-emitting chip 20, an overvoltage protection mechanism is introduced for the device. Specifically, under normal operating conditions, the voltage across the light-emitting chip 20 is within its rated operating range. At this time, the Zener diode 40 is in reverse cutoff, exhibiting high impedance, and does not affect the normal operation of the light-emitting chip 20. When external environmental factors, such as electrostatic discharge or surge voltage, cause the voltage across the light-emitting chip 20 to rise instantaneously and exceed the breakdown voltage of the Zener diode 40, the Zener diode 40 will quickly reverse conduct, forming a low-impedance path. Through this path, the excessive voltage and current are absorbed and discharged by the Zener diode 40, thereby clamping the voltage across the light-emitting chip 20 to its Zener voltage value, effectively preventing overvoltage damage to the internal structure of the light-emitting chip 20. Figure 8 In the illustrated embodiment, the existing circuit layout on the surface of the substrate 10 is utilized to die-bond the Zener diode 40 to the first circuit layer 103, eliminating the need for additional complex connection structures and ensuring the compactness of the overall device structure. Simultaneously, since the light-emitting chip 20 is die-bonded to the first protrusion 1001, and its A and B terminals are electrically connected to the A-terminal pad 1031 and B-terminal pad 1032 respectively, and the Zener diode 40 is also connected in parallel with these pads, the Zener diode 40 can directly and in real-time monitor the voltage state of the light-emitting chip 20. This tight integration not only simplifies the manufacturing process but also ensures that the protection circuit can respond quickly, effectively improving the anti-interference capability and operational stability of the LED device in complex electrical environments.

[0040] To prepare the high-power LED device of Example 1, the present invention also provides a method for manufacturing a high-power LED device, such as... Figure 9 As shown, the manufacturing method includes the following steps: S1: Prepare a metal substrate 100, wherein the first surface of the metal substrate 100 has an integrally formed first boss 1001, and the second surface of the metal substrate 100 has an integrally formed second boss 1002, and the second surface and the first surface are disposed opposite to each other along the thickness direction of the metal substrate 100. A first insulating layer 101 and a second insulating layer 102 are prepared. A first circuit layer 103 including an A-pole pad 1031 and a B-pole pad 1032 is formed on the surface of the first insulating layer 101 according to a preset pattern. A first opening 1010 is opened at the position corresponding to the first boss 1001 of the first insulating layer 101 for the first boss 1001 to pass through. A second circuit layer 104 including an A-pole pin 1041 and a B-pole pin 1042 is formed on the surface of the second insulating layer 102 according to a preset pattern. A second opening 1020 is opened at the position corresponding to the second boss 1002 of the second insulating layer 102 for the second boss 1002 to pass through.

[0041] Specifically, a copper sheet is cut to form a metal substrate 100 with a thickness of 0.5~2.0mm. A first boss 1001 with a height of 0.1~0.2mm is formed on the first surface of the metal substrate 100 by CNC deep milling, and a second boss 1002 with a height of 0.1~0.2mm is formed on the second surface of the metal substrate 100. Then, the surfaces of the first boss 1001 and the second boss 1002 are roughened, cleaned and degreased.

[0042] Furthermore, copper is deposited on the surfaces of the first insulating layer 101 and the second insulating layer 102. A first circuit layer 103, including an A-pole pad 1031 and a B-pole pad 1032, is formed on the surface of the first insulating layer 101 by etching according to a preset pattern. A second circuit layer 104, including an A-pole pin 1041 and a B-pole pin 1042, is formed on the surface of the second insulating layer 102. Furthermore, a window is made at the position corresponding to the first protrusion 1001 in the first insulating layer 101, forming a first opening 1010 through which the first protrusion 1001 can pass; and a window is made at the position corresponding to the second protrusion 1002 in the second insulating layer 102, forming a second opening 1020 through which the second protrusion 1002 can pass. The size of the window is 0.05~0.1mm larger than the distance between one side of the first protrusion 1001 / second protrusion 1002 to ensure that the first protrusion 1001 / second protrusion 1002 can pass smoothly through the insulating layer. The sizes of the first opening 1010 and the second opening 1020 are slightly larger than the sizes of the corresponding first protrusion 1001 and second protrusion 1002 to ensure that the first protrusion 1001 and second protrusion 1002 can pass smoothly through.

[0043] S2: The first insulating layer 101 with the first circuit layer 103, the metal substrate 100, and the second insulating layer 102 with the second circuit layer 104 are sequentially stacked along the thickness direction of the metal substrate 100 to form a laminate. Then, the laminate is vacuum-pressed to form a substrate 10.

[0044] Specifically, the first insulating layer 101 with the first circuit layer 103, the metal substrate 100, and the second insulating layer 102 with the second circuit layer 104 are stacked sequentially from top to bottom, so that the first opening 1010 and the first boss 1001 and the second opening 1020 and the second boss 1002 are precisely aligned to form a laminate. The laminate is then placed in a vacuum hot press to press it together to form substrate 10. By hot pressing the laminate simultaneously from both the top and bottom directions under vacuum conditions, bubbles, delamination, and adhesive overflow can be avoided, thus improving product yield.

[0045] Preferably, after the substrate 10 is formed by vacuum hot pressing, the substrate 10 is subjected to surface treatment, including flattening the substrate 10 to release internal stress, and then polishing, micro-etching and cleaning the first and second bosses 1001, 1002 and the first and second circuit layers 103, 104 to ensure that the surface is clean and flat.

[0046] S3: At least two via structures are formed on the substrate 10, the via structures passing through the first insulating layer 101, the metal substrate 100 and the second insulating layer 102, so that the A-pole pad 1031 is electrically connected to the A-pole pin 1041 through a via structure, and the B-pole pad 1032 is electrically connected to the B-pole pin 1042 through a via structure.

[0047] Specifically, the following method is proposed for forming a via structure on the substrate 10 that at least penetrates the first insulating layer 101, the metal substrate 100, and the second insulating layer 102, which includes the following steps: S31: Drill holes in the substrate 10 to form two vias that penetrate at least the first insulating layer 101, the metal substrate 100, and the second insulating layer 102; Specifically, drilling on the substrate 10 refers to forming holes of a predetermined shape and size on the substrate 10, which has been formed by vacuum hot pressing, by removing material. Its function is to provide physical channels for subsequent insulating and conductive structures, ensuring that conductive paths can penetrate different layers of the substrate 10. Drilling can be performed in various ways. For example, a mechanical drill bit can be used to perform high-speed rotary drilling on the substrate 10 to form through holes with a specific diameter and depth; alternatively, laser drilling technology can be used to precisely ablate the substrate 10 with a high-energy laser beam, thereby forming vias that sequentially penetrate the first insulating layer 101, the metal substrate 100, and the second insulating layer 102; furthermore, it can be achieved through water jet cutting or other methods. Through holes with a diameter of 0.9 to 1.3 mm are formed through drilling.

[0048] S32: Insulating material is inserted into the via to completely cover the via wall. The purpose of this step is to establish reliable electrical isolation between the metal substrate 100 and the conductive pillar 1101 to be formed. The insertion of the insulating material can be achieved by electrophoretic deposition, where insulating particles are uniformly deposited on the inner wall of the via to form a dense insulating wall 1102; alternatively, a uniform insulating film, such as silicon oxide or silicon nitride, can be grown on the inner wall of the via using chemical vapor deposition (CVD) or physical vapor deposition (PVD); or, a liquid insulating resin (e.g., epoxy resin, polyimide) can be sprayed or poured in followed by curing to ensure that the via wall is completely covered by the insulating material, thereby providing sufficient electrical insulation. S33: Drill a hole in the insulating material filling the via to form a hollow insulating wall 1102. The diameter of the hollow portion of the insulating wall 1102 is 0.45~0.50 mm, and it is coaxial with the via. This step aims to precisely form a hollow channel inside the insulating material filling the via, providing space for the subsequent conductive post 1101, while ensuring the thickness and integrity of the insulating wall 1102. The secondary drilling can be performed mechanically using a micro drill bit to precisely remove the central portion of the insulating material, forming a hollow structure with a predetermined inner diameter; or, laser secondary drilling technology can be used to precisely control the energy and path of the laser to ablate a hollow channel inside the insulating material, thereby forming the hollow insulating wall 1102.

[0049] S34: Conductive pillars 1101 with a diameter of 0.40~0.45mm are filled into the hollow space of the insulating wall 1102, so that both ends of the conductive pillars 1101 are electrically connected to the first circuit layer 103 and the second circuit layer 104 respectively, forming a via structure. The purpose of this step is to construct an actual conductive path and realize the electrical connection between the first circuit layer 103 and the second circuit layer 104. The filling of the conductive pillars 1101 can be achieved by electroplating filling technology, where conductive metals such as copper and nickel are filled into the hollow space of the insulating wall 1102 through electrochemical deposition until a solid conductive pillar 1101 is formed; alternatively, conductive paste filling can be used, where conductive silver paste or copper paste is poured into the hollow space and then sintered and solidified to form the conductive pillar 1101; or, the conductive pillars 1101 can be prefabricated and then inserted into the hollow space of the insulating wall 1102, and their two ends are reliably electrically connected to the first circuit layer 103 and the second circuit layer 104 by conductive adhesive or welding.

[0050] Thus, through a step-by-step drilling and filling process, the via structure is precisely constructed, effectively solving the short-circuit risk that may occur when the metal substrate 100 acts as a conductor and the via penetrates the substrate. First, vias penetrating the first insulating layer 101, the metal substrate 100, and the second insulating layer 102 are formed by drilling holes in the substrate 10, laying the foundation for subsequent insulation and conductive structures. Next, insulating material is filled into the vias and completely covers the via walls. This crucial step ensures a reliable insulating layer between the metal substrate 100 and the future conductive pillar 1101, thereby guaranteeing the electrical safety of the device and avoiding short-circuit problems caused by the conductivity of the metal substrate 100. Then, the vias filled with insulating material are drilled a second time to form hollow insulating walls 1102. Compared to directly coating the inner wall of the metal via, this method offers higher geometric accuracy and process stability, avoiding problems of uneven insulation layer thickness or incomplete coverage, further improving the reliability of the insulation. Finally, conductive pillars 1101 are filled into the hollow space of the insulating wall 1102, enabling the conductive pillars 1101 to form a stable electrical connection with the first circuit layer 103 and the second circuit layer 104. This structural design not only ensures a smooth current transmission path but also eliminates the interference of the metal substrate 100 on the conductive path through the physical barrier of the insulating wall 1102, thereby improving the reliability and manufacturing yield of the overall packaging structure. Combined with the integrally formed boss structure of the substrate 10, this method minimizes the heat conduction path between the light-emitting chip 20 and the metal substrate 100. Simultaneously, through a precisely controlled via structure fabrication process, it ensures the reliability of the electrical connection and the integrity of the insulation, thus providing excellent electrothermal performance for high-power LED devices.

[0051] Although the above method can form a via structure on the substrate 10 to achieve interlayer electrical connection, in the actual manufacturing process, the process of forming a hollow insulating wall 1102 by drilling, filling with insulating material, and then drilling again is not only complicated, but also makes it difficult to ensure the uniformity of the thickness of the insulating wall 1102 and the tightness of the fit between the insulating wall 1102 and the inner wall of the via, thus affecting the reliability and heat dissipation performance of the via structure.

[0052] To this end, forming at least two via structures penetrating the first insulating layer 101, the metal substrate 100, and the second insulating layer 102 on the substrate 10 can also be achieved by the following method, which includes the following steps: S31: Drill holes in the substrate 10 to form two vias that penetrate at least the first insulating layer 101, the metal substrate 100, and the second insulating layer 102, wherein the diameter of the vias is 0.9 to 1.3 mm. Furthermore, a composite conductive component 110 is prepared, which includes a conductive post 1101 and an insulating wall 1102 covering the outer peripheral side of the conductive post 1101. S32: Fill the via with the composite conductive component 110 to form a via structure.

[0053] Specifically, preparing the composite conductive component 110 refers to prefabricating or procuring a conductive assembly with a specific structure and material combination before filling it into the via. This prefabrication method aims to integrate conductive and insulating functions into a single unit, thereby simplifying the subsequent assembly process and improving the quality and reliability of the via structure. The composite conductive component 110 is an integrated structure that pre-bonds the conductive and insulating parts. This design makes the installation of the via structure more convenient and precise. The conductive post 1101 is the core conductive part of the composite conductive component 110, and its main function is to provide a low-resistance electrical connection path, electrically connecting the A-pole pad 1031 or B-pole pad 1032 on the first circuit layer 103 to the A-pole pin 1041 or B-pole pin 1042 on the second circuit layer 104. The material of the conductive post 1101 is usually a metal with excellent conductivity, such as copper, silver, gold, or their alloys. The insulating wall 1102 is an insulating layer covering the outer periphery of the conductive post 1101. Its main function is to ensure reliable electrical insulation between the conductive post 1101 and the surrounding metal substrate 100, preventing short circuits. The material of the insulating wall 1102 is usually an insulating material with high dielectric strength and good heat resistance, such as polyimide, epoxy resin, ceramic materials, or glass fiber reinforced resin. Pre-assembling the insulating wall 1102 and the conductive post 1101 into a composite conductive element 110 (diameter 0.9–1.3 mm) with dimensions matching the through hole ensures uniformity of the insulating layer thickness and a tight fit with the conductive post 1101. Filling the through hole with the composite conductive element 110 to form a through hole structure refers to inserting the pre-fabricated composite conductive element 110 into the formed through hole. This filling method can employ various techniques, such as: press-fit, where the composite conductive component 110 is precisely pressed into the through-hole using mechanical force, achieving a tight fixation through an interference fit; adhesive bonding, where an adhesive is applied to the outer periphery of the composite conductive component 110 or the inner wall of the through-hole, then inserted and cured to achieve a strong connection; or welding. After filling, the two ends of the conductive post 1101 in the composite conductive component 110 can directly contact the first circuit layer 103 and the second circuit layer 104, respectively, or the first conductive layer 105 and the second conductive layer 106, formed through thickening treatment, can be electrically connected to the first circuit layer 103 and the second circuit layer 104, respectively. The insulating wall 1102 is tightly fitted to the wall of the through-hole, thus forming a complete through-hole structure. To further enhance the reliability of the connection, partial reflow soldering or the use of conductive adhesive for auxiliary fixation can be performed after pressing.

[0054] Thus, by introducing a pre-fabricated composite conductive component 110, the complex process of filling the holes with insulating material and secondary drilling in the traditional method is replaced. After the substrate 10 is formed by vacuum hot pressing, through-holes penetrating at least the first insulating layer 101, the metal substrate 100, and the second insulating layer 102 are first precisely formed on the substrate 10 by a drilling process; subsequently, the pre-prepared composite conductive component 110 is filled into these through-holes. The composite conductive component 110 consists of an internal conductive pillar 1101 and an insulating wall 1102 covering the outer peripheral side of the conductive pillar 1101. When the composite conductive component 110 is filled into the via, its internal conductive pillar 1101 can reliably connect with the A-pole pad 1031 or B-pole pad 1032 on the first circuit layer 103 and the A-pole pin 1041 or B-pole pin 1042 on the second circuit layer 104. Meanwhile, the external insulating wall 1102 tightly adheres to the via wall, effectively isolating the conductive pillar 1101 from the surrounding metal substrate 100. This integrated, prefabricated filling method ensures the insulation and conductivity of the via structure, avoiding problems such as interface voids and uneven insulation layer thickness caused by uneven filling of insulating material or curing shrinkage in traditional processes. This significantly simplifies the via structure fabrication process while improving its structural stability and electrical reliability, providing efficient and stable interlayer electrical interconnection for high-power LED devices.

[0055] Through the above technical solution, this invention effectively solves the problems of complex traditional processes, poor uniformity of insulating wall 1102 thickness, and easy generation of voids or defects at the interface when forming via structures on substrate 10. By introducing a pre-fabricated composite conductive component 110 and directly filling it into the via, the via structure preparation process is fundamentally simplified, avoiding the cumbersome steps of filling insulating material and secondary drilling on-site. This integrated composite conductive component 110 design ensures a high degree of fit between the insulating wall 1102 and the conductive post 1101, eliminating interface voids and defects caused by material shrinkage or uneven filling, and significantly improving the structural stability and electrical insulation reliability of the via structure. At the same time, the precise dimensional control of the pre-fabricated component allows for higher assembly accuracy of the via structure in the metal substrate 100, reducing manufacturing risks, thereby providing more reliable and efficient interlayer electrical connections for high-power LED devices, and thus ensuring the long-term stable operation and performance of the devices. If the second method described above is chosen to form the via structure, in order to make the conductive pillar 1101 of the composite conductive component 110 electrically connected to the first circuit layer 103 and the second circuit layer 104 respectively, after forming the via structure, the surface of the substrate 10 needs to be surface treated to form a first conductive layer 105 connecting the first circuit layer 103 and one end face of the conductive pillar 1101, and a second conductive layer 106 connecting the second circuit layer 104 and the other end face of the conductive pillar 1101. Specifically, nickel and gold layers are electroplated onto the first circuit layer 103 and the second circuit layer 104 respectively, so that the circuit layer, the hole wall and the conductive pillar 1101 area are metallized and thickened.

[0056] S4: The light-emitting chip 20 with opposite polarities A and B is die-bonded to the first boss 1001, and the A of the light-emitting chip 20 is electrically connected to the A pad 1031, and the B is electrically connected to the B pad 1032.

[0057] Specifically, the light-emitting chip 20 is die-bonded onto the first boss 1001 and wire bonded to it, so that the A-pole of the light-emitting chip 20 is connected to the A-pole pad 1031 through the conductive lead 202, and its B-pole is connected to the B-pole pad 1032 through the conductive lead 202.

[0058] Furthermore, in the actual manufacturing process, if the sum of the thicknesses of the insulating layer and the circuit layer on the surface of the metal substrate 100 does not match the height of the boss, it will result in a height difference between the surface of the boss and the surface of the circuit layer, which will lead to problems such as uneven die bonding, decreased wire bonding stability, and interlayer lamination defects.

[0059] In this regard, in step S1, the sum of the thicknesses of the first insulating layer 101 and the first circuit layer 103 is equal to the height of the first boss 1001, and the sum of the thicknesses of the second insulating layer 102 and the second circuit layer 104 is equal to the height of the second boss 1002.

[0060] Specifically, the first protrusion 1001 is an integrally formed structure on the first surface of the metal substrate 100, serving as the direct die-bonding area for the light-emitting chip 20, and its height is preset. Precisely setting the sum of the thicknesses of the first insulating layer 101 and the first circuit layer 103 to be equal to the height of the first protrusion 1001 means that after the substrate 10 is formed, the top surface of the first protrusion 1001 will be at the same level as the surface of the first circuit layer 103. This thickness matching can be achieved by precisely controlling the thickness of each layer, processing accuracy, and lamination process parameters. For example, during the material selection stage, materials of suitable thickness for the first insulating layer 101 and the first circuit layer 103 are selected based on the preset height of the first protrusion 1001; during the manufacturing process, the thickness of each layer is monitored and adjusted in real time using high-precision measuring equipment.

[0061] Similarly, the second insulating layer 102 is an insulating layer disposed on the second surface of the metal substrate 100, used to isolate the second circuit layer 104 from the metal substrate 100 and provide electrical insulation protection. This layer can be implemented using similar materials and processes as the first insulating layer 101. The second circuit layer 104 includes an A-pole pin 1041 and a B-pole pin 1042 for electrical connection with external circuits. This layer can also be formed from conductive materials such as copper foil or aluminum foil through processes such as photolithography and etching. The second boss 1002 is a structure integrally formed on the second surface of the metal substrate 100, and its height is also preset. By precisely setting the sum of the thicknesses of the second insulating layer 102 and the second circuit layer 104 to be equal to the height of the second boss 1002, it is ensured that the top surface of the second boss 1002 is on the same plane as the surface of the second circuit layer 104. This thickness matching also requires precise material selection and process control to achieve.

[0062] The above manufacturing method achieves flushing of the boss surface and the circuit layer surface by precisely matching the thickness of each functional layer of the substrate 10. In fabricating a high-power LED device, a metal substrate 100 with an integrally formed first boss 1001 and second boss 1002 is first prepared, and a first circuit layer 103 and a second circuit layer 104 are formed on the first insulating layer 101 and the second insulating layer 102, respectively. Subsequently, these layers are stacked sequentially along the thickness direction, and the substrate 10 is formed by a vacuum hot-pressing process. During this process, by setting the sum of the thicknesses of the first insulating layer 101 and the first circuit layer 103 to be consistent with the height of the first boss 1001, it is ensured that when the light-emitting chip 20 is die-bonded, the bottom of the chip is at the same level as the A-pole pad 1031 and the B-pole pad 1032 area, eliminating die-bonding tilt or stress concentration caused by height differences, thereby improving the reliability and stability of die bonding. Meanwhile, the sum of the thicknesses of the second insulating layer 102 and the second circuit layer 104 is set to match the height of the second boss 1002, ensuring the flatness of the back side of the substrate 10. This not only facilitates the tight bonding of the substrate 10 with the external heat sink or circuit board in subsequent processes, reducing contact thermal resistance, but also avoids glue overflow, bubbles, or interlayer delamination caused by uneven thickness during vacuum hot pressing. This precise control of thickness optimizes the flatness of the substrate 10 at the structural level, providing a fundamental guarantee for the efficient heat dissipation and long-term structural stability of high-power LED devices. In this way, the integrally formed boss structure can more effectively serve as the die-bonding area of ​​the light-emitting chip 20, providing a low thermal resistance channel, while precise thickness matching ensures the manufacturing reliability and performance stability of the structure, resulting in superior performance in both heat dissipation and electrical connection of the entire device.

[0063] Thus, the above structural design solves the problems of uneven die bonding, decreased wire bonding stability, and interlayer bonding defects caused by the mismatch between the sum of the thicknesses of the insulating layer and the circuit layer and the height of the boss during the fabrication process. This precise thickness matching ensures the flatness of the die bonding area of ​​the light-emitting chip 20, significantly improving the reliability of die bonding and the stability of wire bonding, and reducing stress concentration caused by height differences. At the same time, the flatness of the back side of the substrate 10 is guaranteed, which is conducive to the tight bonding of the device with the external heat sink or circuit board, thereby effectively reducing contact thermal resistance and further improving the overall heat dissipation performance of high-power LED devices. In addition, during the vacuum hot pressing process, thickness uniformity avoids the generation of manufacturing defects such as bubbles, delamination, or excess adhesive, improving product yield and the structural integrity and long-term reliability of the device.

[0064] To manufacture the high-power LED device of Example 2, such as Figure 10 As shown, after completing step S4, the following steps are also included: S5: A support structure 30 is formed on the substrate 10 to enclose the light-emitting chip 20, and the height of the support structure 30 is not less than the height of the arc of the conductive lead 202. Specifically, the support structure 30 is formed by hot pressing and bonding with a mold, and the bonding material is generally selected as high-temperature resistant silicone or silicone resin. The shortest distance between the inner wall of the support structure 30 and the conductive lead 202 of the light-emitting chip 20 should be greater than 0.05mm to prevent the support structure 30 from touching the conductive lead 202. The height of the formed support structure 30 is preferably 0.3~0.5mm. On the one hand, this ensures that the height of the support structure 30 is not less than the arc height of the conductive lead 202, in order to address reliability issues caused by the conductive lead 202 being crushed or deformed during subsequent storage and use; on the other hand, it avoids an increase in the overall thickness of the device due to excessive height. The color of the support structure 30 is preferably white to facilitate better light emission and reduce light absorption.

[0065] To manufacture the high-power LED device of Example 3, such as Figure 11 As shown, step S4 also includes the following steps: Zener diode 40 is die bonded to B-side pad 1032, so that the B-side at the bottom of the body is electrically connected to the B-side pad 1032. Zener diode 40 is then wired so that the A-side of Zener diode 40 is electrically connected to the A-side pad 1031 through conductive lead 202.

[0066] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application. The singular forms “a,” “the,” and “the” used in the embodiments and claims of this application are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that, unless otherwise stated, “a plurality” means two or more; the terms “first,” “second,” “third,” etc., are used only to distinguish and not to describe a particular order or sequence, nor should they be construed as indicating or implying relative importance. The term “and / or” as used herein refers to and includes any or all possible combinations of one or more associated listed items. When the above description relates to drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. In the description of this application, those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0067] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A high-power LED device, characterized in that: The device includes a substrate and a light-emitting chip disposed on the substrate, wherein the light-emitting chip has an A pole and a B pole with opposite polarities; The substrate includes a metal substrate, a first protrusion integrally formed on a first surface of the metal substrate, a first insulating layer covering the first surface, and a first opening for the first protrusion to pass through at a position corresponding to the first protrusion on the first insulating layer; a first circuit layer is provided on the surface of the first insulating layer facing away from the metal substrate, and the first circuit layer includes A-pole pads and B-pole pads that do not contact each other. The second surface of the metal substrate is provided with an integrally formed second protrusion, wherein the second surface and the first surface are disposed opposite to each other along the thickness direction, the second surface is covered with a second insulating layer, and the second insulating layer is provided with a second opening for the second protrusion to extend out at the position corresponding to the second protrusion; the surface of the second insulating layer facing away from the metal substrate is provided with a second circuit layer, the second circuit layer including A-pole pins and B-pole pins that do not contact each other; The substrate is provided with at least two via structures. The A-pole pad is electrically connected to the A-pole pin through one via structure, and the B-pole pad is electrically connected to the B-pole pin through another via structure. The light-emitting chip is die-bonded on the first boss, and the A-pole of the light-emitting chip is electrically connected to the A-pole pad, and the B-pole is electrically connected to the B-pole pad.

2. The high-power LED device according to claim 1, characterized in that: The orthographic projection of the first boss on the reference plane and the orthographic projection of the second boss on the same reference plane at least partially overlap, wherein the reference plane is a plane perpendicular to the thickness direction of the metal substrate.

3. The high-power LED device according to claim 2, characterized in that: The area of ​​the second boss is not less than 1 / 2 of the area of ​​the second surface of the metal substrate.

4. The high-power LED device according to claim 1, characterized in that: The via structure includes a via penetrating the first insulating layer, the metal substrate, and the second insulating layer, and a composite conductive element disposed within the via. The composite conductive element includes a conductive post and an insulating wall covering the outer peripheral side of the conductive post. The outer peripheral side of the insulating wall is attached to the inner sidewall of the via.

5. The high-power LED device according to claim 4, characterized in that: The orthographic projection of the A-pole pin on the reference plane and the orthographic projection of the A-pole pad on the same reference plane at least partially overlap, and the overlapping portion forms a first overlapping area; one of the via structures is disposed in the first overlapping area, and the via structure penetrates the A-pole pad, the first insulating layer, the metal substrate, the second insulating layer and the A-pole pin; The orthographic projection of the B-pole pin on the reference plane and the orthographic projection of the B-pole pad on the same reference plane at least partially overlap, and the overlapping portion forms a second overlapping area; another via structure is disposed in the second overlapping area, and the via structure penetrates the B-pole pad, the first insulating layer, the metal substrate, the second insulating layer and the B-pole pin.

6. The high-power LED device according to any one of claims 1 to 5, characterized in that: The A-pole and B-pole of the light-emitting chip are both disposed on the top surface of the light-emitting chip. The A-pole is electrically connected to the A-level pad through a conductive lead, and the B-pole is connected to the B-pole pad through a conductive lead. The high-power LED device also includes a support structure disposed on the substrate, the support structure enclosing the light-emitting chip, and the height of the support structure is not less than the height of the conductive lead arc.

7. A method for manufacturing a high-power LED device, characterized in that; Includes the following steps: S1: Prepare a metal substrate, wherein the first surface of the metal substrate has an integrally formed first boss, the second surface of the metal substrate has an integrally formed second boss, and the second surface and the first surface are disposed opposite to each other along the thickness direction of the metal substrate; Prepare a first insulating layer and a second insulating layer. Form a first circuit layer including an A-pole pad and a B-pole pad on the surface of the first insulating layer according to a preset pattern. Open a first opening in the first insulating layer at the position corresponding to the first boss so that the first boss can pass through. A second circuit layer including A-pole pins and B-pole pins is formed on the surface of the second insulating layer according to a preset pattern, and a second opening is made at the position of the second boss in the second insulating layer for the second boss to pass through. S2: The first insulating layer with the first circuit layer, the metal substrate, and the second insulating layer with the second circuit layer are sequentially stacked along the thickness direction to form a laminate. Then, the laminate is vacuum hot-pressed to form a substrate. S3: Form at least two via structures on the substrate, the via structures penetrating the first insulating layer, the metal substrate and the second insulating layer, so that the A-pole pad is electrically connected to the A-pole pin through one via structure and the B-pole pad is electrically connected to the B-pole pin through another via structure; S4: A light-emitting chip with opposite polarities, A and B, is die-bonded to the first boss, and the A terminal of the light-emitting chip is electrically connected to the A terminal pad, and the B terminal is electrically connected to the B terminal pad.

8. The method for manufacturing a high-power LED device according to claim 7, characterized in that: In step S3, forming at least two via structures penetrating the first insulating layer, the metal substrate, and the second insulating layer on the substrate includes the following steps: S31: Drill holes in the substrate to form vias that penetrate the first insulating layer, the metal substrate and the second insulating layer; S32: Insulating material is inserted into the via so that the insulating material completely covers the wall of the via; S33: Drill holes in the insulating material filling the through-hole to form a hollow insulating wall; S34: Fill the hollow space of the insulating wall with conductive pillars, so that the two ends of the conductive pillars are electrically connected to the first circuit layer and the second circuit layer respectively, forming the via structure.

9. The method for manufacturing a high-power LED device according to claim 7, characterized in that: In step S3, forming at least two via structures penetrating the first insulating layer, the metal substrate, and the second insulating layer on the substrate includes the following steps: S31: Drill holes in the substrate to form vias that penetrate the first insulating layer, the metal substrate and the second insulating layer; Prepare a composite conductive component, the composite conductive component including a conductive post and an insulating wall covering the outer peripheral side of the conductive post; S32: The composite conductive element is filled into the via to form the via structure.

10. The method for manufacturing a high-power LED device according to claim 7, characterized in that: In step S1, the sum of the thicknesses of the first insulating layer and the first circuit layer is equal to the height of the first boss, and the sum of the thicknesses of the second insulating layer and the second circuit layer is equal to the height of the second boss.

11. The method for manufacturing a high-power LED device according to any one of claims 7 to 10, characterized in that: It also includes the following steps: S5: A support structure is formed on the substrate to enclose the light-emitting chip, and the height of the support structure is not less than the height of the conductive lead arc.

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