Method for manufacturing a semiconductor structure and display device

Abstract

The application provides a preparation method of a semiconductor structure and a display device. In the preparation method, common functional layers of light emitting devices of different light emitting colors are simultaneously prepared by the same process technology, and different functional layers of the light emitting devices of different light emitting colors are respectively prepared, so that the preparation of the multi-color light emitting device on the substrate can be realized. The coupling and output of multi-color light can be completed without the aid of optical components, the structure of the display system can be simplified, and the cost can be reduced. The above-mentioned method prepares light emitting devices of different colors on the same substrate by means of selective growth, which can reduce the damage to the light emitting devices and improve the preparation yield compared with the etching preparation method. The above-mentioned preparation method can realize large-scale manufacturing and obtain a semiconductor structure capable of full-color display.

Description

Technical Field

[0001] This application relates to the field of semiconductor device manufacturing technology, and more specifically, to a method for preparing a semiconductor structure and a display device. Background Technology

[0002] Microdisplay technology has become a core support for emerging fields such as AR (Augmented Reality), VR (Virtual Reality), near-eye displays, and automotive displays. Currently, this technology has entered a critical stage of large-scale application and technological iteration. MicroLED microdisplay chips, with their advantages of self-emission, high contrast, wide color gamut, fast response speed, and strong environmental adaptability, are gradually becoming the mainstream technology solution for next-generation high-performance microdisplays. However, in the path to achieving full-color, especially monolithic full-color displays, existing technologies still face common industry challenges that are difficult to overcome, becoming the main obstacle restricting the development of MicroLED microdisplay chips towards high integration, miniaturization, and low cost.

[0003] Current mainstream MicroLED full-color implementation solutions mostly rely on the independent fabrication and subsequent optical integration of multi-color micro-display devices (light-emitting devices). This requires precise optical components to couple and output multi-color light, leading to complex display system structures, stringent assembly precision requirements, and significantly increased manufacturing costs. This makes it difficult to meet the development demands for extreme miniaturization and ultra-high resolution in micro-display devices. Meanwhile, while monolithic integration is considered the optimal solution for simplifying structure and improving performance, existing technologies such as quantum dot color conversion and multi-layer heteroepitaxial stacking generally suffer from poor material compatibility, narrow process windows, photoelectric performance degradation, and difficulty in guaranteeing mass production yields. These limitations make it impossible to simultaneously meet the dual requirements of full-color display effects and large-scale manufacturing. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above background, this application provides a method for fabricating a semiconductor structure and a display device to solve the above technical problems.

[0005] A first aspect of this application provides a method for fabricating a semiconductor structure, the method comprising: A substrate is provided, wherein the substrate includes a substrate, a buffer layer and a mask layer stacked together, and the mask layer has a plurality of mask openings that expose the buffer layer; A first conductivity type semiconductor structure is formed on the substrate in the location region of each of the mask openings; A quantum well growth auxiliary layer and a quantum well layer are sequentially fabricated on the side of the first conductivity type semiconductor structure that forms different color light-emitting devices, away from the substrate; After completing the fabrication of the quantum well growth auxiliary layer and the quantum well layer on all the first conductivity type semiconductor structures, the second conductivity type semiconductor structure is simultaneously fabricated on the side of all quantum well layers away from the substrate. The first conductivity type semiconductor structure, the quantum well growth auxiliary layer, the quantum well layer and the second conductivity type semiconductor structure stacked together form a light-emitting device. In the light-emitting devices with different emission colors, the indium content of each quantum well growth auxiliary layer is different, and the indium content of each quantum well layer is different.

[0006] In one possible implementation, the step of providing a substrate includes: Provide a substrate; A buffer layer is fabricated on the substrate; A mask layer is fabricated on the buffer layer, and the mask layer is patterned to form multiple mask openings that expose the buffer layer.

[0007] In one possible implementation, the step of forming a first conductivity type semiconductor structure on the substrate at the location regions of each of the mask openings includes: Seed structures are epitaxially grown at each of the mask opening locations, wherein the seed structures fill the mask openings and form a cone structure on the side of the mask layer away from the substrate; A plurality of mutually spaced first cones are epitaxially grown using a first type of conductive material based on the seed structure, wherein the orthographic projection of the seed structure on the substrate is located within the orthographic projection of the first cones on the substrate; The first cone is subjected to a top-removal process to obtain a first conductivity type semiconductor structure located on the substrate.

[0008] In one possible implementation, the step of removing the top of the first cone to obtain a first conductivity type semiconductor structure located on the substrate includes: A protective layer is fabricated at least around the first cone using epitaxial growth and / or surface deposition, wherein, in a direction perpendicular to the plane of the substrate, the thickness of the protective layer is less than the thickness of the first cone and greater than the thickness of the seed structure; Using the side of the protective layer between adjacent first cones away from the substrate as the cutoff surface, the first cones are de-topped to obtain a first conductivity type semiconductor structure located on the substrate.

[0009] In one possible implementation, the light-emitting device includes a first light-emitting device, a second light-emitting device, and a third light-emitting device of different colors. The step of sequentially fabricating a quantum well growth auxiliary layer and a quantum well layer on the side of the first conductivity type semiconductor structure forming the different colored light-emitting devices away from the substrate includes: A first barrier layer is formed on the side of the first conductivity type semiconductor structure and the protective layer away from the substrate, and a first window is formed at the patterned part of the first barrier layer, wherein the first window only exposes the first conductivity type semiconductor structure used to form the first light-emitting device. A first quantum well growth auxiliary layer and a first quantum well layer are sequentially fabricated on the first conductivity type semiconductor structure exposed by the first window; A second barrier layer is formed on the side of the first quantum well layer and the first barrier layer away from the substrate, and a second window is formed at the patterned part of the first barrier layer and the second barrier layer, wherein the second window only exposes the first conductivity type semiconductor structure used to form the second light-emitting device; A second quantum well growth auxiliary layer and a second quantum well layer are sequentially fabricated on the first conductivity type semiconductor structure exposed by the second window. A third barrier layer is formed on the side of the second quantum well layer and the second barrier layer away from the substrate, and a third window is formed at the patterned part of the first barrier layer, the second barrier layer and the third barrier layer, wherein the third window only exposes the first conductivity type semiconductor structure used to form the third light-emitting device; A third quantum well growth aid layer and a third quantum well layer are sequentially fabricated on the first conductivity type semiconductor structure exposed by the third window.

[0010] In one possible implementation, the step of simultaneously fabricating a second conductivity type semiconductor structure on the side of all quantum well layers away from the substrate after completing the fabrication of the quantum well growth auxiliary layer and the quantum well layer on all first conductivity type semiconductor structures includes: Remove the first barrier layer, the second barrier layer, and the third barrier layer; The second conductivity type semiconductor structure is fabricated simultaneously on the side of the first quantum well layer, the second quantum well layer and the third quantum well layer away from the substrate; The first light-emitting device is formed by stacking a first conductivity type semiconductor structure, a first quantum well growth auxiliary layer, a first quantum well layer, and a second conductivity type semiconductor structure; the second light-emitting device is formed by stacking a first conductivity type semiconductor structure, a second quantum well growth auxiliary layer, a second quantum well layer, and a second conductivity type semiconductor structure; and the third light-emitting device is formed by stacking a first conductivity type semiconductor structure, a third quantum well growth auxiliary layer, a third quantum well layer, and a second conductivity type semiconductor structure.

[0011] In one possible implementation, in light-emitting devices with different emission colors, the step of sequentially fabricating a first quantum well growth auxiliary layer and a first quantum well layer on the first conductivity type semiconductor structure exposed by the first window includes: By adjusting the first growth parameters of epitaxial growth, a first quantum well growth auxiliary layer and a first quantum well layer are sequentially fabricated on the first conductivity type semiconductor structure exposed in the first window. The step of sequentially fabricating a second quantum well growth auxiliary layer and a second quantum well layer on the first conductivity type semiconductor structure exposed in the second window includes: By adjusting the second growth parameters of epitaxial growth, a second quantum well growth auxiliary layer and a second quantum well layer are sequentially fabricated on the first conductivity type semiconductor structure exposed in the second window. The step of sequentially fabricating a third quantum well growth auxiliary layer and a third quantum well layer on the first conductivity type semiconductor structure exposed in the third window includes: By adjusting the third growth parameters of epitaxial growth, a third quantum well growth auxiliary layer and a third quantum well layer are sequentially fabricated on the first conductivity type semiconductor structure exposed in the third window. The first growth parameter, the second growth parameter, and the third growth parameter are different.

[0012] In one possible implementation, the emitted light wavelengths of the first light-emitting device, the second light-emitting device, and the third light-emitting device decrease sequentially. The first growth parameters include a first growth temperature when fabricating the first quantum well growth auxiliary layer and a second growth temperature when fabricating the first quantum well layer; The second growth parameters include a third growth temperature for fabricating the second quantum well growth auxiliary layer and a fourth growth temperature for fabricating the second quantum well layer. The third growth parameter includes a fifth growth temperature for fabricating the third quantum well growth auxiliary layer and a sixth growth temperature for fabricating the third quantum well layer. The first growth temperature, the third growth temperature, and the fifth growth temperature increase sequentially, as do the second growth temperature, the fourth growth temperature, and the sixth growth temperature.

[0013] In one possible implementation, the first growth parameters further include a first proportion of introducing a group V / III precursor when fabricating the first quantum well growth auxiliary layer, and a second proportion of introducing a group V / III precursor when fabricating the first quantum well layer. The second growth parameters also include a third ratio for introducing V / III group precursors when fabricating the second quantum well growth auxiliary layer, and a fourth ratio for introducing V / III group precursors when fabricating the second quantum well layer; The third growth parameters also include a fifth ratio for introducing V / III group precursors when fabricating the third quantum well growth auxiliary layer, and a sixth ratio for introducing V / III group precursors when fabricating the third quantum well layer; The first ratio, the third ratio, and the fifth ratio decrease sequentially, as do the second ratio, the fourth ratio, and the sixth ratio.

[0014] In one possible implementation, the step of simultaneously fabricating a second conductivity type semiconductor structure on the side of all quantum well layers away from the substrate after completing the fabrication of the quantum well growth auxiliary layer and the quantum well layer on all first conductivity type semiconductor structures includes: After completing the fabrication of the quantum well growth auxiliary layer and the quantum well layer on all the first conductivity type semiconductor structures, an electron blocking layer and a second conductivity type semiconductor structure are simultaneously fabricated on the side of all quantum well layers away from the substrate, with the electron blocking layer located between the quantum well layer and the second conductivity type semiconductor structure; In light-emitting devices with different emission colors, the thickness of each electron blocking layer is the same, and the thickness of each second conductivity type semiconductor structure is also the same.

[0015] In one possible implementation, after completing the fabrication of the quantum well growth auxiliary layer and the quantum well layer on all first conductivity type semiconductor structures, and after simultaneously fabricating the second conductivity type semiconductor structure on the side of all quantum well layers away from the substrate, the method further includes: The protective layer is removed by wet etching.

[0016] A second aspect of this application also provides a display device, the display device comprising a semiconductor structure prepared by a preparation method provided in any possible implementation of the first aspect.

[0017] This application provides a method for fabricating a semiconductor structure and a display device. In the semiconductor structure fabrication method, the common functional layers (a first conductivity type semiconductor structure and a second conductivity type semiconductor structure) for light-emitting devices of different colors are simultaneously fabricated using the same process. The different functional layers (a quantum well growth auxiliary layer and a quantum well layer) for light-emitting devices of different colors are fabricated separately, thus enabling the fabrication of multi-color light-emitting devices on a substrate. Multi-color light coupling and output can be achieved without the need for optical components, simplifying the display system structure and reducing costs. Furthermore, the above method, by using selective area growth to fabricate light-emitting devices of different colors on the same substrate, allows for precise control of the emission wavelength of different color light-emitting devices by adjusting the indium content in the quantum well growth auxiliary layer, thereby improving the fabrication efficiency of multi-color light-emitting devices. Compared to etching fabrication, selective area growth reduces damage to the light-emitting devices and improves the fabrication yield. The above fabrication method can achieve large-scale manufacturing and obtain semiconductor structures capable of full-color display. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic flowchart illustrating the semiconductor structure fabrication method provided in this embodiment is illustrated. Figure 2a and Figure 2b Example Figure 1 Corresponding process flow chart; Figure 3 An example of implementation is provided. Figure 1 A flowchart illustrating step S11. Figure 4 Example Figure 3 Corresponding process flow chart; Figure 5 An example of implementation is provided. Figure 1 A flowchart illustrating step S12; Figure 6 Example Figure 5 Corresponding process flow chart; Figure 7 An example of implementation is provided. Figure 1 A flowchart illustrating step S13; Figure 8a and Figure 8b Example Figure 7 Corresponding process flow chart; Figure 9 An example of implementation is provided. Figure 1 A flowchart illustrating step S14; Figure 10 Example Figure 9 Corresponding process flow chart; Figure 11 The example illustrates a semiconductor structure prepared by the method provided in this embodiment.

[0020] Icons: 1-Semiconductor structure; 11-Substrate; 111-Substrate; 112-Buffer layer; 113-Mask layer; 1131-Mask opening; 12-First conductivity type semiconductor structure; 121-Seed structure; 122-First conductivity type semiconductor body; 13-Quantum well growth auxiliary layer; 131-First quantum well growth auxiliary layer; 132-Second quantum well growth auxiliary layer; 133-Third quantum well growth auxiliary layer; 14-Quantum well layer; 141-First quantum well Layer; 142-Second quantum well layer; 143-Third quantum well layer; 15-Second conductivity type semiconductor structure; 16-Protective layer; 171-First barrier layer; 172-Second barrier layer; 173-Third barrier layer; 1711-First window; 1712-Second window; 1713-Third window; 18-Electron barrier layer; 10-Light emission device; 10a-First light emission device; 10b-Second light emission device; 10c-Third light emission device; 20-First cone. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0023] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0024] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0026] To address the technical problems mentioned in the background section, the inventors have innovatively designed the following technical solutions, which will be described in detail below with reference to the accompanying drawings. It should be noted that the deficiencies in the solutions of related technologies are the result of the inventors' practical experience and careful research. Therefore, the discovery process of the aforementioned technical problems and the solutions proposed in the embodiments of this application below should be considered contributions made by the inventors during the invention process, and should not be construed as technical content known to those skilled in the art.

[0027] Please refer to Figure 1 , Figure 2a and Figure 2b , Figure 1 This embodiment illustrates a flowchart of a method for fabricating a semiconductor structure. Figure 2a and Figure 2b Example Figure 1 The corresponding process flow diagram is shown below. Figure 1 , Figure 2a and Figure 2b The method for fabricating the semiconductor structure provided in this embodiment will be described in detail. In this embodiment, the method for fabricating the semiconductor structure includes the following steps.

[0028] Step S11: Provide a substrate 11.

[0029] In this embodiment, the substrate 11 includes a substrate 111, a buffer layer 112, and a mask layer 113 stacked together. The mask layer 113 has a plurality of mask openings 1131 that expose the buffer layer 112.

[0030] The substrate 111 can be a silicon substrate or a sapphire substrate. The buffer layer 112 can be a single-layer structure or a multi-layer structure grown on the substrate 111. The buffer layer 112 is used to suppress dislocation propagation, release interface stress, and improve the lattice mismatch problem between the epitaxial material and the substrate 111.

[0031] The mask layer 113 is located on the side of the buffer layer 112 away from the substrate 111, and the mask layer 113 includes a plurality of mask openings 1131 that expose the buffer layer 112. The area where the mask openings 1131 are located serves as the growth area for subsequent film layers. This growth area can define the position of the fabricated light-emitting device 10. Specifically, the corresponding mask openings 1131 can be formed on the mask layer 113 according to the arrangement of the light-emitting device 10 to be fabricated.

[0032] Step S12: A first conductivity type semiconductor structure 12 is formed on the substrate 11 in the location region where each mask opening 1131 is located.

[0033] In this embodiment, the first conductivity type semiconductor structure 12 has a top surface on the side away from the substrate 11, which can be used to grow subsequent film layers.

[0034] The orthographic projection of the top surface of the first conductivity type semiconductor structure 12 on the substrate 11 away from the substrate 11, and the orthographic projection of the bottom surface of the first conductivity type semiconductor structure 12 on the substrate 11 facing the substrate 11.

[0035] The shape of the top surface of the first conductivity type semiconductor structure 12 on the side away from the substrate 11, projected onto the substrate 11, is the same as the shape of the top surface of the first conductivity type semiconductor structure 12 on the side away from the substrate 11, projected onto the substrate 11.

[0036] In this step, the first conductivity type semiconductor structures 12 used to form different color light-emitting devices 10 are completely identical and can be fabricated simultaneously using a unified process method, which simplifies the process and improves process efficiency.

[0037] Step S13: A quantum well growth auxiliary layer 13 and a quantum well layer 14 are sequentially fabricated on the side of the first conductivity type semiconductor structure 12 that forms different color light-emitting devices 10 away from the substrate 11.

[0038] In this embodiment, depending on the color of the fabricated light-emitting device 10, a quantum well growth auxiliary layer 13 and a quantum well layer 14 can be fabricated on the side of the corresponding first conductivity type semiconductor structure 12 away from the substrate 11.

[0039] In this embodiment, both the quantum well growth auxiliary layer 13 and the quantum well layer 14 contain indium. The quantum well growth auxiliary layer 13 can be used to control the indium content in the quantum well layer 14. The indium content in the quantum well layer 14 corresponding to different light-emitting devices 10 is different, and the indium content in the quantum well growth auxiliary layer 13 of different light-emitting devices 10 is also different.

[0040] In this step, the quantum well growth auxiliary layer 13 and quantum well layer 14 of different color light-emitting devices 10 are fabricated separately to ensure that the indium content in the quantum well growth auxiliary layer 13 and quantum well layer 14 of different color light-emitting devices 10 is different, so as to facilitate the precise control of the emission wavelength of different color light-emitting devices 10.

[0041] For example, the light-emitting device 10 includes a first light-emitting device 10a, a second light-emitting device 10b, and a third light-emitting device 10c. In this step, a first quantum well growth auxiliary layer 131 and a first quantum well layer 141 can be fabricated first on the side of the first conductivity type semiconductor structure 12 away from the substrate 11 corresponding to the first light-emitting device 10a; then, a second quantum well growth auxiliary layer 132 and a second quantum well layer 142 can be fabricated second on the side of the second light-emitting device 10b corresponding to the first conductivity type semiconductor structure 12 away from the substrate 11; and then, a third quantum well growth auxiliary layer 133 and a third quantum well layer 143 can be fabricated third on the side of the third light-emitting device 10c corresponding to the first conductivity type semiconductor structure 12 away from the substrate 11. It is understood that the above is only an example, and the order of fabricating the quantum well growth auxiliary layer 13 and the quantum well layer 14 can also be different from the above description. In this embodiment, the specific order is not limited.

[0042] Step S14: After completing the fabrication of quantum well growth auxiliary layers 13 and quantum well layers 14 on all first conductivity type semiconductor structures 12, second conductivity type semiconductor structures 15 are fabricated simultaneously on the side of all quantum well layers 14 away from the substrate 11.

[0043] In this embodiment, the second conductivity type semiconductor structure 15 used to form different color light-emitting devices 10 can be completely identical and can be fabricated simultaneously using a unified process method, which can simplify the process and improve process efficiency.

[0044] A first conductivity type semiconductor structure 12, a quantum well growth auxiliary layer 13, a quantum well layer 14, and a second conductivity type semiconductor structure 15 are stacked to form a light-emitting device 10. In this embodiment, light-emitting devices 10 of different colors can be arranged in any manner according to related technologies to form pixel units, thereby achieving full-color display.

[0045] For example, the light-emitting device 10 includes a red light-emitting device, a green light-emitting device and a blue light-emitting device. The light-emitting devices 10 of different colors can be arranged in Real, Pentile, diamond or tripod arrangement, etc.

[0046] The above method simultaneously fabricates the common functional layers (first conductivity type semiconductor structure 12 and second conductivity type semiconductor structure 15) of different color-emitting light-emitting devices 10 using a unified process, while separately fabricating the different functional layers (quantum well growth auxiliary layer and quantum well layer) of the different color-emitting light-emitting devices 10. This allows for the fabrication of multi-color light-emitting devices 10 on the substrate 11. Multi-color light coupling and output can be achieved without the need for optical components, simplifying the display system structure and reducing costs. Furthermore, by using selective area growth to fabricate light-emitting devices 10 of different colors on the same substrate 11, the indium content of the quantum well layer 14 can be controlled by adjusting the indium content in the quantum well growth auxiliary layer 13, allowing for precise control of the emission wavelength of different color light-emitting devices and improving the fabrication efficiency of multi-color light-emitting devices. Additionally, compared to etching, selective area growth reduces damage to the light-emitting devices and improves the fabrication yield. This fabrication method enables large-scale manufacturing and the production of semiconductor structures capable of full-color display.

[0047] In one possible implementation, please refer to Figure 3 and Figure 4 Step S11 can be achieved through the following steps.

[0048] Step S111: Provide a substrate 111.

[0049] In this embodiment, substrate 111 includes a silicon substrate or a sapphire substrate.

[0050] Step S112: A buffer layer 112 is fabricated on the substrate 111.

[0051] In this embodiment, a buffer layer 112 can be fabricated on the substrate 111 by chemical vapor deposition. The buffer layer 112 can be a single-layer structure or a multi-layer structure.

[0052] In step S113, a mask layer 113 is fabricated on the buffer layer 112, and the mask layer 113 is patterned to form multiple mask openings 1131 that expose the buffer layer 112.

[0053] In this embodiment, a mask layer 113 can be fabricated on the buffer layer 112 using chemical vapor deposition. The mask layer 113 is then patterned according to the arrangement of the light-emitting device 10 to be fabricated on the substrate 11, forming multiple mask openings 1131 that expose the buffer layer 112. That is, the arrangement of the mask openings 1131 is the same as the arrangement of the light-emitting device 10.

[0054] In one possible implementation, please refer to Figure 5 and Figure 6 Step S12 can be achieved through the following steps.

[0055] Step S121: Seed structures 121 are grown epitaxially at the positions of each mask opening 1131.

[0056] In this embodiment, the seed structure 121 fills the mask opening 1131 and forms a cone structure on the side of the mask layer 113 away from the substrate 11.

[0057] The materials of the seed structure 121 include, but are not limited to, GaN, InGaN, AlGaN, etc.

[0058] Step S122: Using a first type of conductive material, multiple spaced first cones 20 are epitaxially grown based on the seed structure 121.

[0059] Multiple first cones 20 are epitaxially grown on each seed structure 121, with one first cone 20 corresponding to each seed structure 121. The shape of the cone structure in the seed structure 121 determines the shape of the first cone 20. For example, when the cone structure is a square pyramid, the first cone 20 is also a square pyramid.

[0060] In this embodiment, the orthographic projection of the seed structure 121 on the substrate 11 is located within the orthographic projection of the first cone 20 on the substrate 11.

[0061] In this embodiment, the first conductivity type material may include N-type InGaN.

[0062] Step S123: The first cone 20 is de-topped to obtain a first conductivity type semiconductor structure 12 located on the substrate 11.

[0063] In this embodiment, step S123 can be implemented in the following way.

[0064] First, a protective layer 16 is formed at least around the first cone 20 by epitaxial growth and / or surface deposition.

[0065] The materials of the protective layer 16 include, but are not limited to, SiO2, Al2O3, TiN, Si3N4, etc.

[0066] In the direction perpendicular to the plane of the substrate 11, the thickness of the protective layer 16 is lower than the thickness of the first cone 20 and higher than the thickness of the seed structure 121.

[0067] Next, the first cone 20 is de-topped using the side of the protective layer 16 between adjacent first cones 20 that is away from the substrate 11 as the cut-off surface, to obtain a first conductivity type semiconductor structure 12 located on the substrate 11.

[0068] In this embodiment, the first cone 20 can be de-ejected by methods such as chemical etching, thermal annealing and chemical mechanical polishing.

[0069] After the above-mentioned top removal process, the side of the first conductivity type semiconductor structure 12 away from the substrate 11 and the side of the protective layer 16 away from the substrate 11 are flush, so as to facilitate the subsequent film layer fabrication.

[0070] In one possible implementation, the light-emitting device 10 includes a first light-emitting device 10a, a second light-emitting device 10b, and a third light-emitting device 10c, each emitting a different color. Please refer to... Figure 7 , Figure 8a and Figure 8b Step S13 can be achieved through the following steps.

[0071] In step S131, a first barrier layer 171 is formed on the side of the first conductivity type semiconductor structure 12 and the protective layer 16 away from the substrate 11, and a first window 1711 is formed by patterning the first barrier layer 171.

[0072] In step S132, a first quantum well growth auxiliary layer 131 and a first quantum well layer 141 are sequentially fabricated on the first conductivity type semiconductor structure 12 exposed by the first window 1711.

[0073] In this embodiment, a first quantum well growth auxiliary layer 131 and a first quantum well layer 141 are sequentially fabricated on the first conductivity type semiconductor structure 12 exposed by the first window 1711 by adjusting the first growth parameters of epitaxial growth.

[0074] In step S133, a second barrier layer 172 is formed on the side of the first quantum well layer 141 and the first barrier layer 171 away from the substrate 11, and a second window 1712 is formed by patterning the first barrier layer 171 and the second barrier layer 172.

[0075] In this embodiment, a second barrier layer 172 can be fabricated on the entire side of the first quantum well layer 141 and the first barrier layer 171 away from the substrate 11 by deposition or growth. The first barrier layer 171 and the second barrier layer 172 are patterned to form a second window 1712. The second window 1712 exposes only the first conductivity type semiconductor structure 12 forming the second light-emitting device 10b. The material of the second barrier layer 172 includes, but is not limited to, SiO2, Al2O3, TiN, Si3N4, etc.

[0076] In step S134, a second quantum well growth auxiliary layer 132 and a second quantum well layer 142 are sequentially fabricated on the first conductivity type semiconductor structure 12 exposed by the second window 1712.

[0077] In this embodiment, by adjusting the second growth parameters of epitaxial growth, a second quantum well growth auxiliary layer 132 and a second quantum well layer 142 are sequentially fabricated on the first conductivity type semiconductor structure 12 exposed by the second window 1712.

[0078] In step S135, a third barrier layer 173 is formed on the side of the second quantum well layer 142 and the second barrier layer 172 away from the substrate 11, and a third window 1713 is formed by patterning the first barrier layer 171, the second barrier layer 172 and the third barrier layer 173.

[0079] In this embodiment, a third barrier layer 173 can be fabricated on the side of the second quantum well layer 142 and the second barrier layer 172 away from the substrate 11 by deposition or growth. The first barrier layer 171, the second barrier layer 172, and the third barrier layer 173 are patterned to form a third window 1713. The third window 1713 exposes only the first conductivity type semiconductor structure 12 forming the third light-emitting device 10c. The material of the third barrier layer 173 includes, but is not limited to, SiO2, Al2O3, TiN, and Si3N4.

[0080] In step S136, a third quantum well growth auxiliary layer 133 and a third quantum well layer 143 are sequentially fabricated on the first conductivity type semiconductor structure 12 exposed in the third window 1713.

[0081] In this embodiment, a third quantum well growth auxiliary layer 133 and a third quantum well layer 143 are sequentially fabricated on the first conductivity type semiconductor structure 12 exposed by the third window 1713 by adjusting the third growth parameters of epitaxial growth.

[0082] In one possible implementation, please refer to Figure 9 and Figure 10 Step S14 can be achieved through the following steps.

[0083] Step S141: Remove the first barrier layer 171, the second barrier layer 172, and the third barrier layer 173.

[0084] In this embodiment, wet etching, which causes less damage to the device, can be used to sequentially remove the third barrier layer 173, the second barrier layer 172, and the first barrier layer 171, thereby completely exposing the first quantum well layer 141, the second quantum well layer 142, and the third quantum well layer 143.

[0085] In step S142, a second conductivity type semiconductor structure 15 is simultaneously fabricated on the side of the first quantum well layer 141, the second quantum well layer 142, and the third quantum well layer 143 away from the substrate 11.

[0086] A second conductivity type semiconductor structure 15 is fabricated by uniform epitaxial growth on the side of the first quantum well layer 141, the second quantum well layer 142, and the third quantum well layer 143 away from the substrate 11.

[0087] The material of the second conductivity type semiconductor structure 15 includes P-type GaN.

[0088] In this embodiment, a first light-emitting device 10a is formed by stacking a first conductivity type semiconductor structure 12, a first quantum well growth auxiliary layer 131, a first quantum well layer 141, and a second conductivity type semiconductor structure 15. A second light-emitting device 10b is formed by stacking a first conductivity type semiconductor structure 12, a second quantum well growth auxiliary layer 132, a second quantum well layer 142, and a second conductivity type semiconductor structure 15. A third light-emitting device 10c is formed by stacking a first conductivity type semiconductor structure 12, a third quantum well growth auxiliary layer 133, a third quantum well layer 143, and a second conductivity type semiconductor structure 15.

[0089] In one possible implementation, the first growth parameters include a first temperature when fabricating the first quantum well growth auxiliary layer 131 and a second temperature when fabricating the first quantum well layer 141.

[0090] The second growth parameters include a third temperature for fabricating the second quantum well growth auxiliary layer 132 and a fourth temperature for fabricating the second quantum well layer 142.

[0091] The third growth parameters include the fifth temperature for fabricating the third quantum well growth auxiliary layer 133 and the sixth temperature for fabricating the third quantum well layer 143.

[0092] In this embodiment, the first temperature, the third temperature, and the fifth temperature increase sequentially, as do the second temperature, the fourth temperature, and the sixth temperature. For example, the first light-emitting device 10a is a red light-emitting device, the second light-emitting device 10b is a green light-emitting device, and the third light-emitting device 10c is a blue light-emitting device.

[0093] In one possible implementation, the first growth parameters further include a first ratio of introducing the group V / III precursor when fabricating the first quantum well growth auxiliary layer 131, and a second ratio of introducing the group V / III precursor when fabricating the first quantum well layer 141.

[0094] The second growth parameters also include a third ratio for introducing the V / III group precursor when fabricating the second quantum well growth auxiliary layer 132, and a fourth ratio for introducing the V / III group precursor when fabricating the second light-emitting device 10b quantum well layer 142.

[0095] The third growth parameters also include a fifth ratio for introducing V / III group precursors when fabricating the third quantum well growth auxiliary layer 133, and a sixth ratio for introducing V / III group precursors when fabricating the third quantum well layer 143.

[0096] In this embodiment, the first ratio, the third ratio, and the fifth ratio decrease sequentially, as do the second ratio, the fourth ratio, and the sixth ratio.

[0097] By controlling the growth of quantum well growth auxiliary layer 13 and quantum well layer 14 of different color light-emitting devices 10 with different growth parameters, the thickness of quantum well growth auxiliary layer 13 of different color light-emitting devices can be the same, and the thickness of quantum well layer 14 of different color light-emitting devices can also be the same.

[0098] Specifically, in different color light-emitting devices 10, the thickness of the quantum well growth auxiliary layer 13 is greater than or equal to 5 nanometers and less than or equal to 80 nanometers, and the thickness of the quantum well layer 14 is greater than or equal to 2 nanometers and less than or equal to 10 nanometers.

[0099] Furthermore, by controlling the growth of quantum well growth auxiliary layer 13 and quantum well layer 14 of different color light-emitting devices with different growth parameters, the indium concentration of quantum well growth auxiliary layer 13 of different color light-emitting devices can be different, and the indium concentration of quantum well layer 14 of different color light-emitting devices can also be different.

[0100] In detail, the first quantum well growth auxiliary layer 131 has a first indium content, the second quantum well growth auxiliary layer 132 has a second indium content, and the third quantum well growth auxiliary layer 133 has a third indium content, with the first, second, and third indium contents decreasing sequentially. The first indium content is greater than or equal to 15% and less than or equal to 20%, the second indium content is greater than or equal to 10% and less than 15%, and the third indium content is greater than or equal to 1% and less than 10%.

[0101] In this embodiment, the first quantum well layer 141 has a fourth indium content, the second quantum well layer 142 has a fifth indium content, and the third quantum well layer 143 has a sixth indium content. The fourth, fifth, and sixth indium contents decrease sequentially.

[0102] The fourth type has an indium content greater than or equal to 30% and less than or equal to 40%, the fifth type has an indium content greater than or equal to 18% and less than or equal to 25%, and the sixth type has an indium content greater than or equal to 8% and less than or equal to 15%.

[0103] In one possible implementation, please refer to Figure 10In step S14, after the fabrication of the quantum well growth auxiliary layer 13 and the quantum well layer 14 on all the first conductivity type semiconductor structures 12 is completed, an electron blocking layer 18 and a second conductivity type semiconductor structure 15 are simultaneously fabricated on the side of all quantum well layers 14 away from the substrate 11, with the electron blocking layer 18 located between the quantum well layer 14 and the second conductivity type semiconductor structure 15.

[0104] Since the electron blocking layer 18 and the second conductivity type semiconductor structure 15 in the light-emitting devices 10 with different emission colors are fabricated in the same process, in this embodiment, the thickness of each electron blocking layer 18 and the thickness of each second conductivity type semiconductor structure 15 are the same in the light-emitting devices 10 with different emission colors.

[0105] In this embodiment, the electron blocking layer 18 can block electrons from entering the second conductivity type semiconductor structure 15, thereby preventing the lifespan of the light-emitting device 10 from being shortened due to electrons entering the second conductivity type semiconductor structure 15.

[0106] In one possible implementation, after step S14, the fabrication method provided in this embodiment further includes: removing the protective layer 16 using a wet etching method that causes less damage to the device structure, to obtain the desired result. Figure 11 Semiconductor structure 1 is shown.

[0107] Based on the same inventive concept, embodiments of this application also provide a display device, which includes a display panel prepared by the preparation method in the preceding embodiments, or a display panel described in the preceding embodiments. The display device includes an AR display device and / or a VR display device.

[0108] In summary, this application provides a method for fabricating a semiconductor structure and a display device. In the semiconductor structure fabrication method, the common functional layers (a first conductivity type semiconductor structure and a second conductivity type semiconductor structure) for light-emitting devices of different colors are simultaneously fabricated using the same process. Different functional layers (a quantum well growth auxiliary layer and a quantum well layer) for light-emitting devices of different colors are fabricated separately, thus enabling the fabrication of multi-color light-emitting devices on a substrate. Multi-color light coupling and output can be achieved without the need for optical components, simplifying the display system structure and reducing costs. Furthermore, by using selective area growth to fabricate light-emitting devices of different colors on the same substrate, the indium content of the quantum well layer can be controlled by adjusting the indium content in the quantum well growth auxiliary layer, allowing precise control of the emission wavelength of different color light-emitting devices and improving the fabrication efficiency of multi-color light-emitting devices. Compared to etching, selective area growth reduces damage to the light-emitting devices and improves the fabrication yield. This fabrication method enables large-scale manufacturing and the production of semiconductor structures capable of full-color display.

[0109] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A substrate is provided, wherein the substrate includes a substrate, a buffer layer and a mask layer stacked together, and the mask layer has a plurality of mask openings that expose the buffer layer; A first conductivity type semiconductor structure is formed on the substrate in the location region of each of the mask openings; A quantum well growth auxiliary layer and a quantum well layer are sequentially fabricated on the side of the first conductivity type semiconductor structure that forms different color light-emitting devices, away from the substrate; After completing the fabrication of the quantum well growth auxiliary layer and the quantum well layer on all the first conductivity type semiconductor structures, the second conductivity type semiconductor structure is simultaneously fabricated on the side of all quantum well layers away from the substrate. The first conductivity type semiconductor structure, the quantum well growth auxiliary layer, the quantum well layer and the second conductivity type semiconductor structure stacked together form a light-emitting device. In the light-emitting devices with different emission colors, the indium content of each quantum well growth auxiliary layer is different, and the indium content of each quantum well layer is different.

2. The method for preparing the semiconductor structure according to claim 1, characterized in that, The step of providing a substrate includes: Provide a substrate; A buffer layer is fabricated on the substrate; A mask layer is fabricated on the buffer layer, and the mask layer is patterned to form multiple mask openings that expose the buffer layer.

3. The method for preparing the semiconductor structure as described in claim 2, characterized in that, The step of forming a first conductivity type semiconductor structure on the substrate at the location regions of each of the mask openings includes: Seed structures are epitaxially grown at each of the mask opening locations, wherein the seed structures fill the mask openings and form a cone structure on the side of the mask layer away from the substrate; A plurality of mutually spaced first cones are epitaxially grown using a first type of conductive material based on the seed structure, wherein the orthographic projection of the seed structure on the substrate is located within the orthographic projection of the first cones on the substrate; The first cone is subjected to a top-removal process to obtain a first conductivity type semiconductor structure located on the substrate.

4. The method for preparing the semiconductor structure as described in claim 3, characterized in that, The step of removing the top of the first cone to obtain a first conductivity type semiconductor structure located on the substrate includes: A protective layer is fabricated at least around the first cone using epitaxial growth and / or surface deposition, wherein, in a direction perpendicular to the plane of the substrate, the thickness of the protective layer is less than the thickness of the first cone and greater than the thickness of the seed structure; Using the side of the protective layer between adjacent first cones away from the substrate as the cutoff surface, the first cones are de-topped to obtain a first conductivity type semiconductor structure located on the substrate.

5. The method for preparing the semiconductor structure as described in claim 4, characterized in that, The light-emitting device includes a first light-emitting device, a second light-emitting device, and a third light-emitting device with different emission colors. The step of sequentially fabricating a quantum well growth auxiliary layer and a quantum well layer on the side of the first conductivity type semiconductor structure forming the light-emitting devices of different colors away from the substrate includes: A first barrier layer is formed on the side of the first conductivity type semiconductor structure and the protective layer away from the substrate, and a first window is formed at the patterned part of the first barrier layer, wherein the first window only exposes the first conductivity type semiconductor structure used to form the first light-emitting device. A first quantum well growth auxiliary layer and a first quantum well layer are sequentially fabricated on the first conductivity type semiconductor structure exposed by the first window; A second barrier layer is formed on the side of the first quantum well layer and the first barrier layer away from the substrate, and a second window is formed at the patterned part of the first barrier layer and the second barrier layer, wherein the second window only exposes the first conductivity type semiconductor structure used to form the second light-emitting device; A second quantum well growth auxiliary layer and a second quantum well layer are sequentially fabricated on the first conductivity type semiconductor structure exposed by the second window. A third barrier layer is formed on the side of the second quantum well layer and the second barrier layer away from the substrate, and a third window is formed at the patterned part of the first barrier layer, the second barrier layer and the third barrier layer, wherein the third window only exposes the first conductivity type semiconductor structure used to form the third light-emitting device; A third quantum well growth aid layer and a third quantum well layer are sequentially fabricated on the first conductivity type semiconductor structure exposed by the third window.

6. The method for preparing a semiconductor structure as described in claim 5, characterized in that, The step of simultaneously fabricating a second conductivity type semiconductor structure on the side of all quantum well layers away from the substrate after completing the fabrication of the quantum well growth auxiliary layer and the quantum well layer on all first conductivity type semiconductor structures includes: Remove the first barrier layer, the second barrier layer, and the third barrier layer; The second conductivity type semiconductor structure is fabricated simultaneously on the side of the first quantum well layer, the second quantum well layer and the third quantum well layer away from the substrate; The first light-emitting device is formed by stacking a first conductivity type semiconductor structure, a first quantum well growth auxiliary layer, a first quantum well layer, and a second conductivity type semiconductor structure; the second light-emitting device is formed by stacking a first conductivity type semiconductor structure, a second quantum well growth auxiliary layer, a second quantum well layer, and a second conductivity type semiconductor structure; and the third light-emitting device is formed by stacking a first conductivity type semiconductor structure, a third quantum well growth auxiliary layer, a third quantum well layer, and a second conductivity type semiconductor structure.

7. The method for preparing a semiconductor structure as described in claim 5, characterized in that, The step of sequentially fabricating a first quantum well growth auxiliary layer and a first quantum well layer on the first conductivity type semiconductor structure exposed in the first window includes: By adjusting the first growth parameters of epitaxial growth, a first quantum well growth auxiliary layer and a first quantum well layer are sequentially fabricated on the first conductivity type semiconductor structure exposed in the first window. The step of sequentially fabricating a second quantum well growth auxiliary layer and a second quantum well layer on the first conductivity type semiconductor structure exposed in the second window includes: By adjusting the second growth parameters of epitaxial growth, a second quantum well growth auxiliary layer and a second quantum well layer are sequentially fabricated on the first conductivity type semiconductor structure exposed in the second window. The step of sequentially fabricating a third quantum well growth auxiliary layer and a third quantum well layer on the first conductivity type semiconductor structure exposed in the third window includes: By adjusting the third growth parameters of epitaxial growth, a third quantum well growth auxiliary layer and a third quantum well layer are sequentially fabricated on the first conductivity type semiconductor structure exposed in the third window. The first growth parameter, the second growth parameter, and the third growth parameter are different.

8. The method for preparing a semiconductor structure as described in claim 7, characterized in that, The emitted light wavelengths of the first light-emitting device, the second light-emitting device, and the third light-emitting device decrease sequentially. The first growth parameters include a first growth temperature when fabricating the first quantum well growth auxiliary layer and a second growth temperature when fabricating the first quantum well layer; The second growth parameters include a third growth temperature for fabricating the second quantum well growth auxiliary layer and a fourth growth temperature for fabricating the second quantum well layer. The third growth parameter includes a fifth growth temperature for fabricating the third quantum well growth auxiliary layer and a sixth growth temperature for fabricating the third quantum well layer. The first growth temperature, the third growth temperature, and the fifth growth temperature increase sequentially, as do the second growth temperature, the fourth growth temperature, and the sixth growth temperature.

9. The method for preparing a semiconductor structure as described in claim 8, characterized in that, The first growth parameters also include a first ratio of introducing V / III group precursors when fabricating the first quantum well growth auxiliary layer, and a second ratio of introducing V / III group precursors when fabricating the first quantum well layer; The second growth parameters also include a third ratio for introducing V / III group precursors when fabricating the second quantum well growth auxiliary layer, and a fourth ratio for introducing V / III group precursors when fabricating the second quantum well layer; The third growth parameters also include a fifth ratio for introducing V / III group precursors when fabricating the third quantum well growth auxiliary layer, and a sixth ratio for introducing V / III group precursors when fabricating the third quantum well layer; The first ratio, the third ratio, and the fifth ratio decrease sequentially, as do the second ratio, the fourth ratio, and the sixth ratio.

10. The method for preparing a semiconductor structure according to any one of claims 4-9, characterized in that, The step of simultaneously fabricating a second conductivity type semiconductor structure on the side of all quantum well layers away from the substrate after completing the fabrication of the quantum well growth auxiliary layer and the quantum well layer on all first conductivity type semiconductor structures includes: After completing the fabrication of the quantum well growth auxiliary layer and the quantum well layer on all the first conductivity type semiconductor structures, an electron blocking layer and a second conductivity type semiconductor structure are simultaneously fabricated on the side of all quantum well layers away from the substrate, with the electron blocking layer located between the quantum well layer and the second conductivity type semiconductor structure; In light-emitting devices with different emission colors, the thickness of each electron blocking layer is the same, and the thickness of each second conductivity type semiconductor structure is also the same.

11. The method for preparing a semiconductor structure as described in claim 10, characterized in that, After completing the fabrication of the quantum well growth auxiliary layer and the quantum well layer on all first conductivity type semiconductor structures, and following the step of simultaneously fabricating the second conductivity type semiconductor structure on the side of all quantum well layers away from the substrate, the method further includes: The protective layer is removed by wet etching.

12. A display device, characterized in that, The display device includes a semiconductor structure prepared by the method for preparing the semiconductor structure according to any one of claims 1-11.

Images