Leakage-proof metal substrate perovskite solar cell and preparation method thereof

Abstract

The present application relates to a kind of metal base perovskite solar cell of leakage protection and preparation method thereof, belong to solar cell technical field, solve the leakage current loss of serious in prior art metal base perovskite solar cell, short circuit is prone to occur and lead to the problems of low device efficiency, poor stability and poor process feasibility.From bottom to top, the solar cell includes metal base layer, edge insulation layer, hole transport layer, perovskite absorption layer, electron transport layer and top electrode layer in sequence, wherein, the edge insulation layer is located on the edge area of the upper surface of the metal base layer.The edge insulation layer not only can successfully isolate metal base layer and top electrode layer, effectively prevent perovskite solar cell from appearing edge leakage and short circuit phenomenon, but also can provide alignment tolerance and buffer space for subsequent processing top electrode layer, so as to improve the process window and yield of device preparation, promote the industrialization preparation and application of metal base perovskite solar cell.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and in particular to a leakage-proof metal-based perovskite solar cell and its fabrication method. Background Technology

[0002] Perovskite solar cells (PSCs) have attracted widespread attention in recent years due to their excellent light absorption characteristics, carrier transport capabilities, and advantages in low-temperature solution fabrication. The efficiency of their single-junction devices has rapidly increased to over 26%, demonstrating enormous potential for industrial application. In the structure of perovskite solar cell devices, metal foil substrates (such as stainless steel foil) have become an important development direction for flexible perovskite cells due to their high mechanical strength, good heat resistance, and roll-to-roll fabrication capabilities.

[0003] However, due to the high conductivity and large surface roughness of metal substrates, edge leakage and short circuit problems are prone to occur during device fabrication. For example, in the fabrication of perovskite solar cells on metal substrates, the deposition of functional layers at the edges of the effective power generation area of ​​the device is often difficult to completely cover or isolate the metal substrate layer, resulting in a direct conductive path between the top electrode and the bottom metal substrate. This causes severe leakage current loss, reduces the device's open-circuit voltage (Voc) and fill factor (FF), and ultimately limits the improvement of device efficiency. In the modular fabrication of perovskite solar cells, metal substrate devices need to further achieve unit patterning isolation and series integration. However, existing processes lack a simple and effective method for substrate insulation sealing and patterning, making it difficult to balance process feasibility and device performance improvement.

[0004] Therefore, there is an urgent need to develop a leakage-proof metal-based perovskite solar cell and its fabrication method, which is of great significance for suppressing edge leakage of the device and improving efficiency and stability. Summary of the Invention

[0005] Based on the above analysis, the present invention aims to provide a leakage-proof metal-based perovskite solar cell and its fabrication method, in order to solve at least one of the problems of serious leakage current loss, easy short circuit resulting in low device efficiency, poor stability and poor process feasibility in the prior art of metal-based perovskite solar cells.

[0006] On one hand, embodiments of the present invention provide a metal-based perovskite solar cell with leakage protection. From bottom to top, the solar cell sequentially includes a metal substrate layer, an edge insulating layer, a hole transport layer, a perovskite absorber layer, an electron transport layer, and a top electrode layer, wherein the edge insulating layer is located in the edge region of the upper surface of the metal substrate layer.

[0007] Furthermore, the edge insulating layer is continuously distributed circumferentially along the metal substrate layer.

[0008] Furthermore, the material of the edge insulating layer is at least one selected from MgF2, SbO3, Al2O3, polyimide, epoxy resin, and fluorinated polymer.

[0009] Furthermore, the width of the edge insulating layer is 0.5~5mm.

[0010] Furthermore, the thickness of the edge insulating layer is 0.1~10μm.

[0011] Furthermore, a metal grid layer is provided on the top electrode layer.

[0012] Furthermore, on the vertical projection plane from bottom to top, the inner edge of the edge insulating layer coincides with the outer edge of the metal grid layer.

[0013] Furthermore, the metal gate layer includes spaced fine gate lines and main gate lines electrically connected to the fine gate lines.

[0014] Furthermore, the fine grid lines have a parallel, comb-like, grid-like, or strip-like arrangement structure parallel to the long side of the device.

[0015] On the other hand, embodiments of the present invention also provide a method for fabricating a perovskite solar cell, wherein the perovskite solar cell is the leakage-proof metal-substrate perovskite solar cell, and the fabrication method includes the following steps: (1) Clean the metal substrate to remove surface oil and impurities; (2) An edge insulating layer is prepared on the upper surface edge of the metal substrate after the pretreatment in step (1); (3) On the metal substrate on which the edge insulating layer is prepared at the upper surface edge in step (2), a hole transport layer, a perovskite absorption layer, an electron transport layer and a top electrode layer are deposited sequentially.

[0016] Furthermore, the preparation method also includes step (4), specifically preparing a metal gate layer on the top electrode layer.

[0017] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects: 1. Compared with existing laser scribing or edge removal methods, this invention, by setting an edge insulating layer in the edge region of the upper surface of the metal substrate, completely covers the edge of the metal substrate layer. This not only successfully isolates the metal substrate layer from the top electrode layer, effectively preventing edge leakage and short circuits in perovskite solar cells, reducing leakage current loss, and improving device efficiency, with the photoelectric conversion efficiency (PCE) of the cell increasing to ≥17%, but also provides alignment tolerance and buffer space for subsequent processing of the top electrode layer and grid / bus structure. Even if there is a certain alignment deviation or lateral creep of the film layer, it is not easy to trigger unintended contact with the metal substrate, thereby improving the process window and yield of device fabrication (greater than or equal to 80%).

[0018] 2. By selecting the constituent materials of the edge insulating layer and controlling its dimensions (including width, thickness, and density), this invention can improve the impedance value of the insulating layer and its adhesion strength to the metal substrate, resist the erosion of perovskite precursor solvents (such as DMF and DMSO), and effectively improve the photoelectric conversion efficiency and stability of the device while preventing edge leakage and short circuits. In addition, this invention can determine the continuity (continuous or discontinuous) of the edge insulating layer according to the actual application requirements, simplifying the manufacturing process and improving production efficiency and economy while meeting the performance requirements of the device.

[0019] 3. The present invention provides a metal gate layer on the upper surface of the top electrode layer, which can significantly reduce the overall sheet resistance and series resistance while maintaining high light transmittance, and improve the open circuit voltage (Voc), fill factor (FF) and photoelectric conversion efficiency (PCE) of the device; at the same time, the outer edge of the metal gate layer is aligned with the inner edge of the edge insulating layer, which can prevent short circuits at the edge of the device.

[0020] 4. By defining the structure and size of the metal gate lines, including the arrangement, width and thickness of the fine gate lines, the present invention enables the design of the metal gate lines to find the optimal balance between electrical gain (FF enhancement) and optical loss (photocurrent Jsc reduction) in order to maximize the photoelectric conversion efficiency (PCE) of the device.

[0021] 5. This invention uses existing fabrication processes to prepare edge insulating layers and other functional layers on the surface of a metal substrate. No additional equipment is required, the fabrication process is simple, and it is compatible with roll-to-roll fabrication. It is suitable for the industrial fabrication and application of large-area metal substrate perovskite components.

[0022] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0023] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0024] Figure 1 is a schematic diagram of the perovskite solar cell structure of the present invention; Figure 2 This is a schematic diagram of the metal substrate without insulation treatment in Comparative Example 1 of the present invention; Figure 3 This is a schematic diagram of the metal substrate mask used for insulation treatment in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the metal substrate mask used for insulation treatment in Embodiment 2 of the present invention; Figure 5 This is a schematic diagram of the metal substrate mask used for insulation treatment in Embodiment 3 of the present invention; Figure 6 This is a schematic diagram of the comb-shaped metal grid layer on top of the solar cell in Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the parallel metal grid layer on top of the solar cell in Embodiment 8 of the present invention; Figure 8 The IV curve of the perovskite solar cell prepared in Example 1 of this invention; Figure 9 The IV curve of the perovskite solar cell prepared in Example 2 of this invention; Figure 10 The IV curve of the perovskite solar cell prepared in Example 3 of this invention; Figure 11 The IV curve of the perovskite solar cell prepared in Example 4 of this invention; Figure 12 The IV curve of the perovskite solar cell prepared in Example 5 of this invention; Figure 13 The IV curve of the perovskite solar cell prepared in Example 6 of this invention; Figure 14 The IV curve of the perovskite solar cell prepared in Example 7 of this invention; Figure 15The IV curve of the perovskite solar cell prepared in Example 8 of this invention; Figure 16 The IV curve of the perovskite solar cell prepared in Example 9 of this invention; Figure 17 The IV curve of the perovskite solar cell prepared in Example 10 of this invention; Figure 18 The IV curve of the perovskite solar cell prepared in Example 11 of this invention; Figure 19 The IV curve of the perovskite solar cell prepared in Comparative Example 1 of this invention; Figure 20 The IV curve of the perovskite solar cell prepared in Comparative Example 2 of this invention; Figure 21 The IV curve of the perovskite solar cell prepared in Comparative Example 3 of this invention; Figure 22 The IV curve of the perovskite solar cell prepared in Comparative Example 4 of this invention; Figure 23 The IV curve of the perovskite solar cell prepared in Comparative Example 5 of this invention; Figure 24 The IV curve of the perovskite solar cell prepared in Comparative Example 6 of this invention; Figure 25 The IV curve of the perovskite solar cell prepared in Comparative Example 7 of this invention; Figure label: 1-Metallic substrate layer; 2-Edge insulating layer; 3-Hole transport layer; 4-Perovskite absorber layer; 5-Electron transport layer; 6-Top electrode layer; 7-Metallic gate layer. Detailed Implementation

[0025] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which constitute a part of the present invention and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0026] In the fabrication of perovskite solar cells on metal substrates, solution methods such as spin coating, blade coating, or trench coating are often used to prepare functional layers, such as perovskite layers and charge transport layers (ETL / HTL). During the drying process, due to the uneven solvent evaporation rate and surface tension, the liquid is prone to physical shrinkage at the edges of the substrate or pattern, resulting in thinning of the film layer at the edges or even exposure of the substrate. In addition, the surface roughness of metal substrates such as stainless steel is usually higher than that of glass / TCO substrates. Local micro-protrusions will further amplify the problem of discontinuity in the edge film layer, which can easily form a direct conductive path between the top electrode and the metal substrate after the top electrode is deposited, causing edge leakage and short circuit risks.

[0027] In traditional glass / transparent conductive oxide (TCO) substrate perovskite or thin-film solar cell systems, existing technologies typically employ the following methods to overcome edge leakage problems: physical edge cutting or mechanical edge removal: removing unevenly deposited areas at the edges through mechanical scribing or edge removal processes; laser etching isolation: performing laser scribing after the deposition of the bottom electrode or functional layer to electrically isolate different unit areas; mask control of deposition range: limiting the coverage area of ​​the functional layer during the deposition process using a mask.

[0028] However, the aforementioned methods are primarily based on systems designed for glass / TCO substrates where the bottom layer is inherently discontinuously conductive. In metal substrate systems (such as stainless steel foil), the substrate itself is continuously conductive, and even with patterned isolation of the upper functional layers, the bottom layer remains electrically continuous. Therefore, simply relying on laser scribing or edge removal cannot fundamentally eliminate potential short-circuit paths. Furthermore, laser processing of metal substrates may generate areas of molten metal that re-solidify or burrs, further increasing the risk of leakage. Therefore, existing solutions for edge leakage problems in glass / TCO substrate systems are not effectively applicable to perovskite solar cell structures on metal substrates.

[0029] It is evident that the structure and fabrication process of traditional solar cells can easily lead to the formation of a direct conductive path between the top electrode and the bottom metal substrate of metal-based perovskite solar cells, resulting in severe leakage current loss, reduced open-circuit voltage (Voc) and fill factor (FF), and ultimately limiting the improvement of device efficiency. In addition, it also makes it impossible to achieve patterned isolation and series integration of units during the modular fabrication of solar cells, making it difficult to balance process feasibility and device performance improvement.

[0030] Therefore, embodiments of the present invention provide a leakage-proof perovskite solar cell on a metal substrate, as shown in the schematic diagram below. Figure 1 As shown, from bottom to top, the solar cell sequentially includes a metal substrate layer, an edge insulating layer, a hole transport layer, a perovskite absorber layer, an electron transport layer, and a top electrode layer. The edge insulating layer is located in the edge region of the upper surface of the metal substrate layer, as shown below. Figure 2 ,3 As shown in Figure 4.

[0031] Compared with existing technologies that use laser scribing or edge removal to prevent edge leakage in solar cells, this invention, by setting an edge insulating layer in the edge region of the upper surface of the metal substrate, completely covers the edge of the metal substrate layer. This not only successfully isolates the metal substrate layer from the top electrode layer, effectively preventing edge leakage and short circuits in perovskite solar cells, reducing leakage current loss, and improving device efficiency, but also provides alignment tolerance and buffer space for subsequent processing of the top electrode layer and grid / bus structure. Even if there is a certain alignment deviation or lateral creep of the film layer, it is not easy to trigger unintended contact with the metal substrate, thereby improving the process window and yield of device fabrication.

[0032] It should be noted that the metal used as the substrate for perovskite solar cells in this invention should have good electrical conductivity, heat resistance, mechanical strength and surface smoothness, and be able to withstand subsequent coating, evaporation, annealing and vacuum treatment processes, wherein the thickness of the metal substrate is 1-30 μm.

[0033] According to some preferred embodiments of the present invention, the metal used as the substrate of the perovskite solar cell can be stainless steel, titanium, molybdenum, copper or aluminum, preferably 304 stainless steel.

[0034] It should be noted that, in order to improve the bonding ability between the metal substrate and the functional film layer and thus improve the stability of the device, the present invention needs to limit the surface roughness of the metal substrate.

[0035] Specifically, the arithmetic mean roughness Ra of the surface of the metal substrate material is preferably no greater than 500 nm, more preferably 10~200 nm, such as 10 nm, 30 nm, 60 nm, 80 nm, 100 nm, 120 nm, 150 nm, 170 nm, 200 nm. If the roughness is too low, the film adhesion is poor, and the mechanical interlocking with the upper film layer is insufficient, resulting in a decrease in device stability. If the roughness is too high, the film coverage is insufficient, the number of film defects and pinholes increases, and the device performance decreases.

[0036] It should be noted that, in order to better prevent edge leakage and short circuit problems in perovskite solar cells and meet the higher performance requirements of solar cells in special application scenarios, this invention needs to define the specific distribution of the edge insulating layer in the edge region of the upper surface of the metal substrate.

[0037] Specifically, in cases where the edge insulating layer is provided intermittently or discontinuously along the circumferential direction of the metal substrate (e.g.) Figure 2 , 3 In comparison, the edge insulating layer is continuously distributed circumferentially along the metal substrate layer, such as... Figure 4 As shown, a closed insulating barrier can be formed around the effective power generation area of ​​the device, which can not only more thoroughly block the unexpected conduction path between the edge of the top electrode layer, metal gate layer and functional layer and the metal substrate layer, but also reduce the leakage risk caused by edge delamination, local burrs, pinholes and alignment deviations. At the same time, continuous edge sealing helps to improve the consistency of device boundary definition and improve the yield and long-term stability in the fabrication of large-area devices and components.

[0038] When the current of the device is mainly collected along the long side, the epitaxial risk of the top electrode and gate line is mainly concentrated on the opposite two edges, and the control of the non-active area is critical, edge insulation layers can be set only on the opposite two edges. However, the risk control capability of sealing the two edges is usually weaker than that of sealing the four sides continuously. Therefore, it is more suitable for scenarios where the short-circuit risk is relatively controllable, the requirements for component-level reliability are slightly lower, or the specific electrode arrangement has made the risk on the other two edges relatively small.

[0039] This invention can determine the continuity (continuous or discontinuous) of the edge insulation layer according to the actual application requirements, so that the device can meet the performance requirements, simplify the manufacturing process, and improve production efficiency and economy.

[0040] It should be noted that, in order to completely isolate the edge region of the metal substrate from the top electrode layer, prevent the two from forming a direct conductive path, reduce leakage current loss, and at the same time ensure sufficient effective power generation area and normal transport of charge carriers in the device, so as to truly and effectively improve the efficiency and stability of the device, the present invention needs to limit the constituent material, width, thickness and density of the edge insulating layer.

[0041] Specifically, the edge insulating layer is composed of at least one of MgF2, Sb2O3, Al2O3, polyimide, epoxy resin, and fluorinated polymer, preferably MgF2, Sb2O3, or Al2O3.

[0042] Specifically, the width of the edge insulation layer is 0.5~5.0mm, and can be 0.5mm, 0.8mm, 1.0mm, 1.2mm, 1.5mm, 1.7mm, 2.0mm, 2.2mm, 2.5mm, 2.7mm, 3.0mm, 3.3mm, 3.5mm, 3.8mm, 4.0mm, 4.2mm, 4.5mm, 4.7mm, or 5.0mm. If the edge insulation layer is too narrow, it is prone to isolation failure due to alignment misalignment or lateral creep of the functional layer, causing edge leakage; while an excessively wide edge insulation layer will increase the inactive area of ​​the module, reduce the effective power generation area ratio, and lead to a decrease in the overall power of the module.

[0043] Specifically, the thickness of the edge insulating layer is 0.1~10μm, and can be 0.1μm, 0.3μm, 0.6μm, 0.9μm, 1.2μm, 1.5μm, 1.7μm, 2.0μm, 2.2μm, 2.5μm, 2.8μm, 3.1μm, 3.4μm, 3.7μm, 4.0μm, 4.3μm, 4.6μm, 4.9μm, 5.2μm, 5.5μm, 5.8μm, 6.1μm, 6.5μm, 6. 8μm, 7.0μm, 7.3μm, 7.5μm, 7.8μm, 8.2μm, 8.5μm, 8.8μm, 9.1μm, 9.4μm, 9.7μm, 10μm; if the edge insulating layer is too thin, it cannot completely cover the metal protrusions on the substrate surface, which can easily lead to the insulation layer being broken down or to the generation of leakage pinholes; while if it is too thick, it will form an excessively high step at the edge of the power generation area, causing the subsequently deposited functional layer film to break at the step, affecting carrier transport or causing stress shedding.

[0044] This invention improves the impedance value of the insulating layer and the adhesion strength between it and the metal substrate by selecting the material of the edge insulating layer and controlling its size (including width and thickness). It also resists the corrosion of perovskite precursor solvents (such as DMF and DMSO). While preventing edge leakage and short circuits in the device, it can effectively improve the photoelectric conversion efficiency and stability of the device.

[0045] It should be noted that the hole transport layer can be made of any material commonly used in the field of perovskite solar cell technology for preparing hole transport layers, including but not limited to Spiro-OMeTAD (2,2′,7,7′-tetrakis[N,N-di(4-methoxyphenyl)amino]-9,9′-spirodifluorene), NiO X PTAA (poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine]), P3HT (polymer of 3-hexylthiophene) PEDOT:PSS, with a thickness of 3~50 nm.

[0046] It should be noted that the perovskite layer is a material with an ABX3 structure, wherein: A is a monovalent cation, including but not limited to Rb. + Na + K + Cs + HN=CHNH 3+ (represented as FA), CH3NH 3+ (denoted as MA) or combinations thereof; B is a divalent cation, including but not limited to Sn. 2+ Pb 2+ or combinations thereof; X is selected from halide anions, O 2- S 2- and combinations thereof. The halide anions of the present invention include F.- Cl - ,Br - and I - Preferably, the perovskite absorber layer is made of MAPbI3, FAPbI3, or CsPbI3, and has a thickness of 500~1500 nm.

[0047] It should be noted that the electron transport layer can be made of any material commonly used in the field of perovskite solar cell technology for preparing electron transport layers, including but not limited to SnO2, TiO2, ZnO, PFN (9,9-dioctylfluorene-9,9-bisN,N-dimethylaminopropylfluorene) and [6,6]-phenyl-C-butyrate methyl ester (PCBM), with a thickness of 10~50 nm.

[0048] It should be noted that the top electrode layer is a transparent electrode, including but not limited to ultra-thin metal electrodes or conductive oxide electrodes with high light transmittance, such as Ag, ITO, FTO, and AZO, with a thickness of 50-1500 nm.

[0049] Furthermore, in addition to the perovskite solar cells described above, the perovskite solar cells of the present invention may also include any functional layer commonly used in perovskite cells, including but not limited to hole blocking layers, electron blocking layers, and various modification layers. The materials of the hole blocking layers include, but are not limited to, TiO2, ZnO, and Nb2O5; the materials of the electron blocking layers include, but are not limited to, CuSCN (cuprous thiocyanate) and PMMA (polymethyl methacrylate).

[0050] It should be noted that, in order to solve the problem that continuous top electrode layers easily generate significant ohmic losses, leading to increased series resistance, decreased fill factor, and output power loss, which ultimately limits the improvement of device photoelectric conversion efficiency, the present invention requires the provision of a metal gate layer on the top electrode layer.

[0051] Specifically, the metal grid layer includes spaced-apart fine grid lines and main grid lines electrically connected to the fine grid lines. The fine grid lines are used to locally collect photogenerated carriers on the battery surface, while the main grid lines are used to collect the current from each fine grid line and connect to an external circuit. This transforms the top electrode from a "single-surface electrode collection" to a composite conductive structure of "surface electrode local collection + grid line rapid current collection." This type of structure reduces the lateral transport distance of carriers in the high sheet resistance conductive layer, thereby reducing in-plane resistance loss and improving the battery fill factor and overall conversion efficiency.

[0052] It should be noted that the grid structure of the present invention is not set in isolation, but is designed in conjunction with the substrate edge insulation sealing structure.

[0053] Specifically, to reduce series resistance and avoid short circuits in the edge region, the inner edge of the edge insulating layer coincides with the outer edge of the metal gate layer on the vertical projection plane from bottom to top. The alignment error range is 50~500μm. That is, the outer edge of the metal gate layer can be projected within 50~500μm inside the inner edge of the edge insulating layer, or within 50~500μm outside the inner edge of the edge insulating layer. If the outer edge of the metal gate layer is located inside the inner edge of the edge insulating layer but exceeds the range, it will cause the lateral transmission path in the top electrode to increase, the sheet resistance loss and series resistance to increase, and the FF and PCE of the device to decrease. If the position inside the inner edge of the edge insulating layer exceeds the range, it will easily cause direct contact between the gate / top electrode and the metal substrate when there is alignment deviation, film shrinkage or edge burrs, resulting in edge leakage or short circuit.

[0054] It should be noted that the purpose of this invention is to bring the outer edge of the grid line as close as possible to the boundary of the effective power generation area, thereby shortening the lateral conductive path in the top electrode and reducing the in-plane resistance and series resistance; at the same time, the grid line is still located within the insulation safety area and will not cross the boundary to contact the exposed metal substrate, thus taking into account both the requirements of "efficient current collection" and "short circuit prevention", and achieving a better balance between conductivity, optical transmittance and processing feasibility.

[0055] In other words, this solution not only addresses the high series resistance issue inherent in existing top electrode large-area transmission methods, but also prevents unintended contact between the gate lines and the metal substrate as they extend towards the edge by arranging the gate lines in a position that matches the insulating sealing area. This reduces series resistance while suppressing edge short circuits and leakage losses. Because this gate line structure simultaneously addresses both "efficient current collection" and "safe isolation" requirements, it can more effectively improve the device's fill factor and overall photoelectric conversion efficiency compared to existing solutions that only use continuous top electrodes.

[0056] Studies have shown that by optimizing the number and distribution structure of grid lines, the current propagation path in the conductive layer can be effectively reduced, thereby reducing series resistance and improving battery output power.

[0057] More specifically, the fine grid lines have a parallel, comb-like, or grid-like arrangement structure, preferably a parallel arrangement structure parallel to the long side of the device, such as... Figure 6 As shown, this is done to balance carrier collection efficiency with shading loss control.

[0058] More specifically, the linewidth of the fine gate line is preferably 20-200 μm, and can be 20μm, 35μm, 50μm, 65μm, 80μm, 100μm, 120μm, 150μm, 170μm, 200μm, and more preferably 30-100 μm. If the linewidth of the fine gate line is too large, it will increase optical obstruction and reduce short-circuit current. Due to the limitations of the precision of vapor deposition mask, screen printing or electroplating process, the linewidth of the fine gate line cannot be too small. Too small a linewidth will lead to increased line resistance, which is not conducive to effective current collection.

[0059] More specifically, the thickness of the fine gate line is preferably 0.5-20 μm, and can be 0.5μm, 1μm, 3μm, 5μm, 6μm, 8μm, 10μm, 12μm, 15μm, 18μm, 20μm, more preferably 1-10 μm, to ensure that it has a sufficient conductive cross-sectional area; if the thickness is too small, the resistance will be too high, and if the thickness is too large, it will easily increase the difficulty of the process and local stress, affecting the stability of the device.

[0060] More specifically, the spacing between adjacent fine gate lines is preferably 0.5-5 mm, and 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 3.5 mm, 4 mm, 4.5 mm, and 5 mm can be more preferably 1-3 mm. If the spacing is too large, the lateral transport distance of charge carriers in the transparent conductive layer will increase, and the series resistance will increase. If the spacing is too small, the light absorption of the device will be affected due to the increase in the light-shielding area.

[0061] More specifically, the length of the fine gate line can be determined according to the size of the effective power generation area of ​​the device, preferably covering 50%-100% of the length direction of the effective power generation area, and connected to the main bus gate line, which can be 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, or 100%. If the length of the fine gate line is too short, the charge carriers cannot be fully collected in the effective power generation area, increasing the lateral transport distance in the top electrode layer, thereby increasing the series resistance. If it is too long, the fine gate line will extend into the non-effective power generation area or even close to the edge insulation area, which may increase the short circuit risk caused by misalignment with the edge structure.

[0062] More specifically, the linewidth of the main gate line is preferably 0.3-2 mm, and can be 0.3 mm, 0.5 mm, 0.8 mm, 1.0 mm, 1.3 mm, 1.5 mm, 1.7 mm, or 2.0 mm. If the linewidth of the main gate line is too large, it will lead to an increase in the light-blocking area, thereby reducing the light absorption and short-circuit current density of the device; if the width is too small, it will lead to insufficient conductive cross-sectional area and increased resistance, which is not conducive to effectively discharging the current collected by the fine gate line, thus affecting the fill factor.

[0063] More specifically, the thickness of the main gate line is preferably 1-30 μm, and can be 1μm, 3μm, 5μm, 6μm, 8μm, 10μm, 12μm, 15μm, 18μm, 20μm, 22μm, 25μm, 28μm, or 30μm, more preferably 5-10 μm. If the main gate line is too thick, it will increase the amount of material used and the difficulty of fabrication, and may introduce stress concentration or adhesion problems; if it is too thin, it will lead to a large resistance, affect the current bus efficiency, and thus reduce the device performance.

[0064] More specifically, the number of main grid lines can be set to 1-10, which are used to quickly extract the current collected by multiple fine grid lines.

[0065] In some preferred embodiments of the present invention, the material constituting the metal grid layer can be at least one of Ag, Cu, Au, Ni, and Al, preferably Ag or Cu.

[0066] The present invention provides a metal gate layer on the upper surface of the top electrode layer, which can significantly reduce the overall sheet resistance and series resistance while maintaining high light transmittance, and improve the open-circuit voltage (Voc), fill factor (FF) and photoelectric conversion efficiency (PCE) of the device; at the same time, the outer edge of the metal gate layer is aligned with the inner edge of the edge insulating layer, which can prevent short circuits at the edge of the device.

[0067] By defining the structure and size of the metal grid lines, including the arrangement, width, and thickness of the fine grid lines, this invention enables the design of the metal grid lines to find the optimal balance between electrical gain (FF enhancement) and optical loss (reduction of photocurrent Jsc), thereby maximizing the photoelectric conversion efficiency (PCE) during the process.

[0068] Compared to structures that rely solely on continuous top electrodes for carrier collection, this invention introduces a "fine gate line + main gate line" busbar path, which can shorten the lateral transport distance of carriers in the top electrode layer to a certain extent, thereby reducing in-plane resistivity loss. Simultaneously, through the rational design of the fine gate line width and spacing, a balance can be achieved between conductivity and shading loss, with minimal impact on device transmittance. Furthermore, this invention matches the gate line structure with the edge insulation sealing region, making the gate line distribution closer to the boundary of the effective power generation area while avoiding unintended contact with the metal substrate. This optimizes the fill factor and overall photoelectric conversion efficiency while ensuring device safety.

[0069] On the other hand, embodiments of the present invention also provide a method for fabricating a perovskite solar cell, wherein the perovskite solar cell is the leakage-proof metal-substrate perovskite solar cell, and the fabrication method includes the following steps: (1) Clean the metal substrate to remove surface oil and impurities; (2) An edge insulating layer is prepared on the upper surface edge of the metal substrate after the pretreatment in step (1); (3) On the metal substrate on which the edge insulating layer is prepared at the upper surface edge in step (2), a hole transport layer, a perovskite absorption layer, an electron transport layer and a top electrode layer are deposited sequentially.

[0070] It should be noted that in order to effectively remove impurities such as grease and oil stains from the surface of the ferritic stainless steel foil, and to ensure that it can be uniformly and firmly adhered to the substrate in the subsequent process, and to avoid the introduction of moisture or other impurities during the subsequent coating process, the present invention requires a pre-treatment of the metal substrate by cleaning.

[0071] Specifically, in step (1), the specific process for cleaning and pre-treating the metal substrate is as follows: ultrasonic cleaning is performed sequentially with acetone, isopropanol, ethanol, and deionized water for 5-30 minutes each; after drying with pure nitrogen, the substrate is baked at 80-120°C for 10-20 minutes to dry it; then plasma treatment is performed on the metal substrate to thoroughly clean the surface of the metal substrate, ensuring no organic pollutants adhere, improving wettability and promoting the firm adhesion of subsequent film layers.

[0072] It should be noted that the present invention first uses a mask, photoresist or laser processing method to define an insulating edge sealing area around the substrate, and then uses an insulating material to prepare the edge insulating layer in the edge sealing area.

[0073] Specifically, the edge insulating layer can be prepared by various methods such as deposition, printing, and coating. In the actual preparation process, the definition and preparation methods can be freely combined as needed.

[0074] According to some preferred embodiments of the present invention, a combination of metal mask definition + vacuum evaporation edge sealing can be used (applicable to insulating layers of MgF2 material), a combination of mask or partial masking + atomic layer deposition (ALD) (applicable to Al2O3 high-density insulating layers), photoresist patterning + insulating layer deposition + lift-off (applicable to high-precision edge sealing / partial edge sealing), and laser patterning (removing or roughening the interface) + insulating coating / deposition (applicable to roll-to-roll or rapid patterning).

[0075] It should be noted that the present invention uses existing processes to sequentially prepare each functional layer on the metal substrate on which the edge insulating layer is prepared on the upper surface edge, including a hole transport layer, a perovskite absorption layer, an electron transport layer and a top electrode layer.

[0076] Specifically, the method for preparing each functional layer is one of the following: blade coating, magnetron sputtering, injection molding, vacuum evaporation, or electron beam evaporation.

[0077] According to some preferred embodiments of the present invention, the hole transport layer is deposited by means of blade coating or magnetron sputtering, preferably by blade coating of nickel oxide (NiO). x ).

[0078] According to some preferred embodiments of the present invention, CH3NH3PbI3 is coated using a slot coating method. x Cl x The perovskite absorber layer was prepared from a DMF solution.

[0079] According to some preferred embodiments of the present invention, the C60 electron transport layer is prepared by vacuum evaporation.

[0080] According to some preferred embodiments of the present invention, the ITO top electrode layer is prepared by magnetron sputtering.

[0081] According to some preferred embodiments of the present invention, the Ag metal gate layer is prepared by vacuum evaporation or electron beam evaporation.

[0082] It should be noted that, in order to solve the problem that continuous top electrode layers easily generate significant ohmic losses, leading to increased series resistance, decreased fill factor, and output power loss, which ultimately limits the improvement of device photoelectric conversion efficiency, the present invention requires the fabrication of a metal gate layer on the top electrode layer.

[0083] Specifically, the preparation method further includes step (4), which involves preparing a metal gate layer on the top electrode layer. The preparation method of the metal gate layer can be one of mask evaporation, screen printing, electroplating, electrochemical deposition, inkjet printing, or laser-induced transfer, preferably mask evaporation; the material is at least one of Ag, Cu, Ni, Au, and Al, preferably Ag.

[0084] This invention uses existing fabrication processes to prepare edge insulating layers and other functional layers on the surface of a metal substrate. No additional equipment is required, the fabrication process is simple, and it is compatible with roll-to-roll fabrication, making it suitable for the industrial fabrication and application of large-area metal substrate perovskite components.

[0085] Compared with existing laser scribing or edge removal methods, this invention, by setting an edge insulating layer in the edge region of the upper surface of the metal substrate, completely covers the edge of the metal substrate layer. This not only successfully isolates the metal substrate layer from the top electrode layer, effectively preventing edge leakage and short circuits in perovskite solar cells, reducing leakage current loss, and improving device efficiency (photovoltaic conversion efficiency (PCE) to ≥17%), but also provides alignment tolerance and buffer space for subsequent processing of the top electrode layer and grid / bus structure. Even with some alignment deviation or lateral creep of the film layer, it is less likely to trigger unintended contact with the metal substrate, thereby improving the process window and yield (≥80%) of metal-substrate perovskite solar cell device fabrication. Furthermore, the short-circuit current of the metal-substrate perovskite solar cell of this invention is >20 mA·cm⁻¹. -2 The open-circuit voltage is greater than 1V and the fill factor is greater than 60%.

[0086] The technical solution of the present invention will be further described below using examples and comparative examples.

[0087] Example 1 A method for fabricating a perovskite solar cell on a stainless steel substrate containing an MgF2 edge insulating layer includes the following steps: (1) The 304 stainless steel substrate was cleaned and pretreated, including degreasing, cleaning and drying in sequence. Specifically, the substrate was ultrasonically cleaned with acetone, isopropanol and deionized water for 8 min each, dried with nitrogen and baked at 100°C for 15 min to remove residual solvent and water vapor. Then the metal substrate was plasma treated. The surface roughness Ra of the 304 stainless steel substrate was 150 nm. (2) Fix the pretreated 304 stainless steel substrate on a high-rigidity precision carrier. The carrier is provided with positioning holes / positioning slots and cooperates with the mask positioning pins to control the relative position repeatability of the substrate and the mask within ±50 μm. The metal mask with the "sealed window pattern" is bonded to the substrate or bonded with a small gap (≤50 μm to reduce shadowing effect), and then placed into the vapor deposition chamber and evacuated to 5×10⁻⁶. -4 Below Pa; MgF2 was used for the vapor deposition of insulating material at a rate of 0.5 nm / s, the substrate temperature was controlled at 60°C, the average deposition thickness was controlled at 3 μm, and the width was 5 mm. After completion, it was naturally cooled and removed, resulting in a patterned edge insulating layer located on the two continuous edges of the upper surface of the substrate, such as... Figure 3 As shown; (3) On a metal substrate with an edge insulating layer formed on the upper surface edge, a hole transport layer, a perovskite absorber layer, an electron transport layer, and a top electrode layer are sequentially formed, specifically: A 50 nm thick nickel oxide hole transport layer was prepared using a slot coating process, comprising the following steps: during the coating process, the gap between the die and the substrate was set to 150 μm, and the flow rate of the 10 mg / mL nickel oxide solution was 0.20 mL / min. - ¹, The base moving speed is 10 mm / s - ¹; After coating, it is placed on a hot stage at 100°C for annealing for 40 min, and then removed and cooled to room temperature to obtain a nickel oxide hole transport layer with a thickness of 10 nm. CH3NH3PbI3 with a thickness of 1000 nm was prepared using a slit coating process. x Cl x The perovskite absorber layer comprises: CH3NH3PbI3 at a concentration of 1.2 mol / L. x Cl x The DMF solution was injected at a rate of 0.2 ml / min, with a coating gap of 0.2 mm and a coating head moving speed of 7 mm / s. The perovskite film after coating was annealed on a hot plate at 150 °C for 10 min to obtain a perovskite absorber layer with a thickness of 600 nm. An electron transport layer with a thickness of 20 nm was prepared using vacuum evaporation, including: when the vacuum level of the vacuum chamber is lower than 5... 10 -4 Lithium fluoride deposition begins at Pa at a deposition rate of 0.2 A / s and a deposition thickness of 10 nm; subsequently, C60 deposition is performed at a deposition rate of 2 A / s and a deposition thickness of 10 nm. A 65 nm thick Ag top electrode layer was prepared using magnetron sputtering, including: when the vacuum level of the vacuum chamber was lower than 5... 10 -7 Deposition begins at Pa, with an oxygen content of 5% and a deposition rate of 0.25 A / s; (4) A metal gate layer is prepared on the top electrode layer using a mask evaporation method (e.g., Figure 6 As shown in the figure, the fine grid lines have a line width of 100 μm, a thickness of 1 μm, and an interval of 4 mm between adjacent fine grid lines; the main grid lines have a line width of 0.3 mm, a thickness of 1 μm, and a quantity of 4 lines; a safety alignment margin of 300 μm is maintained between the outer edge of the grid lines and the insulating sealing area.

[0088] At room temperature, the short-circuit current (Jsc) of the perovskite solar cell prepared in Example 1 was 22.04 mA cm⁻¹. -2 The open-circuit voltage (Voc) is 1.207V, the fill factor (FF) is 71.42%, and the final photoelectric conversion efficiency (PCE) of the cell is 19.004%. Figure 8 As shown.

[0089] Example 2 A method for preparing a stainless steel substrate perovskite solar cell containing an Sb2O3 edge insulating layer is described. The method is the same as in Example 1, except that in step (2), the pretreated metal substrate is aligned and bonded to a metal mask with a sealed window pattern, then placed into a vapor deposition chamber and evacuated to a vacuum level of 5 × 10⁻⁶. -4 Below Pa; Sb2O3 is used as the evaporation material, the evaporation rate is controlled at 0.2~0.8 nm / s, preferably 0.5 nm / s, the average deposition thickness is 0.3 μm, and the width is 5 mm; after evaporation, it is allowed to cool naturally, and the shielding structure is removed to obtain the edge insulating layer, such as Figure 3 As shown.

[0090] At room temperature, the short-circuit current (Jsc) of the perovskite solar cell prepared in Example 2 is 20.56 mA cm⁻¹. -2 The open-circuit voltage (Voc) is 1.16V, the fill factor (FF) is 77.63%, and the final photoelectric conversion efficiency (PCE) of the cell is 18.52%. Figure 9 As shown.

[0091] Example 3 A method for preparing a stainless steel substrate perovskite solar cell containing an Al2O3 edge insulating layer is described. The method is the same as in Example 1, except that in step (2), the raw materials TMA and water are placed in an atomic layer (ALD) reaction chamber, and Al2O3 is deposited at a reaction temperature of 130°C. TMA (trimethylaluminum) and H2O are typical precursors. The pulse / purge parameters are: TMA pulse 0.2 s, inert gas purge 10 s, H2O pulse 0.1 s, purge 15 s; the single-cycle growth rate is typically 1.2 Å / cycle. An insulating layer with an average thickness of 2 μm and a width of 5 mm is obtained through 10,000 cycles. After deposition, the edge insulating layer is obtained by removing the shielding structure. Figure 3 As shown.

[0092] Under room temperature conditions, the short-circuit current (J) of the perovskite solar cell prepared in Example 3 sc The value is 20.38 mA cm. -2 Open circuit voltage (V) oc The voltage is 1.16V, the fill factor (FF) is 76.00%, and the final photoelectric conversion efficiency (PCE) of the cell is 18.01%. Figure 10 As shown.

[0093] Example 4 This embodiment is the same as the steps in Embodiment 1, except that in step (2), the metal mask with "discontinuous relative edges" is bonded to the substrate or bonded with a small gap (gap ≤ 50 μm to reduce the shadowing effect), and then placed into the vapor deposition chamber and evacuated to 5 × 10⁻⁶. -4 Below Pa; MgF2 was used for the vapor deposition of insulating material at a rate of 0.5 nm / s, the substrate temperature was controlled at 60°C, the average deposition thickness was controlled at 3 μm, and the width was 5 mm. After completion, it was naturally cooled and removed, resulting in a patterned edge insulating layer located on the two continuous edges of the upper surface of the substrate, such as... Figure 4 As shown; Under room temperature conditions, the short-circuit current (J) of the perovskite solar cell prepared in Example 4 sc The value is 22.00 mA cm. -2 Open circuit voltage (V) oc With a voltage of 1.2V, a fill factor (FF) of 70.23%, and a final photoelectric conversion efficiency (PCE) of 18.54%, the cell achieves the following results: Figure 11 As shown.

[0094] Example 5 This embodiment is the same as the steps in Embodiment 1, except that in step (2), the metal mask with "continuous four edges" is attached to the substrate or attached with a small gap (gap ≤ 50 μm to reduce the shadowing effect), and then placed into the vapor deposition chamber and evacuated to 5 × 10⁻⁶. -4 Below Pa; MgF2 was used for the vapor deposition of insulating material at a rate of 0.5 nm / s, the substrate temperature was controlled at 60°C, the average deposition thickness was controlled at 3 μm, and the width was 5 mm. After completion, it was naturally cooled and removed, resulting in a patterned edge insulating layer located on the two continuous edges of the upper surface of the substrate, such as... Figure 5 As shown; Under room temperature conditions, the short-circuit current (J) of the perovskite solar cell prepared in Example 5 sc The value is 21.26 mA cm. -2 Open circuit voltage (V) oc The voltage is 1.178 V, the fill factor (FF) is 77.614%, and the final photoelectric conversion efficiency (PCE) of the cell is 19.43%. Figure 12 As shown.

[0095] Examples 6-11 Using the same preparation steps as in Example 5, except that the perovskite solar cells of Examples 6-11 and Comparative Examples 1-7 were obtained by changing the preparation process or process conditions respectively.

[0096] The physicochemical performance parameters of the batteries prepared in Examples 1-11 and Comparative Examples 1-7 are shown in Table 1.

[0097] Table 1. Physicochemical properties of perovskite solar cells prepared in Examples 1-11 and Comparative Examples 1-7

[0098] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A perovskite solar cell with a metal substrate that is leak-proof, characterized in that, From bottom to top, the solar cell sequentially includes a metal substrate layer, an edge insulating layer, a hole transport layer, a perovskite absorber layer, an electron transport layer, and a top electrode layer, wherein the edge insulating layer is located in the edge region of the upper surface of the metal substrate layer.

2. The solar cell according to claim 1, characterized in that, The edge insulating layer is continuously distributed circumferentially along the metal substrate.

3. The solar cell according to claim 1, characterized in that, The material of the edge insulation layer is at least one of MgF2, SbO3, Al2O3, polyimide, epoxy resin, and fluorinated polymer.

4. The solar cell according to claim 1, characterized in that, The width of the edge insulation layer is 0.5~5mm.

5. The solar cell according to claim 1, characterized in that, The thickness of the edge insulating layer is 0.1~10μm.

6. The solar cell according to claim 1, characterized in that, A metal grid layer is provided on the top electrode layer.

7. The solar cell according to claim 6, characterized in that, On the vertical projection plane from bottom to top, the inner edge of the edge insulating layer coincides with the outer edge of the metal grid layer.

8. The solar cell according to claim 6, characterized in that, The metal grid layer includes spaced fine grid lines and main grid lines electrically connected to the fine grid lines; And / or, the fine grid lines have a parallel, comb-like, grid-like, or strip-like arrangement structure parallel to the long side of the device.

9. A method for preparing a perovskite solar cell, characterized in that, The perovskite solar cell is the leakage-proof metal-substrate perovskite solar cell according to any one of claims 1-8, and the preparation method includes the following steps: (1) Clean the metal substrate to remove surface oil and impurities; (2) An edge insulating layer is prepared on the upper surface edge of the metal substrate after the pretreatment in step (1); (3) On the metal substrate on which the edge insulating layer is prepared at the upper surface edge in step (2), a hole transport layer, a perovskite absorption layer, an electron transport layer and a top electrode layer are deposited sequentially.

10. The preparation method according to claim 9, characterized in that, The preparation method further includes step (4), specifically, preparing a metal grid layer on the top electrode layer.

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