Perovskite / crystalline silicon tandem solar cell and preparation method thereof

Abstract

The application discloses a perovskite / crystalline silicon laminated solar cell and a preparation method thereof. The perovskite / crystalline silicon laminated solar cell comprises a crystalline silicon substrate which is divided into a first region and a second region on the back surface, and the second region is recessed relative to the first region; a tunneling oxide layer formed in the first region; a P-type doped layer formed on the tunneling oxide layer; a dielectric stack formed on the P-type doped layer and the second region; and a plurality of metal electrodes electrically connected with the P-type doped layer, wherein the metal electrodes are arranged in the dielectric stack; and a gap is arranged between any two adjacent metal electrodes. Thus, the short-circuit current density can be improved without sacrificing the open-circuit voltage, and effective technical support is provided for realizing a high-efficiency, high-reliability and mass-production compatible two-terminal perovskite / crystalline silicon laminated solar cell.

Description

Technical Field

[0001] This invention relates to the field of new energy, and more specifically, to a perovskite / crystalline silicon tandem solar cell and its preparation method. Background Technology

[0002] As a key component in renewable energy conversion, solar cells have made significant progress in efficiency improvement and cost reduction in recent years. Among them, crystalline silicon (c-Si) solar cells have long dominated the photovoltaic market due to their mature industrialization foundation and good stability. However, limited by the Shockley-Queisser theoretical limit, the photoelectric conversion efficiency of monocrystalline silicon solar cells is difficult to break through approximately 29.4%. To overcome this efficiency bottleneck, tandem solar cell technology has become an important development direction for the next generation of high-efficiency photovoltaic devices.

[0003] Perovskite / Silicon Tandem Solar Cells effectively broaden the solar spectrum and significantly improve overall photoelectric conversion efficiency by integrating a wide-bandgap perovskite top cell with a narrow-bandgap crystalline silicon bottom cell through spectral complementarity. Especially in 2-terminal (2T) structures, the top and bottom cells are connected in series internally, resulting in a compact device structure, simple external circuitry, and high compatibility with existing photovoltaic module packaging processes, thus attracting widespread attention from academia and industry.

[0004] In two-terminal perovskite / crystalline silicon tandem solar cells, the design of the crystalline silicon bottom cell is particularly critical. Its front side needs to possess excellent long-wavelength response and form a recombination junction with the perovskite top cell with low optical and electrical losses. To achieve this, an electron-selective passivation contact layer and a transparent conductive oxide (TCO) layer are typically introduced on the front side of the crystalline silicon bottom cell to achieve efficient carrier extraction and optical coupling. Simultaneously, the back side of the crystalline silicon bottom cell needs to possess high-quality hole-selective contacts, low interfacial recombination losses, and excellent long-wavelength optical management capabilities to maximize the bottom cell's absorption of near-infrared light.

[0005] Currently, heterojunction with Intrinsic Thin-layer (HIT) crystalline silicon solar cells are widely used as the bottom cells in tandem structures due to their excellent surface passivation properties and high open-circuit voltage. However, HIT cells rely on low-temperature processes, high-cost transparent conductive oxides and silver paste materials, and have stringent manufacturing environment requirements, which limits their cost competitiveness in large-scale industrialization.

[0006] In contrast, crystalline silicon solar cells based on tunnel oxide passivated contact (TOPCon) or POLO (Poly-Si on Oxide) structures show promising prospects for industrialization. These structures typically consist of an ultrathin tunnel oxide layer (such as 1–2 nm thick SiO2) on the surface of a crystalline silicon substrate and a heavily doped polycrystalline silicon (poly-Si) layer covering it. They simultaneously achieve excellent carrier selective transport and interface passivation, and have already achieved conversion efficiencies of >26.9% in single-crystal silicon cells, while also possessing upgrade potential compatible with existing PERC production lines.

[0007] However, the inventors found that when applying TOPCon or POLO crystalline silicon bottom cells to perovskite / crystalline silicon stacked structures, significant technical challenges remain: on the one hand, depositing a p-type poly-Si hole-selective contact layer on the entire back side of the crystalline silicon bottom cell (especially the textured surface) is beneficial for optical light trapping, but it easily leads to severe interfacial recombination, thereby reducing the open-circuit voltage of the bottom cell; on the other hand, if a fully planar back side structure is adopted to suppress recombination, it will weaken the light trapping effect for long-wavelength light, reduce the short-circuit current density of the bottom cell, and thus limit the overall performance of the stacked device. Summary of the Invention

[0008] This invention provides a perovskite / crystalline silicon tandem solar cell and its fabrication method, which can increase the short-circuit current density without sacrificing the open-circuit voltage, providing effective technical support for realizing high-efficiency, high-reliability and mass-producible compatible two-terminal perovskite / crystalline silicon tandem solar cells.

[0009] The embodiments of the present invention are implemented as follows: In a first aspect, the present invention provides a perovskite / crystalline silicon tandem solar cell, comprising: Crystalline silicon substrate; The back side of the crystalline silicon substrate is divided into a first region and a second region, with the second region being recessed relative to the first region; A tunneling oxide layer is formed in the first region, and a P-type doped layer is formed in the tunneling oxide layer, wherein the P-type doped layer is a P-type doped polysilicon layer or a P-type doped polysilicon oxide layer. A dielectric stack formed on the P-type doped layer and the second region, the dielectric stack including a dielectric passivation layer and a back reflective layer; A plurality of metal electrodes electrically connected to the p-type doped layer, the metal electrodes being disposed through the dielectric stack; There is a gap between any two adjacent metal electrodes.

[0010] In an optional embodiment, the first region accounts for 0.5-80% of the area on the back side of the crystalline silicon substrate.

[0011] In an optional embodiment, the first region accounts for 10-60% of the area on the back side of the crystalline silicon substrate.

[0012] In an optional embodiment, the first region accounts for 30-40% of the area on the back side of the crystalline silicon substrate.

[0013] In an optional embodiment, the recess depth of the second region relative to the first region is 0.05-50 μm.

[0014] In an optional embodiment, the recess depth of the second region relative to the first region is 0.1-20 μm.

[0015] In an optional embodiment, the depression depth of the second region relative to the first region is 0.5-10 μm.

[0016] In an optional embodiment, the recess depth of the second region relative to the first region is 0.5-2 μm.

[0017] In an optional implementation, the surface of the first region is a polished plane; The surface of the second region is a polished plane or a pyramid-shaped light-trapping structure.

[0018] In an optional embodiment, all of the metal electrodes occupy 0.05-20% of the area on the back side of the crystalline silicon substrate.

[0019] In an optional embodiment, all of the metal electrodes occupy 0.1-10% of the area on the back side of the crystalline silicon substrate.

[0020] In an optional embodiment, two adjacent metal electrodes are electrically connected by a conductive interconnect; wherein a gap is left between two adjacent conductive interconnects, and the conductive interconnect includes a metal grid, a bus electrode, conductive adhesive, solder ribbon, or conductive interconnect.

[0021] In an optional embodiment, the dielectric stack has a plurality of spaced contact openings in the region corresponding to the first region; each of the metal electrodes passes through one of the contact openings and is electrically connected to the P-type doped layer.

[0022] Secondly, the present invention provides a method for preparing a perovskite / crystalline silicon tandem solar cell, comprising: Provides crystalline silicon substrates; A first region is defined on the back side of the crystalline silicon substrate; A tunneling oxide layer is formed in the first region and a P-type doped layer is formed on the tunneling oxide layer, wherein the P-type doped layer is a P-type doped polysilicon layer or a P-type doped polysilicon oxide layer. A second region is formed on the back side in the area other than the first region, wherein the second region is recessed relative to the first region; A dielectric stack is formed on the P-type doped layer and the second region, wherein the dielectric stack includes a dielectric passivation layer and a back reflective layer; Multiple metal electrodes are formed that pass through the dielectric stack and are electrically connected to the P-type doped layer; wherein a gap is left between any two adjacent metal electrodes.

[0023] In an optional embodiment, the step of forming a plurality of metal electrodes that pass through the dielectric stack and are electrically connected to the P-type doped layer includes: The metal electrode is formed using a burn-through paste and a screen printing process.

[0024] In an optional embodiment, the steps of forming a tunneling oxide layer in the first region and forming a P-type doped layer on the tunneling oxide layer include: First, a tunneling oxide layer is formed on the entire back side of the crystalline silicon substrate, and a P-type doped layer is formed on the tunneling oxide layer. Then, the P-type doped layer in the area outside the first region is removed by patterned etching. or, First, a patterned mask is formed on the back side of the crystalline silicon substrate in a region other than the first region. Then, a tunneling oxide layer is formed in the first region and a P-type doped layer is formed on the tunneling oxide layer. Finally, the mask is removed. or, First, an intrinsic polycrystalline silicon layer or a polycrystalline silicon oxide layer is formed in the first region, and then local boron diffusion, local ion implantation, local laser doping, or local boron paste diffusion are performed.

[0025] In an optional implementation, the step of forming a second region on the back surface in a region other than the first region includes: The area on the back side other than the first area is etched to form the second area; wherein the etching method is one or more of alkaline etching, acid etching, laser etching, plasma etching, reactive ion etching, and metal-assisted chemical etching. The second region is then subjected to alkaline polishing or alkaline anisotropic etching.

[0026] In an optional embodiment, the step of forming a plurality of metal electrodes that pass through the dielectric stack and are electrically connected to the P-type doped layer includes: Multiple spaced-apart contact openings are formed in the region corresponding to the first region on the dielectric stack; A metal electrode is formed at each of the contact openings.

[0027] In an optional embodiment, a plurality of contact openings are formed on the dielectric stack using laser openings, photolithography, wet etching, plasma etching, inkjet etching paste, or screen printing etching paste. The metal electrode is formed at each of the contact openings by means of screen printing, inkjet printing, dispensing, local evaporation, local sputtering, laser transfer, electroplating, chemical plating, or mask deposition.

[0028] In an optional implementation, the step of forming one of the metal electrodes at each of the contact openings includes: First, a contact seed layer that is electrically in contact with the P-type doped layer is formed at the contact opening. Then, a conductive enhancement layer is formed on the contact seed layer. Finally, a protective layer is formed on the conductive enhancement layer. or, After printing silver paste, silver-aluminum paste, aluminum paste, or conductive adhesive at the contact opening, the material is cured.

[0029] The beneficial effects of the embodiments of the present invention compared to the prior art include: The first region is responsible for selective hole extraction and low-resistance electrical contact: its tunneling oxide layer and P-type doped polysilicon layer together form a high-quality passivation contact structure, which improves hole collection efficiency and effectively suppresses interfacial recombination caused by direct contact between the metal electrode and the silicon substrate. In addition, as a local contact window for the metal electrode, this region not only provides a conductive path with low contact resistance, but also has process alignment tolerance due to its certain area, reducing the risk of performance degradation caused by electrode misalignment.

[0030] Meanwhile, the second region, as a non-contact area, significantly enhances the optical management capabilities of the back side by retaining the concave morphology and covering it with a dielectric passivation layer and a back reflective layer. Combined with a high reflectivity dielectric layer, it can effectively improve the round-trip path of near-infrared light in the crystalline silicon bottom cell, thereby improving the absorption efficiency of long-wavelength photons. At the same time, this region avoids continuous coverage of p-type poly-Si and metal, reducing unnecessary parasitic absorption and thermal stress concentration. Furthermore, the physical isolation formed by the height difference further suppresses leakage and short-circuit tendencies caused by lateral diffusion of metal paste or accidental contact.

[0031] Moreover, by having the metal pass through the dielectric stack and then passivate to the p-type doped layer, the actual contact area between the metal electrode and the p-type doped layer can be significantly reduced, thus reducing metal-induced recombination, while still ensuring that charge carriers can be effectively extracted through the contact window. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the perovskite / crystalline silicon tandem solar cell of the present invention; Figure 2 for Figure 1 A schematic diagram of a medium-crystalline silicon substrate; Figure 3 for Figure 1 One of the schematic diagrams showing the distribution of the first and second regions in the middle; Figure 4 for Figure 1 The second schematic diagram showing the distribution of the first and second regions in the middle; Figure 5 for Figure 1 The third schematic diagram showing the distribution of the first and second regions in the middle; Figure 6 for Figure 1 Fourth schematic diagram of the distribution of the first and second regions in the middle; Figure 7 This is a flowchart illustrating the fabrication method of the perovskite / crystalline silicon tandem solar cell of the present invention. Figures 8 to 10 This is a schematic diagram of the formation process of the backside structure of a crystalline silicon substrate; Figure 11 for Figure 7 A flowchart of at least some of the sub-steps in step S500; Figure 12 for Figure 7 A flowchart of at least some of the sub-steps in step S700.

[0034] Icons: 1-Crystal silicon substrate; 101-First region; 102-Second region; 2-Tunneling oxide layer; 3-P-type doped layer; 4-Dielectric stack; 5-Metal electrode; 6-N-type tunneling oxide layer; 7-N-type doped layer; 8-Transparent conductive oxide layer; 9-Hole transport layer; 10-Self-assembled monolayer; 11-Perovskite absorber layer; 12-Passivation layer; 13-Electron transport layer; 14-Transparent conductive electrode; 15-Front-side metal; 16-Antireflection layer; 19-Conductive interconnect. Detailed Implementation

[0035] As used in this article: "Prepared from" is synonymous with "comprising". The terms "comprising", "including", "having", "containing", or any other variations thereof as used herein are intended to cover non-exclusive inclusion. For example, a composition, step, method, article, or apparatus that includes the listed elements is not necessarily limited to those elements, but may include other elements not expressly listed or elements inherent to such composition, step, method, article, or apparatus.

[0036] When a quantity, concentration, or other value or parameter is expressed as a range, a preferred range, or a range defined by a series of upper and lower preferred values, this should be understood as specifically disclosing all ranges formed by any pair of any upper or preferred value with any lower or preferred value, regardless of whether the range is disclosed individually. For example, when the range “1–5” is disclosed, the described range should be interpreted as including ranges “1–4”, “1–3”, “1–2”, “1–2 and 4–5”, “1–3 and 5”, etc. When numerical ranges are described herein, unless otherwise stated, the range is intended to include its endpoints and all integers and fractions within that range.

[0037] refer to Figure 1 and Figure 2 This invention discloses a perovskite / crystalline silicon tandem solar cell, comprising: 1. Crystalline silicon substrate; The back side of the crystalline silicon substrate 1 is divided into a first region 101 and a second region 102, with the second region 102 being recessed relative to the first region 101. In other words, when viewed from the back side of the entire crystalline silicon substrate 1, the first region 101 can be understood as a relatively raised or preserved local platform region, and the second region 102 can be understood as a recessed region, trench region, or low-lying region located between adjacent platform regions.

[0038] A tunneling oxide layer 2 is formed in the first region 101, and a P-type doped layer 3 is formed in the tunneling oxide layer 2. The P-type doped layer 3 is a P-type doped polysilicon layer or a P-type doped polysilicon oxide layer. A dielectric stack 4 is formed on the p-type doped layer 3 and the second region 102. The dielectric stack 4 includes a dielectric passivation layer and a back reflective layer. Multiple metal electrodes 5 are electrically connected to the P-type doped layer 3, and the metal electrodes 5 are disposed in the dielectric stack 4. There is a gap between any two adjacent metal electrodes 5.

[0039] Therefore, dividing the back side of the crystalline silicon substrate 1 into a recessed second region 102 and a non-recessed first region 101, and setting the tunneling oxide layer 2 and the P-type doped layer 3 (such as a P-type doped polysilicon layer or a P-type doped polysilicon oxide layer) only on the first region 101, allows the selective contact of holes to be concentrated in a local area (i.e., the first region 101), which helps to effectively collect the holes in the crystalline silicon substrate 1. Meanwhile, the metal electrode 5 only penetrates the dielectric stack 4 and forms a low-resistance passivation contact with the P-type doped layer 3, without forming a continuous full-contact metal layer on the entire back side of the crystalline silicon substrate 1. Furthermore, the adjacent electrodes are arranged at intervals, which not only ensures efficient hole collection and lateral transport, but also serves as an alignment tolerance region for the metal electrode 5, preventing the metal electrode 5 from directly contacting the second region 102 after offset. This reduces the interface recombination loss caused by the direct large-area contact between the metal electrode 5 and the crystalline silicon substrate 1. As a result, it can maintain effective carrier extraction capability and is beneficial to improving the open-circuit voltage of the bottom cell.

[0040] The second region 102, as a non-contact region that does not directly contact the metal electrode 5, can prevent the P-type doped layer 3 from continuously covering the entire back side of the crystalline silicon substrate 1. At the same time, the height difference relative to the first region 101 can achieve spatial physical isolation, suppressing leakage and short circuit tendencies caused by lateral diffusion or accidental contact of the metal paste during the formation of the metal electrode 5.

[0041] Moreover, the dielectric stack 4 covers the P-type doped layer 3 and the second region 102, which means that the present invention does not only perform dielectric passivation on the second region 102, but simultaneously forms a dielectric passivation layer and a back reflective layer on the entire back side of the crystalline silicon substrate 1, and further enhances the optical path of near-infrared light in the bottom cell through the back reflective layer, thereby promoting the effective absorption of long-wavelength photons and increasing the short-circuit current density.

[0042] Meanwhile, the metal electrode 5 does not directly cover the entire p-type doped layer region, but rather passes through the dielectric stack 4 before making passivated contact with the p-type doped layer. This significantly reduces the actual contact area between the metal electrode 5 and the p-type doped layer, thereby reducing metal-induced recombination, while still ensuring that charge carriers can be effectively extracted through the contact window.

[0043] As described above, the present invention achieves fine-grained control of functional partitioning by constructing a first region 101 and a recessed second region 102 on the back side of a crystalline silicon substrate 1.

[0044] The first region 101 is responsible for selective hole extraction and low-resistance electrical contact: its tunneling oxide layer 2 and P-type doped polysilicon layer together form a high-quality passivation contact structure, which improves hole collection efficiency and effectively suppresses interface recombination caused by direct contact between the metal electrode 5 and the silicon substrate. In addition, as a local contact window of the metal electrode 5, this region not only provides a conductive path with low contact resistance, but also has process alignment tolerance due to its certain area, reducing the risk of performance degradation caused by electrode misalignment.

[0045] Meanwhile, the second region 102, as a non-contact area, significantly enhances the optical management capability of the back side by retaining the concave morphology and covering it with a dielectric passivation layer and a back reflective layer. Combined with a high reflectivity dielectric layer, it can effectively improve the round-trip path of near-infrared light in the crystalline silicon bottom cell, thereby improving the absorption efficiency of long-wavelength photons. At the same time, this region avoids continuous coverage of p-type poly-Si and metal, reducing unnecessary parasitic absorption and thermal stress concentration. Furthermore, the physical isolation formed by the height difference further suppresses the tendency of leakage and short circuit caused by lateral diffusion of metal paste or accidental contact.

[0046] Moreover, by having the metal pass through the dielectric stack 4 and then passivate to the p-type doped layer, the actual contact area between the metal electrode 5 and the p-type doped layer can be significantly reduced, thus reducing metal-induced recombination, while still ensuring that charge carriers can be effectively extracted through the contact window.

[0047] Compared to traditional planar or fully covered back-side structures, this invention utilizes a spatially decoupled layout of "electrical contact" and "optical passivation / reflection," allowing different regions to perform their respective functions—the first region 101 focuses on efficient carrier extraction, while the second region 102 focuses on optical reflection and surface passivation. This functional zoning strategy increases short-circuit current density without sacrificing open-circuit voltage, providing effective technical support for achieving high-efficiency, high-reliability, and mass-producible compatible perovskite / crystalline silicon tandem solar cells.

[0048] It should be noted that in the perovskite / crystalline silicon tandem solar cell disclosed in this invention, a highly integrated, functionally defined multilayer stacked structure is constructed from bottom to top on the front side of the crystalline silicon substrate 1. Starting from the crystalline silicon surface, this structure sequentially includes: an electron-selective passivation contact layer, a composite junction, a transparent conductive oxide layer 8, a hole transport layer 9, a self-assembled monolayer 10, a perovskite absorption layer 11, a passivation layer 12, an electron transport layer 13, a transparent conductive electrode 14, and parallel antireflection layers 16 and front-side metal 15 (such as metal grid lines or auxiliary electrodes). Each layer undertakes a specific physical or electrical function, collectively achieving efficient light absorption, selective carrier extraction, low-loss recombination connections, and excellent optical coupling, thereby supporting the overall performance improvement of the tandem device.

[0049] In detail, the electron selective passivation contact layer is located at the bottom layer on the front side of the crystalline silicon substrate 1. It is usually composed of an n-type tunneling oxide layer 6 and an n-type doped layer 7, i.e., an n-TOPCon structure. The n-type doped layer 7 is an n-type doped polycrystalline silicon layer and / or an n-type doped polycrystalline silicon oxide layer. This electron selective passivation contact layer is mainly used to selectively extract and transport photogenerated electrons generated in the crystalline silicon bottom cell, and form a composite junction of the stacked cell with the transparent conductive oxide layer 8 above.

[0050] The transparent conductive oxide layer 8 (TCO) provides high lateral conductivity and high optical transmittance, serving as both the ohmic contact layer of the recombination junction and a flat, conductive substrate for the upper hole transport layer. The recombination junction (RJ) is the core structure for achieving electrical series connection between the top and bottom cells in a two-terminal tandem solar cell. Its main function is to provide a channel for efficient electron-hole recombination, ensuring current continuity. It also possesses high lateral conductivity to reduce series resistance while maintaining high optical transmittance (>90%) to allow long-wavelength light to penetrate to the crystalline silicon bottom cell. The crystalline silicon bottom cell consists of the electron-selective passivation contact layer, the crystalline silicon substrate 1, and the back side of the crystalline silicon substrate 1.

[0051] Typical materials for the hole transport layer (HTL) include inorganic oxides (such as NiO). x The perovskite absorber layer 11 can be a perovskite absorber layer (e.g., CuSCN) or a small organic molecule / polymer (e.g., PTAA, Spiro-OMeTAD). This layer is located above the composite junction and its main function is to efficiently extract holes generated by the perovskite absorber layer 11 and transport them to the composite junction below, while blocking electron back-injection and reducing interfacial recombination.

[0052] Common molecules used in self-assembled monolayers (SAMs), such as MeO-2PACz, 2PACz, and Br-2PACz, are modified onto the HTL surface via chemisorption. Their key functions include modulating the HTL surface work function, optimizing energy level alignment with the perovskite, and increasing the open-circuit voltage (VOC); passivating HTL surface defects, suppressing non-radiative recombination, inducing preferred orientation growth of perovskite crystals, and improving film crystal quality and coverage uniformity; and, as a hydrophobic interface, enhancing device environmental stability to some extent.

[0053] The perovskite absorber layer 11 uses a wide bandgap (e.g., 1.55–1.85 eV, preferably 1.65–1.75 eV) perovskite material (e.g., FA0.8Cs0.2Pb(I0.6Br0.4)3), with a thickness typically of 500–800 nm. Its core function is to absorb high-energy photons (approximately 300–800 nm) from the solar spectrum, generating electron-hole pairs. Moreover, as the photosensitive active layer of the top cell, its bandgap is well spectrally complementary to that of the crystalline silicon bottom cell (~1.12 eV), thus achieving current matching with the crystalline silicon bottom cell.

[0054] Commonly used materials for passivation layer 12 include fullerene derivatives (such as PCBM, C) 60 LiF, Al2O3, or organic salts. Their main function is to passivate uncoordinated Pb²⁺ on the perovskite surface. + Defects and halogen vacancies inhibit interfacial recombination; at the same time, they block water and oxygen permeation, improving the long-term stability of the device; they also serve as a buffer layer for the electron transport layer 13, improving the interfacial band arrangement and film continuity.

[0055] Typical materials for the electron transport layer (ETL) include SnO2 and TiO2. x ZnO or C 60 The thickness is approximately 10–50 nm. Its function is to efficiently extract photogenerated electrons from the perovskite and transport them to the transparent conductive electrode 14; at the same time, it blocks the reverse transport of holes, maintains carrier selectivity, and maintains high transmittance (especially in the near-infrared band), ensuring that unabsorbed light can penetrate to the crystalline silicon bottom cell.

[0056] The transparent conductive electrode 14 (TCE) is typically an ITO, IZO, or doped ZnO thin film prepared by magnetron sputtering or solution method, possessing both high electrical conductivity (>10³ S / cm) and high light transmittance (>85%). As the front electrode of the top cell, it collects electrons and provides a lateral conductive path; simultaneously, it allows long-wavelength light (e.g., 800–1200 nm) to be efficiently transmitted to the crystalline silicon bottom cell, enabling spectral separation; and it provides a flat, conductive deposition platform for the upper metal grid lines.

[0057] Metal grid lines (or auxiliary electrodes) are typically Ag, Cu, or Ag-Al alloy mesh structures formed by thermal evaporation or screen printing, patterned and distributed on the TCE surface. Their main function is to reduce lateral series resistance and improve the fill factor (FF); they also serve as lead-out electrodes for external circuits to achieve current harvesting.

[0058] The crystalline silicon substrate is preferably an n-type crystalline silicon substrate. The corresponding crystalline silicon substrate 1 can be an n-type monocrystalline silicon wafer with a thickness of 60–300 μm, preferably 80–180 μm. The resistivity of the crystalline silicon substrate 1 can be 0.3–28 Ω·cm, preferably 0.5–5 Ω·cm.

[0059] The surface of the first region 101 is a polished plane, i.e., it has a relatively low surface roughness (e.g., root mean square roughness RMS < 100 nm). The polished plane is conducive to the formation of a uniform, dense and pinhole-free ultrathin tunneling oxide layer 2 (e.g., 1–2 nm thick SiO2); the P-type doped polycrystalline silicon layer or P-type doped polycrystalline silicon oxide layer deposited on this tunneling oxide layer 2 can obtain better crystal quality and doping activation efficiency, thereby improving hole selective transport capability; Meanwhile, if the subsequent metal electrode 5 is screen printed using a burn-through paste, the smooth surface will significantly reduce the contact non-uniformity during the sintering process of the subsequent metal electrode 5, which will help achieve low and stable contact resistance and reduce composite hot spots caused by local high current density.

[0060] The surface of the second region 102 is a polished flat surface or a pyramid-shaped light-trapping structure. It can be flexibly configured according to the device's emphasis on optical performance.

[0061] Pyramid-shaped light-trapping structures can be formed by anisotropic etching of the silicon surface using KOH, NaOH, TMAH, or other alkaline texturing solutions. These structures can be random pyramids, or regular or quasi-regular pyramid structures.

[0062] Polished surfaces can be formed by laser processing, alkaline polishing, anisotropic weak etching, wet smoothing, or chemical mechanical smoothing. For example, a submicron-level alkaline polished surface refers to a surface in the second region 102 where the undulation height, roughness, or local morphological features are at the submicron scale, and its surface is smoother than the traditional random pyramid textured surface.

[0063] If a pyramid-shaped light-trapping structure (typically random or quasi-periodic pyramids with a size of 1–5 μm) is adopted, the multiple reflections and optical path extension of near-infrared light (800–1200 nm) in the crystalline silicon bottom cell can be effectively enhanced, significantly increasing the absorption probability of long-wavelength photons, thereby increasing the short-circuit current density (JSC) of the bottom cell. If a polished plane is used, the focus is more on simplifying the process and improving the dielectric passivation layer (such as Al2O3 / SiN). x The uniformity of the stacked layer coverage is beneficial to obtaining a lower surface recombination rate and a higher dielectric passivation quality, making it suitable for stacked cells with high requirements for electrical passivation.

[0064] Regardless of the morphology, the second region 102 does not have a P-type doped polysilicon layer or metal electrode 5, in order to avoid carrier recombination and parasitic absorption in unnecessary regions.

[0065] In the perovskite / crystalline silicon tandem solar cell disclosed in this invention, the area ratio of the first region 101 on the back side of the crystalline silicon substrate 1 is a key design parameter affecting the device's electrical performance, optical response, and fabrication feasibility. By reasonably controlling this ratio, multi-objective synergistic optimization can be achieved among carrier collection efficiency, surface recombination suppression, optical reflectivity, and metallization cost.

[0066] Specifically, the present invention defines the following preferred ranges: Optionally, the area of ​​the first region 101 can be 0.5–80%, providing a wide range of design freedom to adapt to different battery architectures or process routes. Preferably, the area ratio is controlled within 10-60%, which can effectively balance the hole extraction capability and the optical function of the non-contact area. More preferably, the area ratio is 30-40%, which has been verified as the operating window with the best overall performance. This range is the relatively optimal balance point for achieving high-efficiency stacked cells.

[0067] When the area ratio is small (e.g., <0.5%), most of the back surface remains as the second region 102 of uncovered p-type doped polysilicon. This facilitates the formation of a continuous pyramid-shaped light-trapping structure and the deposition of a high-reflectivity dielectric / metal reflective layer, thereby significantly improving the reception of long-wavelength light (900–1200 nm). However, the small contact area forces photogenerated holes to diffuse laterally over a longer distance within the silicon mass to reach the local p-type doped region. + The contact area introduces significant transmission resistance loss, which may lead to a significant decrease in the fill factor, especially under high injection conditions.

[0068] Conversely, when the area ratio is large (e.g., >80%), p-type doped polysilicon (p + While expanding the coverage area of ​​poly-Si can shorten the hole transport path and enhance hole collection capabilities, it also brings several adverse effects: First, p + Poly-Si is difficult to passivate with high quality on the back surface of n-type crystalline silicon (especially the textured surface), which increases the interfacial recombination rate and reduces the open circuit voltage (VOC). Secondly, p + Poly-Si itself has a high doping concentration, which causes parasitic absorption in the near-infrared band, weakening the effective light intensity transmitted to the bottom cell. Secondly, a larger area of ​​p +Poly-Si deposition and subsequent metallization processes increase material costs and thermal budgets, and may exacerbate thin film stress and process complexity. Meanwhile, the area of ​​the second region 102 is compressed, which limits the implementation space of the efficient back reflection structure and weakens the optical gain.

[0069] Therefore, the present invention preferably controls the area ratio of the first region 101 to 30-40%. Within this range, firstly, the lateral diffusion distance of holes is moderate, which can maintain low transmission loss and high fill factor. Secondly, sufficient area of ​​the second region 102 (60–70%) allows the pyramidal topography or high-reflectivity coating to be preserved, maximizing long-wavelength light capture efficiency. Again, p + Poly-Si has a limited coverage area, which effectively suppresses interfacial recombination and parasitic absorption while maintaining good passivation contact quality. Meanwhile, the metal electrode 5 layout can be matched with standard finger grid lines, taking into account conductivity, shading loss and silver consumption cost. Finally, the overall structure is highly compatible with existing TOPCon or laser-based film-forming processes, and has good feasibility for mass production.

[0070] In the perovskite / crystalline silicon tandem solar cell disclosed in this invention, the geometry and arrangement of the first region 101 (i.e., the functional region for forming p-type passivation contacts and connecting with the metal electrode 5) on the back side of the crystalline silicon substrate 1 are designed as a highly flexible and engineerable structure to take into account electrical performance, optical management and process compatibility.

[0071] The first region 101 can adopt various geometric configurations, including but not limited to point-like (circular, elliptical) and island-like (irregular or regular isolated regions, such as...) Figure 3 ), strip-shaped or linear (extending in a single direction, such as Figure 4 ), rectangle (such as Figure 5 ), circles, ovals (regular closed shapes), grids (such as...) Figure 6 ), honeycomb (periodic connected or semi-connected structure) or any combination of the aforementioned shapes.

[0072] Different shapes have their own physical advantages: point / island structures provide discrete contact points, maximize the area of ​​non-contact regions, which is beneficial for high back-side reflection and light trapping, and is suitable for high VOC guiding designs; strip / line structures are easy to align with finger-shaped metal grid lines, reduce lateral resistance, and improve carrier collection efficiency, which is suitable for high FF requirements; grid / honeycomb structures, while maintaining a good electrical conductivity network, form regular optical microcavities or diffraction structures, which can further control the propagation path of long-wavelength light and achieve enhanced light management.

[0073] The arrangement strategy of multiple first regions 101 can be customized and optimized based on the minority carrier diffusion length of the bottom cell, the layout of the metal electrode 5, and the results of optical simulation.

[0074] For example, periodic arrangement along one direction (one-dimensional array): such as parallel strips, which facilitates alignment with screen-printed metal grid lines and simplifies the alignment process; For example, forming a two-dimensional array along two directions: such as a square, hexagonal, or randomly distributed lattice, can achieve isotropic carrier collection and a more uniform current distribution.

[0075] Between adjacent first regions 101, the second region 102 forms a continuous or discontinuous network of grooves.

[0076] Continuous groove network: When the first region 101 is discretely distributed (such as a lattice or island), the second region 102 is interconnected to form a continuous recessed channel, which is beneficial for preserving the pyramid textured surface over a large area and achieving efficient back reflection. Discontinuous groove network: When the first region 101 is strip-shaped or grid-shaped, the second region 102 may present segmented recesses, but optical gain can still be maintained through local light-trapping structures; The depth, width, and connectivity of the groove network can be synergistically controlled to balance optical trapping, passivation coverage quality, and metal paste flow behavior.

[0077] Furthermore, the height difference between the second region 102 and the first region 101 of the groove network together constitutes a three-dimensional topological isolation structure, which effectively suppresses lateral diffusion during the metal sintering process, avoids electrode bridging or accidental contact with non-contact areas, and improves device yield and reliability.

[0078] The tunneling oxide layer 2 can be SiO x SiO2, SiON, AlO x TiO x Or a combination thereof. Preferably, the tunneling oxide layer 2 is SiO2. x Alternatively, it may be SiO2 with a thickness of 0.5–3.0 nm, more preferably 0.8–2.0 nm. The tunneling oxide layer 2 serves to chemically passivate the crystalline silicon surface while allowing holes to enter the p-type doped polycrystalline silicon layer through tunneling or defect-assisted tunneling mechanisms.

[0079] The p-type doped polycrystalline silicon layer can be a boron-doped polycrystalline silicon layer, a boron-doped microcrystalline silicon layer, a boron-doped nanocrystalline silicon layer, or an oxygen-containing polycrystalline silicon layer. The p-type doped polycrystalline silicon oxide layer can be a p-type poly-SiO₂ layer. x p-type poly-SiC x p-type poly-SiO x C y Or a combination thereof.

[0080] The thickness of the p-type doped polysilicon layer or p-type doped polysilicon oxide layer can be 5–500 nm, preferably 20–250 nm, and more preferably 30–150 nm. Its doping concentration can be 1 × 10¹. 8 –5×10²¹cm - ³, preferably 1×10¹ 9 –1×10²¹cm - ³.

[0081] It should be noted that in the perovskite / crystalline silicon tandem solar cell structure proposed in this invention, the recess depth (i.e., height difference) of the second region 102 relative to the first region 101 is a key process parameter, directly affecting the electrical performance, optical response, and manufacturing feasibility of the device. Therefore, this invention systematically optimizes the recess depth of the second region 102 and sets multiple preferred ranges: Optionally, the second region 102 has a recess depth of 0.05-50 μm relative to the first region 101, covering a wide range of process windows from micro-nano scale to deeper trenches; Preferably, the recess depth is 0.1-20μm; to balance basic spatial isolation with conventional photovoltaic process capabilities; More preferably, the recess depth is 0.5-10μm; within this range, functional zoning and optical enhancement can be effectively achieved.

[0082] More preferably, the indentation depth is 0.5-2μm; this achieves an optimal balance among multiple performance indicators.

[0083] In this way, if the depression is too shallow (<0.5μm), it is difficult to form a clear three-dimensional step structure, resulting in insufficient spatial isolation between the first region 101 (contact area) and the second region 102 (non-contact / optical area); Furthermore, during the sintering process of metal electrode 5, the slurry is prone to lateral diffusion to unintended areas, increasing the risk of accidental contact or local short circuit. At the same time, shallow grooves have limited ability to control surface morphology, making it difficult to effectively retain or construct light-trapping structures such as pyramids, thus weakening the ability to manage near-infrared light on the back side. Furthermore, from an industrialization perspective, precise local etching below 0.5μm places high precision requirements on existing photovoltaic production lines (such as wet etching, laser film opening, etc.), resulting in narrow process windows, low yields, and poor economic efficiency.

[0084] If the recess is too deep (>10μm, especially >20μm), it will significantly increase the difficulty and time cost of the etching process, and may introduce sidewall damage, lattice defects or stress concentration, inducing additional edge recombination. Meanwhile, deep trench structures are prone to uneven coverage, voids or step fractures during subsequent thin film deposition (such as dielectric passivation layers and reflective layers), affecting passivation quality and reflective performance. Furthermore, excessive height differences may interfere with the flatness of metal grid line printing, and may even lead to electrode breakage or poor contact. More importantly, excessive removal of silicon material weakens the bottom cell's ability to absorb long-wavelength light, which in turn reduces short-circuit current and overall power generation efficiency.

[0085] Therefore, the present invention further preferably uses a recess depth of 0.5–2 μm, which is sufficient to form a clear physical boundary, effectively isolate the metal contact area from the optical reflection area, and suppress the diffusion of the slurry; At the same time, it is compatible with existing laser grooving, wet anisotropic etching or dry etching processes for crystalline silicon cells, and has good mass production feasibility. Moreover, the original pyramidal textured surface (typical height 1–3 μm) can be fully preserved in the second region 102, or it can be locally flattened on top of it, thereby maximizing the backlight trapping effect; In addition, this depth range has little impact on the mechanical strength of silicon wafers and will not significantly increase the breakage rate or warping risk; Combined with dielectric passivation layers (such as Al2O3 / SiN) x High-reflectivity backsheets (such as Ag, TiO2 / SiO2DBR) and high-reflectivity backsheets can achieve synergistic optimization among low recombination, high reflectivity, and low parasitic absorption.

[0086] The dielectric passivation layer and the back reflective layer may include aluminum oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, magnesium fluoride, transparent conductive oxide, or combinations thereof.

[0087] Preferably, the dielectric stack 4 can be Al2O3 / SiN. x Al2O3 / SiN x / SiO x SiO x / SiN x Al2O3 / SiO x / SiN x Al2O3 / SiN x / MgF2 or Al2O3 / SiO x / MgF2.

[0088] Among them, Al2O3 can provide strong field-effect passivation and chemical passivation; SiN x It can provide hydrogen passivation, protection, and optical modulation; SiO xIt can be used as a low refractive index adjustment layer, a protective layer, or a reflection enhancement layer; MgF2 can be used as a low refractive index layer to improve back-side optical reflection. Transparent conductive oxides can be used as conductive auxiliary layers or optical adjustment layers in some embodiments.

[0089] The total thickness of the dielectric stack 4 can be 5–500 nm, preferably 20–300 nm. For the Al2O3 layer, its thickness can be 1–30 nm; for SiN… x The layer can be 30–200 nm thick; for SiO x The layer can be 10–300 nm thick. The actual thickness can be designed based on the back reflection of the target wavelength, the passivation quality of the dielectric, and process compatibility.

[0090] Since the metal electrode 5 is only electrically connected to the p-type doped layer 3, the metal electrode 5 only covers the first region 101 and does not cover the second region 102. It does not continuously cover the first region 101 and the second region 102, which can significantly reduce the actual contact area between the metal electrode 5 and the p-type doped layer, reduce metal-induced recombination, and at the same time ensure that the charge carriers can be effectively extracted through the metal electrode 5.

[0091] The metal electrode 5 is in the form of a point electrode, a strip electrode, an island electrode, a mesh electrode, or a combination thereof. The material of the metal electrode 5 includes one or more of the following: silver, aluminum, copper, nickel, titanium, palladium, tin, indium, silver-aluminum alloy, nickel-copper multilayer, titanium-palladium-silver multilayer, nickel-copper-silver multilayer, and titanium-nickel-copper multilayer.

[0092] The metal electrode 5 includes a contact metal layer and a conductive reinforcement layer. The contact metal layer is in direct contact with the p-type doped polysilicon layer or the p-type doped polysilicon oxide layer to reduce contact resistance; the conductive reinforcement layer is disposed above the contact metal layer to reduce the lateral resistance of the metal electrode 5. For example, a Ni / Cu / Ag, Ti / Pd / Ag, Ti / Ni / Cu / Ag, Al / Ag, or Ni / Ag stacked structure can be used.

[0093] The portion of the metal electrode 5 extending out of the dielectric stack 4 may contain local metal points, local metal lines, metal grids, bus electrodes, conductive adhesive, solder ribbons, or conductive interconnect layers, but these metal structures will not form a fully contact metal electrode 5 and conductive interconnect 19 on the entire back side.

[0094] In other words, two adjacent metal electrodes 5 are electrically connected by conductive interconnects 19 to form a complete back-side conductive network. A gap is left between adjacent conductive interconnects 19, meaning the interconnect structure itself is localized and discontinuously arranged to avoid forming a full-surface metal film. The conductive interconnects 19 include a metal grid, bus electrodes, conductive adhesive, solder ribbon, or conductive interconnect layer; enabling the interconnection of the back-side metal electrodes 5 and current collection.

[0095] For example, multiple metal electrodes 5 are respectively disposed above multiple island-shaped first regions 101, that is, each island-shaped first region 101 has one metal electrode 5; adjacent metal electrodes 5 are connected by thin metal wires. The thin metal wires may cross the second region 102, but are preferably disposed above the dielectric passivation layer or back reflective layer of the second region 102, without penetrating the dielectric layer to form direct electrical contact with the crystalline silicon substrate 1 of the second region 102. This ensures that the second region 102 still maintains its non-contact passivation / reflection function.

[0096] For example, the metal electrode 5 is first connected to one or more back bus electrodes, and then connected to the solder ribbon, conductive adhesive, or component interconnection structure through the bus electrodes. The bus electrodes can be located in the edge area of ​​the battery or in a local area on the back.

[0097] For example, the metal electrode 5 is connected to a low-temperature conductive adhesive, a patterned metal foil, a flexible conductive interconnect film, or a conductive tape to meet the requirements of perovskite / crystalline silicon tandem cells for low-temperature packaging and low thermal budget processes.

[0098] Therefore, the present invention allows for the existence of a back-side interconnect structure (i.e., multiple conductive interconnects 19), but requires that the interconnect structure does not form a continuous, fully contact metal layer across the entire back side, nor does it form an effective ohmic contact with the crystalline silicon substrate 1 in the recessed second region 102. While ensuring efficient current conduction, the metal coverage area is strictly limited to avoid the optical and electrical drawbacks caused by fully contact electrodes.

[0099] In order to enable the metal electrode 5 to pass through the dielectric stack 4, a plurality of spaced contact openings are provided on the dielectric stack 4 in the region corresponding to the first region 101; each contact opening is precisely aligned with a first region 101, exposing the underlying P-type doped layer 3. Each metal electrode 5 passes through a contact opening and is electrically connected to the P-type doped layer 3, thereby achieving efficient collection and extraction of holes; The contact openings are spaced apart from each other, and their position, size and number match the layout of the first region 101 and the metal electrode 5 to avoid the failure of the dielectric layer structure or the degradation of optical performance caused by overlapping or excessive density of openings.

[0100] Of course, during the process of forming the metal electrode 5 using screen printing, a burn-through paste can be printed first to burn through the dielectric stack 4 and then electrically connected with the P-type doped layer 3 to form the metal electrode 5. Then, a non-burn-through paste can be printed to form a conductive interconnect 19 to achieve current collection.

[0101] Optionally, the area of ​​all metal electrodes 5 on the back side of the crystalline silicon substrate 1 is 0.05-20%; Preferably, the area ratio is 0.1-10%.

[0102] The aforementioned range of the area ratio of the metal electrode 5 is determined by the synergistic optimization of multiple factors, including the device's electrical performance, optical response, and manufacturing cost. As a key channel for carrier output, the coverage area of ​​the metal electrode 5 directly affects the contact resistance, current collection efficiency, and back-side optical management capabilities.

[0103] When the area of ​​the metal electrode 5 is too low (e.g., close to 0.05%), although it helps to maximize the preservation of the high-reflectivity, low-absorption non-metallic region, thereby improving the utilization efficiency of long-wavelength light, the number or size of local contact points may be insufficient to support efficient carrier extraction. In this case, photogenerated holes need to travel a long lateral transport path to reach the metal contact area, which can easily lead to local current congestion, resulting in potential concentration and increased Joule heating in the contact area. Furthermore, insufficient contact interface may cause contact resistance fluctuations or decreased stability, ultimately manifesting as a reduced fill factor and limited output current.

[0104] Conversely, if the area of ​​the metal electrode 5 is too large (e.g., exceeding 10%, especially close to 20%), although it can provide ample conductive paths and reduce series resistance, large-area metal coverage will introduce significant parasitic light absorption, especially weakening the back reflection effect in the near-infrared band and reducing the short-circuit current density of the crystalline silicon bottom cell. At the same time, the amount of precious metals (such as silver) increases significantly, directly driving up material costs, and the thick metal layer may exacerbate thermal stress and warpage risk, affecting the mechanical reliability and yield of the stacked device.

[0105] Therefore, controlling the total area of ​​the metal electrode 5 within the preferred range of 0.1–10% achieves an effective balance in the following aspects: First, provide contact areas of sufficient density and size to ensure that holes are collected and discharged efficiently and stably, and suppress local current congestion; Secondly, the metal coverage area is limited, while a large area of ​​high-reflectivity passivation area is retained to maintain excellent back-side optical light trapping capability; Finally, while meeting electrical performance requirements, we should rationally control slurry consumption and process complexity to improve economic feasibility.

[0106] An example of the carrier transport process in the perovskite / crystalline silicon tandem solar cell of the present invention is as follows: Under sunlight, short-wavelength light is mainly absorbed by the perovskite top cell, while long-wavelength light passes through the perovskite top cell and enters the crystalline silicon bottom cell. The crystalline silicon bottom cell absorbs the long-wavelength light and generates electron-hole pairs.

[0107] For n-type crystalline silicon bottom cells, electrons are collected through the electron-selective passivation contact layer on the front side of the crystalline silicon substrate 1 and enter the recombination junction, where they recombine with holes transmitted from the perovskite top cell, thereby enabling the series operation of the two-terminal stacked cells.

[0108] Holes generated in the crystalline silicon bottom cell diffuse as minority carriers to the back side. Since the second region 102 on the back side does not form a direct metal electrode 5 contact, the holes are not consumed by metal-induced recombination in the second region 102, but diffuse laterally to the adjacent first region 101. After reaching the first region 101, the holes tunnel through the oxide layer 2 into the p-type doped polycrystalline silicon layer or the p-type doped polycrystalline silicon oxide layer, and then enter the metal electrode 5 through the contact opening, and finally exit through the metal grid, bus electrode, conductive adhesive or solder strip.

[0109] Therefore, the carrier transport path on the back side of this solar cell is as follows: Holes in crystalline silicon substrate 1 → tunneling oxide layer 2 below first region 101 → p-type doped polycrystalline silicon layer or p-type doped polycrystalline silicon oxide layer → metal electrode 5 → back conductive interconnect 19.

[0110] Compared to a fully back-metal contact structure, this invention avoids recombination between the metal electrode 5 and the crystalline silicon substrate 1 across the entire back side. Compared to a structure with only a localized p-type doped layer while the conductive interconnect 19 still fully covers the entire back side, this invention further localizes the metal contact area and the conductive interconnect 19, thereby reducing metal recombination, metal consumption, and mechanical stress.

[0111] An example of the optical management process for the perovskite / crystalline silicon tandem solar cell of the present invention is as follows: In perovskite / crystalline silicon tandem solar cells, the crystalline silicon bottom cell primarily absorbs long-wavelength light transmitted through the perovskite top cell. Therefore, optical management on the back side of the crystalline silicon bottom cell has a significant impact on the current matching and efficiency of the tandem solar cell.

[0112] The second region 102 has a groove structure, and its surface can be a polished plane or a pyramid-shaped light-trapping structure. When the second region 102 is a polished plane, its surface has low roughness, which is beneficial for forming a high-quality passivation interface in the dielectric layer, while achieving high back reflection through the dielectric reflective layer. When the second region 102 adopts a pyramid-shaped light-trapping structure, long-wavelength light incident on the back can be scattered or have its propagation direction changed, thereby increasing the optical path in the crystalline silicon substrate 1 and improving long-wavelength absorption.

[0113] Meanwhile, since the metal electrode 5 is only disposed above the first region 101, the second region 102 is not completely covered by continuous metal. Therefore, the dielectric reflective layer of the second region 102 can fully utilize the back reflection effect, avoiding parasitic absorption, optical boundary deterioration, or reflection loss caused by complete metal coverage.

[0114] In other words, the back-side optical function is separated from the metal contact function by the recessed second region 102, so that the second region 102 is mainly responsible for optical reflection and passivation, while the first region 101 is mainly responsible for hole collection and current extraction. This achieves a decoupling design between the back-side electrical and optical functions.

[0115] refer to Figure 7 The present invention also discloses a method for preparing a perovskite / crystalline silicon tandem solar cell, which can prepare the above-mentioned perovskite / crystalline silicon tandem solar cell. The preparation method includes the following steps: S100 provides a crystalline silicon substrate 1; S300, a first region 101 is defined on the back side of the crystalline silicon substrate 1; S400, a tunneling oxide layer 2 is formed in the first region 101 and a P-type doped layer 3 is formed on the tunneling oxide layer 2, wherein the P-type doped layer 3 is a P-type doped polysilicon layer or a P-type doped polysilicon oxide layer. S500, a second region 102 is formed on the back surface in a region other than the first region 101, wherein the second region 102 is recessed relative to the first region 101; S600, a dielectric stack 4 is formed on the p-type doped layer 3 and the second region 102, wherein the dielectric stack 4 includes a dielectric passivation layer and a back reflective layer (e.g., Figure 9 ); S700, forming multiple metal electrodes 5 that penetrate the dielectric stack 4 and are electrically connected to the P-type doped layer 3; wherein, a gap is left between any two adjacent metal electrodes 5 (e.g., Figure 3 and Figure 10 ).

[0116] The method for fabricating perovskite / crystalline silicon tandem solar cells disclosed in this invention achieves synergistic optimization of electrical contact, surface passivation, and optical management by constructing a composite structure with regionally differentiated morphology and functional integration on the back side of a crystalline silicon substrate 1. This method is not only applicable to the fabrication of high-efficiency two-terminal (2T) tandem devices, but also ensures process compatibility with existing crystalline silicon photovoltaic production lines.

[0117] Specifically: First, by dividing the back side of the crystalline silicon substrate 1 into regions, the first region 101 for electrical contact is clearly defined, laying the structural foundation for the localized integration of subsequent functional layers.

[0118] Secondly, a tunneling oxide layer 2 and a p-type doped layer 3 are sequentially constructed on the first region 101 (see reference). Figure 8This structure forms a high-quality hole-selective passivation contact. While effectively passivating dangling bonds on the silicon surface and reducing the interfacial recombination rate, it allows holes to efficiently transport to the metal electrode 5 via tunneling or defect-assisted mechanisms, thereby supporting a high open-circuit voltage and fill factor. Since this contact structure exists only locally in the first region 101, it avoids recombination losses and optical degradation caused by large-area coverage of p-type polycrystalline silicon on the entire back side (especially the textured surface).

[0119] Subsequently, a second region 102 is formed that is recessed relative to the first region 101 (see reference). Figure 2 and Figure 8 The height difference enables physical isolation, providing spatial constraints for the subsequent local deposition of the metal electrode 5, which helps to suppress lateral diffusion of the slurry and improve contact accuracy and process tolerance.

[0120] Next, a dielectric stack 4 (reference) is deposited over the entire back side (including the P-type doped layer 3 and the recessed second region 102). Figure 9 The dielectric stack 4 may include a dielectric passivation layer (such as Al2O3 and SiO2). x To further suppress surface recombination, and high-reflectivity back reflective layers (such as SiN) are used. x and SiN x O y (and distributed Bragg reflectors) to enhance the reuse of long-wavelength photons. Thanks to the recessed design of the second region 102, the dielectric stack 4 can fully utilize its passivation and optical functions.

[0121] Finally, metal electrodes 5, separated from each other, are fabricated, passing through the dielectric stack 4 and establishing an electrical connection with the p-type doped layer 3. Adjacent metal electrodes 5 are kept spaced apart (see reference). Figure 10 This design satisfies the required conductive network density for current collection while avoiding parasitic absorption caused by continuous metal coverage.

[0122] In detail, in step S100 of providing the crystalline silicon substrate 1: The crystalline silicon substrate 1 is preferably an n-type monocrystalline silicon wafer. The crystalline silicon substrate 1 is cleaned, de-damaged, de-contaminated with organic and metallic substances, and pre-treated. Cleaning methods may include RCA cleaning, ozone cleaning, HF oxide layer removal, alkaline polishing, acid polishing, or a combination thereof.

[0123] The front side of the crystalline silicon substrate 1 can be planarized to facilitate the subsequent formation of a high-quality hole-selective passivation contact layer and a transparent conductive composite junction. The back side of the crystalline silicon substrate 1 is reserved with patterned areas for forming the first region 101 and the recessed second region 102.

[0124] Between step S100 and step S300, the preparation method further includes: Step S200: An electron-selective passivation contact layer is formed on the front side of the crystalline silicon substrate 1; Specifically, a tunneling oxide layer is formed on the front side of the crystalline silicon substrate 1. This tunneling oxide layer can be formed by thermal oxidation, wet chemical oxidation, ozone oxidation, nitric acid oxidation, PECVD, ALD, or a combination thereof.

[0125] Subsequently, an n-type doped polycrystalline silicon layer or an n-type doped polycrystalline silicon oxide layer is formed on the tunneling oxide layer. This layer can be formed by LPCVD, PECVD, PVD, sputtering, hot-wire CVD, or other thin film deposition methods. n-type doping can be achieved through in-situ doping, POCl3 diffusion, ion implantation, phosphate paste diffusion, or phosphosilicate glass diffusion.

[0126] Annealing is then performed to activate the doping and improve the passivation contact quality. The annealing temperature can be 700–1000℃, preferably 800–950℃.

[0127] Step S400, which involves forming the tunneling oxide layer 2 in the first region 101 and forming the p-type doped layer 3 on the tunneling oxide layer 2, includes: First, a tunneling oxide layer 2 is formed on the entire back side of the crystalline silicon substrate 1, and a P-type doped layer 3 is formed on the tunneling oxide layer 2. Then, the P-type doped layer 3 on the back side, except for the first region 101, is removed by patterned etching. or, First, a patterned mask is formed on the back side of the crystalline silicon substrate 1 in the area other than the first region 101. Then, a tunneling oxide layer 2 is formed in the first region 101 and a P-type doped layer 3 is formed on the tunneling oxide layer 2. Finally, the mask is removed. or, First, an intrinsic polycrystalline silicon layer or a polycrystalline silicon oxide layer is formed in the first region 101, and then local boron diffusion, local ion implantation, local laser doping, or local boron paste diffusion are performed.

[0128] Through this step S400, a tunneling oxide layer 2 and a P-type doped layer 3 can be formed on the first region 101.

[0129] refer to Figure 11 Step S500, which involves forming a second region 102 on the back surface in a region other than the first region 101, includes: S510, etching is performed on the area on the back side other than the first region 101 to form the second region 102; The etching methods include one or more of the following: alkaline etching, acid etching, laser etching, plasma etching, reactive ion etching, and metal-assisted chemical etching.

[0130] S520, performs alkaline polishing or alkaline anisotropic etching on the second region 102.

[0131] In other words, after the concave second region 102 is formed, two different surface treatments can be applied to the groove surface.

[0132] One method is to form a submicron-level alkaline polished surface. This process can remove the damaged layer and micro-rough structure on the surface of the groove through alkaline polishing or weak etching, so that the surface of the second region 102 forms a smoother submicron-level polished morphology.

[0133] Another method is to form a pyramid-shaped light-trapping structure. This process involves anisotropically etching the second region 102 using alkaline texturing solutions such as KOH, NaOH, and TMAH, to create a random or regular pyramid-shaped light-trapping structure on the surface of the second region 102, thereby enhancing the multiple reflection and absorption paths of near-infrared light in the bottom cell.

[0134] Through this step S500, a three-dimensional spatial structure in which the first region 101 and the second region 102 coexist can be formed on the back side of the crystalline silicon substrate 1.

[0135] It should be noted that since the tunneling oxide layer 2 and the P-type doped layer 3 have been covered on the first region 101 before the second region 102 is formed, the P-type doped layer 3 can be used as a protective layer alone or a mask can be covered on the P-type doped layer 3 as a protective layer. Then, the region outside the first region 101 is etched to form the recessed second region 102 (if the P-type doped layer 3 was previously covered with a mask, the mask is removed).

[0136] In step S600, when forming the dielectric stack 4 on the p-type doped layer 3 and the second region 102: After forming the first region 101 and the second region 102, a dielectric passivation layer and a back reflective layer are deposited on the back side of the crystalline silicon substrate 1. The dielectric stack 4 covers the first region 101 and the second region 102.

[0137] The dielectric stack 4 can be formed by ALD, PECVD, PVD, thermal oxidation, wet chemical oxidation, evaporation, sputtering, or a combination thereof. Preferably, an Al2O3 layer is deposited first, followed by the deposition of SiN. X SiO X Alternatively, a MgF2 layer can be used to balance surface passivation and backside reflection.

[0138] After this step is completed, the p-type doped layer in the first region 101 is covered by the dielectric stack 4, and the groove surface in the second region 102 is also covered by the dielectric stack 4. At this point, the entire back surface is in a good passivation and reflection state, but metal contact has not yet been formed.

[0139] refer to Figure 12Step S700, which forms a plurality of metal electrodes 5 that pass through the dielectric stack 4 and are electrically connected to the p-type doped layer 3, includes: S710, a plurality of mutually spaced contact openings are formed on the dielectric stack 4 in the region corresponding to the first region 101; In detail, on the surface of the deposited dielectric stack 4, multiple localized, spaced-apart contact openings are formed at the defined first region 101 using micro-nano fabrication techniques. These contact openings penetrate the dielectric stack 4, exposing the underlying P-type doped layer 3, providing an electrical access channel for the subsequent metal electrode 5.

[0140] The method of forming the contact openings is not limited. For example, multiple contact openings can be formed on the dielectric stack 4 by laser opening, photolithography, wet etching, plasma etching, inkjet etching paste or screen printing etching paste. The contact opening is located only above the first region 101, ensuring that the metal only contacts the highly doped p-type layer, avoiding the increase in recombination caused by direct contact with the crystalline silicon substrate 1 or the second region 102; Multiple openings are distributed at intervals, and their density and arrangement match the geometry (dot, strip, grid, etc.) of the first region 101, which ensures both carrier collection efficiency and avoids excessive opening density from damaging the continuity of the dielectric layer. S720, a metal electrode 5 is formed at each contact opening.

[0141] In detail, a metal electrode 5 is formed at each contact opening through screen printing, inkjet printing, dispensing, local evaporation, local sputtering, laser transfer, electroplating, chemical plating, or mask deposition. Each metal electrode 5 passes through the corresponding contact opening and establishes an ohmic or low-resistance electrical connection with the underlying P-type doped layer 3.

[0142] Furthermore, step S720, which involves forming a metal electrode 5 at each contact opening, includes, but is not limited to, the following methods: For example, a contact seed layer that is electrically in contact with the P-type doped layer 3 is first formed at the contact opening, then a conductive enhancement layer is formed on the contact seed layer, and finally a protective layer is formed on the conductive enhancement layer. The contact seed layer material can be selected from Ti, Ni, Pd, Cr, TiW, TiN or thin Ag, etc., with a thickness of 5–50 nm. It is mainly used to provide good interfacial adhesion, prevent subsequent metal layer peeling, and inhibit the diffusion of metal atoms (such as Cu, Al) into the silicon mass, thereby reducing the formation of recombination centers.

[0143] A conductive reinforcement layer is formed by electroplating on the seed contact layer to carry the main current transmission task. The conductive reinforcement layer material can be a highly conductive metal, such as Cu, Ag, Al, or their alloys.

[0144] A protective layer is applied to the surface of the conductive reinforcement layer to improve oxidation resistance, sulfidation resistance, and solderability, ensuring the electrical stability of the device during component packaging and long-term outdoor operation. Protective layer materials include Sn, Ni, Ag, Au, or organic passivation films. This multi-layer structure achieves synergistic optimization of "low resistance contact - high conductivity - high reliability", which is suitable for the stringent requirements of high-efficiency tandem cells for long-term stability and low loss.

[0145] For example, silver paste, silver-aluminum paste, aluminum paste, or conductive adhesive can be printed at the contact opening and then cured.

[0146] In other words, conductive paste is directly printed at the contact opening, and then metal electrode 5 is formed by low-temperature curing (e.g., <250°C).

[0147] Conductive pastes can be made of silver paste, silver-aluminum paste, aluminum paste, conductive adhesive, etc.

[0148] This solution is a mature technology that is compatible with existing photovoltaic production lines, and is especially suitable for use in the independent fabrication stage of crystalline silicon bottom cells. By controlling the paste composition and printing precision, the metal coverage can be controlled within the required range while ensuring contact performance.

[0149] Of course, after the metal electrode 5 is formed, the metal electrode 5 does not form a continuous, fully contacting metal layer on the back side of the entire crystalline silicon substrate 1. Multiple metal electrodes 5 can be connected by conductive interconnects 19 such as metal grids, bus electrodes, solder ribbons, conductive adhesives, or conductive interconnect layers.

[0150] Optionally, in another embodiment, step S700 of forming a plurality of metal electrodes 5 that pass through the dielectric stack 4 and are electrically connected to the p-type doped layer 3 includes: Metal electrodes 5 are formed by using a burn-through paste and a screen printing process. Then, conductive interconnects 19 are printed using a non-burn-through paste to form a bus. In other words, by using screen printing metallization process, a burn-through paste can be used to form electrical contact in the first area, and then a non-burn-through paste can be printed to form a flow.

[0151] Specifically, a burn-through conductive paste (such as silver paste containing glass powder) is first printed at position 101 in the first region. During subsequent heat treatment (such as co-sintering), the paste can penetrate the dielectric stack 4 covering it in situ, directly contact the P-type doped layer 3 and form a low-resistance electrical connection. Subsequently, non-burn-through conductive paste (such as low-temperature silver paste, glass powder-free high-conductivity paste, etc.) is printed on the formed burn-through contact points or their extended areas to construct metal grids, bus electrodes, or interconnect structures, thereby achieving effective current collection and extraction.

[0152] In this embodiment, it is not necessary to pre-form contact openings on the dielectric stack 4 using laser or etching processes. During the sintering process, the burn-through slurry relies on its internal active components (such as low-melting-point glass phases like Bi2O3, PbO, and ZnO-B2O3) to locally melt and etch the dielectric layer, thus completing the integrated process of opening and metal filling in a self-aligned manner.

[0153] Optional, continue to refer to Figure 7 After step S700, the preparation method further includes: S800, a composite junction and perovskite top cell are formed on the electron-selective passivation contact layer; In detail, a transparent conductive oxide layer 8 is formed above the electron-selective passivation contact layer on the front side of the crystalline silicon bottom cell to form a composite junction between the perovskite top cell and the crystalline silicon bottom cell. The transparent conductive oxide layer 8 can be ITO, IZO, AZO, IWO, IO:H, ICO, or a combination thereof.

[0154] Subsequently, a hole transport layer 9, a perovskite absorption layer 11, an electron transport layer 13, a transparent conductive electrode 14, and metal grid lines (or auxiliary electrodes) are sequentially formed on top of the transparent conductive oxide layer 8 to complete the fabrication of the perovskite top cell.

[0155] In summary, this invention, by setting multiple first regions 101 and recessed second regions 102 located between adjacent first regions 101 on the back side of a crystalline silicon substrate, enables the first regions 101 to perform localized hole-selective passivation contact and localized metal extraction functions, and enables the second regions 102 to perform back-side passivation, reflection, and optical management functions. The first regions 101 contain a p-type doped polycrystalline silicon layer or a p-type doped polycrystalline silicon oxide layer, and are in contact with the crystalline silicon substrate 1 through a tunneling oxide layer 2. The second regions 102 form a groove structure within the silicon substrate itself, with a surface morphology of a submicron-level alkaline-polished plane or a pyramid-shaped light-trapping structure. Both the first regions 101 and the second regions 102 are provided with a dielectric passivation layer and a back-side reflective layer, with a contact opening formed only above the first regions 101, and a metal electrode 5 formed at the contact opening.

[0156] Thus, the metal electrode 5 can form an electrical connection with the p-type doped polycrystalline silicon layer or the p-type doped polycrystalline silicon oxide layer without forming a continuous, fully contacting metal layer across the entire back side. This structure achieves a synergistic design of localized hole collection, back-side groove optical management, dielectric passivation reflection, and localized metallization, thereby reducing back-side recombination, reducing metal usage, reducing mechanical stress, improving long-wavelength optical response, and enhancing the compatibility of perovskite / crystalline silicon tandem solar cells for large-area mass production.

[0157] The technical effects of the embodiments of the present invention will be described below with reference to examples, comparative examples, and comparative examples. However, those skilled in the art will understand that the following examples, comparative examples, and comparative examples are only used to illustrate the present invention and should not be regarded as limiting the scope of the present invention.

[0158] Example 1 Multiple island-shaped first regions 101 are formed on the back side of the crystalline silicon substrate 1, and SiO is disposed in each island region. X The tunneling oxide layer 2 and the p-type doped polycrystalline silicon layer are formed. A recessed second region 102 is formed between adjacent island-shaped first regions 101. The surface of the second region 102 is texturized with alkaline solution to form a pyramid-shaped light-trapping structure.

[0159] Subsequently, Al2O3 / SiN was integrally deposited on the first region 101 and the second region 102. x / SiO x Dielectric stack 4. A small contact opening is then formed above each island-shaped first region 101 using a laser, and a dot-shaped metal electrode 5 is formed at the contact opening. Multiple dot-shaped metal electrodes 5 are connected by a thin metal wire or conductive interconnect layer on the back side.

[0160] This structure is suitable for emphasizing long-wavelength light trapping and back-side reflection, and is especially suitable for tandem cells with low current in crystalline silicon bottom cells that require improved infrared response.

[0161] The first region 101 occupies 30% of the area on the back side of the crystalline silicon substrate 1, and the height difference between the first region 101 and the second region 102 is 3.5 μm; the metal electrode 5 occupies 5% of the area on the back side of the crystalline silicon substrate 1.

[0162] Example 2 Multiple parallel strip-shaped first regions 101 are formed on the back side of the crystalline silicon substrate 1, and p-type doped poly-SiO2 is disposed in each strip-shaped region. x / SiO x Passivated contact. Between adjacent strip-shaped regions is a recessed second region 102, which is polished with alkaline solution to form a submicron-level smooth surface.

[0163] Al2O3 / SiN deposited on the entire back side x After the dielectric stack 4 is completed, linear or spaced-point contact openings are formed above the strip-shaped first region 101. Then, strip-shaped metal electrodes 5 are formed at the contact openings and connected to the back bus electrode.

[0164] This structure is suitable for applications emphasizing low-composite and mass-production patterned metallization, and is compatible with screen printing, electroplating, and laser-aperture processes.

[0165] The first region 101 occupies 30% of the area on the back side of the crystalline silicon substrate 1, and the height difference between the first region 101 and the second region 102 is 3.5 μm; the metal electrode 5 occupies 5% of the area on the back side of the crystalline silicon substrate 1.

[0166] Example 3 A grid-like first region 101 is formed on the back side of the crystalline silicon substrate 1, and p-type doped poly-Si or p-type doped poly-SiO is disposed in the grid line regions. x The mesh opening area is a recessed second region 102, and the surface of the second region 102 is a submicron-level alkaline polished plane or a pyramid-shaped light-trapping structure.

[0167] Metal electrodes 5 are positioned above grid intersections, grid segments, or portions of the grid area and are electrically connected to the p-type poly layer via contact openings. This structure shortens the lateral diffusion distance of holes and the metal current collection path, making it suitable for large-area stacked solar cells.

[0168] The first region 101 occupies 30% of the area on the back side of the crystalline silicon substrate 1, and the height difference between the first region 101 and the second region 102 is 3.5 μm; the metal electrode 5 occupies 5% of the area on the back side of the crystalline silicon substrate 1.

[0169] Example 4 Unlike Example 1, in this example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 40%.

[0170] Example 5 Unlike Example 1, in this example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 80%.

[0171] Example 6 Unlike Example 1, in this example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 10%.

[0172] Example 7 Unlike Example 1, in this example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 0.5%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 is 0.05%, and the height difference between the first region 101 and the second region 102 is 0.5 μm.

[0173] Example 8 Unlike Example 1, in this example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 accounts for 80%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 accounts for 20%, and the height difference between the first region 101 and the second region 102 is 50 μm.

[0174] Example 9 Unlike Example 1, in this example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 10%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 is 0.1%, and the height difference between the first region 101 and the second region 102 is 0.1 μm.

[0175] Example 10 Unlike Example 1, in this example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 60%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 is 10%, and the height difference between the first region 101 and the second region 102 is 20 μm.

[0176] Example 11 Unlike Example 1, in this example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 30%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 is 5%, and the height difference between the first region 101 and the second region 102 is 0.5 μm.

[0177] Example 12 Unlike Example 1, in this example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 accounts for 40%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 accounts for 5%, and the height difference between the first region 101 and the second region 102 is 10 μm.

[0178] Example 13 Unlike Example 1, in this example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 35%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 is 5%, and the height difference between the first region 101 and the second region 102 is 0.5 μm.

[0179] Example 14 Unlike Example 1, in this example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 35%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 is 5%, and the height difference between the first region 101 and the second region 102 is 2 μm.

[0180] Example 15 Unlike Example 1, in this example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 35%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 is 5%, and the height difference between the first region 101 and the second region 102 is 1.2 μm.

[0181] Compare with Example 1 Unlike Example 1, in this comparative example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 5%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 is 0.075%, and the height difference between the first region 101 and the second region 102 is 0.075 μm.

[0182] Compare with Example 2 Unlike Example 1, in this comparative example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 20%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 is 0.075%, and the height difference between the first region 101 and the second region 102 is 0.3 μm.

[0183] Compare with Example 3 Unlike Example 1, in this comparative example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 70%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 is 15%, and the height difference between the first region 101 and the second region 102 is 35 μm.

[0184] Compare with Example 4 Unlike Example 1, in this comparative example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 50%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 is 15%, and the height difference between the first region 101 and the second region 102 is 15 μm.

[0185] Compare with Example 5 Unlike Example 1, in this comparative example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 50%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 is 15%, and the height difference between the first region 101 and the second region 102 is 6 μm.

[0186] Reference example 1 Unlike Example 1, in this reference example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 0.4%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 is 0.04%, and the height difference between the first region 101 and the second region 102 is 0.04 μm.

[0187] Reference example 2 Unlike Example 1, in this reference example, the area of ​​the first region 101 on the back side of the crystalline silicon substrate 1 is 85%, the area of ​​the metal electrode 5 on the back side of the crystalline silicon substrate 1 is 22%, and the height difference between the first region 101 and the second region 102 is 55 μm.

[0188] Comparative Example 1 Unlike Example 1, in this comparative example, the back side of the crystalline silicon substrate 1 is not divided into a first region 101 and a recessed second region 102. Instead, it is fully covered by p-type TOPCon (i.e., tunneling oxide layer 2, p-type doped layer 3 and dielectric stack 4) and fully covered by metal electrode layer 5. That is, the coverage area of ​​p-type TOPCon and the coverage area of ​​metal electrode layer 5 are the same as the back side area of ​​crystalline silicon substrate 1.

[0189] Comparative Example 2 Unlike Example 1, in this comparative example, the back side of the crystalline silicon substrate 1 is partially covered with p-type TOPCon (island-shaped distribution, occupying 25% of the back side area) and full-area metal (i.e., the coverage area of ​​the metal electrode 5 layer is the same as the back side area of ​​the crystalline silicon substrate 1).

[0190] The parameter data for Examples 1-15, Comparative Example 15, Reference Examples 1 and 2, and Comparative Examples 1 and 2 are shown in Table 1 below: Table 1

[0191] The performance data of perovskite / crystalline silicon tandem solar cells in Examples 1-15, Comparative Example 15, Reference Examples 1 and 2, and Comparative Examples 1 and 2 were tested below. These examples, comparative examples, reference examples, and comparative examples are based on reasonable assumptions / simulation predictions made under the same perovskite top cell structure, the same crystalline silicon substrate 1, the same test conditions, and parameter variation trends. These assumptions can be replaced with actual test results. The test results are shown in Table 2 below: Table 2

[0192] As shown in Table 2, compared with the full-area p-type TOPCon and full-area metal structure of Comparative Example 1, the embodiments of the present invention, by dividing the back of the crystalline silicon bottom cell into a first region 101 and a recessed second region 102, and ensuring that the metal electrode 5 forms an effective electrical connection only in the corresponding area of ​​the first region 101, can improve Voc, Jsc, and FF overall. Compared with Comparative Example 2, Embodiments 1–6 further localize the back metal electrode 5, avoiding the adverse effects of full-area metal coverage on back optical reflection, metal recombination, and mechanical stress, thus achieving higher conversion efficiency.

[0193] From the parameter variation trend, when the height difference of the recessed second region 102 is too small, such as in Examples 7, 9, Comparative Examples 1 and 2, although etching damage can be reduced, the spatial isolation and optical control effects are insufficient. At the same time, the low proportion of metal electrodes 5 leads to an increase in local contact resistance and lateral transport loss, resulting in a lower FF. When the height difference is too large, such as in Examples 8, 10, Comparative Examples 3 and 2, the risk of groove edge recombination, process damage, and structural stress increases, and both Voc and FF are affected to some extent.

[0194] When the area ratio of the metal electrode 5 is low, metal-induced recombination and metal parasitic absorption are low, but the current collection capability is insufficient, which easily leads to an increase in series resistance and a decrease in flyback factor (FF). When the area ratio of the metal electrode 5 is high, although the current collection capability is enhanced, the metal coverage leads to an increase in backside parasitic absorption, stress, and recombination. Therefore, the area ratio of the metal electrode 5 is preferably 0.1–10%, and can be further taken as about 5%.

[0195] When the area of ​​the first region 101 is low, such as in Examples 6, 7, and Comparative Example 1, the p-type passivated contact area is insufficient, the lateral diffusion distance of holes is long, and transmission loss is easily generated; when the area of ​​the first region 101 is high, such as in Examples 5, 8, and Comparative Example 2, p-type poly-Si or p-type poly-SiO x The increased parasitic absorption and recombination caused by the region leads to a decrease in Voc and efficiency. Therefore, the area ratio of the first region 101 is preferably 10–60%, and more preferably 30–40%. A comprehensive comparison shows that Examples 13–15 perform better under the conditions of a height difference of 0.5–2 μm, a metal electrode 5 area ratio of approximately 5%, and a first region 101 area ratio of approximately 35%, with Example 15 predicting a conversion efficiency of 32.08%.

[0196] In summary, the present invention has at least the following technical effects through the above-described perovskite / crystalline silicon tandem solar cell.

[0197] First, reduce backside composite loss.

[0198] The p-type doped polysilicon layer or p-type doped polysilicon oxide layer is only disposed in the first region 101 to avoid the formation of p-type poly passivation contacts on the entire back side, especially on large-area rough surfaces, thereby reducing interfacial recombination.

[0199] Second, improve the optical management capabilities on the back side.

[0200] The second region 102 is a recessed structure, the surface of which can be a submicron alkaline polished plane or a pyramid-shaped light-trapping structure, and is covered with a dielectric passivation / reflection layer, which can enhance long-wavelength back reflection and light trapping, and improve the infrared response of crystalline silicon bottom cells.

[0201] Third, reduce the amount of metal used on the back.

[0202] The metal electrode 5 is only disposed above the first region 101 and does not form a continuous contact metal layer on the entire surface, thus significantly reducing the amount of metal materials such as silver, aluminum, and copper used.

[0203] Fourth, reduce mechanical stress and the risk of warping.

[0204] Since there is no continuous full metal layer on the back, the stress caused by the thermal expansion mismatch between the metal layer and the silicon substrate is reduced, which is beneficial to the reliability of thin silicon wafers and large-area stacked cells.

[0205] Fifth, reduce the risk of metal-induced recombination and leakage.

[0206] The metal electrode 5 contacts only the p-type poly layer in the first region 101 through the contact opening, while the second region 102 is covered by the dielectric layer and remains in a non-contact state, which can avoid leakage and recombination caused by direct contact between the metal and the silicon substrate or the groove area.

[0207] Sixth, improve the process tolerance of local contact.

[0208] The p-type poly region in the first region 101 has a larger area than the contact opening area, which can provide alignment tolerance for the laser opening and the metal electrode 5 and reduce the risk of failure caused by pattern offset.

[0209] Seventh, improve mass production compatibility.

[0210] The metal electrode 5 of the present invention can be realized by processes such as laser opening, screen printing, electroplating, conductive adhesive, local PVD or laser transfer, which is more suitable for industrial large-area perovskite / crystalline silicon tandem cells.

[0211] The above description is merely a specific embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A perovskite / crystalline silicon tandem solar cell, characterized in that, include: Crystalline silicon substrate (1); The back side of the crystalline silicon substrate (1) is divided into a first region (101) and a second region (102), and the second region (102) is recessed relative to the first region (101); A tunneling oxide layer (2) is formed in the first region (101), and a P-type doped layer (3) is formed in the tunneling oxide layer (2), wherein the P-type doped layer (3) is a P-type doped polysilicon layer or a P-type doped polysilicon oxide layer. A dielectric stack (4) is formed on the P-type doped layer (3) and the second region (102), the dielectric stack (4) including a dielectric passivation layer and a back reflective layer; Multiple metal electrodes (5) electrically connected to the P-type doped layer (3) are disposed in the dielectric stack (4). There is a gap between any two adjacent metal electrodes (5).

2. The perovskite / crystalline silicon tandem solar cell according to claim 1, characterized in that, The first region (101) accounts for 0.5-80% of the area on the back side of the crystalline silicon substrate (1); Preferably, the area ratio is 10-60%; Preferably, the area ratio is 30-40%.

3. The perovskite / crystalline silicon tandem solar cell according to claim 1, characterized in that, The second region (102) has a recess depth of 0.05-50 μm relative to the first region (101); Preferably, the depth of the depression is 0.1-20 μm; Preferably, the depth of the depression is 0.5-10 μm; Preferably, the depth of the depression is 0.5-2 μm.

4. The perovskite / crystalline silicon tandem solar cell according to claim 1, characterized in that, The surface of the first region (101) is a polished plane; The surface of the second region (102) is a polished plane or a pyramid-shaped light trapping structure.

5. The perovskite / crystalline silicon tandem solar cell according to claim 1, characterized in that, The area of ​​all the metal electrodes (5) on the back side of the crystalline silicon substrate (1) is 0.05-20%; Preferably, the area ratio is 0.1-10%.

6. The perovskite / crystalline silicon tandem solar cell according to claim 1, characterized in that, The two adjacent metal electrodes (5) are electrically connected by a conductive interconnect (19); wherein, there is a gap between the two adjacent conductive interconnects (19), and the conductive interconnect (19) includes a metal grid, a bus electrode, conductive adhesive, solder strip or conductive interconnect layer; And / or, The dielectric stack (4) has a plurality of spaced contact openings in the region corresponding to the first region (101); each metal electrode (5) passes through one of the contact openings and is electrically connected to the P-type doped layer (3).

7. A method for fabricating a perovskite / crystalline silicon tandem solar cell, characterized in that, include: Provide a crystalline silicon substrate (1); A first region (101) is defined on the back side of the crystalline silicon substrate (1). A tunneling oxide layer (2) is formed in the first region (101) and a P-type doped layer (3) is formed on the tunneling oxide layer (2), wherein the P-type doped layer (3) is a P-type doped polysilicon layer or a P-type doped polysilicon oxide layer. A second region (102) is formed on the back side in the area other than the first region (101), wherein the second region (102) is recessed relative to the first region (101); A dielectric stack (4) is formed on the P-type doped layer (3) and the second region (102), wherein the dielectric stack (4) includes a dielectric passivation layer and a back reflective layer; Multiple metal electrodes (5) are formed through the dielectric stack (4) and electrically connected to the P-type doped layer (3); wherein a gap is left between any two adjacent metal electrodes (5).

8. The method for preparing a perovskite / crystalline silicon tandem solar cell according to claim 7, characterized in that, The steps of forming a tunneling oxide layer (2) in the first region (101) and forming a P-type doped layer (3) on the tunneling oxide layer (2) include: First, a tunneling oxide layer (2) is formed on the entire back side of the crystalline silicon substrate (1), and a P-type doped layer (3) is formed on the tunneling oxide layer (2). Then, the P-type doped layer (3) in the area outside the first region (101) is removed by patterned etching. or, First, a patterned mask is formed on the back side of the crystalline silicon substrate (1) in the area other than the first region (101). Then, a tunneling oxide layer (2) is formed in the first region (101) and a P-type doped layer (3) is formed on the tunneling oxide layer (2). Finally, the mask is removed. or, First, an intrinsic polycrystalline silicon layer or a polycrystalline silicon oxide layer is formed in the first region (101), and then local boron diffusion, local ion implantation, local laser doping or local boron paste diffusion are performed.

9. The method for preparing a perovskite / crystalline silicon tandem solar cell according to claim 7, characterized in that, The step of forming a second region (102) on the back side in a region other than the first region (101) includes: The area on the back surface other than the first area (101) is etched to form the second area (102); wherein the etching method is one or more of alkaline etching, acid etching, laser etching, plasma etching, reactive ion etching, and metal-assisted chemical etching; The second region (102) is subjected to alkaline polishing or alkaline anisotropic etching; And / or, The step of forming a plurality of metal electrodes (5) that pass through the dielectric stack (4) and are electrically connected to the p-type doped layer (3) includes: The metal electrode (5) is formed by screen printing metal using a burn-through paste.

10. The method for preparing a perovskite / crystalline silicon tandem solar cell according to claim 7, characterized in that, The step of forming a plurality of metal electrodes (5) that pass through the dielectric stack (4) and are electrically connected to the p-type doped layer (3) includes: Multiple spaced-apart contact openings are formed on the medium stack (4) in the region corresponding to the first region (101); A metal electrode (5) is formed at each of the contact openings; Preferably, a plurality of contact openings are formed on the dielectric stack (4) by means of laser opening, photolithography etching, wet etching, plasma etching, inkjet etching paste or screen printing etching paste; The metal electrode (5) is formed at each of the contact openings by means of screen printing, inkjet printing, dispensing, local evaporation, local sputtering, laser transfer, electroplating, chemical plating or mask deposition. Preferably, the step of forming one of the metal electrodes (5) at each of the contact openings includes: First, a contact seed layer that is electrically in contact with the P-type doped layer (3) is formed at the contact opening. Then, a conductive enhancement layer is formed on the contact seed layer. Finally, a protective layer is formed on the conductive enhancement layer. or, After printing silver paste, silver-aluminum paste, aluminum paste, or conductive adhesive at the contact opening, the material is cured.

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