Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a substrate, pixel circuits, light emitting elements, a first power supply line and a second power supply line on the substrate, a first end of the pixel circuit is electrically connected with the first power supply line, a second end of the pixel circuit is electrically connected with a first pole of the light emitting element, a second pole of the light emitting element is electrically connected with the second power supply line, the first power supply line and the second power supply line are used for providing a power supply signal for light emission, a plurality of pixel circuits are arranged in an array in a first direction and a second direction, the first direction and the second direction intersect, the first power supply line comprises a first power supply branch and a second power supply branch, the first power supply branch and the second power supply branch are electrically connected with each other, and the first power supply branch and the second power supply branch both extend along the second direction, the width of the first power supply branch in the first direction is different from the width of the second power supply branch in the first direction. The embodiment of the application can improve the display performance of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide range of applications, becoming the mainstream of display devices.

[0003] However, the display performance of current OLED display products needs to be improved. Summary of the Invention

[0004] This application provides a display panel and a display device that can improve the display performance of the display panel.

[0005] In a first aspect, embodiments of this application provide a display panel, comprising: a substrate and pixel circuits, a light-emitting element, a first power line, and a second power line located on the substrate; a first end of the pixel circuit is electrically connected to the first power line, a second end of the pixel circuit is electrically connected to a first electrode of the light-emitting element, and a second electrode of the light-emitting element is electrically connected to the second power line; the first power line and the second power line are used to provide a power signal for emitting light; a plurality of pixel circuits are arranged in an array in a first direction and a second direction, the first direction and the second direction intersecting; the first power line includes a first power branch and a second power branch, the first power branch and the second power branch are electrically connected to each other, and both the first power branch and the second power branch extend along the second direction, the width of the first power branch in the first direction is different from the width of the second power branch in the first direction.

[0006] In some embodiments of the first aspect, the first power supply branch line is electrically connected to the pixel circuit through a via, and the width of the first power supply branch line in the first direction is greater than the width of the second power supply branch line in the first direction.

[0007] Preferably, the orthographic projection shape of the first power supply branch line on the substrate and the orthographic projection shape of the second power supply branch line on the substrate are different.

[0008] In some embodiments of the first aspect, the orthographic projection of the first power supply branch line on the substrate and the orthographic projection of the second power supply branch line on the substrate do not overlap, and the display panel further includes an initialization signal line extending along the second direction. In the first direction, an initialization signal line or a second power supply branch line is provided between two adjacent first power supply branches.

[0009] Preferably, the initialization signal line and the second power supply branch line are arranged alternately along the first direction;

[0010] Preferably, the initialization signal line includes at least one of a first initialization signal line, a second initialization signal line, and a third initialization signal line, wherein the first initialization signal line, the second initialization signal line, the third initialization signal line, and the second power supply branch line are located in the same metal layer;

[0011] Preferably, in the first direction, multiple first power branches are provided between two adjacent second power branches;

[0012] Preferably, the orthographic projections of the first initialization signal line and the second initialization signal line on the substrate do not overlap with the orthographic projections of the first power supply line on the substrate; or, the orthographic projections of the first initialization signal line, the second initialization signal line, and the third initialization signal line on the substrate do not overlap with the orthographic projections of the first power supply line on the substrate.

[0013] Preferably, the first initialization signal line, the second initialization signal line, and the third initialization signal line are connected to different voltages;

[0014] Preferably, in the first direction, the second power supply branch line is located between two data lines between two adjacent first power supply branches, the first initialization signal line is located between two data lines between two adjacent first power supply branches, the second initialization signal line is located between two data lines between two adjacent first power supply branches, and the third initialization signal line is located between two data lines between two adjacent first power supply branches; or, in the first direction, the second power supply branch line is located outside the region between two data lines between two adjacent first power supply branches, the first initialization signal line is located outside the region between two data lines between two adjacent first power supply branches, the second initialization signal line is located outside the region between two data lines between two adjacent first power supply branches, and the third initialization signal line is located outside the region between two data lines between two adjacent first power supply branches.

[0015] Preferably, the first power supply branch and the second power supply branch are located in the same metal layer.

[0016] In some embodiments of the first aspect, the first power branch line and the second power branch line are located in different metal layers, and an insulating layer is provided between the first power branch line and the second power branch line in the thickness direction of the display panel. The orthographic projection of the first power branch line on the substrate and the orthographic projection of the second power branch line on the substrate at least partially overlap.

[0017] Preferably, the display panel further includes an initialization signal line extending along the second direction, wherein the orthographic projection of the initialization signal line on the substrate and the orthographic projection of the first power supply branch line on the substrate at least partially overlap.

[0018] Preferably, the initialization signal line and the second power supply branch line are arranged alternately along the first direction;

[0019] Preferably, the initialization signal line includes at least one of a first initialization signal line, a second initialization signal line, and a third initialization signal line, wherein the first initialization signal line, the second initialization signal line, the third initialization signal line, and the second power supply branch line are located in the same metal layer;

[0020] Preferably, the first central axis of the first power branch line and the second central axis of the second power branch line coincide, and the first central axis and the second central axis extend along the second direction;

[0021] Preferably, the first initialization signal line, the second initialization signal line, and the third initialization signal line are connected to different voltages.

[0022] In some embodiments of the first aspect, in the first direction, two data lines extending in the second direction are provided between two adjacent first power supply branches;

[0023] Preferably, the first power supply line and the data line are located in the same metal layer;

[0024] Preferably, in at least a portion of the region, in the first direction, a first trace extending in the second direction is provided between two adjacent first power supply branches;

[0025] Preferably, at least a portion of the data lines are electrically connected to the first trace via a second trace, the second trace extending along a first direction;

[0026] Preferably, in the first direction, the first trace is located between two data lines between two adjacent first power branches; or, in the first direction, the first trace is located outside the area between two data lines between two adjacent first power branches.

[0027] Preferably, the first trace, the first power branch, and the data line are located in the same metal layer.

[0028] In some embodiments of the first aspect, the display panel includes a plurality of circuit columns, each circuit column including a plurality of pixel circuits arranged along a second direction, and a first power supply branch line at least partially overlaps with the orthographic projections of the two circuit columns on the substrate.

[0029] Preferably, multiple first power supply branches are arranged along a first direction, and multiple second power supply branches are arranged along a first direction;

[0030] Preferably, the display panel further includes a third power branch line, which extends along a first direction, and the first power branch line, the second power branch line, and the third power branch line are electrically connected to each other.

[0031] Preferably, the third power supply branch line is located in a different metal layer than the first power supply branch line and the second power supply branch line;

[0032] Preferably, a plurality of third power supply branches are arranged at intervals along the first direction, and the third power supply branches are electrically connected to two adjacent first power supply branches;

[0033] Preferably, in the first direction, the size of the third power supply branch line is smaller than the size of the two pixel circuits;

[0034] Alternatively, the third power supply branch can be electrically connected to at least three first power supply branches;

[0035] Preferably, in the first direction, the size of the third power supply branch line is greater than twice the size of a pixel circuit.

[0036] In some embodiments of the first aspect, the display panel further includes at least one of a first connecting line, a second connecting line, and a third connecting line extending along a first direction, at least two of the first connecting line, the second connecting line, and the third connecting line are arranged to overlap in a second direction, the first connecting line is electrically connected to a first initialization signal line, the second connecting line is electrically connected to a second initialization signal line, and the third connecting line is electrically connected to a third initialization signal line.

[0037] Preferably, the display panel further includes a third power branch line, which extends along a first direction. The first power branch line, the second power branch line, and the third power branch line are electrically connected to each other. The third power branch line and at least one of the first connecting line, the second connecting line, and the third connecting line are located in the same metal layer.

[0038] In some embodiments of the first aspect, the pixel circuit includes a driving transistor, a first initialization transistor, a second initialization transistor, and a third initialization transistor;

[0039] The first terminal of the driving transistor is electrically connected to the first power supply line;

[0040] The first terminal of the first initialization transistor is electrically connected to the first initialization signal line, and the second terminal of the first initialization transistor is electrically connected to the gate of the driving transistor.

[0041] The first terminal of the second initialization transistor is electrically connected to the second initialization signal line, and the second terminal of the second initialization transistor is electrically connected to the first terminal of the light-emitting element.

[0042] The first terminal of the third initialization transistor is electrically connected to the third initialization signal line, and the second terminal of the third initialization transistor is electrically connected to the first terminal of the driving transistor.

[0043] Secondly, embodiments of this application provide a display panel, including:

[0044] The substrate and the pixel circuit, light-emitting element, first power line, initialization signal line and data line located on the substrate, wherein the pixel circuit is electrically connected to the first power line, initialization signal line, data line and the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the second power line.

[0045] Multiple pixel circuits are arranged in an array in the first direction and the second direction, and the first direction and the second direction intersect.

[0046] The first power line includes a first power branch and a second power branch, which are electrically connected to each other, and both the first power branch and the second power branch extend along a second direction.

[0047] Initialization signal lines and second power supply lines are arranged alternately along a first direction. One first power supply line overlaps with the orthographic projection of two circuit columns on the substrate. The circuit columns include multiple pixel circuits arranged along a second direction.

[0048] Two data lines are provided between the two adjacent first power supply branches.

[0049] Thirdly, embodiments of this application provide a display device, including a display panel as described in any one of the embodiments of the first and second aspects.

[0050] According to the display panel and display device provided in the embodiments of this application, the first power line includes a first power branch line and a second power branch line extending along a second direction. The width of the first power branch line in the first direction is different from the width of the second power branch line in the first direction, which is equivalent to widening the width of the first power line in the first direction. This can significantly reduce the voltage drop (IR drop) of the first power line in the display area, thereby improving the display uniformity of the display panel, especially the display uniformity under high brightness.

[0051] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0052] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0053] Figure 1 A schematic diagram of a wiring structure for a display panel according to a comparative example of this application is shown.

[0054] Figure 2This illustration shows a structural schematic diagram of a display panel provided in an embodiment of this application;

[0055] Figure 3 This illustration shows a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0056] Figure 4 This illustration shows a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0057] Figure 5 This illustration shows a wiring structure diagram of a display panel provided in an embodiment of this application;

[0058] Figure 6 This diagram illustrates another wiring structure for the display panel provided in an embodiment of this application.

[0059] Figure 7 This diagram illustrates yet another wiring structure of the display panel provided in an embodiment of this application;

[0060] Figure 8 This diagram illustrates yet another wiring structure of the display panel provided in an embodiment of this application;

[0061] Figure 9 This illustration shows a schematic diagram of a film layer stacking structure for a display panel provided in an embodiment of this application;

[0062] Figure 10 This diagram illustrates another film layer stacking structure of the display panel provided in an embodiment of this application;

[0063] Figure 11 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0064] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0065] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0066] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0067] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0068] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0069] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0070] As OLED display panels gain increasing market penetration, some customers are demanding higher brightness levels to provide a better consumer experience. However, higher brightness often results in lower brightness uniformity, which can lead to yield losses for panel manufacturers.

[0071] The design of the first power line (ELVDD) within the display area is one of the main factors affecting the brightness uniformity of the display panel. In a comparative example, such as... Figure 1 As shown, the first power line ELVDD in the display area can be designed as a grid structure. Specifically, the first power line ELVDD extending in the first direction X and the first power line ELVDD extending in the second direction Y are designed in different metal layers, and the two are electrically connected through vias.

[0072] The higher the brightness specification of an OLED display panel, the worse the brightness uniformity of the display panel under high brightness, which will directly affect the yield of the display panel. Figure 1 While the grid design shown can improve display uniformity to some extent, simply relying on this grid wiring method using the first power line ELVDD still cannot meet the requirement of brightness uniformity under high brightness.

[0073] Therefore, how to improve display uniformity without being limited by the PPI of the display panel is a technical problem that those skilled in the art are committed to solving.

[0074] To address the aforementioned technical problems, this application provides a display panel and a display device. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display panel and the display device.

[0075] This application provides a display panel. For example, the display panel may be an organic light-emitting diode (OLED) display panel.

[0076] Please refer to the reference. Figures 2 to 10 The display panel provided in this application embodiment includes a substrate 00, a pixel circuit 10, a light-emitting element 20, a first power line ELVDD and a second power line ELVSS, and the pixel circuit 10, the light-emitting element 20, the first power line ELVDD and the second power line ELVSS are located on the substrate 00.

[0077] The first terminal of the pixel circuit 10 is electrically connected to the first power line ELVDD, and the second terminal of the pixel circuit 10 is electrically connected to the first electrode of the light-emitting element 20. The second electrode of the light-emitting element 20 is electrically connected to the second power line ELVSS. The first power line ELVDD and the second power line ELVSS are used to provide a power signal for light emission. For example, the first electrode of the light-emitting element 20 is the anode, and the second electrode of the light-emitting element 20 is the cathode. The first power line ELVDD is used to provide a positive voltage, and the second power line ELVSS is used to provide a negative voltage.

[0078] Multiple pixel circuits 10 are arranged in an array along a first direction X and a second direction Y, where the first direction X and the second direction Y intersect. For example, the first direction X is the row direction and the second direction Y is the column direction.

[0079] The first power line ELVDD is located in the display area of ​​the display panel. The first power line ELVDD includes a first power branch line ELVDD1 and a second power branch line ELVDD2. The first power branch line ELVDD1 and the second power branch line ELVDD2 are electrically connected to each other, and both the first power branch line ELVDD1 and the second power branch line ELVDD2 extend along the second direction Y. The width of the first power branch line ELVDD1 in the first direction X is different from the width of the second power branch line ELVDD2 in the first direction X.

[0080] It should be noted that, Figures 5 to 8 The dashed box indicates the approximate location of the pixel circuit 10; the dashed box is not used to define the specific shape of the pixel circuit 10. Figure 5 For example, Figure 5 The image shows the approximate location of the 8-pixel circuit 10 arranged in 2 rows and 4 columns. Additionally, Figures 5 to 8 The substrate is hidden within the drawing. Figures 5 to 8 The diagram shows the projection structure of each trace on the substrate, with different colored fills indicating different film layers in the display panel and the same colored fills indicating the same film layer in the display panel.

[0081] Understandably, both the first power supply line ELVDD1 and the second power supply line ELVDD2 are electrically connected to the first terminal of the pixel circuit 10, and both the first power supply line ELVDD1 and the second power supply line ELVDD2 are used to transmit the first power signal.

[0082] The width of the first power branch line ELVDD1 in the first direction X is different from the width of the second power branch line ELVDD2 in the first direction X, including: the width of the first power branch line ELVDD1 in the first direction X is greater than the width of the second power branch line ELVDD2 in the first direction X; or, the width of the first power branch line ELVDD1 in the first direction X is less than the width of the second power branch line ELVDD2 in the first direction X.

[0083] For example, as the first power branch line ELVDD1 extends, the width of the first power branch line ELVDD1 in the first direction X can vary. The width of the first power branch line ELVDD1 in the first direction X is different from the width of the second power branch line ELVDD2 in the first direction X, including: the average width of the first power branch line ELVDD1 in the first direction X is different from the average width of the second power branch line ELVDD2 in the first direction X.

[0084] According to the display panel provided in the embodiments of this application, the first power line includes a first power branch line and a second power branch line extending along a second direction. The width of the first power branch line in the first direction is different from the width of the second power branch line in the first direction, which is equivalent to widening the width of the first power line in the first direction. This can significantly reduce the voltage drop (IR drop) of the first power line in the display area, thereby improving the display uniformity of the display panel, especially the display uniformity under high brightness.

[0085] In some embodiments, the first power line ELVDD1 is electrically connected to the pixel circuit 10 through a via, and the width of the first power line ELVDD1 in the first direction X is greater than the width of the second power line ELVDD2 in the first direction X.

[0086] For example, the width of the first power branch line ELVDD1 in the first direction X is greater than the width of the second power branch line ELVDD2 in the first direction X, including: the average width of the first power branch line ELVDD1 in the first direction X is greater than the average width of the second power branch line ELVDD2 in the first direction X.

[0087] For example, such as Figure 3 or Figure 4 As shown, the first power line ELVDD is electrically connected to the first electrode of transistor T5 in pixel circuit 10. The first power branch line ELVDD1 and the first electrode of transistor T5 are located in different film layers. The first power branch line ELVDD1 and the first electrode of transistor T5 are electrically connected through a via.

[0088] In this embodiment, the width of the first power line ELVDD1 is relatively large, so that the first power line ELVDD1 has sufficient area to contact the via, thereby reducing the contact resistance between the first power line ELVDD1 and the via and further improving the display uniformity.

[0089] For example, such as Figures 6 to 8 As shown in any of the accompanying figures, the orthographic projection shape of the first power supply line ELVDD1 on the substrate is different from that of the second power supply line ELVDD2 on the substrate.

[0090] For example, the first power supply branch ELVDD1 is approximately a broken line in the second direction Y. The second power supply branch ELVDD2 is approximately a straight line in the second direction Y.

[0091] In some embodiments, such as Figure 5 , Figure 7 , Figure 8 As shown in any of the accompanying drawings, the orthographic projections of the first power supply line ELVDD1 and the second power supply line ELVDD2 on the substrate do not overlap. The display panel also includes an initialization signal line Vref extending along the second direction Y. In the first direction X, an initialization signal line Vref is provided between two adjacent first power supply lines ELVDD1, or a second power supply line ELVDD2 is provided between two adjacent first power supply lines ELVDD1.

[0092] Understandably, at least two of the first power supply branches, ELVDD1, are connected not to the initialization signal line Vref, but to the second power supply branch, ELVDD2.

[0093] like Figure 3 or Figure 4 As shown, the initialization signal line Vref is electrically connected to the pixel circuit 10. The initialization signal line Vref is used to provide an initialization signal to initialize the target node in the pixel circuit 10. For example, the initialization signal on the initialization signal line Vref is used to initialize at least one of the gate potential of the driving transistor T1, the first / second electrode potential of the driving transistor T1, and the first electrode potential of the light-emitting element 20 in the pixel circuit 10.

[0094] The inventors discovered that, to further improve brightness uniformity, especially under high brightness conditions, the most direct approach is to widen the line width of the first power line ELVDD. However, the wiring method of the first power line ELVDD remains the same. Figure 1 As shown, directly widening the first power line will obviously be limited by the pixel density (Pixels Per Inch, PPI) of the display panel. The higher the PPI, the more limited the wiring space, and the lower the light transmittance of the pixels.

[0095] In this embodiment, the conventional wiring method for the first power line ELVDD and the initialization signal line Vref is broken. Instead, it is designed such that at least two first power lines ELVDD1 are connected not by the initialization signal line Vref, but by a second power line ELVDD2. For example, compare with reference... Figure 5 and Figure 1 This is equivalent to Figure 1 The initialization signal line Vref1 in the code is replaced with... Figure 5The second power supply branch line ELVDD2 in the first power supply line, which extends along the second direction Y, includes not only the first power supply branch line ELVDD1 but also the second power supply branch line ELVDD2. This can reduce the voltage drop of the first power supply line without being limited by PPI or causing a decrease in transmittance, thereby improving display uniformity, especially display uniformity at high brightness.

[0096] For example, the first power supply branch ELVDD1 and the second power supply branch ELVDD2 are located on the same metal layer. This reduces the number of metal layers in the display panel, which is beneficial for achieving a thinner and lighter design.

[0097] For example, the initialization signal line Vref and the second power supply line ELVDD2 are arranged alternately along the first direction X.

[0098] For example, the number of initialization signal lines Vref is greater than the number of second power supply lines ELVDD2.

[0099] For example, the initialization signal line Vref includes at least one of a first initialization signal line Vref1, a second initialization signal line Vref2, and a third initialization signal line Vref3, wherein the first initialization signal line Vref1, the second initialization signal line Vref2, the third initialization signal line Vref3, and the second power supply branch line ELVDD2 are located on the same metal layer.

[0100] For example, please refer to the reference. Figure 3 and Figure 5 The initialization signal line Vref includes a first initialization signal line Vref1 and a second initialization signal line Vref2. The pixel circuit includes a driving transistor T1, a first initialization transistor T4, and a second initialization transistor T7. The first terminal of the driving transistor T1 is electrically connected to the first power supply line ELVDD. The first terminal of the first initialization transistor T4 is electrically connected to the first initialization signal line Vref1, and the second terminal of the first initialization transistor T4 is electrically connected to the gate of the driving transistor T1. The first terminal of the second initialization transistor T7 is electrically connected to the second initialization signal line Vref2, and the second terminal of the second initialization transistor T7 is electrically connected to the first terminal of the light-emitting element 20.

[0101] In this example, the initialization signal on the first initialization signal line Vref1 is used to initialize the gate potential of the driving transistor T1, and the initialization signal on the second initialization signal line Vref2 is used to initialize the first electrode potential of the light-emitting element 20.

[0102] For example, please refer to the reference. Figure 4 and Figures 6 to 8In any of the following, the initialization signal line Vref includes a first initialization signal line Vref1, a second initialization signal line Vref2, and a third initialization signal line Vref3; the pixel circuit includes a driving transistor T1, a first initialization transistor T4, a second initialization transistor T7, and a third initialization transistor T8; the first terminal of the driving transistor T1 is electrically connected to the first power supply line ELVDD; the first terminal of the first initialization transistor T4 is electrically connected to the first initialization signal line Vref1, and the second terminal of the first initialization transistor T4 is electrically connected to the gate of the driving transistor T1; the first terminal of the second initialization transistor T7 is electrically connected to the second initialization signal line Vref2, and the second terminal of the second initialization transistor T7 is electrically connected to the first terminal of the light-emitting element 20; the first terminal of the third initialization transistor T8 is electrically connected to the third initialization signal line Vref3, and the second terminal of the third initialization transistor T8 is electrically connected to the first terminal of the driving transistor T1.

[0103] In this example, the initialization signal on the first initialization signal line Vref1 is used to initialize the gate potential of the driving transistor T1, and the initialization signal on the third initialization signal line Vref3 is used to initialize the first electrode potential of the driving transistor T1.

[0104] For example, such as Figure 3 or Figure 4 As shown, the pixel circuit also includes a data writing transistor T2, a threshold compensation transistor T3, and light emission control transistors T5 and T6. Data represents the data line, and SP1, SP2, SN1, and SN2 represent different scan lines.

[0105] For example, the first initialization signal line Vref1, the second initialization signal line Vref2, and the third initialization signal line Vref3 are connected to different voltages. In this way, different nodes can be initialized based on different voltages to flexibly meet the initialization requirements of different nodes.

[0106] For example, in the first direction X, multiple first power lines ELVDD1 are arranged between two adjacent second power lines ELVDD2. It is understood that in this example, the number of first power lines ELVDD1 is greater than the number of second power lines ELVDD2.

[0107] As described above, this application is equivalent to... Figure 1 The initialization signal line Vref1 is replaced with the second power branch line ELVDD2. In this example, the number of first power branch lines ELVDD1 is greater than the number of second power branch lines ELVDD2. That is, only a portion of the initialization signal line Vref1 is replaced with the second power branch line ELVDD2. This ensures that the first initialization signal line Vref1 still exists, while also widening the line width of the first power line and improving display uniformity.

[0108] As an example, with Figure 5 For example, the first initialization signal line Vref1, the second initialization signal line Vref2, and the second power supply line ELVDD2 are located in the same metal layer. In this metal layer, from left to right, the first line is the first initialization signal line Vref1, the second line is the second initialization signal line Vref2, the third line is the second power supply line ELVDD2, and the fourth line is the second initialization signal line Vref2.

[0109] It should be noted that, Figures 5 to 8 Only a portion of the wiring is shown. Figures 5 to 8 The area shown is a repeating unit; the display panel includes multiple repeating units. For example, Figure 5 The 8-pixel circuit in row 2, column 4 is located in a repeating unit, and multiple Figure 5 The repeating units shown are arranged in an array in the first and second directions, forming the wiring structure of the entire display area of ​​the display panel.

[0110] For example, such as Figure 5 As shown, the orthographic projections of the first initialization signal line Vref1 and the second initialization signal line Vref2 on the substrate do not overlap with the orthographic projection of the first power supply line ELVDD1 on the substrate. This allows the first initialization signal line Vref1, the second initialization signal line Vref2, and the first power supply line ELVDD1 to be placed on the same metal layer, which helps reduce the number of metal layers in the display panel, thus meeting the requirements for a thinner and lighter design.

[0111] For example, the orthographic projections of any two of the first initialization signal line Vref1, the second initialization signal line Vref2, the second power supply branch line ELVDD2, and the first power supply branch line ELVDD1 onto the substrate do not overlap.

[0112] Or, such as Figure 7 or Figure 8 As shown, the orthographic projections of the first initialization signal line Vref1, the second initialization signal line Vref2, and the third initialization signal line Vref3 on the substrate do not overlap with the orthographic projection of the first power supply line ELVDD1 on the substrate. This allows the first initialization signal line Vref1, the second initialization signal line Vref2, the third initialization signal line Vref3, and the first power supply line ELVDD1 to be placed on the same metal layer, which helps reduce the number of metal layers in the display panel, thus meeting the requirements for a thinner and lighter design.

[0113] For example, the orthographic projections of any two of the first initialization signal line Vref1, the second initialization signal line Vref2, the third initialization signal line Vref3, the second power supply branch line ELVDD2, and the first power supply branch line ELVDD1 onto the substrate do not overlap.

[0114] For example, in the first direction X, each pair of adjacent first power supply branches ELVDD1 constitutes a first branch group, and two data lines data are provided between the two first power supply branches ELVDD1 in the same first branch group.

[0115] As an example, such as Figure 5 As shown, in the first direction X, the second power supply branch line ELVDD2 is located between two data lines (data) between two adjacent first power supply branches ELVDD1; the first initialization signal line Vref1 is located between two data lines (data) between two adjacent first power supply branches ELVDD1; and the second initialization signal line Vref2 is located between two data lines (data) between two adjacent first power supply branches ELVDD1. Alternatively, as... Figure 7 As shown, in the first direction X, the second power supply branch line ELVDD2 is located between two data lines data between two adjacent first power supply branches ELVDD1, the first initialization signal line Vref1 is located between two data lines data between two adjacent first power supply branches ELVDD1, the second initialization signal line Vref2 is located between two data lines data between two adjacent first power supply branches ELVDD1, and the third initialization signal line Vref3 is located between two data lines data between two adjacent first power supply branches ELVDD1.

[0116] As another example, such as Figure 8 As shown, in the first direction X, the second power supply line ELVDD2 is located outside the region between the two data lines data between the two adjacent first power supply lines ELVDD1, the first initialization signal line Vref1 is located outside the region between the two data lines data between the two adjacent first power supply lines ELVDD1, the second initialization signal line Vref2 is located outside the region between the two data lines data between the two adjacent first power supply lines ELVDD1, and the third initialization signal line Vref3 is located outside the region between the two data lines data between the two adjacent first power supply lines ELVDD1.

[0117] In some embodiments, such as Figure 6As shown, the first power branch line ELVDD1 and the second power branch line ELVDD2 are located in different metal layers. In the thickness direction of the display panel, an insulating layer is provided between the first power branch line ELVDD1 and the second power branch line ELVDD2. The orthographic projection of the first power branch line ELVDD1 on the substrate and the orthographic projection of the second power branch line ELVDD2 on the substrate at least partially overlap.

[0118] In this embodiment, the first power branch line ELVDD1 and the second power branch line ELVDD2 are disposed on different metal layers and at least partially overlap, so that the first power branch line ELVDD1 and the second power branch line ELVDD2 can be disposed simultaneously in a limited space, thereby improving display uniformity without being limited by PPI.

[0119] For example, please continue to refer to Figure 6 When the orthographic projections of the first power branch line ELVDD1 and the second power branch line ELVDD2 on the substrate at least partially overlap, the display panel further includes an initialization signal line Vref extending along the second direction Y, wherein the orthographic projection of the initialization signal line Vref on the substrate and the orthographic projection of the first power branch line ELVDD1 on the substrate at least partially overlap. In this example, the initialization signal line Vref and the first power branch line ELVDD1 at least partially overlap, allowing both the initialization signal line Vref and the first power branch line ELVDD1 to be simultaneously provided within a limited space, thereby improving display uniformity without being limited by PPI.

[0120] For example, the initialization signal line Vref and the second power supply line ELVDD2 are arranged alternately along the first direction X.

[0121] For example, the initialization signal line Vref includes at least one of a first initialization signal line Vref1, a second initialization signal line Vref2, and a third initialization signal line Vref3, wherein the first initialization signal line Vref1, the second initialization signal line Vref2, the third initialization signal line Vref3, and the second power supply branch line ELVDD2 are located on the same metal layer.

[0122] For example, please refer to the reference. Figure 4 and Figure 6The initialization signal line Vref includes a first initialization signal line Vref1, a second initialization signal line Vref2, and a third initialization signal line Vref3. The pixel circuit includes a driving transistor T1, a first initialization transistor T4, a second initialization transistor T7, and a third initialization transistor T8. The first terminal of the driving transistor T1 is electrically connected to the first power supply line ELVDD. The first terminal of the first initialization transistor T4 is electrically connected to the first initialization signal line Vref1, and the second terminal of the first initialization transistor T4 is electrically connected to the gate of the driving transistor T1. The first terminal of the second initialization transistor T7 is electrically connected to the second initialization signal line Vref2, and the second terminal of the second initialization transistor T7 is electrically connected to the first terminal of the light-emitting element 20. The first terminal of the third initialization transistor T8 is electrically connected to the third initialization signal line Vref3, and the second terminal of the third initialization transistor T8 is electrically connected to the first terminal of the driving transistor T1.

[0123] In this example, the initialization signal on the first initialization signal line Vref1 is used to initialize the gate potential of the driving transistor T1, and the initialization signal on the third initialization signal line Vref3 is used to initialize the first electrode potential of the driving transistor T1.

[0124] For example, the first initialization signal line Vref1, the second initialization signal line Vref2, and the third initialization signal line Vref3 are connected to different voltages. In this way, different nodes can be initialized based on different voltages to flexibly meet the initialization requirements of different nodes.

[0125] For example, such as Figure 6 As shown, in the first direction X, the first initialization signal line Vref1, the second initialization signal line Vref2 and the third initialization signal line Vref3, the second power supply branch line ELVDD2, the first initialization signal line Vref1, the second initialization signal line Vref2 and the third initialization signal line Vref3, and the second power supply branch line ELVDD2 are arranged in that order.

[0126] For example, such as Figure 6 As shown, the first central axis L1 of the first power branch line ELVDD1 and the second central axis L2 of the second power branch line ELVDD2 coincide, and the first central axis L1 and the second central axis L2 extend along the second direction Y. It should be noted that... Figure 6 The first centerline L1 and the second centerline L2 are virtual centerlines and are not used to represent actual wiring.

[0127] In this example, the central axes of both coincide, which makes better use of space and avoids affecting PPI.

[0128] In some embodiments, such as Figures 5 to 8As shown, in the first direction X, two data lines extending along the second direction Y are provided between two adjacent first power supply branches ELVDD1.

[0129] For example, in the first direction X, each pair of adjacent first power supply branches ELVDD1 constitutes a first branch group. Within the same first branch group, there are two data lines data between the two first power supply branches ELVDD1. There are no data lines data between different first branch groups.

[0130] In this embodiment, two data lines are set between two adjacent first power supply lines ELVDD1, which can improve space utilization and thus improve PPI.

[0131] For example, in the second direction Y, the pixel circuits 10 of the same column are electrically connected to the same data line.

[0132] For example, the first power line ELVDD1 and the data line data are located on the same metal layer. It is understood that the first power line ELVDD1 and the data line data do not overlap, thereby avoiding signal crosstalk.

[0133] For example, such as Figures 6 to 8 As shown, in at least a portion of the region, in the first direction X, a first trace FIAA1 extending along the second direction Y is provided between two adjacent first power supply branches ELVDD1. The first trace FIAA1 can be used to transmit data signals or other signals or is in a floating state.

[0134] At least a portion of the data line is electrically connected to the first data line FIAA1 via the second data line FIAA2, which extends along the first direction X.

[0135] Understandably, the first trace FIAA1 and the second trace FIAA2, which are electrically connected to the data line, are used to transmit data signals. Both the first trace FIAA1 and the second trace FIAA2 are located in the display area. This design allows for fanout routing in the display area, thereby reducing the bezel of the display panel.

[0136] The first trace FIAA1 and the second trace FIAA2, which are not electrically connected to the data line, can be used to transmit other signals or are in a floating state.

[0137] As an example, such as Figure 6 or Figure 7 As shown, in the first direction X, the first trace FIAA1 is located between two data lines data between two adjacent first power supply branches ELVDD1.

[0138] As another example, such as Figure 8 As shown, in the first direction X, the first trace FIAA1 is located outside the area between the two data lines data between the two adjacent first power supply branches ELVDD1.

[0139] For example, the first trace FIAA1, the first power branch line ELVDD1, and the data line data are located on the same metal layer. This reduces the number of metal layers in the display panel, enabling a thinner and lighter design.

[0140] In some embodiments, such as Figure 2 As shown, the display panel includes a plurality of circuit columns 10b arranged along a first direction X, and the circuit columns 10b include a plurality of pixel circuits 10 arranged along a second direction Y. Figures 5 to 8 As shown, a first power supply branch line ELVDD1 at least partially overlaps with the orthographic projections of the two circuit columns 10b on the substrate.

[0141] For example, two circuit columns 10b can share a single first power supply line ELVDD1. In other words, a single first power supply line ELVDD1 can be electrically connected to the pixel circuits 10 in the two circuit columns 10b via vias, thereby enabling the single first power supply line ELVDD1 to supply power to both circuit columns 10b. In this example, the first power supply line ELVDD1 can have a higher width in the first direction X, while avoiding affecting the light transmittance of the pixels.

[0142] For example, multiple first power lines ELVDD1 are arranged along a first direction X, and multiple second power lines ELVDD2 are arranged along the first direction X. As described above, the number of first power lines ELVDD1 is greater than the number of second power lines ELVDD2.

[0143] For example, the display panel also includes a third power branch line ELVDD3, which extends along a first direction X, and the first power branch line ELVDD1, the second power branch line ELVDD2 and the third power branch line ELVDD3 are electrically connected to each other.

[0144] The extension direction of the third power line ELVDD3 intersects the extension directions of the first power line ELVDD1 and the second power line ELVDD2. The first power line ELVDD1, the second power line ELVDD2, and the third power line ELVDD3 together form a grid-like first power line ELVDD, which can further reduce the voltage drop of the first power line ELVDD and improve display uniformity, especially the display uniformity under high brightness.

[0145] For example, the third power branch ELVDD3 is located on a different metal layer than the first power branch ELVDD1 and the second power branch ELVDD2.

[0146] For example, the first power branch ELVDD1 and the second power branch ELVDD2 are located on the same metal layer, while the third power branch ELVDD3 is located on another metal layer. Alternatively, the first power branch ELVDD1, the second power branch ELVDD2, and the third power branch ELVDD3 are located on three different metal layers.

[0147] For example, such as Figures 5 to 8 As shown, the third power branch line ELVDD3 is connected to the first power branch line ELVDD1 through the first via h1, and the third power branch line ELVDD3 is connected to the second power branch line ELVDD2 through the second via h2.

[0148] As an example, such as Figure 5 , Figure 7 or Figure 8 As shown, multiple third power lines ELVDD3 are arranged at intervals along the first direction X, and each third power line ELVDD3 is electrically connected to two adjacent first power lines ELVDD1. Each third power line ELVDD3 is electrically connected to two adjacent first power lines ELVDD1 through a first via h1, and some third power lines ELVDD3 are electrically connected to second power lines ELVDD2 through a second via h2.

[0149] When multiple third power supply lines ELVDD3 are arranged at intervals along the first direction X, the size of the third power supply line ELVDD3 in the first direction X is smaller than the size of two pixel circuits 10.

[0150] As another example, such as Figure 6 As shown, the third power branch line ELVDD3 is electrically connected to at least three first power branches ELVDD1. For example, the third power branch line ELVDD3 is electrically connected to any one of the first power branches ELVDD1 via a first via h1. Additionally, the third power branch line ELVDD3 is electrically connected to the second power branch line ELVDD2 via a second via h2.

[0151] In this example, the third power branch ELVDD3 is a continuous trace extending in the first direction X.

[0152] For example, when the third power branch line ELVDD3 is electrically connected to at least three first power branches ELVDD1, the size of the third power branch line ELVDD3 in the first direction X is greater than twice the size of a pixel circuit 10.

[0153] In some embodiments, such as Figures 5 to 8As shown, the display panel also includes at least one of a first connecting line vref_1, a second connecting line vref_2, and a third connecting line vref_3 extending along the first direction X.

[0154] The first connection line vref_1 is electrically connected to the first initialization signal line Vref1, the second connection line vref_2 is electrically connected to the second initialization signal line Vref2, and the third connection line vref_3 is electrically connected to the third initialization signal line Vref3.

[0155] The extension directions of the first connecting line vref_1 and the first initialization signal line Vref1 intersect each other, and the two together form a grid, which can reduce the voltage drop of the first initialization signal line and thus improve the uniformity of the display.

[0156] The extension directions of the second connecting line vref_2 and the second initialization signal line Vref2 intersect each other, and the two together form a grid, which can reduce the voltage drop of the second initialization signal line and thus improve the uniformity of the display.

[0157] The extension directions of the third connection line vref_3 and the third initialization signal line Vref3 intersect each other, and the two together form a grid, which can reduce the voltage drop of the third initialization signal line and thus improve the uniformity of the display.

[0158] For example, such as Figure 5 As shown, the first connecting line vref_1 and the second connecting line vref_2 overlap in the second direction Y. Alternatively, as... Figures 6 to 8 As shown, at least two of the first connecting line vref_1, the second connecting line vref_2, and the third connecting line vref_3 are arranged to overlap in the second direction Y.

[0159] For example, the display panel also includes a third power branch line ELVDD3, which extends along a first direction X. The first power branch line ELVDD1, the second power branch line ELVDD2, and the third power branch line ELVDD3 are electrically connected to each other. The third power branch line ELVDD3 and at least one of the first connecting line vref_1, the second connecting line vref_2, and the third connecting line vref_3 are located in the same metal layer.

[0160] For example, such as Figure 5 As shown, the third power supply line ELVDD3 and the first connection line vref_1 and the second connection line vref_2 are located on the same metal layer.

[0161] For example, such as Figure 6As shown, the second connection line vref_2 includes a first part and a second part. The first part of the second connection line vref_2 and the first connection line vref_1, the first initialization signal line Vref1, the second initialization signal line Vref2, the third initialization signal line Vref3, and the second power supply line ELVDD3 are located on the same metal layer. The second part of the second connection line vref_2 and the third power supply line ELVDD3 are located on the same metal layer. The first part of the second connection line vref_2 and the second initialization signal line Vref2 at least partially overlap, and the second part of the second connection line vref_2 at least partially overlaps with the first initialization signal line Vref1 and the third initialization signal line Vref3. The second part of the second connection line vref_2 can be referred to as a crossover. In addition, the first connection line Vref_1 also includes a crossover, and the crossover of the first connection line Vref_1 at least partially overlaps with the second initialization signal line Vref2, the third initialization signal line Vref3, and the second power supply line ELVDD3.

[0162] For example, such as Figure 7 or Figure 8 As shown, the third power supply line ELVDD3 and the first connection line vref_1 and the second connection line vref_2 are located on the same metal layer.

[0163] For example, the display panel provided in this application embodiment includes a low-temperature polycrystalline oxide (LTPO) display panel. For instance... Figure 9 or Figure 10 As shown, the display panel includes a first semiconductor layer B1, a second semiconductor layer B2, a first gate metal layer M1, a capacitor metal layer MC, a second gate metal layer GATO, a third metal layer SD1, a fourth metal layer SD2, and an anode metal layer RE. Figure 10 It also includes a fifth metal layer, SD3. Among them, GI1, GI2, GI3, IMD, ILD1, PLN1, PLN2, PLN3, VIA, PDL, etc. represent insulating layers.

[0164] For example, the material of the first semiconductor layer B1 includes low-temperature poly-silicon (LTPS), and the material of the second semiconductor layer B2 includes indium gallium zinc oxide (IGZO).

[0165] As an example, please refer to the reference. Figure 5 and Figure 9The first connection line Vref_1, the second connection line Vref_2, and the third power supply line ELVDD3 are located on the third metal layer SD1. The first power supply line ELVDD1, the second power supply line ELVDD2, the data line data, the first initialization signal line Vref1, and the second initialization signal line Vref2 are located on the fourth metal layer M4.

[0166] in addition, Figure 5 In this context, the PLN2 hole is used for electrical connection between the third metal layer SD1 and the fourth metal layer SD2.

[0167] As another example, please refer to the reference. Figure 6 and Figure 10 The first initialization signal line Vref1, the second initialization signal line Vref2, the third initialization signal line Vref3, the second power supply branch line ELVDD2, the first part of the first connection line Vref_1, and the first part of the second connection line Vref_2 are located on the third metal layer SD1. The third power supply branch line ELVDD3, the second trace FIAA2, and the second part of the second connection line Vref_2 (the crossover of the second connection line Vref_2) are located on the fourth metal layer SD2. The first power supply branch line ELVDD1, the data line data, and the first trace FIAA1 are located on the fifth metal layer SD3. The third connection line Vref_3 is located on the second gate metal layer GATO, and the second part of the first connection line Vref_1 (the crossover of the first connection line Vref_1) is located on the first gate metal layer M1.

[0168] in addition, Figure 6 In this diagram, ILD1 is an electrical connection hole between the first gate metal layer M1 and the third metal layer SD1; CNTO is an electrical connection hole between the second gate metal layer GATO and the third metal layer SD1; PLN2 is an electrical connection hole between the third metal layer SD1 and the fourth metal layer SD2; and PLN3 is an electrical connection hole between the fourth metal layer SD2 and the fifth metal layer SD3.

[0169] As yet another example, please refer to the reference. Figure 7 and Figure 9 The third power supply branch line ELVDD3, the first connection line Vref_1, the second connection line Vref_2, and the second trace FIAA2 are located on the third metal layer SD1. The first initialization signal line Vref1, the second initialization signal line Vref2, the third initialization signal line Vref3, the first power supply branch line ELVDD1, the second power supply branch line ELVDD2, and the first trace FIAA1 are located on the fourth metal layer SD2. The third connection line Vref_3 is located on the second gate metal layer GATO.

[0170] in addition, Figure 7In the diagram, the CNTO hole is an electrical connection hole between the second gate metal layer GATO and the third metal layer SD1; the PLN2 hole is an electrical connection hole between the third metal layer SD1 and the fourth metal layer SD2.

[0171] As yet another example, please refer to the reference. Figure 8 and Figure 9 The third power supply branch line ELVDD3, the first connection line Vref_1, the second connection line Vref_2, and the second trace FIAA2 are located on the third metal layer SD1. The first initialization signal line Vref1, the second initialization signal line Vref2, the third initialization signal line Vref3, the first power supply branch line ELVDD1, the second power supply branch line ELVDD2, and the first trace FIAA1 are located on the fourth metal layer SD2. The third connection line Vref_3 is located on the second gate metal layer GATO.

[0172] in addition, Figure 7 In the diagram, the CNTO hole is an electrical connection hole between the second gate metal layer GATO and the third metal layer SD1; the PLN2 hole is an electrical connection hole between the third metal layer SD1 and the fourth metal layer SD2.

[0173] Based on the same technical concept, embodiments of this application also provide a display panel. For example... Figures 2 to 10 As shown, the display panel includes: a substrate 00, a pixel circuit 10, a light-emitting element 20, a first power line ELVDD, a second power line ELVSS, an initialization signal line Vref, and a data line data. The pixel circuit 10 is electrically connected to the first power line ELVDD, the initialization signal line Vref, the data line data, and the first electrode of the light-emitting element 20. The second electrode of the light-emitting element 20 is electrically connected to the second power line ELVSS.

[0174] Multiple pixel circuits 10 are arranged in an array along the first direction X and the second direction Y, and the first direction X and the second direction Y intersect.

[0175] The first power line ELVDD includes a first power branch line ELVDD1 and a second power branch line ELVDD2. The first power branch line ELVDD1 and the second power branch line ELVDD2 are electrically connected to each other, and both the first power branch line ELVDD1 and the second power branch line ELVDD2 extend along the second direction Y.

[0176] The initialization signal line Vref and the second power supply line ELVDD2 are arranged alternately along the first direction X. A first power supply line ELVDD1 overlaps with the orthographic projection of two circuit columns 10b on the substrate. The circuit column 10b includes a plurality of pixel circuits 10 arranged along the second direction Y.

[0177] Two data lines, data, are set between the two adjacent first power supply branches, ELVDD1.

[0178] The orthographic projections of the first power supply line ELVDD1 and the second power supply line ELVDD2 on the substrate may overlap or not overlap.

[0179] According to the display panel provided in the embodiments of this application, the first power line includes a first power branch line and a second power branch line extending along a second direction. The width of the first power branch line in the first direction is different from the width of the second power branch line in the first direction, which is equivalent to widening the width of the first power line in the first direction. This can significantly reduce the voltage drop (IR drop) of the first power line in the display area, thereby improving the display uniformity of the display panel, especially the display uniformity under high brightness.

[0180] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-level is high and the off-level is low. That is, when the gate potential of an N-type transistor is high, its first and second terminals are connected; when the gate potential is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the gate potential of a P-type transistor is low, its first and second terminals are connected; when the gate potential is high, its first and second terminals are off. In specific implementation, the gate of each transistor is used as its control electrode. Furthermore, depending on the signal and type of the gate of each transistor, its first electrode can be used as the source and its second electrode as the drain, or its first electrode can be used as the drain and its second electrode as the source. No distinction is made here. In addition, the on-level and off-level in the embodiments of this application are general terms. The on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / turn off the transistor.

[0181] This application also provides a display device, including the display panel provided in this application. Please refer to... Figure 11 , Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 11 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 11This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0182] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, include: The substrate and a pixel circuit, a light-emitting element, a first power line and a second power line located on the substrate, wherein a first end of the pixel circuit is electrically connected to the first power line, a second end of the pixel circuit is electrically connected to the first electrode of the light-emitting element, and a second electrode of the light-emitting element is electrically connected to the second power line, and the first power line and the second power line are used to provide a power signal for light emission; The plurality of pixel circuits are arranged in an array in a first direction and a second direction, wherein the first direction and the second direction intersect. The first power line includes a first power branch and a second power branch, which are electrically connected to each other and both extend along the second direction. The width of the first power branch in the first direction is different from the width of the second power branch in the first direction.

2. The display panel according to claim 1, characterized in that, The first power supply branch line is electrically connected to the pixel circuit through a via, and the width of the first power supply branch line in the first direction is greater than the width of the second power supply branch line in the first direction. Preferably, the orthographic projection shape of the first power supply branch line on the substrate is different from the orthographic projection shape of the second power supply branch line on the substrate.

3. The display panel according to claim 1, characterized in that, The orthographic projections of the first power branch line and the second power branch line on the substrate do not overlap. The display panel also includes an initialization signal line extending along the second direction. In the first direction, the initialization signal line or the second power branch line is provided between two adjacent first power branch lines. Preferably, the initialization signal line and the second power supply branch line are arranged alternately along the first direction; Preferably, the initialization signal line includes at least one of a first initialization signal line, a second initialization signal line, and a third initialization signal line, wherein the first initialization signal line, the second initialization signal line, the third initialization signal line, and the second power supply branch line are located in the same metal layer; Preferably, in the first direction, multiple first power branches are provided between two adjacent second power branches; Preferably, the orthographic projections of the first initialization signal line and the second initialization signal line on the substrate do not overlap with the orthographic projections of the first power supply branch line on the substrate; Alternatively, the orthographic projections of the first initialization signal line, the second initialization signal line, and the third initialization signal line onto the substrate do not overlap with the orthographic projections of the first power supply branch line onto the substrate; Preferably, the first initialization signal line, the second initialization signal line, and the third initialization signal line are connected to different voltages; Preferably, in the first direction, the second power branch line is located between two data lines between two adjacent first power branches, the first initialization signal line is located between two data lines between two adjacent first power branches, the second initialization signal line is located between two data lines between two adjacent first power branches, and the third initialization signal line is located between two data lines between two adjacent first power branches; or, in the first direction, the second power branch line is located outside the region between two data lines between two adjacent first power branches, the first initialization signal line is located outside the region between two data lines between two adjacent first power branches, the second initialization signal line is located outside the region between two data lines between two adjacent first power branches, and the third initialization signal line is located outside the region between two data lines between two adjacent first power branches. Preferably, the first power branch and the second power branch are located in the same metal layer.

4. The display panel according to claim 1, characterized in that, The first power branch line and the second power branch line are located in different metal layers. An insulating layer is provided between the first power branch line and the second power branch line in the thickness direction of the display panel. The orthographic projection of the first power branch line on the substrate and the orthographic projection of the second power branch line on the substrate at least partially overlap. Preferably, the display panel further includes an initialization signal line extending along the second direction, wherein the orthographic projection of the initialization signal line on the substrate and the orthographic projection of the first power supply branch line on the substrate at least partially overlap; Preferably, the initialization signal line and the second power supply branch line are arranged alternately along the first direction; Preferably, the initialization signal line includes at least one of a first initialization signal line, a second initialization signal line, and a third initialization signal line, wherein the first initialization signal line, the second initialization signal line, the third initialization signal line, and the second power supply branch line are located in the same metal layer; Preferably, the first central axis of the first power branch line and the second central axis of the second power branch line coincide, and the first central axis and the second central axis extend along the second direction; Preferably, the first initialization signal line, the second initialization signal line, and the third initialization signal line are connected to different voltages.

5. The display panel according to claim 1, characterized in that, In the first direction, two data lines extending along the second direction are provided between two adjacent first power supply branches; Preferably, the first power supply line and the data line are located on the same metal layer; Preferably, in at least a portion of the region, in the first direction, a first trace extending along the second direction is provided between two adjacent first power branch lines; Preferably, at least a portion of the data lines are electrically connected to the first trace via a second trace, the second trace extending along the first direction; Preferably, in the first direction, the first trace is located between two data lines between two adjacent first power branches; or, in the first direction, the first trace is located outside the area between two data lines between two adjacent first power branches. Preferably, the first trace, the first power branch, and the data line are located on the same metal layer.

6. The display panel according to claim 1, characterized in that, The display panel includes multiple circuit columns, each circuit column including multiple pixel circuits arranged along the second direction, and a first power supply branch line at least partially overlaps with the orthographic projections of two circuit columns on the substrate; Preferably, the plurality of first power supply branches are arranged along the first direction, and the plurality of second power supply branches are arranged along the first direction; Preferably, the display panel further includes a third power branch line, which extends along the first direction, and the first power branch line, the second power branch line, and the third power branch line are electrically connected to each other. Preferably, the third power branch line is located in a different metal layer than the first power branch line and the second power branch line; Preferably, a plurality of the third power supply branches are arranged at intervals along the first direction, and the third power supply branches are electrically connected to two adjacent first power supply branches; Preferably, in the first direction, the size of the third power supply branch line is smaller than the size of the two pixel circuits; Alternatively, the third power branch line can be electrically connected to at least three of the first power branch lines; Preferably, in the first direction, the size of the third power supply branch line is greater than twice the size of one of the pixel circuits.

7. The display panel according to claim 3 or 4, characterized in that, The display panel further includes at least one of a first connecting line, a second connecting line, and a third connecting line extending along the first direction. At least two of the first connecting line, the second connecting line, and the third connecting line are arranged to overlap in the second direction. The first connecting line is electrically connected to the first initialization signal line, the second connecting line is electrically connected to the second initialization signal line, and the third connecting line is electrically connected to the third initialization signal line. Preferably, the display panel further includes a third power branch line extending along the first direction, wherein the first power branch line, the second power branch line, and the third power branch line are electrically connected to each other, and the third power branch line and at least one of the first connecting line, the second connecting line, and the third connecting line are located in the same metal layer.

8. The display panel according to claim 3 or 4, characterized in that, The pixel circuit includes a driving transistor, a first initialization transistor, a second initialization transistor, and a third initialization transistor; The first terminal of the driving transistor is electrically connected to the first power line. The first terminal of the first initialization transistor is electrically connected to the first initialization signal line, and the second terminal of the first initialization transistor is electrically connected to the gate of the driving transistor. The first terminal of the second initialization transistor is electrically connected to the second initialization signal line, and the second terminal of the second initialization transistor is electrically connected to the first terminal of the light-emitting element; The first terminal of the third initialization transistor is electrically connected to the third initialization signal line, and the second terminal of the third initialization transistor is electrically connected to the first terminal of the driving transistor.

9. A display panel, characterized in that, include: The substrate and a pixel circuit, a light-emitting element, a first power line, an initialization signal line, and a data line located on the substrate, wherein the pixel circuit is electrically connected to the first power line, the initialization signal line, the data line, and the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to the second power line; The plurality of pixel circuits are arranged in an array in a first direction and a second direction, wherein the first direction and the second direction intersect. The first power line includes a first power branch and a second power branch, which are electrically connected to each other, and both the first power branch and the second power branch extend along the second direction. The initialization signal line and the second power supply line are arranged alternately along the first direction, and one of the first power supply lines overlaps with the orthographic projection of two circuit columns on the substrate. The circuit columns include a plurality of pixel circuits arranged along the second direction. Two data lines are provided between two adjacent first power supply branches.

10. A display device, characterized in that, Includes the display panel according to any one of claims 1-9.

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