Display panel, preparation method of display panel and electronic device

Abstract

Embodiments of the present application provide a display panel, a preparation method of the display panel and an electronic device, and relate to the technical field of display. In the display panel, a first protection structure is arranged on a side of the second planarization layer away from the second wiring structure, and a normal projection of the first protection structure on the array substrate covers at least an area where the film layer via hole is located. In this way, the second planarization layer in the area where the film layer via hole is located can be protected by the first protection structure in subsequent light-emitting device patterning and subsequent other etching processes, so as to avoid the second wiring structure being exposed from being over-etched or being short-circuited by the etched residual conductive substance. In this way, it can be ensured that the display panel does not have bright lines or dark line defects, and the display effect of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the display panel, and an electronic device. Background Technology

[0002] Organic Light Emitting Diode (OLED) is considered the next-generation display technology after liquid crystal display (LCD). Due to its superior color and image quality, it is widely used in various consumer electronics products such as smartphones, televisions, laptops, desktop computers, automotive displays, and wearable devices, becoming the mainstream technology in display panels. In traditional display panel manufacturing, a fine metal mask (FMM) is typically used to pattern the light-emitting pixels. FMM technology is mature and has extensive mass production experience. However, FMM technology also suffers from limitations in precision, high development costs, and long development cycles. Fine metal mask-less technology eliminates the limitations of traditional OLED processes on display size, resolution, and other screen performance aspects, offering advantages such as high performance, full-size display, and agile delivery. Patents CN118251982A, CN116648095A, CN117062489A, CN 118742138A, CN118678783A, CN118660598A, CN118675450A, CN118824188A, and CN118781966A describe relevant content on the technology of non-fine metal mask, for reference.

[0003] However, the current manufacturing process of OLED display products still needs further improvement. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above background, this application provides a display panel, a method for manufacturing the display panel, and an electronic device.

[0005] A first aspect of this application provides a display panel, the display panel including a display area and a non-display area, the non-display area including a border area and a bonding area located on the side of the border area away from the display area, the display panel further including:

[0006] An array substrate includes a substrate and a first wiring layer, a first planarization layer, a second wiring layer, and a second planarization layer sequentially stacked in a direction away from the substrate. The first wiring layer includes a plurality of first wiring structures located in the bonding region. The first planarization layer includes a plurality of film-layer vias located in the bonding region. The second wiring layer includes a plurality of second wiring structures located in the display region, the border region, and the bonding region, and electrically connected to corresponding first wiring structures through corresponding film-layer vias. The second planarization layer is located at least in the bonding region.

[0007] The protective layer includes at least a plurality of first protective structures located in the bonding region, the plurality of first protective structures being located on the side of the second planarization layer away from the second trace layer, and the orthogonal projection of the plurality of first protective structures on the substrate at least covering the orthogonal projection of the film layer vias on the substrate.

[0008] In one possible implementation of this application, the second planarization layer is further located in the display area, the array substrate further includes a plurality of pixel driving circuits located in the display area, the plurality of pixel driving circuits being located on the side of the second planarization layer closer to the substrate, the second wiring structure being electrically connected to the plurality of pixel driving circuits in the display area, the protective layer further includes a second protective structure located in the display area, and the display panel further includes:

[0009] A pixel defining layer, located in the display area, is disposed on the side of the second protective structure away from the substrate, and encloses and forms a plurality of pixel openings;

[0010] Multiple light-emitting devices are located in the display area. Each light-emitting device includes a first electrode, a portion of which is located between the second protective structure and the pixel defining layer, and another portion is exposed from the corresponding pixel opening.

[0011] Preferably, the orthographic projection of the first electrode on the substrate lies within the orthographic projection of the second protective structure on the substrate.

[0012] In one possible implementation of this application, the display panel further includes:

[0013] An isolation structure is located on the side of the pixel defining layer away from the array substrate. In the display area, the isolation structure includes an isolation opening, wherein the orthographic projection of the isolation opening on the array substrate covers the orthographic projection of the pixel opening on the array substrate.

[0014] Preferably, the light-emitting device further includes a light-emitting material layer and a second electrode, wherein the first electrode, the light-emitting material layer and the second electrode are stacked in a direction away from the array substrate; wherein the second electrode is electrically connected to the isolation structure.

[0015] In one possible implementation of this application, the display panel further includes a dam located in the border area;

[0016] Preferably, the non-display area surrounds the periphery of the display area, and the border area surrounds the periphery of the display area;

[0017] Preferably, the dam is disposed in the same layer as the first leveling layer and / or the second leveling layer.

[0018] In one possible implementation of this application, the array substrate further includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on the substrate, wherein the second wiring layer is the fourth conductive layer and the first wiring layer is the third conductive layer.

[0019] In one possible implementation of this application, the membrane via exposes at least a portion of the first trace structure;

[0020] The second wiring structure is distributed at least along the sidewall of the membrane via and connected to the first wiring structure exposed by the membrane via. Near the location of the membrane via, the wiring thickness of the second wiring structure is uneven.

[0021] The diameter of the through-hole in the film layer gradually increases from the bottom of the through-hole towards the direction away from the array substrate;

[0022] Preferably, the sidewall thickness of the membrane via gradually decreases towards the center of the membrane via;

[0023] Preferably, the trace thickness of the second trace structure at the opening position near the through-hole of the film layer is greater than the trace thickness of the second trace structure at the opening position away from the through-hole of the film layer.

[0024] In one possible implementation of this application, the thickness of the second planarization layer near the opening of the through-hole in the film layer is less than the thickness of the second planarization layer away from the opening of the through-hole in the film layer.

[0025] In one possible implementation of this application, the orthographic projection of the first protective structure on the array substrate covers the second trace structure near the opening of the via in the film layer;

[0026] Preferably, in the bonding area and in the direction away from the display area, the distance between the edge of the first protective structure and the through-hole of the film layer is 8um-14um.

[0027] In one possible implementation of this application, the display panel further includes a touch function layer, which includes a first touch trace layer, a touch insulating layer, and a second touch trace layer stacked together. The touch insulating layer includes a touch insulating structure located in the bonding area, and the second touch trace layer includes a touch trace structure located in the bonding area. The orthographic projection of the touch trace structure on the substrate is located within the orthographic projection of the touch insulating structure on the substrate.

[0028] In a direction away from the display area, the edges of the touch trace structure and the touch insulation structure projected onto the substrate overlap with the projected images of the film through-holes onto the substrate.

[0029] The touch-sensitive insulating structure is located on the side of the first protective structure away from the substrate, wherein the touch-sensitive insulating structure covers a portion of the first protective structure;

[0030] In a plane perpendicular to the substrate, the first protective structure covered by the touch insulation structure has a first thickness, and the first protective structure not covered by the touch insulation structure has a second thickness, wherein the first thickness is greater than the second thickness.

[0031] In one possible implementation of this application, the display panel further includes an optical adhesive layer located on the side of the touch functional layer away from the array substrate;

[0032] In the bonding area, the orthographic projection of the edge of the first protective structure on the array substrate lies within the orthographic projection of the optical adhesive layer on the array substrate.

[0033] In one possible implementation of this application, the display panel further includes a bonding electrode located in the bonding area, the bonding electrode being electrically connected to the second trace structure;

[0034] The bonding electrode and the second trace structure are disposed on the same layer.

[0035] In one possible implementation of this application, the protective layer comprises an inorganic material layer;

[0036] The protective layer is a single-layer structure of silicon oxide or silicon nitride, or a stacked structure formed by alternating silicon oxide and silicon nitride.

[0037] Preferably, the protective layer is a silicon nitride layer.

[0038] A second aspect of this application also provides a method for manufacturing a display panel, the display panel including a display area and a non-display area, the non-display area including a border area and a bonding area located on the side of the border area away from the display area, the method comprising:

[0039] An array substrate is provided, wherein the array substrate includes a substrate and a first wiring layer, a first planarization layer, a second wiring layer, and a second planarization layer sequentially stacked in a direction away from the substrate. The first wiring layer includes a plurality of first wiring structures located in the bonding region. The first planarization layer includes a plurality of film layer vias located in the bonding region. The second wiring layer includes a plurality of second wiring structures located in the display region, the border region, and the bonding region, and electrically connected to the corresponding first wiring structure through the corresponding film layer vias. The second planarization layer is located at least in the bonding region.

[0040] A protective material layer is fabricated on the array substrate;

[0041] The protective material layer is etched to form a protective layer comprising a plurality of first protective structures located at least in the bonding region, wherein the orthogonal projection of the plurality of first protective structures on the substrate at least covers the orthogonal projection of the film layer vias on the substrate.

[0042] In one possible implementation of this application, after the step of etching the protective material layer and forming a protective layer comprising at least a plurality of first protective structures located in the bonding region, the method further includes:

[0043] A touch functional layer is fabricated on the side of the protective layer away from the array substrate. The touch functional layer includes a first touch wiring layer, a touch insulating layer, and a second touch wiring layer stacked together. The touch insulating layer includes a touch insulating structure located in the bonding area. The second touch wiring layer includes a touch wiring structure located in the bonding area. The orthographic projection of the touch wiring structure on the substrate is located within the orthographic projection of the touch insulating structure on the substrate.

[0044] An optical adhesive layer is fabricated that at least covers the touch functional layer and the protective layer in the bonding area.

[0045] A third aspect of this application also provides an electronic device, the electronic device comprising a display panel as described in any possible implementation of the first aspect, or a display panel prepared by a method for preparing a display panel as described in any possible implementation of the second aspect. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 A schematic diagram illustrating the area distribution of the display panel is provided.

[0048] Figure 2 Example Figure 1 One of the schematic diagrams of the membrane layer in the fixed region of China;

[0049] Figure 3 Example Figure 1 One of the schematic diagrams of the film layer in the central display area;

[0050] Figure 4 Example Figure 1 A schematic diagram of part of the film layer in the middle frame region;

[0051] Figure 5 Example Figure 1 Schematic diagram of the membrane layer in the fixed area of ​​the middle section (Part 2);

[0052] Figure 6 Example Figure 1 Schematic diagram of the membrane layer in the fixed area of ​​China (Part 3);

[0053] Figure 7 Example Figure 1 Schematic diagram of the membrane layer in the fixed area of ​​the Chinese border (Part 4);

[0054] Figure 8 Example Figure 1 Schematic diagram of cable routing in the Zhongbangding area;

[0055] Figure 9 Example Figure 8 Schematic diagram of the cross section at position BB;

[0056] Figure 10 A schematic diagram of one possible structure for an isolation structure is shown;

[0057] Figure 11 An example of another possible structural diagram of the isolation structure is shown;

[0058] Figure 12 Example Figure 1 Schematic diagram of the film layer in the central display area (Part 2);

[0059] Figure 13 Example Figure 1 Schematic diagram of the film layer in the central display area (Part 3);

[0060] Figure 14 A flowchart illustrating the method for manufacturing the display panel provided in this embodiment is shown.

[0061] Figure 15 Example Figure 14 Corresponding process flow diagram;

[0062] Figure 16 Another part of the process flow diagram of the method for manufacturing the display panel provided in this embodiment is illustrated.

[0063] Icons: 1-Display panel; 11-Array substrate; 101-Through-hole in film layer; 1101-Substrate; 111-First wiring layer; 1111-First wiring structure; 112-First planarization layer; 113-Second wiring layer; 1131-Second wiring structure; 114-Second planarization layer; 116-Pixel driving circuit; 12-Isolation structure; 1201-Isolation opening; 121-First isolation portion; 122-Second isolation portion; 123-Third isolation portion; 13-Light-emitting device; 131-First electrode; 132-Light-emitting material layer ; 133-Second electrode; 14-Pixel defining layer; 1401-Pixel opening; 15-Protective layer; 151-First protective structure; 152-Second protective structure; 161-First encapsulation layer; 1611-Encapsulation unit; 162-Second encapsulation layer; 163-Third encapsulation layer; 17-Touch functional layer; 171-Touch insulating structure; 172-Touch wiring structure; 18-Optical adhesive layer; 19-Bonding electrode; 20-Protective material layer; 30-Touch material layer; 301-Touch insulating material layer; 302-Touch conductive material layer. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0065] In the description of this application, it should be noted that the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this application is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0066] Increasing the density of light-emitting devices (i.e., pixel density) in display panels is a crucial way to improve display quality. However, current display panels manufactured using fine metal vapor deposition (FMM) technology are limited by technological constraints that prevent further increases in light-emitting device density. Through long-term research, the inventors discovered that to address the technical challenge of limiting light-emitting device density, some display panels incorporate isolation structures. During the full-layer vapor deposition of the light-emitting material layer and electrodes, these layers can be separated at the isolation structure locations. Through multiple vapor deposition and etching processes, light-emitting devices of different colors can be formed within different isolation openings; this process is also known as light-emitting device patterning. However, these display panels exhibit defects such as dark or bright lines, affecting display quality.

[0067] To address the aforementioned problems, the inventors have innovatively designed the following technical solutions, which will be described in detail below with reference to the accompanying drawings. It should be noted that the deficiencies in the existing solutions are the result of the inventors' practical experience and careful research. Therefore, the discovery process of the aforementioned technical problems and the solutions proposed in this embodiment below are contributions made by the inventors to this application during the invention process, and should not be construed as technical content known to those skilled in the art.

[0068] Please refer to Figure 1 and Figure 2 , Figure 1 A schematic diagram illustrating the area distribution of the display panel is provided. Figure 2 Example Figure 1 A schematic diagram of the film layer in area AB2 of the display panel. The display panel 1 includes a display area AA and a non-display area AB. The non-display area AB includes a border area AB1 and a bonding area AB2 located on the side of the border area AB1 away from the display area AA. For example, the display area AA can be a rectangular area, and the border area AB1 can be an annular area surrounding the display area AA. The border area AB1 can include an upper border area, a lower border area, a left border area, and a right border area. The bonding area AB2 can be located on the side of the lower border area away from the display area AA.

[0069] In this embodiment, the display panel 1 includes an array substrate 11 and a protective layer 15. The array substrate 11 has a multi-layer structure, including a substrate 1101 and a first wiring layer 111, a first planarization layer 112, a second wiring layer 113, and a second planarization layer 114 sequentially stacked along a direction away from the substrate 1101. The first wiring layer 111 includes a plurality of first wiring structures 1111 located in the bonding area AB2. The first planarization layer 112 includes a plurality of film-layer vias 101 located in the bonding area AB2. The second wiring layer 113 includes a plurality of second wiring structures 1131 located in the display area AA, the border area AB1, and the bonding area AB2. In the bonding area AB2, the second wiring structures 1131 are electrically connected to the corresponding first wiring structures 1111 through the film-layer vias 101, wherein the second wiring structures 1131 can be used to transmit data voltage signals Vdata. The second planarization layer 114 is located at least in the bonding area AB2, and the second planarization layer 114 covers the second trace structure 1131.

[0070] The protective layer 15 includes at least one first protective structure 151 located in the bonding region AB2. The first protective structure 151 is located on the side of the second planarization layer 114 away from the second wiring layer 113. The orthogonal projection of the first protective structure 151 on the substrate 1101 at least covers the orthogonal projection of the film layer via 101 on the substrate 1101.

[0071] In this embodiment, for example, the protective layer 15 may include a first protective structure 151, the orthographic projection of the first protective structure 151 on the substrate 1101 covering the orthographic projection of all the film through holes 101 on the substrate 1101; the protective layer 15 may also include a number of first protective structures 151 equal to the number of film through holes 101, the first protective structures 151 and the film through holes 101 are in one-to-one correspondence, and the orthographic projection of the first protective structure 151 on the substrate 1101 covers the orthographic projection of the corresponding film through hole 101 on the substrate 1101.

[0072] After analyzing the causes of dark or bright line defects, the inventors discovered that the aforementioned defects are related to the over-etching of the second trace structure 1131 at the location of the via 101 in the film layer. Specifically, during the patterning of the light-emitting device and subsequent etching processes (such as the patterning of the touch electrode), the second planarization layer 114 at the location of the via 101 in the film layer may be etched, thereby exposing the second trace structure 1131 at this location. Over-etching of the second trace structure 1131 at this location leads to the breakage or increased obstruction of the second trace structure 1131, thus forming a bright line defect; or the exposed adjacent second trace structures 1131 are connected by the conductive material remaining after etching, thereby short-circuiting the adjacent second trace structures 1131, thus forming a dark line defect.

[0073] To address the aforementioned technical issues, this embodiment of the application provides a first protective structure 151 on the side of the second planarization layer 114 away from the second trace structure 1131, ensuring that the orthogonal projection of the first protective structure 151 on the array substrate 11 at least covers the area where the film through-hole 101 is located. In this way, during subsequent patterning of light-emitting devices and other etching processes, the first protective structure 151 can protect the second planarization layer 114 in the area where the film through-hole 101 is located, preventing the second trace structure 1131 from being exposed and short-circuited by over-etching or residual conductive material after etching. This ensures that the display panel 1 will not have bright or dark lines, improving the display effect of the display panel 1.

[0074] Further, please refer to Figure 3 The second planarization layer 114 is also located in the display area AA. The array substrate 11 also includes a plurality of pixel driving circuits 116 located in the display area AA. The plurality of pixel driving circuits 116 are located on the side of the second planarization layer 114 close to the substrate 1101. The second wiring structure 1131 electrically connects the plurality of pixel driving circuits 116 in the display area AA. The protective layer 15 also includes a second protective structure 152 located in the display area AA.

[0075] In this embodiment, the display panel 1 further includes a pixel defining layer 14 and a plurality of light-emitting devices 13. The pixel defining layer 14 is located in the display area AA and is disposed on the side of the second protective structure 152 away from the substrate 1101, forming a plurality of pixel openings 1401. In this embodiment, the pixel defining layer 14 can be an organic pixel defining layer or an inorganic pixel defining layer. Preferably, the pixel defining layer 14 is an inorganic pixel defining layer, that is, the pixel defining layer 14 includes inorganic materials. When the pixel defining layer 14 is an inorganic pixel defining layer, the pixel defining layer 14 can be a single-layer structure of silicon oxide (SiOx) or silicon nitride (SiNx), or a stacked structure formed by alternating silicon oxide and silicon nitride.

[0076] Multiple light-emitting devices 13 are located in the display area AA. Each light-emitting device 13 includes a first electrode 131. A portion of the first electrode 131 is located between the second protective structure 152 and the pixel defining layer 14, while another portion of the first electrode 131 is exposed from the corresponding pixel opening 1401. The first electrode 131 is electrically connected to the pixel driving circuit 116 through the second wiring structure 1131. The orthographic projection of the first electrode 131 on the substrate 1101 lies within the orthographic projection of the second protective structure 152 on the substrate 1101. This design isolates the first electrode 131 from moisture in the film layer below it, preventing corrosion and preventing moisture from entering the device and causing dark spots.

[0077] Furthermore, please refer to again Figure 3 In this embodiment, the display panel 1 further includes an isolation structure 12, which is located on the side of the pixel defining layer 14 away from the array substrate 11. In the display area AA, the isolation structure 12 encloses a plurality of isolation openings 1201 on the pixel defining layer 14. In this embodiment, the pixel openings 1401 and the isolation openings 1201 correspond one-to-one, and the pixel openings 1401 communicate with their corresponding isolation openings 1201. For example, the orthographic projection of the pixel opening 1401 onto the array substrate 11 lies within the orthographic projection of the isolation opening 1201 onto the array substrate 11. At least a portion of the light-emitting devices 13 are located within their corresponding pixel openings 1401.

[0078] Furthermore, please refer to again Figure 3 The light-emitting device 13 further includes a light-emitting material layer 132 and a second electrode 133. The first electrode 131, the light-emitting material layer 132, and the second electrode 133 are stacked in a direction away from the array substrate 11, wherein the second electrode 133 is electrically connected to the isolation structure 12. In this embodiment, the first electrode 131 can be the anode of the light-emitting device 13, and the second electrode 133 can be the cathode of the light-emitting device 13.

[0079] Please refer to Figure 4 In this embodiment, the display panel 1 further includes a dam 22 located in the border area AB1. The dam 22 forms a barrier structure to prevent the organic material layer from overflowing, so that the organic material layer is only located on the side of the dam 22 facing the display area AA, thereby ensuring the effectiveness of the encapsulation of the display panel 1.

[0080] In this embodiment, the non-display area AB surrounds the periphery of the display area AA, the border area AB1 surrounds the periphery of the display area AA, and the orthographic projection of the dam 22 on the substrate 1101 also surrounds the periphery of the display area AA. The dam 22 and the first planarization layer 112 and / or the second planarization layer 114 are disposed in the same layer, that is, the dam 22 can be composed of at least one of the first planarization layer 112 and the second planarization layer 114 of the same layer and the same material.

[0081] For example, please refer to Figure 5 The array substrate 11 includes a first conductive layer (M1), a second conductive layer (M2), a third conductive layer (M3), and a fourth conductive layer (M4) sequentially stacked on a substrate 1101. A second wiring layer 113 corresponds to the fourth conductive layer M4, and a first wiring layer 111 corresponds to the third conductive layer M3. A second wiring structure 1131 can be formed from the fourth conductive layer M4, and a first wiring structure 1111 can be formed from the third conductive layer M3. The second wiring structure 1131 is connected to the first wiring structure 1111 through a film via 101 to achieve cross-film electrical signal transmission.

[0082] In this embodiment, the membrane via 101 exposes at least a portion of the first wiring structure 1111, and the second wiring structure 1131 is distributed at least along the sidewall of the membrane via 101 and connected to the exposed first wiring structure 1111.

[0083] Further research by the inventors revealed that the trace thickness of the second trace structure 1131 is uneven near the location of the through-hole 101 in the film layer. For details, please refer to [link / reference needed]. Figure 2 The trace thickness d2 of the second trace structure 1131 near the opening of the via 101 is greater than the trace thickness d1 of the second trace structure 1131 away from the opening of the via 101. The reason for the above-mentioned film thickness distribution of the second trace structure 1131 is that the aperture of the via 101 gradually increases from the bottom of the via 101 away from the array substrate 11, the sidewall thickness of the via 101 gradually decreases towards the center of the via, and the curvature of the sidewall of the via 101 is smaller near the opening. At the opening of the via 101, metal is more easily deposited to form a thicker second trace structure 1131.

[0084] Please refer to this again. Figure 2 Because the thickness d2 of the second wiring structure 1131 near the opening of the via 101 is greater than the thickness d1 of the second wiring structure 1131 away from the opening of the via 101, the thickness d4 of the second planarization layer 114 near the opening of the via 101 will be less than the thickness d3 of the second planarization layer 114 away from the opening of the via 101. That is, the thickness of the second planarization layer 114 near the opening of the via 101 is thinner. This makes the second planarization layer 114 at this location easier to completely etch during patterning of the light-emitting device and subsequent etching processes, exposing the second wiring structure 1131 at this location. This increases the risk of the second wiring structure 1131 being over-etched or connected by residual conductive material from etching at this location.

[0085] To address the aforementioned technical issues, in this embodiment, the orthogonal projection of the first protective structure 151 in the protective layer 15 onto the array substrate 11 covers the second trace structure 1131 located near the opening of the via 101 in the film layer. This design allows the first protective structure 151 to cover the thinnest part of the second planarization layer 114, preventing the second trace structure 1131 at that location from being exposed after the second planarization layer 114 at that location is completely etched.

[0086] In this embodiment, please refer again. Figure 2In the direction away from the display area AA and in the bonding area AB2, the distance L between the edge of the first protective structure 151 and the film layer via 101 is 8µm-14µm. The distance L between the edge of the first protective structure 151 and the film layer via 101 refers to the distance between the edge of the first protective structure 151 and the bottom of the film layer via 101 near that edge. Exemplarily, the distance L includes 8µm, 8.1µm, 8.35µm, 8.55µm, 8.84µm, 9.2µm, 9.8µm, 10µm, 10.25µm, 10.7µm, 11.1µm, 11.6µm, 12µm, 12.4µm, 12.75µm, 13.1µm, 13.5µm, 13.85µm, or 14µm, etc.

[0087] In this embodiment, the protective layer 15 includes an etching-resistant inorganic material layer, meaning the material of the protective layer 15 may include an etching-resistant inorganic material. The protective layer 15 can be a single-layer structure of silicon oxide or silicon nitride, or it can be a stacked structure formed by alternating layers of silicon oxide and silicon nitride. Optionally, the protective layer 15 is a single-layer structure of silicon nitride, meaning the protective layer 15 is a silicon nitride layer.

[0088] Further, please refer to Figure 6 The display panel 1 also includes a touch function layer, which includes a first touch wiring layer, a touch insulating layer and a second touch wiring layer stacked together. The touch insulating layer includes a touch insulating structure 171 located in the bonding area AB2, and the second touch wiring layer includes a touch wiring structure 172 located in the bonding area AB2. The orthographic projection of the touch wiring structure 172 on the substrate 1101 is located within the orthographic projection of the touch insulating structure 171 on the substrate 1101.

[0089] In the direction away from the display area AA, the edges of the touch trace structure 172 and the touch insulation structure 171 projected onto the substrate 1101 overlap with the projection of the film through hole 101 onto the substrate 1101. That is, the ends of the touch trace structure 172 and the touch insulation structure 171 on the side away from the display area AA are located above the film through hole 101.

[0090] In this embodiment, please refer again. Figure 6 The touch-sensitive insulating structure 171 is located on the side of the first protective structure 151 away from the substrate 1101, wherein the touch-sensitive insulating structure 171 covers a portion of the first protective structure 151. In a plane perpendicular to the substrate 1101, the first protective structure 151 covered by the touch-sensitive insulating structure 171 has a first thickness, and the first protective structure 151 not covered by the touch-sensitive insulating structure 171 has a second thickness, wherein the first thickness is greater than the second thickness. That is, the portion of the touch-sensitive insulating structure 171 not covered by the first protective structure 151 will be partially etched.

[0091] In this embodiment, in the bonding area AB2, the orthographic projection of the touch insulating structure 171 on the substrate 1101 is located within the orthographic projection of the first protective structure 151 on the substrate 1101. This prevents the etching solution from etching the second planarization layer 114 during the patterning process of forming the touch insulating structure 171, thus preventing the second wiring structure 1131 from being exposed or even connected by over-etched or etched residual conductive material.

[0092] Specifically, in one possible implementation, both the second wiring structure 1131 and the touch wiring structure 172 adopt a titanium-aluminum-titanium stacked structure. Without the first protective structure 151, the second planarization layer 114 near the via 101 is easily etched away, exposing the second wiring structure 1131 near the via 101. The exposed titanium and aluminum top layers of the second wiring structure 1131 may be etched, leading to increased impedance and causing poor bright lines. Furthermore, a step difference exists at the boundary of the touch insulating structure 171, making it easy for the conductive layer to be incompletely etched at this step difference during the patterning process of the touch wiring structure 172, leaving residues. These residual conductive materials can short-circuit adjacent second wiring structures 1131, causing poor dark lines. The first protective structure 151 prevents these issues from occurring, thus ensuring the display effect of the display panel 1.

[0093] Further, please refer to Figure 7 The display panel 1 also includes an optical adhesive layer 18, which is located on the side of the touch functional layer away from the array substrate 11. In the bonding area AB2, the orthographic projection of the edge of the first protective structure 151 onto the array substrate 11 lies within the orthographic projection of the optical adhesive layer 18 onto the array substrate 11. That is, in the bonding area AB2, the first protective structure 151 is covered by the optical adhesive layer 18. This design allows the first protective structure 151 to be protected by the optical adhesive layer 18, preventing it from peeling off from other film layers due to stress during subsequent processes, thus protecting the signal traces underneath.

[0094] Please refer to Figure 8 and Figure 9 In this embodiment, the display panel 1 further includes a bonding electrode 19 located in the bonding area AB2, and the bonding electrode 19 is connected to the second trace structure 1131. The bonding electrode 19 and the second trace structure 1131 are disposed in the same layer, meaning that the bonding electrode 19 and the second trace structure 1131 can be formed from the same conductive layer, i.e., the materials of the bonding electrode 19 and the second trace structure 1131 can be the same.

[0095] In this embodiment, please refer to Figure 10The isolation structure 12 includes a first isolation portion 121 and a second isolation portion 122 stacked sequentially. The orthographic projection of the first isolation portion 121 on the array substrate 11 lies within the orthographic projection of the second isolation portion 122 on the array substrate 11. The second isolation portion 122 extends relative to the first isolation portion 121 toward the corresponding isolation opening 1201. In a cross-section perpendicular to the plane of the array substrate 11 and passing through the center of the isolation opening 1201, the cross-section of the isolation structure 12 can be T-shaped. The first isolation portion 121 is a conductive isolation portion, and the first electrode 131 can be electrically connected to the first isolation portion 121. For example, the first electrode 131 is electrically connected by overlapping with the first isolation portion 121.

[0096] Further, please refer to Figure 11 In this embodiment, the isolation structure 12 further includes a third isolation portion 123. The third isolation portion 123, the first isolation portion 121, and the second isolation portion 122 are sequentially stacked in a direction away from the array substrate 11. The orthographic projection of the first isolation portion 121 onto the array substrate 11 may lie within the orthographic projection of the third isolation portion 123 onto the array substrate 11. The cross-section of the isolation structure 12 may be I-shaped on a cross-section perpendicular to the plane of the array substrate 11 and passing through the center of the isolation opening 1201. The third isolation portion 123 is a conductive isolation portion, and the first electrode 131 can also be electrically connected to the third isolation portion 123. For example, the first electrode 131 is electrically connected by overlapping with the third isolation portion 123.

[0097] Optionally, the first isolation part 121 may be made of aluminum, silver or copper, the second isolation part 122 may be made of titanium or molybdenum, and the third isolation part 123 may be made of molybdenum or titanium.

[0098] Furthermore, in this embodiment, please refer to Figure 12 The display panel 1 also includes a thin-film encapsulation layer located on the light-emitting side of the light-emitting device 13. The thin-film encapsulation layer includes a first encapsulation layer 161, which includes multiple encapsulation units 1611. In the display area AA, different encapsulation units 1611 are used to encapsulate the light-emitting devices 13 within different isolation openings 1201. Exemplarily, two adjacent encapsulation units 1611 used to encapsulate light-emitting devices 13 of different colors are disconnected on the side of the isolation structure 12 away from the array substrate 11; two adjacent encapsulation units 1611 used to encapsulate light-emitting devices of the same color can be connected to each other on the side of the isolation structure 12 away from the array substrate 11.

[0099] Further, please refer to Figure 13 In this embodiment, the thin film encapsulation layer further includes a second encapsulation layer 162, which is located on the side of the encapsulation unit 1611 away from the array substrate 11, and the second encapsulation layer 162 at least covers the encapsulation unit 1611.

[0100] The second encapsulation layer 162 has a flat surface on the side away from the array substrate 11.

[0101] Furthermore, please refer to again Figure 13 The thin-film encapsulation layer also includes a third encapsulation layer 163, which is located on the side of the second encapsulation layer 162 away from the array substrate 11.

[0102] Optionally, the first encapsulation layer 161 and the third encapsulation layer 163 are inorganic encapsulation layers, and the second encapsulation layer 162 is an organic encapsulation layer. For example, the first encapsulation layer 161 and the third encapsulation layer 163 can be formed by chemical vapor deposition (CVD), and the second encapsulation layer 162 can be formed by inkjet printing (IJP).

[0103] It is understood that the display panel 1 may also include a touch function layer, an optical adhesive layer, a polarizer and a cover plate, etc., which are stacked sequentially on the side of the third encapsulation layer 163 away from the substrate 1101. The above-mentioned film layers are conventional film layers of the display panel, and will not be described in detail here.

[0104] Based on the same inventive concept, this application also provides a method for manufacturing a display panel, which can manufacture the display panel described in the previous embodiments. The following describes the method in conjunction with... Figure 14 The flowchart shown and Figure 15 The preparation process diagram shown provides a detailed description of this preparation method.

[0105] Step S110: Provide an array substrate 11.

[0106] In this embodiment, the array substrate 11 includes a substrate 1101 and a first wiring layer 111, a first planarization layer 112, a second wiring layer 113, and a second planarization layer 114 sequentially stacked in a direction away from the substrate 1101. The first wiring layer 111 includes a plurality of first wiring structures 1111 located in the bonding region AB2. The first planarization layer 112 includes a plurality of film-layer vias 101 located in the bonding region AB2. The second wiring layer 113 includes a plurality of second wiring structures 1131 located in the display region AA, the border region AB1, and the bonding region AB2. In the bonding region AB2, the second wiring structures 1131 are electrically connected to the corresponding first wiring structures 1111 through the film-layer vias 101, wherein the second wiring structures 1131 can be used to transmit data voltage signals Vdata. The second planarization layer 114 is located at least in the bonding region AB2 and covers the second wiring structures 1131.

[0107] Step S120: A protective material layer 20 is fabricated on the array substrate 11.

[0108] The protective material layer 20 is made of inorganic materials. For example, the protective material layer 20 can be made by chemical vapor deposition. The material of the protective material layer 20 can be silicon nitride.

[0109] Step S130: Etching the protective material layer 20 to form a protective layer 15 including a plurality of first protective structures 151 located at least in the bonding region AB2.

[0110] Among them, the orthogonal projection of the plurality of first protective structures 151 on the substrate 1101 at least covers the orthogonal projection of the film through-hole 101 on the substrate 1101.

[0111] In the above preparation method, a protective layer 15 is prepared on the side of the second planarization layer 114 away from the second wiring structure 1131 in the array substrate 11, and the orthogonal projection of the first protective structure 151 in the protective layer 15 on the substrate 1101 at least covers the area where the film layer via 101 is located. In this way, during the subsequent patterning of light-emitting devices and other subsequent etching processes, the second planarization layer 114 in the area where the film layer via 101 is located can be protected by the first protective structure 151, avoiding the second wiring structure 1131 being exposed and shorted by over-etching or the conductive material remaining after etching. This can ensure that the display panel 1 will not have bright lines or dark lines, and improve the display effect of the display panel 1.

[0112] Further, please refer to Figure 16 After step S130, the method for preparing the display panel provided in this application embodiment further includes the following steps.

[0113] First, a touch function layer is fabricated on the side of the protective layer 15 away from the array substrate 11. The touch function layer includes a first touch wiring layer, a touch insulating layer, and a second touch wiring layer stacked together. The touch insulating layer includes a touch insulating structure located in the bonding area AB2. The second touch wiring layer includes a touch wiring structure located in the bonding area AB2. The orthographic projection of the touch wiring structure on the substrate 1101 is located within the orthographic projection of the touch insulating structure on the substrate 1101.

[0114] Specifically, a touch material layer 30 can be fabricated on the side of the protective layer 15 away from the array substrate 11. The touch material layer 30 is etched to form a touch functional layer 17. The touch functional layer 17 includes a touch insulating structure 171 formed by the etched touch insulating material layer 301 and a touch wiring structure 172 formed by the etched touch conductive material layer 302.

[0115] Next, an optical adhesive layer 17 is fabricated that covers at least the touch function layer 17 and the protective layer 15 in the bonding area AB2.

[0116] Based on the same inventive concept, embodiments of this application also provide an electronic device, which includes the display panel provided in this application. The electronic device may include smartphones, tablets, in-vehicle display devices, smart wearable devices, televisions, laptops, and other devices with display functions.

[0117] This application provides a display panel, a method for manufacturing the display panel, and an electronic device. In the display panel, a first protective structure is provided on the side of the second planarization layer away from the second wiring structure, and the orthogonal projection of the first protective structure on the array substrate at least covers the area where the film layer via is located. In this way, during subsequent patterning of light-emitting devices and other subsequent etching processes, the second planarization layer in the area where the film layer via is located can be protected by the first protective structure, avoiding over-etching or short-circuiting by residual conductive material after the second wiring structure is exposed. This ensures that the display panel will not have bright or dark lines, thus improving the display effect of the display panel.

[0118] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area. The non-display area includes a border area and a bonding area located on the side of the border area away from the display area. The display panel also includes: An array substrate includes a substrate and a first wiring layer, a first planarization layer, a second wiring layer, and a second planarization layer sequentially stacked in a direction away from the substrate. The first wiring layer includes a plurality of first wiring structures located in the bonding region. The first planarization layer includes a plurality of film-layer vias located in the bonding region. The second wiring layer includes a plurality of second wiring structures located in the display region, the border region, and the bonding region, and electrically connected to corresponding first wiring structures through corresponding film-layer vias. The second planarization layer is located at least in the bonding region. The protective layer includes at least one first protective structure located in the bonding region, the at least one first protective structure being located on the side of the second planarization layer away from the second trace layer, and the orthogonal projection of the at least one first protective structure on the substrate at least covering the orthogonal projection of the film layer via on the substrate.

2. The display panel as described in claim 1, characterized in that, The second planarization layer is also located in the display area. The array substrate further includes a plurality of pixel driving circuits located in the display area. The plurality of pixel driving circuits are located on the side of the second planarization layer closer to the substrate. The second wiring structure is electrically connected to the plurality of pixel driving circuits in the display area. The protective layer further includes a second protective structure located in the display area. The display panel further includes: A pixel defining layer, located in the display area, is disposed on the side of the second protective structure away from the substrate, and encloses and forms a plurality of pixel openings; Multiple light-emitting devices are located in the display area. Each light-emitting device includes a first electrode, a portion of which is located between the second protective structure and the pixel defining layer, and another portion is exposed from the corresponding pixel opening. Preferably, the orthographic projection of the first electrode on the substrate lies within the orthographic projection of the second protective structure on the substrate.

3. The display panel as described in claim 2, characterized in that, The display panel also includes: An isolation structure is located on the side of the pixel defining layer away from the array substrate. In the display area, the isolation structure includes an isolation opening, wherein the orthographic projection of the isolation opening on the array substrate covers the orthographic projection of the pixel opening on the array substrate. Preferably, the light-emitting device further includes a light-emitting material layer and a second electrode, wherein the first electrode, the light-emitting material layer and the second electrode are stacked in a direction away from the array substrate; wherein the second electrode is electrically connected to the isolation structure.

4. The display panel as described in claim 1, characterized in that, The display panel also includes a dam located in the border area; Preferably, the non-display area surrounds the periphery of the display area, and the border area surrounds the periphery of the display area; Preferably, the dam is disposed in the same layer as the first leveling layer and / or the second leveling layer.

5. The display panel as described in claim 1, characterized in that, The array substrate further includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked sequentially on the substrate, wherein the second wiring layer is the fourth conductive layer and the first wiring layer is the third conductive layer.

6. The display panel as described in claim 1, characterized in that, The membrane vias expose at least a portion of the first wiring structure. The second wiring structure is distributed at least along the sidewall of the membrane via and connected to the first wiring structure exposed by the membrane via. Near the location of the membrane via, the wiring thickness of the second wiring structure is uneven. The diameter of the through-hole in the film layer gradually increases from the bottom of the through-hole towards the direction away from the array substrate; Preferably, the sidewall thickness of the membrane via gradually decreases towards the center of the membrane via; Preferably, the trace thickness of the second trace structure at the opening position near the through-hole of the film layer is greater than the trace thickness of the second trace structure at the opening position away from the through-hole of the film layer.

7. The display panel as described in claim 6, characterized in that, The thickness of the second planarization layer near the opening of the membrane via is less than the thickness of the second planarization layer away from the opening of the membrane via.

8. The display panel as described in claim 1, characterized in that, The orthographic projection of the first protective structure on the array substrate covers the second trace structure near the opening of the via in the film layer; Preferably, in the bonding area and in the direction away from the display area, the distance between the edge of the first protective structure and the through-hole of the film layer is 8um-14um.

9. The display panel as claimed in claim 1, characterized in that, The display panel further includes a touch function layer, which includes a first touch trace layer, a touch insulating layer, and a second touch trace layer stacked together. The touch insulating layer includes a touch insulating structure located in the bonding area, and the second touch trace layer includes a touch trace structure located in the bonding area. The orthographic projection of the touch trace structure on the substrate is located within the orthographic projection of the touch insulating structure on the substrate. In a direction away from the display area, the edges of the touch trace structure and the touch insulation structure projected onto the substrate overlap with the projected images of the film through-holes onto the substrate. The touch-sensitive insulating structure is located on the side of the first protective structure away from the substrate, wherein the touch-sensitive insulating structure covers a portion of the first protective structure; In a plane perpendicular to the substrate, the first protective structure covered by the touch insulation structure has a first thickness, and the first protective structure not covered by the touch insulation structure has a second thickness, wherein the first thickness is greater than the second thickness.

10. The display panel as claimed in claim 9, characterized in that, The display panel further includes an optical adhesive layer, which is located on the side of the touch function layer away from the array substrate; In the bonding area, the orthographic projection of the edge of the first protective structure on the array substrate lies within the orthographic projection of the optical adhesive layer on the array substrate.

11. The display panel as claimed in claim 1, characterized in that, The display panel also includes a bonding electrode located in the bonding area, the bonding electrode being electrically connected to the second trace structure; The bonding electrode and the second trace structure are disposed on the same layer.

12. The display panel as claimed in claim 1, characterized in that, The protective layer includes an inorganic material layer; The protective layer is a single-layer structure of silicon oxide or silicon nitride, or a stacked structure formed by alternating silicon oxide and silicon nitride. Preferably, the protective layer is a silicon nitride layer.

13. A method for manufacturing a display panel, characterized in that, The display panel includes a display area and a non-display area, the non-display area including a border area and a bonding area located on the side of the border area away from the display area, the method including: An array substrate is provided, wherein the array substrate includes a substrate and a first wiring layer, a first planarization layer, a second wiring layer, and a second planarization layer sequentially stacked in a direction away from the substrate. The first wiring layer includes a plurality of first wiring structures located in the bonding region. The first planarization layer includes a plurality of film layer vias located in the bonding region. The second wiring layer includes a plurality of second wiring structures located in the display region, the border region, and the bonding region, and electrically connected to the corresponding first wiring structure through the corresponding film layer vias. The second planarization layer is located at least in the bonding region. A protective material layer is fabricated on the array substrate; The protective material layer is etched to form a protective layer comprising a plurality of first protective structures located at least in the bonding region, wherein the orthogonal projection of the plurality of first protective structures on the substrate at least covers the orthogonal projection of the film layer vias on the substrate.

14. The method for manufacturing a display panel as described in claim 13, characterized in that, After the step of etching the protective material layer and forming a protective layer comprising at least a plurality of first protective structures located in the bonding region, the method further includes: A touch functional layer is fabricated on the side of the protective layer away from the array substrate. The touch functional layer includes a first touch wiring layer, a touch insulating layer, and a second touch wiring layer stacked together. The touch insulating layer includes a touch insulating structure located in the bonding area. The second touch wiring layer includes a touch wiring structure located in the bonding area. The orthographic projection of the touch wiring structure on the substrate is located within the orthographic projection of the touch insulating structure on the substrate. An optical adhesive layer is fabricated that at least covers the touch functional layer and the protective layer in the bonding area.

15. An electronic device, characterized in that, The electronic device includes a display panel as described in any one of claims 1-12, or a display panel prepared by the method described in any one of claims 13-14.

Images