Display panel and display device

Abstract

The application provides a display panel and a display device, and solves the problem of poor display uniformity of display products in the prior art. The display panel comprises a substrate, a plurality of pixel circuits and a first gate signal line, the pixel circuits and the first gate signal line are located on one side of the substrate, and the first gate signal line extends along a first direction; the first gate signal line comprises a first conductor segment, a second conductor segment and a third conductor segment which are connected in sequence along the first direction, and the second conductor segment surrounds a hole region; the first conductor segment comprises a plurality of first sub-conductor segments which are connected in sequence, the third conductor segment comprises a plurality of third sub-conductor segments which are connected in sequence, the length of the orthogonal projection of the first sub-conductor segment, the second conductor segment and the third sub-conductor segment on the substrate in the first direction is equal, the number of the pixel circuits connected by the first sub-conductor segment and the third sub-conductor segment is equal and greater than the number of the pixel circuits connected by the second conductor segment, and the impedance of the first sub-conductor segment, the second conductor segment and the third sub-conductor segment is equal.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, current display products have poor display uniformity. Summary of the Invention

[0004] In view of this, the present application provides a display panel and a display device, which solves the problem of poor display uniformity in the prior art.

[0005] This application provides a display panel, which includes a display area and an aperture area, with the display area surrounding the aperture area. The display panel includes a substrate, a plurality of pixel circuits, and a first gate signal line. The pixel circuits are located on one side of the substrate. The first gate signal line is located on one side of the substrate and extends along a first direction. The first gate signal line includes a first conductor segment, a second conductor segment, and a third conductor segment connected sequentially along the first direction, with the second conductor segment surrounding the aperture area. The first conductor segment includes a plurality of first sub-conductor segments connected sequentially, and the third conductor segment includes a plurality of third sub-conductor segments connected sequentially. The orthographic projections of the first, second, and third sub-conductor segments onto the substrate have equal lengths in the first direction. The number of pixel circuits connected to the first and third sub-conductor segments is equal and greater than the number of pixel circuits connected to the second conductor segment. The impedances of the first, second, and third sub-conductor segments are equal.

[0006] In one embodiment, a second gate signal line is further included, extending along a first direction. The second gate signal line is located on the side of the first gate signal line away from the via region and is adjacent to the first gate signal line. The second gate signal line includes a fourth conductor segment, a fifth conductor segment, and a sixth conductor segment connected sequentially along the first direction. The fifth conductor segment surrounds the via region. The length of the orthographic projection of the fifth conductor segment on the substrate in the first direction is less than the length of the orthographic projection of the second conductor segment on the substrate in the first direction. The number of pixel circuits connected to the fifth conductor segment is greater than the number of pixel circuits connected to the second conductor segment. The impedances of the fifth conductor segment and the second conductor segment are equal.

[0007] In one embodiment, the fourth conductor segment includes a plurality of fourth sub-conductor segments, the sixth conductor segment includes a plurality of sixth sub-conductor segments, and the fourth sub-conductor segment, the sixth sub-conductor segment, and the first sub-conductor segment have equal lengths in the first direction when projected onto the substrate, the number of connected pixel circuits is equal, and the impedance is equal.

[0008] In one embodiment, a third gate signal line is further included, which extends along a first direction. The third gate signal line includes a plurality of seventh conductor segments. The seventh conductor segments and the first sub-conductor segments have the same length in the first direction when projected onto the substrate. They are connected to the same number of pixel circuits and have the same impedance.

[0009] In one embodiment, one of the plurality of seventh conductor segments is located on the side of the second conductor segment away from the hole area.

[0010] In one embodiment, the first sub-conductor segment includes a plurality of first conductive portions and a plurality of second conductive portions, the second conductive portions being connected to adjacent first conductive portions, the second conductive portions and the first conductive portions being located in different conductive layers, and the orthographic projections of the second conductive portions on the substrate and the orthographic projections of the first conductive portions on the substrate overlapping; the third sub-conductor segment includes a plurality of third conductive portions and a plurality of fourth conductive portions, the fourth conductive portions being connected to adjacent third conductive portions, the fourth conductive portions and the third conductive portions being located in different conductive layers, and the orthographic projections of the fourth conductive portions on the substrate and the orthographic projections of the third conductive portions on the substrate overlapping.

[0011] In one embodiment, the second conductor segment is in the same layer as the first conductive portion and the third conductive portion.

[0012] In one embodiment, the orthographic projections of the first and third conductor segments onto the substrate are concave-convex curves.

[0013] In one embodiment, the orthographic projection of the second conductor segment onto the substrate is arc-shaped.

[0014] A second aspect of this application provides a display device including the aforementioned display panel.

[0015] According to the embodiments of this application, the display panel and display device include a display area and an aperture area, with the display area surrounding the aperture area. The display panel includes a substrate, multiple pixel circuits, and a first gate signal line. The pixel circuits are located on one side of the substrate. The first gate signal line is located on one side of the substrate and extends along a first direction. The first gate signal line includes a first conductor segment, a second conductor segment, and a third conductor segment connected sequentially along the first direction. The second conductor segment surrounds the aperture area. The first conductor segment includes multiple first sub-conductor segments connected sequentially, and the third conductor segment includes multiple third sub-conductor segments connected sequentially. The orthographic projections of the first, second, and third sub-conductor segments onto the substrate have equal lengths in the first direction. The number of pixel circuits connected to the first and third sub-conductor segments is equal and greater than the number of pixel circuits connected to the second conductor segment. The impedances of the first, second, and third sub-conductor segments are equal. The above embodiment sets the impedance of the second conductor segment closer to the hole area and the first and third sub-conductor segments farther from the hole area in the first gate signal line to be equal. Therefore, the difference in the signal controlling the pixel circuit by the first sub-conductor segment, the third sub-conductor segment and the second conductor end is small, thereby reducing the brightness difference of the sub-pixels corresponding to different pixel circuits and improving the display uniformity of the display panel. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the cross-sectional structure of a display module in related technologies.

[0017] Figure 2a yes Figure 1 The diagram shows the structure of the first sub-lead segment of the display panel.

[0018] Figure 2b yes Figure 1 The diagram shows the structure of the third sub-lead segment of the display panel.

[0019] Figure 3 yes Figure 1 The diagram shows another partial structure of the first gate signal line of the display panel.

[0020] Figure 4 This is a cross-sectional structural diagram of the display panel provided in the second embodiment of this application.

[0021] Figure 5 This is a partial structural schematic diagram of the display panel provided in the third embodiment of this application.

[0022] Figure 6a yes Figure 5 The diagram shows the structure of the fourth sub-lead segment of the display panel.

[0023] Figure 6b yes Figure 5The diagram shows the structure of the sixth sub-lead segment of the display panel.

[0024] Figure 7 yes Figure 5 This is a schematic diagram of another partial structure of the second gate signal line of the display panel.

[0025] Figure 8 This is a partial structural schematic diagram of the display panel provided in the fourth embodiment of this application.

[0026] Figure 9 This is a partial structural schematic diagram of the display panel provided in the fifth embodiment of this application.

[0027] Figure 10 This is a schematic diagram of the cross-sectional structure of the display module provided in the embodiment of this application.

[0028] Figure 11 This is a schematic diagram of the structure of the display device provided in the embodiments of this application. Detailed Implementation

[0029] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0030] Current display devices typically include a front-facing camera, necessitating either a punch-hole design or an under-display camera. Because the load on the gate signal lines differs between the punch-hole area and the display area, this difference in signal attenuation ultimately leads to uneven brightness and poor display uniformity.

[0031] In view of this, embodiments of this application provide a display panel and a display device. The display panel includes a display area and an aperture area, with the display area surrounding the aperture area. The display panel includes a substrate, a plurality of pixel circuits, and a first gate signal line. The pixel circuits are located on one side of the substrate. The first gate signal line is located on one side of the substrate and extends along a first direction. The first gate signal line includes a first conductor segment, a second conductor segment, and a third conductor segment connected sequentially along the first direction. The second conductor segment surrounds the aperture area. The first conductor segment includes a plurality of first sub-conductor segments connected sequentially, and the third conductor segment includes a plurality of third sub-conductor segments connected sequentially. The orthographic projections of the first, second, and third sub-conductor segments onto the substrate have equal lengths in the first direction. The number of pixel circuits connected to the first and third sub-conductor segments is equal and greater than the number of pixel circuits connected to the second conductor segment. The impedances of the first, second, and third sub-conductor segments are equal. The above embodiment sets the impedance of the second conductor segment closer to the hole area and the first and third sub-conductor segments farther from the hole area in the first gate signal line to be equal. Therefore, the difference in the signal controlling the pixel circuit by the first sub-conductor segment, the third sub-conductor segment and the second conductor end is small, thereby reducing the brightness difference of the sub-pixels corresponding to different pixel circuits and improving the display uniformity of the display panel.

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a structure is referred to as being "on" or "below" another structure, the structure may be directly on or below the other structure, or there may be intermediate structures. The same reference numerals always indicate the same structure. Structures referred to herein include any of the following: membrane, element, device, component, assembly.

[0034] When a structure is referred to as being “connected” to another structure, it can be directly connected to the other structure or indirectly connected to the other structure by means of one or more intermediate structures placed between them.

[0035] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0036] In this specification, the term "same-layer arrangement" refers to a structure formed by two (or more) structures through the same patterning process, and their materials may be the same or different.

[0037] Figure 1 This is a partial structural schematic diagram of the display panel provided in the first embodiment of this application. For example... Figure 1 As shown, the display panel 100 includes a display area 101 and an aperture area 102, with the display area 101 surrounding the aperture area 102. The display panel 100 includes a substrate 10, a plurality of pixel circuits 20, and a first gate signal line 30. The pixel circuits 20 are located on one side of the substrate 10, and the first gate signal line 30 is located on one side of the substrate 10. The first gate signal line 30 extends along a first direction X and includes a first conductor segment 31, a second conductor segment 32, and a third conductor segment 33 connected sequentially along the first direction. The second conductor segment 32 surrounds the aperture area 102.

[0038] The first conductor segment 31 includes a plurality of first sub-conductor segments 311 connected in sequence, and the third conductor segment 33 includes a plurality of third sub-conductor segments 331 connected in sequence. The length L1 of the orthographic projection of the first sub-conductor segment 311 on the substrate 10 in the first direction X, the length L2 of the orthographic projection of the second conductor segment 32 on the substrate 10 in the first direction X, and the length L3 of the orthographic projection of the third sub-conductor segment 331 on the substrate 10 in the first direction X are equal. The number of pixel circuits 20 connected to the first sub-conductor segment 311 is equal to the number of pixel circuits 20 connected to the second sub-conductor segment 331, and is greater than the number of pixel circuits 20 connected to the second conductor segment 32. The impedances of the first sub-conductor segment 311, the second conductor segment 32, and the third sub-conductor segment 331 are equal.

[0039] This application provides a display panel and a display device. The display panel includes a display area and an aperture area, with the display area surrounding the aperture area. The display panel includes a substrate, a plurality of pixel circuits, and a first gate signal line. The pixel circuits are located on one side of the substrate. The first gate signal line is located on one side of the substrate and extends along a first direction. The first gate signal line includes a first conductor segment, a second conductor segment, and a third conductor segment connected sequentially along the first direction. The second conductor segment surrounds the aperture area. The first conductor segment includes a plurality of first sub-conductor segments connected sequentially, and the third conductor segment includes a plurality of third sub-conductor segments connected sequentially. The lengths of the orthographic projections of the first sub-conductor segments, the second conductor segment, and the third sub-conductor segments on the substrate in the first direction X are equal. The number of pixel circuits connected to the first sub-conductor segments and the third sub-conductor segments are equal and greater than the number of pixel circuits connected to the second conductor segment. The impedances of the first sub-conductor segments, the second conductor segment, and the third sub-conductor segments are equal. The above embodiment sets the impedance of the second conductor segment closer to the hole area and the first and third sub-conductor segments farther from the hole area in the first gate signal line to be equal. Therefore, the difference in the signal controlling the pixel circuit by the first sub-conductor segment, the third sub-conductor segment and the second conductor end is small, thereby reducing the brightness difference of the sub-pixels corresponding to different pixel circuits and improving the display uniformity of the display panel.

[0040] Optionally, in one embodiment, the substrate 10 can be a substrate, which may include, but is not limited to, any one of conductive silicon (Si) substrates, silicon oxide (SiOx) substrates, aluminum oxide (Al2O3) substrates (i.e., sapphire substrates), silicon carbide (SiC) substrates, and gallium nitride (GaN) substrates. Furthermore, the substrate can also be a flexible substrate, for example, a flexible substrate made of polyimide (PI).

[0041] Optionally, in one embodiment, the pixel circuit 20 includes transistors and capacitors. It should be understood that the embodiments of this application do not limit the specific structure of the pixel circuit 20; for example, the pixel circuit 20 can be a 2T2C pixel circuit, a 7T1C pixel circuit, an 8T1C pixel circuit, etc.

[0042] Optionally, in one embodiment, the orthographic projection of the first gate signal line 30 on the substrate 10 and the orthographic projection of the via region 102 on the substrate 10 do not overlap.

[0043] Optionally, in one embodiment, the orthographic projection of the second conductor segment 32 onto the substrate 10 is arc-shaped.

[0044] Figure 2a yes Figure 1 The diagram shown is a structural schematic of the first sub-conductor segment of the display panel. Figure 2b yes Figure 1The diagram shows the structure of the third sub-conductor segment of the display panel. Figure 2a and Figure 2b As shown, in one embodiment, the first sub-conductor segment 311 includes a plurality of first conductive portions 3111 and a plurality of second conductive portions 3112. The second conductive portions 3112 are connected to adjacent first conductive portions 3111. The second conductive portions 3112 and the first conductive portions 3111 are located in different conductive layers. The orthographic projection of the second conductive portion 3112 on the substrate 10 and the orthographic projection of the first conductive portion 3111 on the substrate 10 overlap, thereby increasing the impedance of the first sub-conductor segment 311.

[0045] In one embodiment, the third sub-conductor segment 331 includes a plurality of third conductive portions 3311 and a plurality of fourth conductive portions 3312. The fourth conductive portions 3312 connect adjacent third conductive portions 3311. The fourth conductive portions 3312 and the third conductive portions 3311 are located in different conductive layers. The orthographic projection of the fourth conductive portion 3312 on the substrate 10 and the orthographic projection of the third conductive portion 3311 on the substrate 10 overlap, thereby increasing the impedance of the third sub-conductor segment 331.

[0046] Furthermore, in one embodiment, the second conductor segment 32 is in the same layer as the first conductive portion 3111 and the third conductive portion 3311.

[0047] Furthermore, in one embodiment, the first conductive part 3111 and the second conductive part 3112 are connected via a via.

[0048] Furthermore, in one embodiment, the third conductive portion 3311 and the fourth conductive portion 3312 are connected via a via.

[0049] Figure 3 yes Figure 1 This is a schematic diagram of another partial structure of the first gate signal line of the display panel. (See diagram below.) Figure 3 As shown, in one embodiment, the orthographic projection of the first conductor segment 31 on the substrate 10 and the orthographic projection of the third conductor segment 33 on the substrate 10 are concave and convex curves, thereby increasing the impedance of the first conductor segment 31 and the third conductor segment 33.

[0050] Figure 4 This is a schematic cross-sectional view of the display panel provided in the second embodiment of this application. (See attached diagram.) Figure 3 As shown, in one embodiment, the display panel 100 may further include a sub-pixel 60, which is located on the side of the pixel circuit 20 away from the substrate 10. The sub-pixel 60 and the pixel circuit 20 are electrically connected and correspondingly arranged. For example, one pixel circuit 20 is connected to one sub-pixel 60; or, for example, at least two pixel circuits 20 are connected to one sub-pixel 60.

[0051] Optionally, in one embodiment, sub-pixel 60 can be a light-emitting device of various colors, such as red sub-pixel R, green sub-pixel G, blue sub-pixel B, white sub-pixel W, etc.

[0052] Optionally, in one embodiment, the sub-pixel 60 includes a first electrode 61 and a second electrode 62 stacked together, and at least one light-emitting functional layer 63 located between the first electrode 61 and the second electrode 62, wherein the second electrode 62 is located on the side of the first electrode layer facing away from the substrate 10. The first electrode 61 may be an anode, and the second electrode 62 may be a cathode. The at least one light-emitting functional layer 63 includes an emitting layer (EML), and may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), and an electron-blocking layer (EBL) located between the anode and the emitting layer (EML), and at least one of an electron injection layer (EIL), an electron transport layer (ETL), and a hole-blocking layer (HBL) located between the cathode and the emitting layer (EML).

[0053] Optionally, in one embodiment, the display panel 100 may further include a pixel definition layer 70, which encloses a pixel opening Q, exposing at least a portion of the first electrode 61, and the light-emitting functional layer 63 is located within the pixel opening Q.

[0054] Optionally, in one embodiment, the pixel definition layer 70 can be a light-transmitting material to allow light from the sub-pixels 60 to pass through the pixel definition layer 70 more effectively. Optionally, the pixel definition layer 70 can be an opaque material, which can improve the light absorption of the pixel definition layer 70, reduce the reflectivity of the display panel, further reduce optical crosstalk between adjacent sub-pixels 60, and improve the display effect of the display panel 100.

[0055] Optionally, in one embodiment, the pixel definition layer 70 is made of an inorganic material.

[0056] Optionally, the display panel 100 also includes a thin film encapsulation layer 80. The thin film encapsulation layer 80 is located on the side of the second electrode 62 away from the substrate 10. The thin film encapsulation layer 80 is used to encapsulate the sub-pixel 60, which can isolate water and oxygen, reduce the probability of failure of the sub-pixel 60 and the underlying layer structure due to impurities such as water and oxygen entering the sub-pixel 60, and ensure that the manufacturing process of the display panel 100 does not affect the lifespan and reliability of the OLED device.

[0057] Optionally, in one embodiment, the thin-film encapsulation layer 80 includes a first encapsulation layer 81, a second encapsulation layer 82, and a third encapsulation layer 83 sequentially stacked on the side of the second electrode 62 facing away from the substrate 10.

[0058] Optionally, in one embodiment, the first encapsulation layer 81 and the third encapsulation layer 83 are inorganic encapsulation layers. For example, the material of the inorganic encapsulation layer is silicon oxide, silicon oxynitride, or silicon nitride, etc. The inorganic encapsulation layer can be a single layer, multiple layers, composite layers, etc.

[0059] Optionally, in one embodiment, the second encapsulation layer 82 is an organic encapsulation layer. Exemplarily, the organic encapsulation layer is made of fiber materials, resin materials, or materials used in multilayer boards, etc. The organic encapsulation layer can be a single layer, multiple layers, composite layers, etc.

[0060] Figure 5 This is a partial structural schematic diagram of the display panel provided in the third embodiment of this application. For example... Figure 5 As shown, in one embodiment, the display panel 100 further includes a second gate signal line 40, which extends along a first direction X. The second gate signal line 40 is located on the side of the first gate signal line 30 away from the hole region 102 and is adjacent to the first gate signal line 30.

[0061] Specifically, in one embodiment, the second gate signal line 40 includes a fourth conductor segment 41, a fifth conductor segment 42, and a sixth conductor segment 43 extending along a first direction X. The fifth conductor segment 42 surrounds the via region 102. The length L5 of the orthographic projection of the fifth conductor segment 42 onto the substrate 10 in the first direction X is less than the length L2 of the orthographic projection of the second conductor segment 32 onto the substrate 10 in the first direction X. The number of pixel circuits 20 connected to the fifth conductor segment 42 is greater than the number of pixel circuits 20 connected to the second conductor segment 32. The impedance of the fifth conductor segment 42 is equal to the impedance of the second conductor segment 32.

[0062] Furthermore, in one embodiment, the fourth conductor segment 41 includes a plurality of fourth sub-conductor segments 411, and the sixth conductor segment 43 includes a plurality of sixth sub-conductor segments 431. The length L4 of the orthographic projection of the fourth sub-conductor segment 411 onto the substrate 10 in the first direction X, the length L6 of the orthographic projection of the sixth sub-conductor segment 431 onto the substrate 10 in the first direction X, and the length L1 of the orthographic projection of the first sub-conductor segment 311 onto the substrate 10 in the first direction X are equal. The number of pixel circuits 20 connected to the fourth sub-conductor segment 411, the number of pixel circuits 20 connected to the sixth sub-conductor segment 431, and the number of pixel circuits 20 connected to the first sub-conductor segment 311 are equal. The impedance of the fourth sub-conductor segment 411, the impedance of the sixth sub-conductor segment 431, and the impedance of the first sub-conductor segment 311 are equal.

[0063] Optionally, in one embodiment, the orthographic projection of the fifth conductor segment 42 on the substrate 10 is arc-shaped.

[0064] Optionally, in one embodiment, the orthographic projection of the second gate signal line 40 on the substrate 10 and the orthographic projection of the via region 102 on the substrate 10 do not overlap.

[0065] Figure 6a yes Figure 5 The diagram shows the structure of the fourth sub-conductor segment of the display panel. Figure 6b yes Figure 5 The diagram shows the structure of the sixth sub-lead segment of the display panel. Figure 6a and Figure 6b As shown, in one embodiment, the fourth sub-conductor segment 411 includes a plurality of fifth conductive portions 4111 and a plurality of sixth conductive portions 4112. The sixth conductive portions 4112 connect to adjacent fifth conductive portions 4111. The sixth conductive portions 4112 and the fifth conductive portions 4111 are located in different conductive layers. The orthographic projection of the sixth conductive portion 4112 on the substrate 10 and the orthographic projection of the fifth conductive portion 4111 on the substrate 10 overlap, thereby increasing the impedance of the fourth sub-conductor segment 411.

[0066] In one embodiment, the sixth sub-conductor segment 431 includes a plurality of seventh conductive portions 4311 and a plurality of eighth conductive portions 4312. The eighth conductive portions 4312 connect to adjacent seventh conductive portions 4311. The eighth conductive portions 4312 and the seventh conductive portions 4311 are located in different conductive layers. The orthographic projection of the eighth conductive portion 4312 on the substrate 10 and the orthographic projection of the seventh conductive portion 4311 on the substrate 10 overlap, thereby increasing the impedance of the sixth sub-conductor segment 431.

[0067] Furthermore, in one embodiment, the fifth conductor segment 42, the fifth conductive portion 4111, and the seventh conductive portion 4311 are on the same layer.

[0068] Furthermore, in one embodiment, the fifth conductive part 4111 and the sixth conductive part 4112 are connected via a via.

[0069] Furthermore, in one embodiment, the seventh conductive part 4311 and the eighth conductive part 4312 are connected via a via.

[0070] Figure 7 yes Figure 5 This is another partial structural diagram of the second gate signal line of the display panel shown. (See diagram below.) Figure 7 As shown, in one embodiment, the orthographic projection of the fourth conductor segment 41 on the substrate 10 and the orthographic projection of the sixth conductor segment 43 on the substrate 10 are concave and convex curves, thereby increasing the impedance of the fourth conductor segment 41 and the sixth conductor segment 43.

[0071] Figure 8This is a partial structural schematic diagram of the display panel provided in the fourth embodiment of this application. For example... Figure 8 As shown, in one embodiment, the display panel 100 further includes a third gate signal line 50, which extends along a first direction X. The third gate signal line 50 includes a plurality of seventh conductor segments 51. The length L7 of the orthographic projection of the seventh conductor segment 51 on the substrate 10 in the first direction X is equal to the length L1 of the orthographic projection of the first sub-conductor segment 311 on the substrate 10 in the first direction X. The number of pixel circuits 20 connected to the seventh conductor segment 51 is equal to the number of pixel circuits 20 connected to the first sub-conductor segment 311. The impedance of the seventh conductor segment 51 is equal to the impedance of the first sub-conductor segment 311.

[0072] Specifically, in one embodiment, one of the plurality of seventh conductor segments 51 is located on the side of the second conductor segment 32 away from the hole region 102.

[0073] Optionally, in one embodiment, the orthographic projection of the third gate signal line 50 on the substrate 10 and the orthographic projection of the via region 102 on the substrate 10 do not overlap.

[0074] Figure 9 This is a partial structural schematic diagram of the display panel provided in the fifth embodiment of this application. For example... Figure 9 As shown, in one embodiment, the display panel 100 further includes a gate driving circuit 90, which is capable of providing appropriate voltage and current signals to the gate.

[0075] Optionally, in one embodiment, the first gate signal line 30, the second gate signal line 40, and the third gate signal line are all electrically connected to the gate drive circuit 90.

[0076] Optionally, in one embodiment, there may be two gate driving circuits 90, which are located on opposite sides of the display panel 100.

[0077] Specifically, in one embodiment, the side of the first conductor segment 31 away from the second conductor segment 32 is connected to the gate drive circuit 90, and the side of the third conductor segment 33 away from the second conductor segment 32 is connected to the gate drive circuit 90.

[0078] Specifically, in one embodiment, the side of the fourth conductor segment 41 away from the fifth conductor segment 42 is connected to the gate drive circuit 90, and the side of the sixth conductor segment 43 away from the fifth conductor segment 42 is connected to the gate drive circuit 90.

[0079] Specifically, in one embodiment, both ends of the third gate signal line 50 are connected to the gate drive circuit 90.

[0080] Optionally, in one embodiment, the number of first gate signal lines 30 can be two, with the two first gate signal lines 30 located on both sides of the via region 102.

[0081] Optionally, in one embodiment, the number of second gate signal lines 40 can be two, with the two second gate signal lines 40 located on both sides of the hole region 102 respectively.

[0082] Optionally, in one embodiment, the number of third gate signal lines 50 can be at least two, and the at least two third gate signal lines 50 are located on both sides of the hole region 102.

[0083] This application provides a display panel including a display area and an aperture area, with the display area surrounding the aperture area. The display panel includes a substrate, multiple pixel circuits, and a first gate signal line. The pixel circuits are located on one side of the substrate. The first gate signal line is located on one side of the substrate and extends along a first direction. The first gate signal line includes a first conductor segment, a second conductor segment, and a third conductor segment connected sequentially along the first direction. The second conductor segment surrounds the aperture area. The first conductor segment includes multiple first sub-conductor segments connected sequentially, and the third conductor segment includes multiple third sub-conductor segments connected sequentially. The orthographic projections of the first, second, and third sub-conductor segments onto the substrate have equal lengths in the first direction. The number of pixel circuits connected to the first and third sub-conductor segments is equal and greater than the number of pixel circuits connected to the second conductor segment. The impedances of the first, second, and third sub-conductor segments are equal. The above embodiment sets the impedance of the second conductor segment closer to the hole area and the first and third sub-conductor segments farther from the hole area in the first gate signal line to be equal. Therefore, the difference in the signal controlling the pixel circuit by the first sub-conductor segment, the third sub-conductor segment and the second conductor end is small, thereby reducing the brightness difference of the sub-pixels corresponding to different pixel circuits and improving the display uniformity of the display panel.

[0084] One embodiment of this application also provides a display module. Figure 10 This is a schematic cross-sectional view of the display module provided in an embodiment of this application. Figure 10 As shown, the display module 200 includes the display panel 100 provided in the above embodiments, or the display panel 100 obtained by the preparation method provided in the above embodiments.

[0085] Optionally, in one embodiment, the display module 200 further includes a cover plate 210 located on the side of the thin film encapsulation layer 80 away from the substrate 10. The cover plate 210 is the outermost protective component of the display module 200 and is typically made of transparent or translucent material. The cover plate 210 is used to protect the display panel 100 inside the display module 200 from physical damage, dust or moisture, while also providing touch functionality.

[0086] Specifically, the cover plate 210 can provide physical protection for the display panel 100, preventing damage to the display panel 100 from scratches, impacts, etc.

[0087] Specifically, the cover plate 210 has high transmittance, ensuring the display effect of the display module 200.

[0088] Optionally, in one embodiment, the cover plate 210 may be a glass cover plate.

[0089] Optionally, in one embodiment, the display module 200 further includes an optical adhesive layer 220 located between the display panel 100 and the cover plate 210 to bond the display panel 100 and the cover plate 210 together.

[0090] It should be understood that the specific type of optical adhesive layer 220 is not shown in the embodiments of this application. For example, optical adhesive layer 220 can be a solid optical adhesive, which can be pre-formed into a film, is easy to bond, and is suitable for mass production; or optical adhesive layer 220 can be a liquid optical adhesive, which is suitable for complex structures such as curved screens; or optical adhesive layer 220 can be an anti-blue light optical adhesive, which contains blue light absorbers and can reduce harmful blue light.

[0091] Optionally, in one embodiment, the display module 200 further includes a touch metal layer 230, which is located between the display panel 100 and the optical adhesive layer 220. The touch metal layer 230 can sense the user's touch operation and convert the sensed touch operation into an electrical signal, which is then transmitted to the driving circuit of the display panel 100. Optionally, the touch metal layer 230 can be a single-layer structure. Optionally, the touch metal layer 230 can be a multi-layer structure.

[0092] The display module 200 provided according to any embodiment of this application and the display panel 100 provided in the embodiments of this application belong to the same inventive concept and have corresponding film layer structures and beneficial effects. Details not described in detail in the embodiments of the display module 200 can be found in the embodiments of the display panel 100, and will not be repeated here.

[0093] One embodiment of this application also provides a display device. Figure 11 This is a schematic diagram of the structure of the display device provided in the embodiments of this application. Figure 11 As shown, the display device 300 includes the display panel 100 provided in the above embodiments, or the display module 200 provided in the above embodiments. The display device 300 is a product with image display function. For example, the display device 300 can be used to display static images, such as pictures or photographs. The display device can also be used to display dynamic images, such as videos.

[0094] In addition, the display device 300 can also perform functions such as taking photos, recording videos, fingerprint recognition, and facial recognition. Accordingly, the display device 300 also includes at least one functional module for implementing the above functions, such as an under-display camera or an under-display fingerprint recognition sensor.

[0095] The display device 300 provided according to any embodiment of this application belongs to the same inventive concept as the display panel 100 or display module 200 provided in the embodiments of this application, and has corresponding film layer structures and beneficial effects. Details not described in detail in the embodiments of the display device 300 can be found in the embodiments of the display panel 100 or display module 200, and will not be repeated here.

[0096] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0097] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0098] It should also be noted that in the apparatus, equipment, and methods of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions of this application.

[0099] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0100] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

[0101] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a hole area, the display area surrounding the hole area; the display panel includes: substrate; Multiple pixel circuits, the pixel circuits being located on one side of the substrate; and A first gate signal line is located on one side of the substrate and extends along a first direction. The first gate signal line includes a first conductor segment, a second conductor segment, and a third conductor segment connected sequentially along the first direction, and the second conductor segment surrounds the hole region. The first conductor segment includes a plurality of first sub-conductor segments connected in sequence, and the third conductor segment includes a plurality of third sub-conductor segments connected in sequence. The lengths of the orthographic projections of the first sub-conductor segment, the second conductor segment, and the third sub-conductor segment on the substrate in the first direction are equal. The number of pixel circuits connected to the first sub-conductor segment and the third sub-conductor segment are equal and greater than the number of pixel circuits connected to the second conductor segment. The impedances of the first sub-conductor segment, the second conductor segment, and the third sub-conductor segment are equal.

2. The display panel according to claim 1, characterized in that, It also includes a second gate signal line, which extends along the first direction and is located on the side of the first gate signal line away from the via region, and is adjacent to the first gate signal line; the second gate signal line includes a fourth conductor segment, a fifth conductor segment, and a sixth conductor segment connected sequentially along the first direction, the fifth conductor segment surrounding the via region; the length of the orthographic projection of the fifth conductor segment on the substrate in the first direction is less than the length of the orthographic projection of the second conductor segment on the substrate in the first direction, the number of pixel circuits connected to the fifth conductor segment is greater than the number of pixel circuits connected to the second conductor segment, and the impedances of the fifth conductor segment and the second conductor segment are equal.

3. The display panel according to claim 2, characterized in that, The fourth conductor segment includes multiple fourth sub-conductor segments, and the sixth conductor segment includes multiple sixth sub-conductor segments. The lengths of the orthogonal projections of the fourth sub-conductor segment, the sixth sub-conductor segment, and the first sub-conductor segment on the substrate are equal in a first direction. The number of pixel circuits connected to them is equal, and their impedances are equal.

4. The display panel according to any one of claims 1-3, characterized in that, It also includes a third gate signal line that extends along the first direction. The third gate signal line includes a plurality of seventh conductor segments. The seventh conductor segments and the first sub-conductor segments have the same length in the first direction when projected onto the substrate. They are connected to the same number of pixel circuits and have the same impedance.

5. The display panel according to claim 4, characterized in that, One of the plurality of seventh conductor segments is located on the side of the second conductor segment away from the hole area.

6. The display panel according to claim 1, characterized in that, The first sub-conductor segment includes a plurality of first conductive portions and a plurality of second conductive portions. The second conductive portions connect adjacent first conductive portions. The second conductive portions and the first conductive portions are located in different conductive layers. The orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first conductive portion on the substrate overlap. The third sub-conductor segment includes multiple third conductive parts and multiple fourth conductive parts. The fourth conductive parts connect adjacent third conductive parts. The fourth conductive parts and the third conductive parts are located in different conductive layers. The orthographic projection of the fourth conductive part on the substrate and the orthographic projection of the third conductive part on the substrate overlap.

7. The display panel according to claim 6, characterized in that, The second conductor segment is in the same layer as the first conductive part and the third conductive part.

8. The display panel according to claim 1, characterized in that, The orthographic projections of the first conductor segment and the third conductor segment onto the substrate are concave-convex curves.

9. The display panel according to claim 8, characterized in that, The orthographic projection of the second conductor segment onto the substrate is arc-shaped.

10. A display device, characterized in that, The display panel includes any one of claims 1-9.

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