Display panel, manufacturing method therefor, and display device

Abstract

The application provides a display panel and a preparation method thereof and a display device. The display panel comprises a first functional layer and a second functional layer. The first functional layer is provided with a control chip area and a test circuit area. The second functional layer is provided with a display area and a non-display area. The wiring structure comprises a first signal wiring, a second signal wiring and a third signal wiring. The first signal wiring is arranged on the second functional layer, one end of the first signal wiring extends to the display area and / or the non-display area, and the other end of the first signal wiring extends to a bending structure. The second signal wiring is arranged on the first functional layer, one end of the second signal wiring extends to the test circuit area, and the other end of the second signal wiring extends to the bending structure and is connected with the first signal wiring. The third signal wiring is arranged on the first functional layer, one end of the third signal wiring extends to the test circuit area, and the other end of the third signal wiring extends to the control chip area. The display panel is beneficial to reducing the size of the frame outside the display area, and is beneficial to realizing the control of the pixels by the control chip and enabling the detection of the pixels by the test circuit.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a display panel and its preparation method, and a display device. Background Technology

[0002] Active-matrix organic light-emitting diode (AMOLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, power saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current display products needs to be improved. Summary of the Invention

[0004] The purpose of this application is to provide a display panel and its manufacturing method, as well as a display device, in order to solve the problem of low performance of display products in traditional technologies.

[0005] A first aspect of this application provides a display panel, comprising:

[0006] The first functional layer includes a control chip area and a test circuit area.

[0007] The second functional layer has a display area and a non-display area.

[0008] A bent structure having a first end and a second end that are far apart from each other, the bent structure being configured in a bent shape such that the first end and the second end are oriented in the same direction; the first end is located on the first functional layer, and the second end is located on the second functional layer;

[0009] The trace structure includes a first signal trace, a second signal trace, and a third signal trace. The first signal trace is disposed on the second functional layer, with one end extending to the display area and / or the non-display area, and the other end extending to the bent structure. The second signal trace is disposed on the first functional layer, with one end extending to the test circuit area and the other end extending to the bent structure and connecting to the first signal trace. The third signal trace is disposed on the first functional layer, with one end extending to the test circuit area and the other end extending to the control chip area.

[0010] In some embodiments of this application, at least one of the first signal trace, the second signal trace, and the third signal trace satisfies the following: the number of the signal traces is multiple, and the multiple signal traces are alternately arranged in different conductive layers.

[0011] In some embodiments of this application, the display area has pixel rows, the pixel arrangement direction of the pixel rows is a first direction, and two adjacent signal traces along the first direction are located in different conductive layers.

[0012] In some embodiments of this application, the display area has column pixels, the pixel arrangement direction of the column pixels is a second direction, and the wiring structure is located in different conductive layers along the second direction.

[0013] In some embodiments of this application, the process error value of the third signal trace is greater than the process error value of the second signal trace, and the process error value of the second signal trace is greater than the process error value of the first signal trace.

[0014] The multiple second signal traces and the multiple third signal traces are arranged in an alternating order along the first direction in the opposite direction.

[0015] In some embodiments of this application, the plurality of second signal traces and the plurality of first signal traces are alternated in the same order along the first direction.

[0016] In some embodiments of this application, the first signal trace includes a plurality of reverse-order display area fan-out traces and a plurality of sequential non-display area fan-out traces, wherein the plurality of reverse-order display area fan-out traces are interspersed among the plurality of sequential non-display area fan-out traces.

[0017] In some embodiments of this application, the routing structure is a data signal routing structure.

[0018] In some embodiments of this application, the conductive layer is a metal wiring layer.

[0019] A second aspect of this application also provides a method for manufacturing a display panel, applicable to the aforementioned display panel, the method comprising:

[0020] Obtain the trace lengths of the first signal trace, the second signal trace, and the third signal trace;

[0021] The longest trace among the first signal trace, the second signal trace, and the third signal trace is determined as the reverse-order trace, and the rest are determined as the sequential traces; wherein the reverse-order traces are the opposite of the sequential traces in alternation along the first direction, and the first direction of the pixel row is the pixel arrangement direction.

[0022] A third aspect of this application also provides a display device, including the display panel as described above.

[0023] The beneficial effects of the present invention embodiments compared with the prior art are as follows: The above-mentioned display panel, manufacturing method, and display device include a first functional layer and a second functional layer. A control chip area and a test circuit area are disposed on the first functional layer; a display area and a non-display area are disposed on the second functional layer; a bending structure has a first end and a second end that are far apart from each other, and the bending structure is configured in a bent shape so that the first end and the second end are oriented in the same direction; the first end is located on the first functional layer, and the second end is located on the second functional layer; the wiring structure includes a first signal trace, a second signal trace, and a third signal trace, the first signal trace being disposed on the second functional layer, with one end extending to the display area and / or the non-display area. The first signal trace is located on the first functional layer, extending from one end to the test circuit area and from the other end to the bent structure, where it connects to the first signal trace. The second signal trace is located on the first functional layer, extending from one end to the test circuit area and from the other end to the control chip area. In this application, the traces are routed within the bent structure to connect different functional layers. This not only helps to reduce the size of the bezel outside the display area but also electrically connects the control chip area, the test circuit area, and the display / non-display area, facilitating the control chip's control of pixels and enabling the test circuit to detect pixels, thereby improving the performance of the display panel. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application;

[0025] Figure 2 This is a schematic diagram of the structure of a display panel provided in another embodiment of this application;

[0026] Figure 3 This is a schematic diagram of the structure of a display panel provided in another embodiment of this application;

[0027] Figure 4 This is a schematic diagram of the structure of a display panel provided in another embodiment of this application;

[0028] Figure 5 This is a schematic diagram of the structure of a display panel provided in yet another embodiment of this application;

[0029] Figure 6 This is a schematic diagram illustrating the steps of a method for manufacturing a display panel according to an embodiment of this application.

[0030] Specific annotations in the attached diagrams: 100 - Second functional layer, 110 - Test circuit area, 120 - Control chip area, 200 - First functional layer, 210 - Display area, 220 - Non-display area, 300 - Bending structure, 400 - Routing structure, 410 - First signal routing, 411 - Fan-out routing of reverse display area, 422 - Fan-out routing of sequential non-display area, 420 - Second signal routing, 430 - Third signal routing, a - First direction, b - Second direction. Detailed Implementation

[0031] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0032] It should be noted that when a component is referred to as being "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0033] It should be understood that the terms "length", "width", "upper", "lower", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0035] It's important to understand that in the field of display panel technology, as display devices continue to evolve towards thinner, lighter, and higher-performance designs, the structural design of display panels faces numerous challenges. In related technologies, the structural layout of display panels often features relatively simple functional layers, with simplistic and inflexible connections between different functional layers, making it difficult to meet increasingly complex display needs and functional expansion requirements. For example, in some display panels, the control chip area and the test circuit area are often located on the same functional layer. This not only increases the layout pressure on that functional layer, leading to complex wiring, but may also affect the performance of the chips and circuits. Simultaneously, the division between display and non-display areas is often inadequate, with the non-display area occupying a large space and reducing the screen-to-body ratio of the display panel.

[0036] In terms of signal transmission, traditional wiring structures suffer from unstable signal transmission and susceptibility to interference. Due to the chaotic distribution of different signal traces and the lack of an effective connection system, display signals are prone to attenuation and distortion during transmission, thus affecting display quality and causing issues such as color deviation and uneven brightness. Furthermore, when testing the display panel, test signals are difficult to transmit accurately and quickly to the test circuit area, impacting testing efficiency and accuracy, and hindering the timely detection and resolution of display panel problems.

[0037] Based on this, this application improves the related display panel, manufacturing method, and display device.

[0038] Please see Figure 1 , Figure 1 This diagram illustrates the structure of the display panel in this embodiment. The display panel of this embodiment includes a first functional layer 200, a second functional layer 100, a bending structure 300, and a wiring structure 400. The first functional layer 200 has a control chip area 120 and a test circuit area 110. The second functional layer 100 has a display area 210 and a non-display area 220 / 210. The bending structure 300 has a first end and a second end that are far apart from each other. The bending structure 300 is configured in a bent shape so that the first end and the second end are oriented in the same direction. The first end is located on the first functional layer 200, and the second end is located on the second functional layer 100. On the 0th layer; the wiring structure 400 includes a first signal trace 410, a second signal trace 420, and a third signal trace 430. The first signal trace 410 is disposed on the second functional layer 100, with one end extending to the display area 210 and / or the non-display area 220210, and the other end extending to the bent structure. The second signal trace 420 is disposed on the first functional layer 200, with one end extending to the test circuit area 110, and the other end extending to the bent structure and connecting to the first signal trace 410. The third signal trace 430 is disposed on the first functional layer 200, with one end extending to the test circuit area 110 and the other end extending to the control chip area 120.

[0039] It should be explained that the first functional layer 200 and the second functional layer 100 are different layer structures with specific functions in the display panel. The first functional layer 200 houses the control chip area 120 and the test circuit area 110, which are used to carry the control chip (IC) and test circuits to realize functions such as control and testing of the display panel. The control chip area 120 is the control core of the entire display panel. The control chip can control and manage various functions of the display panel, such as controlling the display content, brightness, and color parameters of the display area 210, and also coordinating the testing work of the test circuit area 110. The test circuit area 110 is used to perform performance testing on the display panel, detecting whether various performance indicators of the display panel meet the requirements, such as detecting whether there are dead pixels or bright pixels in the display area 210, and detecting whether signal transmission is normal. The test results can be fed back to the control chip area 120 for corresponding adjustments and repairs. The second functional layer 100 is provided with a display area 210 and a non-display area 220210. The display area 210 is used to present information such as images and text, and is the area where users can directly observe and interact. The non-display area 220210 is usually around the display area 210 and is used to set up some auxiliary circuits and components, such as power supply circuits and signal processing circuits, to support the normal operation of the display area 210.

[0040] Understandably, the first signal trace 410 is disposed on the first functional layer 200, with one end extending to the display area 210 and / or the non-display area 220210, and the other end extending to the bent structure. Its function is to transmit signals from the display area 210 and / or the non-display area 220210 to the bent structure for connection with the second signal trace 420, thus enabling signal transmission between different functional layers. The second signal trace 420 is disposed on the second functional layer 100, with one end extending to the test circuit area 110, and the other end extending to the bent structure and connecting with the first signal trace 410. It is responsible for transmitting signals from the test circuit area 110 to the bent structure, where they merge with the first signal trace 410, and then being transmitted to the display area 210 and / or the non-display area 220210, or feeding back signals from the display area 210 and / or the non-display area 220210 to the test circuit area 110. The third signal trace 430 is located on the second functional layer 100, extending one end to the test circuit area 110 and the other end to the control chip area 120. Its main function is to transmit signals between the test circuit area 110 and the control chip area 120, enabling the control chip to obtain the test results of the test circuit and perform corresponding control and adjustment based on the results.

[0041] This embodiment connects the first functional layer 200 and the second functional layer 100 through a bending structure 300, making the layout of the display panel more compact and facilitating the thinning of the display panel. Furthermore, the signal transmission path constructed by the wiring structure 400 ensures stable transmission of display signals, test signals, etc., between various functional areas, improving the display stability and testing accuracy of the display panel. In terms of display, it ensures that the display area 210 can accurately receive signals from the control chip, presenting high-quality images. In terms of testing, it facilitates performance testing of the display panel, allowing for timely detection and resolution of potential problems, and improving the product yield.

[0042] In some embodiments, the test circuit can be used as an array test circuit or an ESD (Electro-Static Discharge) protection circuit.

[0043] In some embodiments of this application, please refer to Figure 2 , Figure 2 A schematic diagram of the display panel provided in this embodiment is shown. At least one of the first signal trace 410, the second signal trace 420, and the third signal trace 430 in this embodiment satisfies the following condition: the number of signal traces is multiple, and the multiple signal traces are alternately arranged in different conductive layers.

[0044] It needs to be explained that, such as Figure 2 As shown, among multiple signal traces, those of different thicknesses are laid out in different conductive layers. Alternating routing refers to each pair or more adjacent signal traces being placed in different conductive layers. For example, in the horizontal direction, the nth signal trace and the (n+1)th signal trace can be placed in different conductive layers; alternatively, in the horizontal direction, the nth signal trace and the (n+1)th signal trace can be placed in the same conductive layer, while the (n+2)th signal trace and the (n+1)th signal trace are placed in different conductive layers. The specific alternation method can be selected according to the actual situation.

[0045] Understandably, the internal space of a display panel is limited, especially as the number of signals that need to be transmitted continues to increase with the development of display technology. If all signal traces are placed on the same conductive layer, insufficient wiring space will result in overly dense wiring, increasing the risk of short circuits and interference. By alternating multiple signal traces across different conductive layers, the vertical space of the display panel can be fully utilized, avoiding overcrowding on the same layer and allowing for a more orderly arrangement of signal traces. The signal connections between different functional areas of the display panel (such as the control chip area 120, the test circuit area 110, and the display area 210) are complex. Alternating wiring allows for more flexible signal path planning, enabling traces to better bypass other components and circuits, adapting to complex circuit layout requirements, and improving the feasibility and efficiency of wiring.

[0046] Furthermore, electromagnetic fields are generated during signal transmission through traces. When multiple signal traces are too close together and on the same layer, these electromagnetic fields can interfere with each other, affecting signal transmission quality. Alternating signal traces across different conductive layers increases the distance between traces, effectively reducing the impact of electromagnetic interference. For example, traces on different layers can be isolated by insulating layers, reducing coupling effects between signals and enabling more stable signal transmission. Within the same conductive layer, crosstalk can occur between adjacent traces, meaning a signal in one trace can interfere with signals in adjacent traces. By distributing signal traces across different layers, the possibility of crosstalk can be significantly reduced, ensuring that the signal in each trace is accurately transmitted to its destination, thus improving the signal transmission reliability of the display panel.

[0047] Please refer to the embodiments described in this application. Figure 2 In this embodiment, the display area 210 has pixel rows, and the pixel arrangement direction of the pixel rows is a first direction a. Along the first direction a, two adjacent signal traces are located in different conductive layers.

[0048] It is understood that in the embodiments of this application, each pair of adjacent signal traces are located in different conductive layers, that is, the nth signal trace and the (n+1)th signal trace are located in different conductive layers.

[0049] In some embodiments of this application, please refer to Figure 3 , Figure 3 A schematic diagram of the structure of the display panel provided in this embodiment is shown; the display area 210 of this embodiment has column pixels, the pixel arrangement direction of the column pixels is the second direction b, and the wiring structure 400 is located in different conductive layers along the second direction b.

[0050] It is important to know that in the field of display panel technology, as display devices continue to develop towards higher resolution and higher image quality, higher requirements are placed on the precision and stability of the internal circuit wiring of display panels. Among these requirements, FIAA (FanoutinAA) technology, as an effective means to optimize wiring layout and improve the utilization rate of the display area, has been widely used.

[0051] In the display panel manufacturing industry, the internal wiring structure becomes complex when FIAA technology is used and the IC source is set in a specific reverse order. In this case, signal traces on different conductive layers are susceptible to process fluctuations during actual manufacturing, leading to deviations in the process parameters of each conductive layer. This inevitably results in significant resistance differences between the signal traces on different conductive layers. Sudden changes in resistance values ​​severely impact the stability of signal transmission, thus interfering with the normal operation of the display panel. Particularly noticeable in the displayed image is the appearance of vertical stripes, significantly reducing display quality and affecting the user's visual experience. Related technologies typically compensate for the resistance of signal traces. However, simply compensating for resistance cannot fundamentally solve the problem of sudden changes in resistance between adjacent FIAA layers caused by process fluctuations, and the risk of vertical stripe display abnormalities remains high.

[0052] It is understood that in this embodiment, the same trace structure 400 is laid out on different conductive layers. This allows the resistance fluctuations caused by differences in the characteristics of a single conductive layer to be canceled out or reduced when multiple conductive layers are used. For example, one conductive layer may have a higher resistance due to manufacturing issues, while another may have a lower resistance. When the same trace is distributed across these two conductive layers, the overall resistance will be closer to the design value, thus reducing the resistance difference between the multiple trace structures 400. In a display panel, excessive resistance differences can lead to inconsistencies in signal transmission, affecting the uniformity of light emission from column pixels. By reducing the resistance differences between the trace structures 400, each column pixel can receive a more stable and consistent signal, thereby improving the display uniformity of the display area 210 and reducing problems such as uneven brightness and color deviation in the displayed image.

[0053] Please refer to the embodiments described in this application. Figure 3 In this embodiment, the process error value of the third signal trace 430 is greater than that of the second signal trace 420, and the process error value of the second signal trace 420 is greater than that of the first signal trace 410; the alternation order of the plurality of second signal traces 420 and the plurality of third signal traces 430 along the first direction a is opposite.

[0054] It should be explained that the process error value can be understood as the difference in the dimensions of traces in different conductive layers. A larger process error can increase trace resistance, leading to signal attenuation and delay during transmission. For the third signal trace 430, due to its larger process error value, the signal transmission is more likely to be affected; the second signal trace 420 is next; and the first signal trace 410 is relatively less affected. Specifically, in the design of the display panel, the third signal trace 430 is longer, therefore its impedance difference is greater.

[0055] Understandably, the alternation order of the multiple second signal traces 420 and the multiple third signal traces 430 along the first direction a is reversed. This design is to address the impact of process errors. For example, the alternation order of the multiple second signal traces 420 along the first direction a is 1 / 2 / 1, meaning that according to the order of the first direction a, the first second signal trace 420 is placed in the first conductive layer, the second second signal trace 420 is placed in the second conductive layer, the third second signal trace 420 is placed in the first conductive layer, and so on. The alternation order of the multiple third signal traces 430 along the first direction a is 2 / 1 / 2, meaning that according to the order of the first direction a, the first third signal trace 430 is placed in the second conductive layer, the second third signal trace 430 is placed in the first conductive layer, the third third signal trace 430 is placed in the second conductive layer, and so on.

[0056] Due to process errors, if signal traces of the same type are arranged closely in the same order, errors may accumulate, further exacerbating signal interference and transmission problems. By arranging the second signal trace 420 and the third signal trace 430 alternately in opposite orders, the process error distribution in the first direction a can be more dispersed. Specifically, if the resistance of a trace structure 400 of the same length in the first conductive layer is greater than its resistance in the second conductive layer, then the resistance of all signal traces 1 disposed in the first conductive layer will be greater than the resistance of all signal traces 2 disposed in the second conductive layer. In this embodiment, the third signal trace 430 and the second signal trace 420 are placed in different conductive layers. Therefore, the resistance of signal trace 1 will decrease, and the resistance of signal trace 2 will increase, thereby reducing the resistance difference between signal trace 1 and signal trace 2.

[0057] Please refer to the embodiments described in this application. Figure 3 In this embodiment, the multiple second signal traces 420 and the multiple first signal traces 410 alternate in the same order along the first direction a.

[0058] It is understandable that, for example, the alternating order of multiple second signal traces 420 along the first direction a is 1 / 2 / 1, that is, according to the order of the first direction a, the first second signal trace 420 is placed in the first conductive layer, the second second signal trace 420 is placed in the second conductive layer, the third second signal trace 420 is placed in the first conductive layer, and so on. Similarly, the alternating order of multiple first signal traces 410 along the first direction a is 1 / 2 / 1, that is, according to the order of the first direction a, the first first signal trace 410 is placed in the first conductive layer, the second first signal trace 410 is placed in the second conductive layer, the third first signal trace 410 is placed in the first conductive layer, and so on.

[0059] Since the resistance of the third signal trace 430 fluctuates more due to process errors, it is chosen to keep the first signal trace 410 and the second signal trace 420 in the same conductive layer, while replacing the third signal trace 430 in another conductive layer. This is to help to bring the resistance of the trace structure 400 closer to a balanced resistance value.

[0060] In some embodiments of this application, please refer to Figure 4 , Figure 4 A schematic diagram of the structure of the display panel provided in this application embodiment is shown. The first signal trace 410 of this embodiment includes a plurality of reverse-order display area fan-out traces 411 and a plurality of reverse-order display area fan-out traces 412, with the plurality of reverse-order display area fan-out traces 411 interspersed among the plurality of reverse-order display area fan-out traces 412.

[0061] Understandably, given the limited internal space of a display panel, an interleaved wiring arrangement makes full use of every available space for cabling. Compared to separating and centrally arranging the two types of cabling, the interleaved approach avoids situations where cabling is too dense in one area while wasting space in another, achieving efficient use of cabling space and helping to realize more complex and comprehensive signal transmission functions within a limited panel area.

[0062] In some embodiments of this application, the routing structure 400 is a data signal routing structure 400.

[0063] In some embodiments of this application, the conductive layer is a metal wiring layer. Specifically, the conductive layer is made of molybdenum material.

[0064] In some embodiments of this application, please refer to Figure 5 , Figure 5A schematic diagram of the display panel structure provided in this embodiment is shown. In this embodiment, FIAA (Fanoutin AA) technology is used to fabricate the display panel. When the IC source (IC signal source) is defined as reverse order, the wiring structure on both sides of the screen becomes more complex. The reverse-order FIAA (reverse-order display area fanout trace 411) needs to be interwoven with the sequential non-FIAA (reverse-order display area fanout trace 412) to meet the signal transmission requirements of different areas of the display panel. Although this interleaved wiring method achieves specific functions, it also brings potential problems. After setting two adjacent signal traces to be located on the first conductive layer and the second conductive layer respectively, the differences in process characteristics and process fluctuations of different conductive layers during manufacturing will affect the resistance value of the signal traces.

[0065] Specifically, in the display panel manufacturing process, Develop and Etch are critical process steps. The After Develop Inspection (ADI) and After Etch Inspection (AEI) values ​​are used to measure the actual state of the metal layer after these two process steps. Due to process variations, the ADI or AEI values ​​of the first and second conductive layers will inevitably deviate. Process variations can stem from various factors, such as exposure dose deviations during photolithography, subtle changes in etchant concentration, and equipment stability. These factors cause inconsistencies in critical dimensions such as thickness and width between the first and second conductive layers, thus affecting their electrical properties, with changes in resistance being particularly significant.

[0066] Due to deviations in the ADI or AEI values ​​of the first and second conductive layers, the actual resistance values ​​of adjacent signal traces laid on these two conductive layers differ significantly. Resistance is a crucial parameter affecting signal transmission; inconsistencies in resistance can lead to varying degrees of signal attenuation, delay, and distortion during transmission. For example, if the resistance of a signal trace on the first conductive layer increases due to process variations, while the resistance of a signal trace on the adjacent second conductive layer remains relatively normal, the signal transmission characteristics of these two adjacent traces will be drastically different, severely impacting the consistency and stability of the display panel's signal transmission. Excessive resistance differences between adjacent signal traces can easily cause vertical stripe display anomalies during display panel operation. This is because pixel emission in a display panel relies on accurate signal driving; when there are significant differences in the signals transmitted by adjacent signal traces, the corresponding pixels cannot respond accurately, resulting in stripes with inconsistent brightness and color in the vertical direction, greatly reducing display quality and affecting user experience.

[0067] In display panels using reverse-order ICs, reverse-order FIAAs are interspersed among sequential non-FIAAs, which helps ensure that each area of ​​the display panel can accurately receive and process signals. For example... Figure 5 As shown, the routing in Fanout segments A, B, and C represents the first signal trace 410, the second signal trace 420, and the third signal trace 430, respectively. In the routing of Fanout segments A, B, and C, if an alternating pattern of 1 / 2 / 1 / 2… (i.e., first conductive layer, second conductive layer, and so on) is used from left to right, then adjacent signal traces will be located on the first and second conductive layers, respectively. Under ideal process conditions, this alternating layout can optimize the signal transmission path by utilizing the characteristics of different metal layers.

[0068] However, process fluctuations are unavoidable in actual production. Critical Dimension (CD) is a crucial indicator of manufacturing process precision; it represents the actual size of the pattern formed after processes such as photolithography. For the first and second conductive layers, their actual process CD ranges often differ. For example, if the first conductive layer experiences a +0.4µm increase in CD, while the second conductive layer experiences a -0.4µm decrease in CD, the actual linewidth difference between the two will be as high as 0.8µm. This linewidth difference can significantly impact the electrical properties of the metal line.

[0069] In the signal transmission process of a display panel, data loading refers to the process of the signal being applied to the load (such as a pixel). When the impedance difference between adjacent signal lines is large, the voltage, current, and other parameters applied to the pixel will be inconsistent when the signal is transmitted to the pixel. This causes the pixel's light emission state to fail to accurately correspond to the input image data, which may ultimately lead to abnormalities in the displayed image, such as uneven brightness and color deviation, seriously affecting the display quality of the display panel and the user experience.

[0070] In the embodiments of this application, if the CD value of the first conductive layer is positively biased or the CD value of the second conductive layer is negatively biased, or if the CD value of the first conductive layer is negatively biased / the CD value of the second conductive layer is positively biased, the source trace resistance of the FanoutB&C segment will be complementary because the first and second conductive layers are used separately. The impedance of adjacent signal traces will be less affected by process fluctuations, reducing the risk of vertical display abnormalities in the FIAA section on both sides of the screen. In the test of the display panel prepared using the technical solution of the embodiments of this application, there are no obvious vertical stripe display abnormalities in the QT (Quarter Test) lamp-on test stage of the screen, and the display effect is excellent.

[0071] Furthermore, in order to better implement the display panel in any of the above embodiments, based on the above display panel, please refer to... Figure 6 , Figure 6 The illustration shows a schematic diagram of the steps in the method for manufacturing a display panel provided in this embodiment; this application also provides a method for manufacturing a display panel, applied to the above-mentioned display panel, the method for manufacturing the display panel comprising:

[0072] S100: Obtain the trace lengths of the first signal trace 410, the second signal trace 420, and the third signal trace 430; specifically, the length of the signal traces significantly affects the signal transmission characteristics, such as resistance. Obtaining the trace lengths of the first signal trace 410, the second signal trace 420, and the third signal trace 430 is helpful for subsequent routing on different conductive layers.

[0073] S200: Among the first signal trace 410, the second signal trace 420, and the third signal trace 430, the longest trace is selected as the reverse-order trace, and the rest are selected as the sequential traces; wherein the reverse-order traces and the sequential traces alternate along the first direction a in the opposite order, and the first direction a of the pixel row is the pixel arrangement direction. Specifically, generally speaking, the longer the trace length, the greater the interference and loss the signal experiences during transmission, and the more obvious the signal delay will be.

[0074] It is understandable that alternating between reverse and sequential traces can effectively balance the resistance differences caused by manufacturing errors between different traces. In the manufacturing process of display panels, various uncontrollable factors can lead to manufacturing errors, causing deviations in the resistance values ​​of different traces. For example, in a certain area, manufacturing errors may cause the resistance of sequential traces to increase. However, since adjacent traces are reverse-order, their resistance changes due to manufacturing errors differ from those of sequential traces; the direction and degree of their resistance deviations differ. This difference allows reverse-order traces to neutralize the impact to some extent when the resistance of sequential traces increases. Overall, the alternating arrangement avoids excessive accumulation of resistance deviations on a particular type of trace, balancing the resistance differences between different traces and thus mitigating the signal transmission degradation caused by excessive resistance differences.

[0075] Furthermore, in order to better implement the display panel in any of the above embodiments, this application also provides a display device, including the display panel as described above, based on the above display panel.

[0076] In some embodiments, the display device may be a mobile phone, tablet, desktop computer, laptop computer, wearable device, automotive screen, sensor device, etc.

[0077] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0078] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0079] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0080] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0081] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, include: The first functional layer includes a control chip area and a test circuit area. The second functional layer has a display area and a non-display area. A bent structure having a first end and a second end that are far apart from each other, the bent structure being configured in a bent shape such that the first end and the second end are oriented in the same direction; the first end is located on a first functional layer, and the second end is located on a second functional layer; The trace structure includes a first signal trace, a second signal trace, and a third signal trace. The first signal trace is disposed on the second functional layer, with one end extending to the display area and / or the non-display area, and the other end extending to the bent structure. The second signal trace is disposed on the first functional layer, with one end extending to the test circuit area and the other end extending to the bent structure and connecting to the first signal trace. The third signal trace is disposed on the first functional layer, with one end extending to the test circuit area and the other end extending to the control chip area.

2. The display panel according to claim 1, characterized in that, At least one of the first signal trace, the second signal trace, and the third signal trace satisfies the following condition: the number of the signal traces is multiple, and the multiple signal traces are alternately arranged in different conductive layers.

3. The display panel according to claim 2, characterized in that, The display area has pixel rows, and the pixel arrangement direction of the pixel rows is a first direction. Two adjacent signal traces along the first direction are located in different conductive layers.

4. The display panel according to claim 3, characterized in that, The display area has columns of pixels, the pixel arrangement direction of the columns of pixels is a second direction, and the trace structure is located in different conductive layers along the second direction.

5. The display panel according to claim 4, characterized in that, The process error value of the third signal trace is greater than the process error value of the second signal trace, and the process error value of the second signal trace is greater than the process error value of the first signal trace. The multiple second signal traces and the multiple third signal traces are arranged in an alternating order along the first direction in the opposite direction.

6. The display panel according to claim 5, characterized in that, The multiple second signal traces and the multiple first signal traces are arranged in the same alternating order along the first direction.

7. The display panel according to claim 2, characterized in that, The first signal trace includes multiple fan-out traces of reverse-order display areas and multiple fan-out traces of sequential non-display areas, with the multiple fan-out traces of reverse-order display areas interspersed among the multiple fan-out traces of sequential non-display areas.

8. The display panel according to any one of claims 1 to 7, characterized in that, The routing structure is a data signal routing structure.

9. The display panel according to any one of claims 1 to 7, characterized in that, The conductive layer is a metal wiring layer.

10. A method for manufacturing a display panel, characterized in that, The display panel described in any one of claims 1 to 9 is used in a method for manufacturing the display panel comprising: Obtain the trace lengths of the first signal trace, the second signal trace, and the third signal trace; The longest trace among the first signal trace, the second signal trace, and the third signal trace is determined as the reverse-order trace, and the rest are determined as the sequential traces; wherein the reverse-order traces are the opposite of the sequential traces in alternation along the first direction, and the first direction of the pixel row is the pixel arrangement direction.

11. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 10.

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