Electronic device and method of manufacturing the same

Abstract

An electronic device and a manufacturing method thereof are provided. The electronic device includes a display panel displaying an image, a circuit board coupled to the display panel, and a metal pattern electrically connecting the display panel to the circuit board. The display panel includes a base layer having a first opening defined therein, an insulating layer disposed on the base layer and having a second opening defined therein to overlap the first opening, and a conductive pattern disposed on the insulating layer and having a conductive opening defined therein to expose at least a portion of an inner surface of the insulating layer defining the second opening.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0057709, filed on April 30, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of this disclosure described herein relate to electronic devices and methods of manufacturing the same, and more specifically, to electronic devices with improved reliability and methods for manufacturing electronic devices. Background Technology

[0004] Multimedia devices such as televisions, mobile phones, tablet computers, car navigation systems, and portable game consoles can utilize a variety of electronic devices. These electronic devices may include a display panel for displaying images and a circuit board connected to the display panel that provides drive signals to it. The display panel includes a display section for displaying images and panel pads disposed around its periphery to provide drive signals to the display section.

[0005] The display unit included in the electronic device may include multiple pixels for displaying images and a driver chip for driving the pixels. The electronic device may also include a sensor for sensing external input, and the electronic device can simultaneously display images and sense external input. Summary of the Invention

[0006] The electronic device includes a display panel for displaying images, a circuit board coupled to the display panel, and a metal pattern electrically connecting the display panel to the circuit board. The display panel includes a base layer having a first opening defined therein, an insulating layer disposed on the base layer and having a second opening defined therein that overlaps with the first opening, and a conductive pattern disposed on the insulating layer and having a conductive opening defined therein, the conductive opening exposing at least a portion of the inner surface of the insulating layer defining the second opening.

[0007] The electronic device includes a display panel for displaying images, a processor for providing image data to the display panel, a circuit board coupled to the display panel, a metal pattern electrically connecting the display panel to the circuit board, a window disposed on the display panel, and a housing disposed below the display panel, coupled to the window, and housing the display panel and the circuit board. The display panel includes a base layer having a first opening defined therein, an insulating layer disposed on the base layer and having a second opening defined therein overlapping the first opening, and a conductive pattern disposed on the insulating layer and having a conductive opening defined therein, the conductive opening exposing at least a portion of the inner surface of the insulating layer defining the second opening.

[0008] A method for manufacturing an electronic device includes: forming a base layer having a first opening defined therein; forming an insulating layer on the base layer having a second opening defined therein overlapping the first opening; forming a conductive pattern on the insulating layer; patterning the conductive pattern to form a conductive opening exposing at least a portion of an inner surface of the insulating layer defining the second opening; providing a bump electrode of a circuit board in the first opening; and forming a metal pattern in the second opening. The conductive pattern is electrically connected to the bump electrode via the metal pattern. Attached Figure Description

[0009] The above and other objects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0010] Figure 1 This is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0011] Figure 2 This is an exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0012] Figure 3 This is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0013] Figure 4 This is a schematic cross-sectional view of a display module according to an embodiment of the present disclosure.

[0014] Figure 5 This is a plan view of a display panel according to an embodiment of the present disclosure.

[0015] Figure 6 This is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0016] Figure 7A This is a plan view of the input sensing layer according to an embodiment of the present disclosure.

[0017] Figure 7B It is along Figure 7A A cross-sectional view of the input sensing layer taken by line II-II'.

[0018] Figure 8 This is an enlarged plan view of a portion of a display module according to an embodiment of the present disclosure.

[0019] Figure 9 It is along Figure 8 The cross-sectional view of the display module is captured by line III-III'.

[0020] Figure 10 This is an enlarged plan view of the non-display area of ​​a display module according to an embodiment of the present disclosure.

[0021] Figure 11 yes Figure 10 A magnified plan view of a portion of the non-display area.

[0022] Figure 12 It is along Figure 11 The line IV-IV' is a cross-sectional view of a portion of the display panel.

[0023] Figure 13A and Figure 13B This is a cross-sectional view of a portion of a display panel according to an embodiment of the present disclosure.

[0024] Figure 14 yes Figure 10 A magnified plan view of a portion of the non-display area.

[0025] Figure 15 It is along Figure 14 The line V-V' is a cross-sectional view of a portion of the display panel.

[0026] Figure 16 This is a cross-sectional view of a portion of a display panel according to an embodiment of the present disclosure.

[0027] Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 17E , Figure 17F , Figure 17G , Figure 17H and Figure 17I It is a plan view of a conductive pattern according to various embodiments of the present disclosure.

[0028] Figure 18A and Figure 18B It is a plan view of a conductive pattern according to an embodiment of the present disclosure.

[0029] Figure 19 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0030] Figure 20 A schematic diagram of an electronic device according to various embodiments of the present disclosure is shown.

[0031] Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 21E , Figure 21F , Figure 21G , Figure 21H and Figure 21I This is a view illustrating the steps of an electronic device manufacturing method according to an embodiment of the present disclosure. Detailed Implementation

[0032] Various changes can be made to this disclosure, and various embodiments of this disclosure can be implemented. Therefore, specific embodiments are shown in the accompanying drawings and described herein as examples. However, it should be understood that this disclosure is not necessarily to be construed as limited thereto and covers all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.

[0033] In this specification, when a component (or region, layer, section, etc.) is referred to as being “on”, “connected to”, or “linked to” another component, it means that the component may be directly on, directly connected to, or linked to the other component, or a third component may exist between them.

[0034] Throughout the accompanying drawings and this disclosure, the same reference numerals may refer to the same components. While each drawing may represent one or more specific embodiments of the present disclosure and is drawn to scale so that relative lengths, thicknesses, and angles can be inferred from them, it should be understood that the invention is not necessarily limited to the relative lengths, thicknesses, and angles shown. These values ​​may be varied within the spirit and scope of this disclosure, for example, to account for manufacturing limitations, etc. As used herein, the term "and / or" includes all of one or more combinations defined by the relevant components.

[0035] Terms such as "first," "second," etc., may be used to describe various components, but these components should not necessarily be limited by these terms. Terms may be used to distinguish one component from others. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless otherwise stated, singular terms may include plural forms.

[0036] Furthermore, terms such as "below," "under," "above," and "over" are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative concepts and are described based on the directions shown in the accompanying drawings.

[0037] It should be understood that terms such as “comprising,” “including,” and “having”, when used herein, specify the presence of the stated features, numbers, steps, operations, components, parts, or combinations thereof, but do not necessarily exclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0038] As used herein, the term "direct setting" can mean that there may be no additional layer, membrane, region, or plate between one part (such as a layer, membrane, region, or plate) and another part. For example, the term "direct setting" can mean setting two layers or two components without any additional components, such as adhesive components, between them.

[0039] Embodiments of this disclosure relate to advanced electronic devices, specifically display devices, designed to have improved electrical bonding and reliability. The device may include a display panel for displaying images and a circuit board for driving the display panel. A metallic pattern electrically connects the display panel to the circuit board. The structure of the display panel may include a base layer having a first opening, an insulating layer having a second opening overlapping the first opening, and a conductive pattern with conductive openings formed on the insulating layer. The conductive openings expose a portion of the inner surface of the insulating layer, which enables reliable electrical bonding and ensures structural integrity.

[0040] The manufacturing method may include forming openings in a base layer and an insulating layer, depositing a conductive pattern, and then introducing metallic ink into a second opening. During the photocuring step, light passes through the conductive openings in the conductive pattern, ensuring that the metallic ink is fully exposed and properly sintered into a solid conductive metal pattern. This process not only establishes an electrical connection between the bump electrodes of the circuit board and the conductive pattern of the display panel, but also improves the quality and reliability of the cured metallic ink. By allowing light to reach all parts of the ink, the process avoids partial curing, resulting in a stronger and more uniform electrical bond.

[0041] Embodiments of this disclosure provide electronic devices with improved electrical reliability by optimizing the interface between the display panel and its circuit board. This design addresses the problems of incomplete curing and bonding failures often seen in conventional structures. Embodiments of this disclosure also enable narrower bezel designs and support applications in foldable or flexible devices by reducing stress in the bonding areas. By combining structural modifications to the display panel with a carefully tailored curing process for metallic inks, embodiments of this disclosure improve both manufacturing efficiency and device performance, making them suitable for a wide range of multimedia and mobile electronic products.

[0042] In the following description, an embodiment of the display device will be described with reference to the accompanying drawings.

[0043] Figure 1 This is a perspective view of an electronic device according to an embodiment of the present disclosure. Figure 2 This is an exploded perspective view of an electronic device according to an embodiment of the present disclosure. Figure 3 This is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0044] Reference Figure 1 An electronic device ED according to embodiments of the present disclosure may include a display surface DS defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The electronic device ED can provide an image IM to a user through the display surface DS.

[0045] The display surface DS may include a display area DA and a non-display area NDA adjacent to the display area DA (e.g., surrounding the display area DA on at least both sides of the display area DA). The display area DA may be the area where an image IM is displayed, and the non-display area NDA may be (e.g., by excluding pixels) the area where the image IM is not displayed. The non-display area NDA may surround the display area DA. However, it is not limited to this, and the shapes of the display area DA and the non-display area NDA may be modified.

[0046] In the following text, the direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. The third direction DR3 serves as the basis for distinguishing the front and rear surfaces of each component from one another. The expression "when viewed from above the plane" or "in a plan view" as used herein can be defined as the state in which the electronic device ED is observed in the third direction DR3.

[0047] In embodiments of this disclosure, the electronic device ED may be a foldable electronic device capable of folding about a folding axis to at least a significant extent without causing cracks or other damage. The folding axis may be parallel to a first direction DR1 or a second direction DR2 and may define a folding region within a portion of the display area DA. The electronic device ED may be folded inward such that opposite sides of the display area DA face each other (so that the display area DA is protected when in this state), or it may be folded outward such that opposite sides of the display area DA are separated from each other (so that the display area DA remains visible when in this state).

[0048] Reference Figure 2 Electronic devices (EDs) may include display devices (DDs), electronic modules (EMs), power supply modules (PSMs), and housings (HMs). Although in Figure 2 The electronic device ED is schematically shown, but the electronic device ED may also include mechanical structures (e.g., hinges) for controlling the operation of the display device DD (e.g., folding or rolling).

[0049] The display device DD generates an image IM and senses external input. The display device DD includes a window WM, an upper component UM, a display module DM, a lower component LM, a circuit board (or flexible circuit board) FCB, and a driver chip DIC. The upper component UM includes components disposed on top of the display module DM, while the lower component LM includes components disposed below the display module DM.

[0050] The window WM provides the front surface for the electronic device ED. The window WM includes a transmissive area TA and a bezel area BZA. Figure 1The display surface DS shown in the diagram has a display area DA and a non-display area NDA defined by a transmission area TA and a border area BZA. The transmission area TA is the area through which the image passes, and the border area BZA is the area that covers the structure / components located below the window WM and through which no image passes.

[0051] The display module DM includes and Figure 1 The display area DA and the non-display area NDA shown correspond to the display area DM-DA and the non-display area DM-NDA. The expression "one area / part corresponds to another area / part" as used herein means that the areas / parts overlap with each other and are not necessarily limited to the same area.

[0052] The pad area PA is located on one side of the non-display area DM-NDA. The pad area PA is the area that is electrically connected (or joined) to the circuit board FCB, which will be described below. In this embodiment, the pad area PA is defined on the rear surface of the display module DM.

[0053] The display module DM has a substantially quadrilateral shape in a plan view. The expression "substantially quadrilateral shape" as used herein includes not only a quadrilateral shape in the mathematical sense, but also shapes that are similar to quadrilaterals and can be perceived as quadrilaterals by the user. For example, a substantially quadrilateral shape can include a quadrilateral shape with rounded corner areas. Furthermore, a substantially quadrilateral shape is not necessarily limited to the display panel DP (see [link to documentation]). Figure 4 The fact that the edge of a surface is a straight line, and that edge can include curved areas.

[0054] The upper component UM may include a protective film or an optical film. The optical film may include polarizers and retarders for reducing the reflection of external light. The lower component LM may include a protective film for the display panel DP, a support component for supporting the display panel DP, and a digitizer. Detailed descriptions of the upper component UM and the lower component LM are given below.

[0055] The circuit board FCB is located below the display module DM. The circuit board FCB can be attached to the rear surface of the display panel DP. The circuit board FCB electrically connects the display panel DP and the main circuit board MCB (see reference). Figure 3 The circuit board FCB includes at least one insulating layer and at least one conductive layer. The conductive layer may include multiple signal lines.

[0056] The driver chip (DIC) can be mounted on the circuit board (FCB). The driver chip (DIC) can include driving circuitry for driving the pixels of the display panel (DP), such as data driver circuitry. Although... Figure 2The diagram shows a structure in which the driver chip DIC is mounted on the circuit board FCB, but this disclosure is not necessarily limited thereto. For example, the driver chip DIC may be mounted on the display module DM or the main circuit board.

[0057] The electronic module (EM) may include a control module, a wireless communication module, an image input module, a sound input module, a sound output module, a memory, and an external interface module. The EM may include a main circuit board, and the module may be mounted on the main circuit board or electrically connected to the main circuit board via a flexible circuit board. The EM is electrically connected to the power supply module (PSM).

[0058] Although not shown separately, the electronic device ED may also include an electro-optical module. The electro-optical module can be an electronic component that outputs or receives optical signals. The electro-optical module may include a camera module and / or a proximity sensor. The camera module can capture external images through a portion of the display panel DP.

[0059] Figure 2 The housing HM shown is connected to the display device DD, specifically to the window WM, to accommodate other modules. Although the housing HM is shown as having a monolithic shape, the housing HM is not necessarily limited to this. The housing HM may include multiple parts (e.g., side parts and bottom parts) that are connected to each other.

[0060] Figure 3 It is along Figure 2 A cross-sectional view of the display device DD taken by line I-I'. (Refer to...) Figure 3 The window WM may include a base substrate BS and a border pattern BM disposed on the lower surface of the base substrate BS. The base substrate BS may include a synthetic resin film or a glass substrate. The base substrate BS may have a multilayer structure. The base substrate BS may include a thin glass substrate, a protective film disposed on the thin glass substrate, and an adhesive layer connecting the thin glass substrate and the protective film.

[0061] The border pattern BM can be a colored light-blocking film and can be formed, for example, by a coating method. The border pattern BM can include a base material and a dye or pigment mixed in the base material. The border pattern BM and... Figure 1 The non-display area NDA and shown Figure 2 The border regions BZA shown overlap. The border pattern BM can be disposed on the lower surface of the base substrate BS. When the base substrate BS has a multilayer structure, the border pattern BM can be disposed between interfaces defined by multiple layers. For example, the border pattern BM can be disposed between a thin glass substrate and a protective film. Although not shown separately, the window WM can also include at least one of a hard coating, an anti-fingerprint layer, and an anti-reflective layer on the upper surface of the base substrate BS.

[0062] The upper component UM may include an upper membrane. The upper membrane may include a synthetic resin membrane. The synthetic resin membrane may include polyimide, polycarbonate, polyamide, cellulose triacetate, polymethyl methacrylate, or polyethylene terephthalate.

[0063] The upper film can be configured to absorb external impacts applied to the front surface of the display device DD. In embodiments of this disclosure, the display module DM may include a color filter, which replaces the polarizing film as an anti-reflective component, thereby reducing the impact intensity on the front surface of the display device DD. The upper film can compensate for the reduced impact intensity achieved by applying the color filter.

[0064] Upper component UM and border area BZA (refer to) Figure 2 ) and transmission region TA (refer to Figure 2 The upper component UM may overlap only with a portion of the border region BZA. A portion of the border pattern BM may be exposed from the upper component UM. In embodiments of this disclosure, the upper component UM may be omitted. In embodiments of this disclosure, the upper component UM may be replaced by an optical film including a polarizer and a retarder.

[0065] The display device DD may also include an adhesive layer between the upper component UM and the window WM, connecting the upper component UM and the window WM. The adhesive layer may be a pressure-sensitive adhesive (PSA) film or an optically clear adhesive (OCA).

[0066] The display module DM is positioned below the upper component UM. The display module DM and the border area BZA (see reference) Figure 2 ) and transmission region TA (reference) Figure 2 The display module DM can completely overlap with the upper component UM within the border area BZA. When viewed from above the plane, the side surfaces of the display module DM can be aligned with the side surfaces of the upper component UM, and the corners of the display module DM can be aligned with the corners of the upper component UM.

[0067] In the bezel area BZA, the pad area PA of the display module DM can overlap with the upper component UM. The portion of the display module DM corresponding to the pad area PA can be bonded to the lower surface of the upper component UM via an adhesive layer. Because the pad area PA overlaps with the upper component UM, and the portion of the display module DM overlapping the pad area PA is bonded to the upper component UM, the upper component UM can adequately support the pad area PA when the circuit board FCB is bonded to the pad area PA.

[0068] The lower component LM may include a lower membrane PF and a cover plate CP. In embodiments of this disclosure, the lower component LM may also include a support plate and a digitizer.

[0069] The lower film PF can expose the pad area PA of the display module DM. The lower film PF can have a smaller size than the display module DM. For example, the lower film PF can overlap only with the display area DM-DA of the display module DM. The opening area PF-OP corresponding to the non-display area DM-NDA can be defined in the lower film PF. Alternatively, the lower film PF can have a size that substantially corresponds to the display module DM. In this case, the opening area PF-OP corresponding to the pad area PA can be defined in the lower film PF. The pad area PA can be exposed through the opening area PF-OP.

[0070] A cover plate (CP) can be disposed below the lower film (PF). The cover plate (CP) increases resistance to compressive forces generated by external pressure. Therefore, the cover plate (CP) can be used to prevent deformation of the display module (DM). The cover plate (CP) can comprise flexible plastic materials, such as polyimide or polyethylene terephthalate. Furthermore, the cover plate (CP) can be a colored film with low light transmittance. The cover plate (CP) can absorb light incident from the outside. For example, the cover plate (CP) can be a black synthetic resin film. When the display device (DD) is viewed from above the window (WM), the components disposed below the cover plate (CP) are invisible to the user.

[0071] A support plate may be further disposed below the cover plate CP. The support plate may include a high-strength metal material. The support plate may include a fiber-reinforced composite material. The support plate may include reinforcing fibers disposed within the matrix portion. The reinforcing fibers may be carbon fiber or glass fiber. The matrix portion may include a polymer resin. The matrix portion may include a thermoplastic resin. For example, the matrix portion may include polyamide resin or polypropylene resin. For example, the reinforcing fiber composite material may be carbon fiber reinforced plastic (CFRP) or glass fiber reinforced plastic (GFRP).

[0072] The main circuit board (MCB) can be disposed on the lower surface of the circuit board (FCB). The FCB may include an insulating film and conductive wiring mounted on the insulating film. The MCB may include signal lines and electronic components. The electronic components may be connected to the signal lines and may be electrically connected to the display module (DM). The electronic components generate various types of electrical signals (e.g., signals for generating images or signals for sensing external inputs) or process sensed signals. The MCB may be provided separately to correspond to each electrical signal to be generated and processed. Three or more main circuit boards may be provided, and the MCB is not necessarily limited to any one embodiment.

[0073] The main circuit board (MCB) may include a driver chip (DIC) installed within the main circuit board (MCB). Figure 2 ).

[0074] Reference Figure 2 and Figure 3The circuit board FCB is attached to the rear surface of the display panel DP (e.g., rear bonding). Since the non-display area DM-NDA of the display module DM is not bent, defects that would occur when the non-display area DM-NDA of the display panel DP is bent can be prevented. Furthermore, the area of ​​the bezel region BZA of the window WM used to cover the non-display area DM-NDA of the display panel DP can be reduced.

[0075] Therefore, foldable electronic devices can have a display surface divided into a display area for images and a surrounding non-display area. Foldable electronic devices can have a layered display module including a window, upper and lower components, a circuit board, and a driver chip. The display module has additional components such as pad areas for electrical bonding, a protective film, a cover plate, and optional reinforcements such as a support plate. By attaching the circuit board to the rear surface of the display panel, this design prevents bending defects in the non-display area and reduces bezel size, thereby improving durability and enabling a thinner device configuration.

[0076] Figure 4 This is a schematic cross-sectional view of a display module according to an embodiment of the present disclosure.

[0077] Reference Figure 4 The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may include a base layer BL, a circuit layer DP-CL, a light-emitting element layer DP-ED, and a packaging layer TFE.

[0078] A circuit layer DP-CL is disposed on the upper surface of the base layer BL. The base layer BL can be a flexible substrate capable of being bent, folded, or rolled to at least a significant extent without causing cracks or other damage. The base layer BL can be a glass substrate, a metal substrate, or a polymer substrate. However, embodiments of this disclosure are not necessarily limited thereto, and the base layer BL can be an inorganic layer, an organic layer, or a composite layer. The base layer BL has a shape substantially the same as that of the display panel DP.

[0079] The base layer BL can have a multilayer structure. For example, the base layer BL may include a first synthetic resin layer, a second synthetic resin layer, and an inorganic layer disposed therebetween. Each of the first and second synthetic resin layers may include a polyimide resin, but is not particularly limited thereto.

[0080] The DP-CL circuit layer can be disposed on the base layer BL. The DP-CL circuit layer may include multiple insulating layers, multiple semiconductor patterns, multiple conductive patterns, and signal lines. The DP-CL circuit layer may include pixel driving circuitry. In the following text, unless otherwise stated, when component A and component B are disposed on the same layer, it can be interpreted that component A and component B are formed using the same process and include the same materials or have the same stacked structure. Conductive patterns or semiconductor patterns disposed on the same layer can be interpreted as described above.

[0081] The light-emitting element layer DP-ED can be disposed on the circuit layer DP-CL. The light-emitting element layer DP-ED can include light-emitting elements. For example, light-emitting elements can include organic light-emitting materials, inorganic light-emitting materials, organic-inorganic light-emitting materials, quantum dots, quantum rods, micro LEDs, or nano LEDs.

[0082] A TFE (Transmission Equipment) encapsulation layer can be disposed on the DP-ED (Distributed Photoelectric Element) layer. The TFE protects the DP-ED from foreign matter such as moisture, oxygen, and dust particles. The TFE may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. The TFE may also include a stacked structure of a first inorganic encapsulation layer, an organic layer, and a second inorganic encapsulation layer.

[0083] The input sensing layer (ISL) can be directly disposed on the display panel (DP). The ISL can sense user input, for example, through electromagnetic induction or capacitive methods. The display panel (DP) and the ISL can be formed in a continuous process. The term "directly disposed" as used herein can mean that a third component is not disposed between the ISL and the DP. For example, a separate adhesive layer may not be required between the ISL and the DP.

[0084] Figure 5 This is a plan view of a display panel according to an embodiment of the present disclosure. Figure 6 This is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0085] like Figure 5 As shown, the display panel DP may include a scan driver circuit SDC, multiple signal lines SGL, and multiple pixels PX. The multiple pixels PX are disposed in the display area DP-DA. Each of the pixels PX includes a light-emitting element and a pixel driving circuit connected thereto. The scan driver circuit SDC, multiple signal lines SGL, and pixel driving circuit may be included in... Figure 6 In the driving element layer 120 shown.

[0086] The scan driver circuit SDC may include a gate driver circuit. The gate driver circuit generates multiple scan signals and sequentially outputs these signals to multiple scan lines GL, which will be described below. The scan driver circuit SDC may also include an emitter driver circuit, distinct from the gate driver circuit. The emitter driver circuit can output scan signals to another set of scan lines.

[0087] The scan driver circuit SDC may include multiple thin-film transistors formed using the same process as the pixel driver circuit (e.g., low-temperature polycrystalline silicon (LTPS) process or low-temperature polycrystalline oxide (LTPO) process).

[0088] The multiple signal lines SGL include scan lines GL, data lines DL, power lines PL, and control signal lines CSL. Each scan line GL is connected to a corresponding pixel PX among the multiple pixels PX, and each data line DL is connected to a corresponding pixel PX among the multiple pixels PX. The power line PL is connected to the multiple pixels PX. The data lines DL provide data signals to the pixels PX. The control signal lines CSL can provide control signals to the scan driver circuit SDC.

[0089] like Figure 8 As shown, the power line PL may include a first power line PL1 that receives a first power supply voltage and a second power line PL2 that receives a second power supply voltage having a level higher than the first power supply voltage. The first power supply voltage is provided to the pixel PX via the first power line PL1, and the second power supply voltage is provided to the pixel PX via the second power line PL2. Although in Figure 5 The diagram shows one control signal line CSL as an example, but multiple control signal lines CSL can be provided.

[0090] Scan lines GL, data lines DL, and power lines PL can overlap with the display area DP-DA and the non-display area DP-NDA, and control signal lines CSL can overlap with the non-display area DP-NDA. The ends of multiple signal lines SGL can be aligned on one side of the non-display area DP-NDA. Each of the multiple signal lines SGL can have a single-unit shape, but can include multiple portions disposed on different layers. The different portions, separated from each other by an insulating layer, can be connected through contact holes penetrating the insulating layer. For example, the data line DL can include a first portion disposed in the display area DP-DA and a second portion disposed in the non-display area DP-NDA on a different layer than the layer where the first portion is disposed. The first and second portions can include different materials and can have different stacking structures.

[0091] The display panel DP may include insulating patterns DMP1 and DMP2. Figure 5The diagram illustrates a first insulating pattern DMP1 and a second insulating pattern DMP2 as examples. The first insulating pattern DMP1 and the second insulating pattern DMP2 are disposed in the non-display area DP-NDA and surround the display area DP-DA. Each of the first insulating pattern DMP1 and the second insulating pattern DMP2 may have a closed line shape. The first insulating pattern DMP1 and the second insulating pattern DMP2 serve as dams to prevent liquid organic materials from overflowing during the inkjet process of the display panel DP. A description of this is given below.

[0092] Figure 6 It shows the corresponding Figure 5 The cross-section of the display module DM with pixel PX.

[0093] The pixel driving circuit PC that drives the light-emitting element (LD) can include multiple pixel driving elements. The pixel driving circuit PC can include multiple transistors and capacitors Cst. Figure 6 The image shows silicon transistor S-TFT and oxide transistor O-TFT as examples. Figure 6 The pixel driving circuit PC is merely an example, and the configuration of the pixel driving circuit PC is not limited to this. The pixel driving circuit PC may include only one of silicon transistor S-TFT and oxide transistor O-TFT.

[0094] In this embodiment, the base layer 110 comprises multiple layers, but for simplicity, it is shown as a single layer. The base layer 110 may include a synthetic resin, such as polyimide. The base layer 110 can be formed by coating a working substrate (or carrier substrate) with a synthetic resin layer. The working substrate can be removed when the display module DM is completed through subsequent processes.

[0095] Reference Figure 6 A barrier layer 10br may be disposed on the base layer 110. The barrier layer 10br prevents the introduction of foreign matter. The barrier layer 10br may include at least one inorganic layer. The barrier layer 10br may include a silicon oxide layer and a silicon nitride layer. Multiple silicon oxide layers and multiple silicon nitride layers may be provided. The silicon oxide layers and silicon nitride layers may be stacked alternately.

[0096] The barrier layer 10br may include a lower barrier layer 10br1 and an upper barrier layer 10br2. A first shielding electrode BMLa may be disposed between the lower barrier layer 10br1 and the upper barrier layer 10br2. The first shielding electrode BMLa may be configured to correspond to a silicon transistor S-TFT. The first shielding electrode BMLa may include a metal, such as molybdenum.

[0097] The first shielding electrode BMLa can receive a bias voltage. The first shielding electrode BMLa can receive a first power supply voltage. The first shielding electrode BMLa can prevent the potential caused by polarization from affecting the silicon transistor S-TFT. The first shielding electrode BMLa can block external light from reaching the silicon transistor S-TFT. In embodiments of this disclosure, the first shielding electrode BMLa can be a floating electrode isolated from other electrodes or wiring.

[0098] A buffer layer 10bf may be disposed on the barrier layer 10br. The buffer layer 10bf can prevent metal atoms or impurities from diffusing from the base layer 110 to the first semiconductor pattern SC1 on the buffer layer 10bf. The buffer layer 10bf may include at least one inorganic layer. The buffer layer 10bf may include a silicon oxide layer and a silicon nitride layer.

[0099] A first semiconductor pattern SC1 may be disposed on the buffer layer 10bf. The first semiconductor pattern SC1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the first semiconductor pattern SC1 may include low-temperature polycrystalline silicon.

[0100] Depending on whether doping is performed, the first semiconductor pattern SC1 can have different electrical properties. The first semiconductor pattern SC1 may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be an undoped region, or it may be a region lightly doped than the first region. In this embodiment, the first semiconductor pattern SC1 may be a semiconductor pattern of an N-type transistor.

[0101] The first region may have a higher conductivity than the second region. The first region may be used essentially as an electrode or a signal line. The second region may substantially correspond to the channel region (or active region) of a transistor. For example, a portion of the first semiconductor pattern SC1 may be the channel of a transistor, another portion may be the source or drain of a transistor, and the remainder may be a connecting electrode or a connecting signal line.

[0102] The source region SE1, channel region AC1 (or active region), and drain region DE1 of a silicon transistor S-TFT can be formed by a first semiconductor pattern SC1. The source region SE1 and drain region DE1 can extend from the channel region AC1 in opposite directions in cross-section.

[0103] The first insulating layer 10 may be disposed on the buffer layer 10bf. The first insulating layer 10 may cover the first semiconductor pattern SC1. The first insulating layer 10 may be an inorganic layer. The first insulating layer 10 may be a single layer of silicon oxide. Not only the first insulating layer 10, but also the inorganic layer of the driving element layer 120 described below may have a single-layer structure or a multi-layer structure, and may include at least one of the aforementioned materials, but is not limited thereto.

[0104] The gate GT1 of the silicon S-TFT is disposed on the first insulating layer 10. The gate GT1 may be part of a metal pattern. The gate GT1 may overlap with the channel region AC1. In the process of doping the first semiconductor pattern SC1, the gate GT1 may be a mask. The first electrode CE10 of the capacitor Cst may be disposed on the first insulating layer 10. Figure 6 As shown, the first electrode CE10 can have a monolithic shape together with the gate GT1.

[0105] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate GT1. In embodiments of this disclosure, the upper electrode overlapping the gate GT1 may be further disposed on the second insulating layer 20. The second electrode CE20 overlapping the first electrode CE10 may be disposed on the second insulating layer 20. When viewed from above the plane, the upper electrode may have a monolithic shape together with the second electrode CE20.

[0106] The second shielding electrode BMLb is disposed on the second insulating layer 20. The second shielding electrode BMLb may be configured to correspond to the oxide transistor O-TFT. In embodiments of this disclosure, the second shielding electrode BMLb may be omitted. According to embodiments of this disclosure, the first shielding electrode BMLb may extend below the oxide transistor O-TFT to replace the second shielding electrode BMLb.

[0107] The third insulating layer 30 may be disposed on the second insulating layer 20. The second semiconductor pattern SC2 may be disposed on the third insulating layer 30. The second semiconductor pattern SC2 may include the channel region AC2 of an oxide transistor O-TFT. The second semiconductor pattern SC2 may include a metal oxide semiconductor. The second semiconductor pattern SC2 may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or zinc oxide (ZnO). x ) or indium oxide (In2O3).

[0108] Metal-oxide-semiconductor (MOS) devices may include multiple regions SE2, AC2, and DE2, distinguished from each other based on whether the transparent conductive oxide is reduced. Regions where the transparent conductive oxide is reduced (hereinafter referred to as reduced regions) have higher conductivity than regions where the transparent conductive oxide is not reduced (hereinafter referred to as non-reduced regions). Reduced regions essentially serve as the source or drain of a transistor or as signal lines. Non-reduced regions essentially correspond to the semiconductor regions (or channels) of a transistor. For example, a portion of the second semiconductor pattern SC2 may be a semiconductor region of a transistor, another portion may be the source region SE2 or the drain region DE2 of a transistor, and the remainder may be a signal transmission region.

[0109] The fourth insulating layer 40 can be disposed on the third insulating layer 30. For example... Figure 6 As shown, the fourth insulating layer 40 may cover the second semiconductor pattern SC2. In embodiments of this disclosure, the fourth insulating layer 40 may be an insulating pattern that overlaps with the gate GT2 of the oxide transistor O-TFT and exposes the source region SE2 and drain region DE2 of the oxide transistor O-TFT.

[0110] The gate GT2 of the oxide transistor O-TFT is disposed on the fourth insulating layer 40. The gate GT2 of the oxide transistor O-TFT may be part of a metal pattern. The gate GT2 of the oxide transistor O-TFT overlaps with the channel region AC2.

[0111] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may cover the gate GT2. Each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 may be an inorganic layer.

[0112] The first connection pattern CNP1 and the second connection pattern CNP2 can be disposed on the fifth insulating layer 50. The first connection pattern CNP1 and the second connection pattern CNP2 can be formed using the same process and therefore can have the same material and the same stacking structure. The first connection pattern CNP1 can be connected to the drain region DE1 of the silicon transistor S-TFT through a first pixel contact hole PCH1 penetrating the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50. The second connection pattern CNP2 can be connected to the source region SE2 of the oxide transistor O-TFT through a second pixel contact hole PCH2 penetrating the fourth insulating layer 40 and the fifth insulating layer 50. The connection relationship between the first connection pattern CNP1 and the silicon transistor S-TFT, and the connection relationship between the second connection pattern CNP2 and the oxide transistor O-TFT, are not necessarily limited to these.

[0113] Insulating layer 60 can be disposed on fifth insulating layer 50. Third connection pattern CNP3 can be disposed on insulating layer 60. Third connection pattern CNP3 can be connected to first connection pattern CNP1 through third pixel contact hole PCH3 penetrating insulating layer 60. Data line DL can be disposed on insulating layer 60. Upper insulating layer 70 can be disposed on insulating layer 60 and can cover third connection pattern CNP3 and data line DL. Third connection pattern CNP3 and data line DL can be formed by the same process and therefore can have the same material and the same stacking structure. Each of insulating layer 60 and upper insulating layer 70 can be an organic layer.

[0114] The first shielding electrode BMLa, the gate GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate GT2 of the oxide transistor O-TFT may comprise molybdenum (Mo), a molybdenum-containing alloy, titanium (Ti), or a titanium-containing alloy, all of which have good heat resistance. The first connection pattern CNP1 and the second connection pattern CNP2 may comprise aluminum, which has high electrical conductivity. The first connection pattern CNP1 and the second connection pattern CNP2 may have a titanium / aluminum / titanium three-layer structure.

[0115] The light-emitting element (LD) may include an anode (AE) (or a first electrode), a light-emitting layer (EL), and a cathode (CE) (or a second electrode). The anode (AE) of the LD may be disposed on the upper insulating layer 70. The anode (AE) may be a (semi-)transmitting electrode or a reflective electrode. The anode (AE) may include a stacked structure of ITO / Ag / ITO sequentially stacked on top of each other. The positions of the anode (AE) and the cathode (CE) may be interchanged.

[0116] A pixel-defining layer (PDL) may be disposed on the upper insulating layer 70. The PDL may be an organic layer. The PDL may have light-absorbing properties. For example, the PDL may be black in color. The PDL may include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The PDL may correspond to a light-blocking pattern with light-blocking properties.

[0117] The pixel defining layer (PDL) may cover a portion of the anode (AE). For example, an opening PDL-OP exposing a portion of the anode (AE) may be defined within the pixel defining layer (PDL). The light-emitting region (LA) may be defined corresponding to the opening PDL-OP. In embodiments of this disclosure, a hole control layer may be disposed between the anode (AE) and the light-emitting layer (EL). The hole control layer may include a hole transport layer and may further include a hole injection layer. An electron control layer may be disposed between the light-emitting layer (EL) and the cathode (CE). The electron control layer may include an electron transport layer and may further include an electron injection layer.

[0118] Encapsulation layer 140 may cover the light-emitting element (LD). Encapsulation layer 140 may include an inorganic encapsulation layer 141, an organic encapsulation layer 142, and an inorganic encapsulation layer 143 sequentially stacked on top of each other. However, the layers constituting encapsulation layer 140 are not limited to these. Inorganic encapsulation layers 141 and 143 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Each of inorganic encapsulation layers 141 and 143 may have a multilayer structure. Organic encapsulation layer 142 may include an acrylic organic layer, but is not limited to this.

[0119] The input sensing layer (ISL) may include at least one conductive layer (or at least one sensor conductive layer) and at least one insulating layer (or at least one sensor insulating layer). In this embodiment, the input sensing layer (ISL) may include a first insulating layer 210 (or a first sensor insulating layer), a first conductive layer 220, a second insulating layer 230 (or a second sensor insulating layer), a second conductive layer 240, and a third insulating layer 250 (or a third sensor insulating layer). Figure 6 The conductive lines of the first conductive layer 220 and the conductive lines of the second conductive layer 240 are schematically shown in the figure.

[0120] The first insulating layer 210 can be directly disposed on the display panel DP. The first insulating layer 210 can be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Each of the first conductive layer 220 and the second conductive layer 240 can have a single-layer structure or a multilayer structure stacked on a third-direction DR3. The first conductive layer 220 and the second conductive layer 240 can include conductive lines defining electrodes with a mesh shape. The conductive lines of the first conductive layer 220 and the second conductive layer 240 can be connected by penetrating contact holes in the second insulating layer 230 or can be unconnected. The connection relationship between the conductive lines of the first conductive layer 220 and the conductive lines of the second conductive layer 240 can be determined according to the type of sensor forming the input sensing layer ISL.

[0121] The first conductive layer 220 and the second conductive layer 240, having a single-layer structure, may comprise a metal layer or a transparent conductive layer. The metal layer may comprise molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The transparent conductive layer may comprise a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). x Alternatively, it can be indium zinc tin oxide (IZTO). Furthermore, the transparent conductive layer may include conductive polymers such as PEDOT, metal nanowires, or graphene.

[0122] The first conductive layer 220 and the second conductive layer 240, having a multilayer structure, may include metal layers. The metal layers may have a three-layer structure, such as titanium / aluminum / titanium. The multilayer conductive layer may include at least one metal layer and at least one transparent conductive layer. A second insulating layer 230 may be disposed between the first conductive layer 220 and the second conductive layer 240. A third insulating layer 250 may cover the second conductive layer 240. In embodiments of this disclosure, the third insulating layer 250 may be omitted. The second insulating layer 230 and the third insulating layer 250 may include inorganic or organic layers.

[0123] Therefore, the layered structure of a display module can include a flexible base layer, a circuit layer with driving elements, a light-emitting layer, and a packaging layer for protection. The display module can integrate both silicon transistors and oxide transistors, various insulating layers and connection layers, and the pixel architecture can include electrodes, a light-emitting layer, and a pixel definition layer to control light emission. An input sensing layer with conductive and insulating films can be added to achieve capacitive or inductive touch input while maintaining transparency and durability.

[0124] Figure 7A This is a plan view of the input sensing layer according to an embodiment of the present disclosure. Figure 7B It is along Figure 7A A cross-sectional view of the input sensing layer taken by line II-II'.

[0125] like Figure 7A As shown, the input sensing layer ISL includes a sensing region IS-DA and a non-sensing region IS-NDA adjacent to the sensing region IS-DA. The sensing region IS-DA and the non-sensing region IS-NDA correspond to... Figure 5 The diagram shows the display area DP-DA and the non-display area DP-NDA. The input sensing layer ISL includes first electrodes E1-1 to E1-5 (or first sensing electrodes), second electrodes E2-1 to E2-4 (or second sensing electrodes), a first signal line SL1 (or a first sensor signal line), and a second signal line SL2 (or a second sensor signal line). Figure 7A The first insulating pattern DMP1 and the second insulating pattern DMP2 are also shown to indicate the positions of the first insulating pattern DMP1 and the second insulating pattern DMP2 relative to the input sensing layer ISL.

[0126] First electrodes E1-1 to E1-5 and second electrodes E2-1 to E2-4, which are insulated from and intersecting each other, are disposed in the sensing area IS-DA. A first signal line SL1 connected to the first electrodes E1-1 to E1-5 and a second signal line SL2 electrically connected to the second electrodes E2-1 to E2-4 are disposed in the non-sensing area IS-NDA. Either the first signal line SL1 or the second signal line SL2 transmits a drive signal from an external circuit for sensing an external input to the corresponding electrode, while the other signal line outputs a sensing signal. The capacitance change between the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 is measured based on the sensing signal. Although a mutual capacitance type input sensing layer is shown as an example in this embodiment, the disclosure is not necessarily limited thereto. A self-capacitance type input sensing layer can be applied. A self-capacitance type input sensing layer may include a type of sensing electrode.

[0127] Each of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may have a mesh shape in which a plurality of openings are defined. The plurality of openings may be defined as light-emitting areas LA corresponding to the display panel DP (see reference). Figure 6 ).exist Figure 6 The diagram shows an opening E-OP corresponding to a light-emitting region LA. Second electrodes E2-1 to E2-4 are insulated from and intersect with the first electrodes E1-1 to E1-5. Any of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 can have a single-cell shape. In this embodiment, first electrodes E1-1 to E1-5 with a single-cell shape are shown as an example. First electrodes E1-1 to E1-5 may include a sensing portion SP1 and an intermediate portion CP1.

[0128] Each of the second electrodes E2-1 to E2-4 may include a sensing pattern SP2 and a bridging pattern CP2 (or a connection pattern). Two adjacent sensing patterns SP2 may be connected by two bridging patterns CP2, but the number of bridging patterns is not necessarily limited.

[0129] Reference Figures 6 to 7B The bridging pattern CP2 can be formed by the first conductive layer 220, and the plurality of first electrodes E1-1 to E1-5 and the sensing pattern SP2 can be formed by the second conductive layer 240. The bridging pattern CP2 can be connected to the sensing pattern SP2 through the contact hole TH-I formed in the second insulating layer 230.

[0130] In this embodiment, Figure 7A Each of the first signal line SL1 and the second signal line SL2 can be generated by Figure 6 The first conductive layer 220 is formed. Therefore, Figure 7AEach of the first signal line SL1 and the second signal line SL2 can be connected to Figure 7B The bridging pattern CP2 is disposed on the same layer. However, it is not limited thereto, each of the first signal line SL1 and the second signal line SL2 may be formed by the second conductive layer 240. Each of the first signal line SL1 and the second signal line SL2 may include both a line formed by the first conductive layer 220 and a line formed by the second conductive layer 240.

[0131] Figure 8 This is an enlarged plan view of a portion of a display module according to an embodiment of the present disclosure. For example, Figure 8 This is an enlarged plan view of the non-display area DP-NDA of the display module DM. Figure 9 It is along Figure 8 The cross-sectional view of the display module is captured by line III-III'. For example, Figure 9 It shows the corresponding Figure 8 The cross-sectional structure of the non-display area DP-NDA of the display module DM of line III-III'.

[0132] like Figure 8 and Figure 9 As shown, the display area DP-DA and non-display area DP-NDA of the display module DM are assigned with Figure 5 The display area DP-DA and the non-display area DP-NDA of the display panel DP are the same as the reference numerals in the attached diagram. Furthermore, the display area DP-DA and the non-display area DP-NDA can respectively correspond to... Figure 7A The sensing area IS-DA and the non-sensing area IS-NDA. In Figure 7A Of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 shown, the first electrode E1-5 and the second electrodes E2-1 to E2-3 are shown in Figure 8 In the display area DP-DA, and it is understood that the configuration of the display panel DP in the display area DP-DA is at least similar to the configuration described above.

[0133] Figure 8 It shows the basis Figure 5 and Figure 7A A magnified view of a corner region CA (or vertex region) and a portion of the non-display region DP-NDA located below the display region DP-DA when viewed from above the plane. Figure 8 Among the multiple components shown, those that overlap are components placed on different layers.

[0134] The first power line PL1 and the second power line PL2 are located in the non-display area DP-NDA. The first power line PL1 can be extended through the corner area CA. Figure 5 The left-hand non-display area DP-NDA is shown. When viewed from above the plane, the boundary line between the display area DA and the non-display area DP-NDA in the corner area CA can be substantially curved. Figure 8 In the diagram, the boundary line between the display area DA and the non-display area DP-NDA is shown as a dashed line.

[0135] The first power line PL1 can pass through Figure 5 The left non-display area DP-NDA is shown, and can extend to the upper non-display area DP-NDA and the right non-display area DP-NDA. When viewed from above the plane, the second power line PL2 can be disposed in the non-display area DP-NDA, which is located below the display area DP-DA, and the second power line PL2 can extend in the first direction DR1. The first power line PL1 and the second power line PL2 can be connected to... Figure 6 The third connection pattern CNP3 shown is set on the same layer.

[0136] A first voltage line VL1 and a second voltage line VL2 are disposed in the non-display area DP-NDA. Although one first voltage line VL1 and one second voltage line VL2 are shown, this disclosure is not necessarily limited thereto, and multiple first voltage lines VL1 and multiple second voltage lines VL2 may be provided. The first voltage line VL1 may receive a first voltage, and the second voltage line VL2 may receive a second voltage higher than the first voltage. In embodiments of this disclosure, the first voltage may be a first power supply voltage, and the second voltage may be a second power supply voltage.

[0137] When viewed from above the plane, the first voltage line VL1 and the second voltage line VL2 do not overlap with the second power line PL2, and are positioned below the second power line PL2. The edge EG of the display module DM can be... Figure 9 The edge 110-EG of the base layer 110 shown. The edge 110-EG of the base layer 110 refers to the state of the side surface of the base layer 110 when viewed from above the plane. The first voltage line VL1 and the second voltage line VL2 can be connected to... Figure 6 The third connection pattern CNP3 shown is set on the same layer, or it can be set on the same layer as the first connection pattern CNP1.

[0138] At least one control signal line (CSL) is located in the non-display area DP-NDA. The control signal line (CSL) can be connected via the corner area (CA). Figure 5 The scan driver circuit SDC is shown in the diagram. The control signal line CSL can overlap with the first power supply line PL1 and the second power supply line PL2. Figure 6The first shielding electrode BMLa, the gate GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate GT2 of the oxide transistor O-TFT shown are disposed in the same layer.

[0139] The data cable DL is positioned within the display area DP-DA and the non-display area DP-NDA. The portion of the data cable DL that overlaps with the display area DP-DA can be... Figure 6 One of the first connection pattern CNP1 and the third connection pattern CNP3 shown is set on the same layer. The portion of the data line DL that overlaps with the non-display area DP-NDA can be... Figure 6 The first shielding electrode BMLa, the gate GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate GT2 of the oxide transistor O-TFT shown are disposed in the same layer. The portions of the data line DL that overlap with the display area DP-DA and the portions of the data line DL that overlap with the non-display area DP-NDA can be penetrated. Figure 6 The contact holes of the corresponding layers in the barrier layer 10br, buffer layer 10bf, and insulating layers 10 to 70 shown are connected. The connection point between the portion of the data line DL that overlaps with the display area DP-DA and the portion of the data line DL that overlaps with the non-display area DP-NDA can be located in the non-display area DP-NDA adjacent to the boundary line between the display area DP-DA and the non-display area DP-NDA.

[0140] The data line DL can cross the first voltage line VL1, the second voltage line VL2, and the second power line PL2. The electrostatic discharge (ESD) protection circuit connected to the data line DL, the first voltage line VL1, and the second voltage line VL2 is located in the non-display area DP-NDA. The ESD protection circuit can also be located between the first voltage line VL1 and the second voltage line VL2. Figure 8 In the example, an electrostatic discharge (ESD) protection circuit is shown. However, it is not necessarily limited to this; an ESD protection circuit can be connected to each data line DL, or multiple ESD protection circuits can be connected to the respective data lines DL.

[0141] The second signal line SL2 is disposed in the non-display area DP-NDA. The second signal line SL2 may overlap with the control signal line CSL, and may overlap with the first power line PL1 or the second power line PL2. Each of the second signal lines SL2 may be connected to the corresponding electrode among the second electrodes E2-1 to E2-3 disposed in the display area DP-DA.

[0142] exist Figure 8The image shows an alignment mark AM set in the corner region CA as an example. The alignment mark AM can be used as a reference point for aligning the display module DM with the mask during the deposition process.

[0143] Reference Figure 9 The structure and reference of the base layer 110, driving element layer 120, light-emitting element layer 130, encapsulation layer 140 and input sensing layer ISL disposed in the display area DP-DA Figure 6 The configurations described are identical, and to the extent that the element is not described in detail with respect to this figure, it can be understood that the element is at least similar to a corresponding element described elsewhere in this disclosure. Figure 9 The diagram illustrates the point. Figure 6 The pixel driving circuit of the PC uses silicon transistors S-TFTs. (Refer to...) Figure 6 Each of the described barrier layer 10br, buffer layer 10bf, insulating layers 10 to 50, and pixel defining layer PDL can extend from the display area DP-DA to the non-display area DP-NDA. The shape of the extension can vary depending on the layers among the barrier layer 10br, buffer layer 10bf, insulating layers 10 to 50, and pixel defining layer PDL. (See reference...) Figure 6 Each of the described insulating layer 60, upper insulating layer 70, encapsulation layer 140, first insulating layer 210, second insulating layer 230, and third insulating layer 250 can extend from the display area DP-DA to the non-display area DP-NDA. The shape of the extension can vary depending on the layers among the insulating layer 60, upper insulating layer 70, encapsulation layer 140, first insulating layer 210, second insulating layer 230, and third insulating layer 250. Each of the insulating layer 60, upper insulating layer 70, encapsulation layer 140, first insulating layer 210, second insulating layer 230, and third insulating layer 250 can be disposed within a portion of the non-display area DP-NDA.

[0144] Figure 10 This is an enlarged plan view of the non-display area of ​​a display module according to an embodiment of the present disclosure. Figure 10 yes Figure 8 The image shows a magnified view of the non-display area DP-NDA. Figure 10 The image shows some of the data lines DL.

[0145] Reference Figure 10 A first voltage line VL1 and a second voltage line VL2 can be configured. Multiple electrostatic discharge (ESD) protection circuits can be configured to be spaced apart from each other between the first voltage line VL1 and the second voltage line VL2. The ESD protection circuits may include a first transistor connected to the data line DL in a diode configuration from the first voltage line VL1 and a second transistor connected to the second voltage line VL2 in a diode configuration from the data line DL.

[0146] Each of the multiple data lines DL can be electrically connected to the conductive pattern CDP via a contact hole CH. The contact hole CH is shown adjacent to the first voltage line VL1, but can be arranged differently. The conductive pattern CDP can include a molybdenum-containing alloy, titanium (Ti), or a titanium-containing alloy. In an embodiment, the conductive pattern CDP can include aluminum with high conductivity. The conductive pattern CDP can have a titanium / aluminum / titanium three-layer structure.

[0147] Multiple conductive patterns CDPs can be provided. The conductive patterns CDPs can be positioned in the direction opposite to the second direction DR2 of the first voltage line VL1. The conductive patterns CDPs can be positioned in a one-to-one correspondence with the data line DL. The conductive patterns CDPs can be arranged alternately and spaced apart from each other in the first direction DR1. The positions of the conductive patterns CDPs are merely illustrative and can be varied. Conductive openings COPs can be defined in each of the conductive patterns CDPs. A detailed description of this is given below.

[0148] Figure 11 yes Figure 10 A magnified plan view of a portion of the non-display area. For example, Figure 11 This is an enlarged plan view of the conductive pattern CDP according to an embodiment of the present disclosure. Figure 12 It is along Figure 11 A cross-sectional view of a portion of the display panel, taken by line IV-IV'. Figure 11 middle, Figure 10 One of the conductive patterns CDP is magnified and shown on a plane. Figure 12 In the original text, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, the insulating layer 60, and the upper insulating layer 70 are omitted, and can be combined with... Figure 6 The same description applies to omitted components. Furthermore, duplicate descriptions that are identical to those given above will be omitted.

[0149] Reference Figure 12 A first opening (BOP) can be defined in the base layer 110. The base layer 110 may include a thin glass substrate, a protective film disposed on the thin glass substrate, and an adhesive layer connecting the thin glass substrate and the protective film. Components of the circuit board FCB can be disposed in the first opening (BOP). For example, the circuit board FCB can be in the display panel DP (see...). Figure 3 The circuit board FCB is bent and attached to the display panel DP while being bent on the rear surface of the circuit board FCB. The adhesive layer AF can be disposed between the lower surface of the base layer 110 and the circuit board FCB. The circuit board FCB can be fixed to the lower surface of the base layer 110 by the adhesive layer AF.

[0150] The circuit board FCB may include a base film BF and bump electrodes BMP disposed on the base film BF. The base film BF may have a monolithic shape and may be electrically connected to the bump electrodes BMP. In this case, the base film BF may include multiple lines internally. However, it is not limited to this; the base film BF may only be attached to the bump electrodes BMP and may not be electrically connected to them. In this case, the base film BF may include a synthetic resin material, such as polyimide. The bump electrodes BMP may be disposed on the base film BF. Multiple bump electrodes BMP may be provided.

[0151] The adhesive layer AF can be disposed between the base film BF and the lower surface of the base layer 110. According to embodiments of the present disclosure, the adhesive layer AF may include a non-conductive material. For example, the adhesive layer AF may include a non-conductive film.

[0152] According to embodiments of this disclosure, the second opening IOP may be defined within the first insulating layer 10. The first insulating layer 10 may include an inner surface IS defining the second opening IOP. The second opening IOP may be connected to... Figure 11 The conductive pattern CDP shown overlaps with the design. For example, the second opening IOP can be with... Figure 11 The conductive pattern CDP shown includes partially overlapping circular shapes.

[0153] A metallic pattern (MP) can be set within a second opening (IOP). For example, the metallic pattern (MP) can fill the second opening (IOP). The metallic pattern (MP) can be a pattern obtained by curing metallic ink. The metallic pattern (MP) can include solder paste. The metallic pattern (MP) can be formed from metallic ink containing silver or copper. The metallic pattern (MP) can be formed by photocuring metallic ink.

[0154] Let's refer to each other. Figure 11 and Figure 12 The conductive pattern CDP may include a first portion B1 that overlaps with the second opening IOP, a second portion B2 that does not overlap with the second opening IOP, and a third portion B3 that connects the first portion B1 and the second portion B2. For example... Figure 12 As shown, the first portion B1 can be disposed within the second opening IOP, and the second portion B2 can be disposed outside the second opening IOP. The third portion B3 can be disposed within the second opening IOP. For example, the third portion B3 can be disposed on the inner surface IS.

[0155] According to embodiments of this disclosure, a conductive opening COP may be defined within a conductive pattern CDP to expose at least a portion of the inner surface IS of the first insulating layer 10. The conductive opening COP may include a first conductive opening COP1 and a second conductive opening COP2. At least a portion of the inner surface IS of the first insulating layer 10 may be exposed by the first conductive opening COP1. A plurality of first conductive openings COP1 may be provided. The second conductive opening COP2 may be defined within a first portion B1. For example, the second conductive opening COP2 may be formed at the center of the conductive pattern CDP. The first conductive opening COP1 and the second conductive opening COP2 each overlap with a second opening IOP. The second conductive opening COP2 may have a width smaller than the width of the second opening IOP.

[0156] The bump electrode BMP can be electrically connected to the conductive pattern CDP. For example, the bump electrode BMP can be electrically connected to the conductive pattern CDP via a metal pattern MP. In an embodiment, the metal pattern MP can be disposed in the second opening IOP. The metal pattern MP can cover the upper surface of the first portion B1 and can cover at least a portion of the upper surface of the second portion B2. Furthermore, the metal pattern MP can be in direct contact with the first portion B1 to the third portion B3. For example, the metal pattern MP can also be disposed in the first conductive opening COP1 and the second conductive opening COP2 to directly contact at least a portion of the first portion B1 to the third portion B3 and the inner surface IS of the first insulating layer 10.

[0157] The metallic pattern MP can be formed by photocuring metallic ink. When light is emitted from the outside into the metallic ink in the second opening IOP, the light emitted to the metallic ink may be reflected by the conductive pattern CDP having a titanium / aluminum / titanium three-layer structure, so that a portion of the metallic ink may not be sintered. Since the conductive opening COP is defined in the conductive pattern CDP of this disclosure, the metallic ink can receive light through the conductive opening COP in the photocuring metallic ink step, and therefore the photocuring step can be performed efficiently. For example, the metallic ink can be completely sintered to form the metallic pattern MP, and as a result, a display device DD with improved electrical reliability can be provided (see reference). Figure 2 ).

[0158] Figure 13A and Figure 13B This is a cross-sectional view of a portion of a display panel according to an embodiment of the present disclosure.

[0159] refer to Figure 13AThe base layer 110a may include a first sub-base layer SBL1, a sub-insulating layer SIL disposed on the first sub-base layer SBL1, and a second sub-base layer SBL2 disposed on the sub-insulating layer SIL. A first opening BOP may be defined within the first sub-base layer SBL1. Each of the first sub-base layer SBL1 and the second sub-base layer SBL2 may include the same material. For example, each of the first sub-base layer SBL1 and the second sub-base layer SBL2 may include a polyimide resin.

[0160] exist Figure 13A In this configuration, the metal pattern MP can be set in the base layer 110a. For example, the metal pattern MP can be set in the second opening IOP. Figure 13A As shown, the metal pattern MP may not contact at least a portion of the upper surface of the second part B2.

[0161] refer to Figure 13B The first insulating layer 10 may include an inner surface ISa defining a second opening IOP. The inner surface ISa may include a curved surface. For example, the inner surface ISa may include a curved surface recessed in the thickness direction of the base layer 110a. As a result, in the step of photocuring the metallic ink to form a metallic pattern MP, the light path toward the metallic ink can be shortened, and thus the metallic ink can effectively receive light through the conductive opening COP.

[0162] Figure 14 yes Figure 10 A magnified plan view of a portion of the non-display area. For example, Figure 14 This is an enlarged plan view of the conductive pattern CDPa according to an embodiment of the present disclosure. Figure 15 It is along Figure 14 The line V-V' is a cross-sectional view of a portion of the display panel.

[0163] refer to Figure 15 A metal pattern MP can be formed under the first part B1. For example, the metal pattern MP can contact the lower surface of the first part B1 to electrically connect the circuit board FCBa and the conductive pattern CDPa.

[0164] The circuit board FCBa may include a base film BFa and a bump electrode BMPa disposed on the base film BFa. According to embodiments of this disclosure, a first sub-opening SOP1 may be defined in the bump electrode BMPa, and a second sub-opening SOP2 may be defined in the base film BFa. When viewed from above the plane, the first sub-opening SOP1 and the second sub-opening SOP2 may overlap with a first portion B1. In embodiments, the second sub-opening SOP2 may have a width greater than the width of the first sub-opening SOP1. The openings corresponding to the first sub-opening SOP1 and the second sub-opening SOP2 may be defined in the adhesive layer AFa.

[0165] The metal pattern MP can be disposed in the first sub-opening SOP1 and the second sub-opening SOP2. The metal pattern MP can cover at least a portion of the lower surface of the bump electrode BMPa. The metal pattern MP can be disposed in the first sub-opening SOP1 and the second sub-opening SOP2 to electrically connect the circuit board FCBa and the conductive pattern CDPa.

[0166] Reference Figure 14 and Figure 15 The insulating opening COPa can be disposed on the side surface of the first insulating layer 10 and the side surface of the upper barrier layer 10br2. The insulating opening COPa may not be formed at the center of the conductive pattern CDPa. However, this disclosure is not necessarily limited thereto, and the insulating opening COPa can be as follows: Figure 11 The second conductive opening COP2, as shown, is formed at the center of the conductive pattern CDPa. In this case, the insulating opening COPa can have a width smaller than that of the first sub-opening SOP1.

[0167] Figure 16 This is a cross-sectional view of a portion of a display panel according to an embodiment of the present disclosure.

[0168] Reference Figure 16 , with circuit board FCB (refer to Figure 12 The connecting portion CNP of the electrical connection can be disposed below the adhesive layer AFa. The connecting portion CNP may include a first sub-part SB1 and a second sub-part SB2. The first sub-part SB1 may be made of the same material as the conductive pattern CDP, and the second sub-part SB2 may be made of the same material as the first insulating layer 10. The first sub-part SB1 may be referred to as a sub-conductive pattern. The first sub-part SB1 may be with... Figure 15 The base film BFa of the circuit board FCBa shown is electrically connected. For example, the base film BFa of the circuit board FCBa can be electrically connected to the conductive pattern CDP via the first sub-part SB1 and the metal pattern MP.

[0169] Figures 17A to 17I It is a plan view of a conductive pattern according to various embodiments of the present disclosure.

[0170] Reference Figure 17A When viewed from above the plane, the conductive opening COPb defined in the conductive pattern CDP can have a triangular shape.

[0171] Reference Figure 17B When viewed from above the plane, the conductive opening COPc defined in the conductive pattern CDP can have a rectangular shape. Furthermore, when viewed from above the plane, the conductive opening COPc located at the center of the conductive pattern CDP can have a rhomboid shape.

[0172] Reference Figure 17C and Figure 17D Two conductive openings, COPd or COPe, can be defined within a conductive pattern CDP. The conductive openings COPd or COPe can be symmetrical about each other with respect to the center of the conductive pattern CDP.

[0173] Reference Figure 17E The conductive opening COPf defined in the conductive pattern CDP can be formed through the outer surface of the conductive pattern CDP.

[0174] refer to Figure 17F The conductive opening COPg defined in the conductive pattern CDP can be provided as an opening extending from the center of the conductive pattern CDP.

[0175] Reference Figure 17G Multiple conductive openings (COPh) can be defined within a conductive pattern (CDP). For example... Figure 17G As shown, nine conductive openings (COPh) can be provided.

[0176] refer to Figure 17H and Figure 17I Multiple conductive openings COPi or COPj defined in the conductive pattern CDP can be patterned and provided in any area.

[0177] Figure 18A and Figure 18B It is a plan view of a conductive pattern according to an embodiment of the present disclosure.

[0178] Reference Figure 18A When viewed from above the plane, the portion of the conductive pattern CDPa that defines the conductive opening COP can have a rhomboid shape. For example, the portion of the conductive pattern CDPa that defines the conductive opening COP can have a quadrilateral shape.

[0179] refer to Figure 18B When viewed from above the plane, the portion of the conductive pattern CDPb that defines the conductive opening COP can have a polyhedral shape. For example, the portion of the conductive pattern CDPb that defines the conductive opening COP can have a hexagonal shape.

[0180] Therefore, according to embodiments of this disclosure, the sensing layer may include a first electrode and a second electrode arranged in a cross pattern, as well as signal lines in a non-sensing area, to detect external input through capacitance changes. Conductive patterns, openings, and metal patterns may be arranged and shaped to ensure a reliable electrical connection between the circuit board and the display, while enabling efficient photocuring of the metal ink for a strong, uniform bond.

[0181] Figure 19This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0182] Reference Figure 19 An electronic device ED according to an embodiment of the present disclosure may include a display module DM, a processor 12, a memory 13, and a power module 14.

[0183] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0184] The data required for the operation of the processor 12 or the display module DM can be stored in the memory 13. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module DM, and the display module DM can process the provided signals and output image information through the display screen.

[0185] The power module 14 may include a power supply module such as a power adapter or battery device and a power conversion module, which converts the power supplied by the power supply module and generates the power required for the operation of the electronic device ED.

[0186] At least one of the components of the above-described electronic device ED may be included in the display device DD (refer to the above embodiment) Figure 2 In addition, some of the individual modules that are functionally included in one module may be included in the display device DD (refer to...). Figure 2 In ), while other modules can be integrated with the display device DD (refer to ). Figure 2 ) are provided separately. For example, the display device DD (refer to Figure 2 The device may include a display module DM, and the processor 12, memory 13, and power module 14 may be in the electronic device ED that is not the display device DD (see reference). Figure 2 It is provided in the form of other devices.

[0187] Figure 20 A schematic diagram of an electronic device according to various embodiments of the present disclosure is shown.

[0188] Reference Figure 20 The application uses a display device DD (refer to) according to an embodiment. Figure 2The various electronic devices ED can include not only electronic devices for displaying images, such as smartphones 10_1a, tablet computers 10_1b, laptops / notebook computers 10_1c, TVs 10_1d, and computer monitors 10_1e, but also wearable electronic devices containing display modules, such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c, as well as vehicle electronic devices 10_3 containing display modules, such as central information displays (CIDs) and interior mirror displays installed on the vehicle's instrument panel, center console trim, and dashboard.

[0189] Figures 21A to 21I This is a view illustrating the steps of an electronic device manufacturing method according to an embodiment of the present disclosure. (Refer to...) Figures 21A to 21I In the description of the method of manufacturing an electronic device according to embodiments of the present disclosure, components that are the same as those described above will be given the same reference numerals, and to the extent that an element is not described in detail with respect to the figure, it may be understood that the element is at least similar to a corresponding element that has been described elsewhere in this disclosure.

[0190] refer to Figure 21A The steps of forming a base layer 110, a lower barrier layer 10br1, and an upper barrier layer 10br2 that are stacked sequentially on top of each other can be performed. The steps of forming the base layer 110, the lower barrier layer 10br1, and the upper barrier layer 10br2 can be performed sequentially.

[0191] refer to Figure 21B This allows for the etching of the lower barrier layer 10br1 and the upper barrier layer 10br2. (See reference...) Figure 21C The process can perform the steps of forming a first insulating layer 10 on a base layer 110, a lower barrier layer 10br1, and an upper barrier layer 10br2, and the step of forming a preliminary conductive pattern CDP-P on the first insulating layer 10. The preliminary conductive pattern CDP-P can have a titanium / aluminum / titanium three-layer structure.

[0192] refer to Figure 21D It can perform etching of the initial conductive pattern CDP-P (refer to...) Figure 21C The steps of ) and the first insulating layer 10. The conductive pattern CDP can be formed by etching the initial conductive pattern CDP-P (refer to) Figure 21C To form it. In the step of etching the first insulating layer 10, it can be formed by... Figure 12 The second opening IOP is defined in the first insulating layer 10 shown.

[0193] Let's refer to each other. Figure 11 , Figure 12 and Figure 21EThe step of forming a conductive opening COP in a conductive pattern CDP can be performed. A separate mask can be used to form the conductive opening COP. The conductive opening COP can expose at least a portion of the inner surface IS of the first insulating layer 10 to the outside. In the process of forming the conductive opening COP, the conductive pattern CDP may include a first portion B1, a second portion B2, and a third portion B3.

[0194] refer to Figure 21F The step of etching the base layer 110 can be performed. The step of etching the base layer 110 can be performed by a laser emitted from a laser device. The first opening BOP can be formed in the base layer 110 by applying a laser to the base layer 110.

[0195] Reference Figure 21G The step of placing the circuit board FCB in the first opening BOP can be performed. The circuit board FCB can be disposed on the lower surface of the base layer 110. The adhesive layer AF can be disposed between the circuit board FCB and the lower surface of the base layer 110. The circuit board FCB can be fixed to the lower surface of the base layer 110 by the adhesive layer AF.

[0196] The circuit board FCB may include a base film BF and bump electrodes BMP disposed on the base film BF. The base film BF may have a monolithic shape and may be electrically connected to the bump electrodes BMP. The bump electrodes BMP may be fixed to the lower surface of the base layer 110 by an adhesive layer AF.

[0197] Let's refer to each other. Figure 21H and Figure 21I This allows for the formation of a metallic pattern MP on a bump electrode (BMP) and a conductive pattern (CDP). For example... Figure 21H As shown, the preliminary metal pattern MP-P can be set in the second opening IOP (see reference). Figure 12 The preliminary metal pattern MP-P can be a metallic ink before it is cured. The preliminary metal pattern MP-P can be photocured by emitting light (Lg) onto it. Since the conductive pattern CDP of this disclosure defines a conductive opening COP (refer to...), the preliminary metal pattern MP-P can be photocured. Figure 11 Therefore, in the step of photocuring the initial metal pattern MP-P, the metal ink can receive light through the conductive opening COP, and thus the photocuring step can be performed efficiently. For example, the metal ink can be completely sintered to form the metal pattern MP, and as a result, a display device DD with improved electrical reliability can be provided (see reference). Figure 2 The metal pattern MP can contact the conductive pattern CDP and the bump electrode BMP to electrically connect the circuit board FCB and the conductive pattern CDP.

[0198] As described above, conductive openings can be defined in the conductive patterns included in the electronic devices of this disclosure. Therefore, in the step of photocuring the metallic ink to form a metallic pattern, the metallic ink can receive light through the conductive openings, and thus the photocuring step can be performed efficiently. As a result, the metallic ink can be completely sintered to form a metallic pattern, and an electronic device with improved electrical reliability can be provided.

[0199] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of this disclosure.

Claims

1. Electronic devices, including: The display panel is configured to display images; The circuit board is connected to the display panel; as well as Metallic patterns are used to electrically connect the display panel to the circuit board. The display panel includes: The base layer has a first opening therein; An insulating layer disposed on the base layer, the insulating layer having a second opening defined therein, the second opening overlapping the first opening; and A conductive pattern is disposed on the insulating layer, the conductive pattern having a conductive opening defined therein, the conductive opening exposing at least a portion of the inner surface of the insulating layer, wherein the inner surface defines the second opening.

2. The electronic device according to claim 1, wherein, The metal pattern is disposed in the second opening and contacts the inner surface of the insulating layer.

3. The electronic device according to claim 2, wherein, The conductive pattern includes: The first part overlaps with the second opening; and The second part does not overlap with the second opening. The metal pattern covers the upper surface of the first part.

4. The electronic device according to claim 3, wherein, The conductive pattern further includes a third portion configured to connect the first portion to the second portion and disposed on the inner surface of the insulating layer, and The conductive opening is defined in the third part.

5. The electronic device according to claim 4, wherein, The conductive opening includes a plurality of conductive openings, and at least one of the plurality of conductive openings is defined in the first portion.

6. The electronic device according to claim 3, wherein, The metal pattern covers at least a portion of the upper surface of the second part.

7. The electronic device according to claim 2, wherein, The lower surface of the metal pattern is in contact with the bump electrode of the circuit board.

8. The electronic device according to claim 1, wherein, The conductive pattern includes: The first part overlaps with the second opening; and The second part does not overlap with the second opening. The metal pattern is disposed in the first opening and in contact with the first portion.

9. The electronic device according to claim 8, wherein, The circuit board includes: Base membrane; and A bump electrode is disposed between the base film and the base layer. The bump electrode and the conductive pattern are electrically connected to each other through the metal pattern.

10. The electronic device according to claim 9, wherein, The metal pattern is exposed through the first opening, and The metal pattern and the bump electrode are electrically connected to each other in the first opening.

11. The electronic device according to claim 10, wherein, The first sub-opening, which overlaps with the first portion, is defined within the bump electrode. Wherein, the second sub-opening overlapping the first sub-opening is defined within the base membrane, and The second sub-opening has a width greater than that of the first sub-opening.

12. The electronic device according to claim 11, wherein, The metal pattern is disposed in the first sub-opening and the second sub-opening, and The metal pattern covers at least a portion of the lower surface of the bump electrode.

13. The electronic device according to claim 10, further comprising: The connection portion includes sub-conductive patterns electrically connected to the circuit board. The conductive pattern and the sub-conductive pattern are electrically connected to each other through the metal pattern.

14. The electronic device according to claim 1, further comprising: A barrier layer is disposed between the base layer and the insulating layer.

15. The electronic device according to claim 1, wherein, The base layer includes a first sub-base layer, a sub-insulating layer disposed on the first sub-base layer, and a second sub-base layer disposed on the sub-insulating layer. The first opening is defined within the first sub-base layer.

16. The electronic device according to claim 1, wherein, The inner surface includes a curved surface that is recessed in the thickness direction of the base layer.

17. Electronic devices, including: The display panel is configured to display images; The processor is configured to provide image data to the display panel; The circuit board is connected to the display panel; Metallic patterns are used to electrically connect the display panel to the circuit board; A window is provided on the display panel; as well as A housing, disposed below the display panel and connected to the window, is configured to house the display panel and the circuit board. The display panel includes: The base layer has a first opening therein; An insulating layer disposed on the base layer, the insulating layer having a second opening defined therein that overlaps with the first opening; and A conductive pattern is disposed on the insulating layer, the conductive pattern having a conductive opening defined therein that exposes at least a portion of an inner surface of the insulating layer, wherein the inner surface defines the second opening.

18. A method for manufacturing an electronic device, the method comprising: A base layer is formed having a first opening therein; An insulating layer is formed on the base layer, the insulating layer having a second opening therein that overlaps with the first opening; A conductive pattern is formed on the insulating layer; The conductive pattern is patterned to form a conductive opening that exposes at least a portion of the inner surface of the insulating layer, wherein the inner surface defines the second opening; A bump electrode for the circuit board is provided in the first opening; and A metallic pattern is formed in the second opening. The conductive pattern is electrically connected to the bump electrode through the metal pattern.

19. The method according to claim 18, wherein, The patterning of the conductive pattern is performed after the second opening is formed.

20. The method according to claim 18, wherein, When the metal pattern is formed, the metal pattern comes into contact with the inner surface of the insulating layer.

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