Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises: a display area having an axis along a first direction; a non-display area at least partially surrounding the display area; the non-display area comprising a first edge area, a second edge area and a binding area, located on the same side of the display area along the first direction, the first edge area and the second edge area being respectively located on both sides of the display area along a second direction; at least a part of the area of the second edge area after symmetry about the axis is located in the first edge area; a substrate, at least part of the substrate being located in the display area and at least part of the substrate being located in the non-display area; a display function layer arranged on one side of the substrate; at least part of the display function layer is located in the display area and at least part of the display function layer is located in the non-display area; the display function layer comprises a plurality of virtual units, and at least part of the virtual units are arranged in the first edge area. The display panel and the display device disclosed by the application can improve the uniformity of the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In the non-display area of ​​the display panel, there is a region for bonding other circuit boards, such as flexible circuit boards. Considering the shape of the circuit boards, the bonding area is located near one edge of the display panel, resulting in an asymmetrical structure. When manufacturing such a display panel, the area of ​​one corner of the non-display area is larger than the area of ​​the other corner, causing inconsistencies in the manufacturing process and resulting in uneven circuitry, which in turn leads to uneven display quality. Summary of the Invention

[0003] This application provides a display panel and display device that can improve the uniformity of display effect.

[0004] In a first aspect, embodiments of this application provide a display panel, comprising: a display area having an axis along a first direction; a non-display area at least partially surrounding the display area; the non-display area includes a first edge area, a second edge area, and a bonding area, the first edge area, the second edge area, and the bonding area being located on the same side of the display area along the first direction, the first edge area and the second edge area being located on opposite sides of the display area along a second direction, the first direction and the second direction intersecting; at least a portion of the area of ​​the second edge area symmetrical about the axis is located within the first edge area; a substrate, at least a portion of the substrate being located in the display area, and at least a portion of the substrate being located in the non-display area; a display functional layer disposed on one side of the substrate; at least a portion of the display functional layer being located in the display area, and at least a portion of the display functional layer being located in the non-display area; the display functional layer includes a plurality of virtual units, at least a portion of which are disposed in the first edge area.

[0005] According to an embodiment of the first aspect of this application, the display functional layer includes an array layer, the array layer includes a plurality of driving circuits, the driving circuits are located in the non-display area; the virtual unit includes a plurality of virtual circuits, at least a portion of the virtual circuits are on the same layer as at least a portion of the driving circuits and are insulated from each other.

[0006] According to an embodiment of the first aspect of this application, the driving circuit includes a thin-film transistor, and at least a portion of the virtual circuit is disposed on the same layer as the thin-film transistor.

[0007] According to an embodiment of the first aspect of this application, a thin-film transistor includes an active layer, a gate insulating layer, a gate, and an interlayer insulating layer stacked sequentially; a virtual circuit includes a first inorganic layer, a first insulating layer, a first metal layer, and a second insulating layer stacked sequentially; the first inorganic layer and the active layer are disposed on the same layer, the first insulating layer and the gate insulating layer are disposed on the same layer, the first metal layer and the gate are disposed on the same layer, and the second insulating layer and the interlayer insulating layer are disposed on the same layer.

[0008] According to an embodiment of the first aspect of this application, the non-display area further includes a third edge area, which is located on one side of the display area along the second direction, and at least a portion of the driving circuits are located in the third edge area; the number of driving circuits per unit area in the third edge area is n1, and the number of virtual circuits per unit area in the first edge area is n2, wherein n1 = n2.

[0009] According to an embodiment of the first aspect of this application, the display functional layer includes an array layer, the array layer includes a plurality of pixel circuits, the pixel circuits are located in the display area; the virtual unit includes a plurality of virtual circuits, at least a portion of the virtual circuits are on the same layer as at least a portion of the pixel circuits and are insulated from each other.

[0010] According to an embodiment of the first aspect of this application, the pixel circuit includes a thin-film transistor, and at least a portion of the virtual circuit is disposed on the same layer as the thin-film transistor.

[0011] According to an embodiment of the first aspect of this application, a thin-film transistor includes an active layer, a gate insulating layer, a gate, and an interlayer insulating layer stacked sequentially; a virtual circuit includes a first inorganic layer, a first insulating layer, a first metal layer, and a second insulating layer stacked sequentially; the first inorganic layer and the active layer are disposed on the same layer, the first insulating layer and the gate insulating layer are disposed on the same layer, the first metal layer and the gate are disposed on the same layer, and the second insulating layer and the interlayer insulating layer are disposed on the same layer.

[0012] According to an embodiment of the first aspect of this application, the number of pixel circuits per unit area in the display area is n3, and the number of virtual circuits per unit area in the first edge area is n2, wherein n3 = n2.

[0013] According to an embodiment of the first aspect of this application, the display function layer includes a light-emitting device layer, which includes a plurality of light-emitting devices located in the display area; the virtual unit includes a plurality of virtual devices, at least a portion of which is on the same layer as at least a portion of the virtual device and is insulated from it.

[0014] According to an embodiment of the first aspect of this application, the number of light-emitting devices per unit area in the display area is n4, and the number of virtual devices per unit area in the first edge area is n5, wherein n4 = n5.

[0015] According to an embodiment of the first aspect of this application, the distance from one end of the binding area near the first edge area along the second direction to the axis is D1, and the distance from one end of the binding area near the second edge area along the second direction to the axis is D2, wherein D1 > D2.

[0016] According to an embodiment of the first aspect of this application, at least a portion of the virtual units are located in the second edge region.

[0017] Secondly, embodiments of this application provide a display device, including the display panel of the first aspect of this application.

[0018] In the display panel and display device provided in this application embodiment, the display area of ​​the display panel has an axis along a first direction. The first edge area, the second edge area, and the bonding area of ​​the non-display area are located on the same side of the display area along the first direction. The first edge area and the second edge area are respectively located on both sides of the display area along the second direction. The first edge area and the second edge area correspond to the two corners of the side edge of the display panel where the bonding area is located. At least a portion of the area of ​​the second edge area after symmetry about the axis is located within the first edge area. The first edge area is larger than the second edge area, so that the display panel forms an asymmetrical structure. The display functional layer located on one side of the substrate includes multiple virtual units. The virtual units are set in the first edge area. By setting virtual units in the first edge area, the manufacturing process of the display functional layer in the first edge area is similar to the manufacturing process in the display area, thereby making the circuit arrangement of the display panel in the first edge area and the display area more uniform, and thus making the display effect of the display panel in this application embodiment more uniform. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a plan view of a display panel according to an embodiment of this application.

[0021] Figure 2 for Figure 1 A partial enlarged view of the display panel in region S1 of this application embodiment.

[0022] Figure 3 This is a schematic diagram of a layer structure of the display panel in the display area according to an embodiment of this application.

[0023] Figure 4 for Figure 1Another enlarged view of the display panel in region S1 of the present application embodiment.

[0024] Figure 5 This is a schematic diagram of a layer structure of a display panel in the first edge region according to an embodiment of this application.

[0025] Figure 6 for Figure 1 A partial enlarged view of the display panel in region S2 of this application embodiment.

[0026] Figure 7 This is a schematic diagram of another layer structure of the display panel in the third edge region according to an embodiment of this application.

[0027] Figure 8 for Figure 1 Another enlarged view of the display panel in region S1 of the present application embodiment.

[0028] Figure 9 This is a schematic diagram of another layer structure of the display panel in the first edge region according to an embodiment of this application.

[0029] Figure 10 for Figure 1 A partial enlarged view of the display panel in region S3 of an embodiment of this application.

[0030] Figure 11 This is a schematic diagram of another layer structure of the display panel in the display area according to an embodiment of this application.

[0031] Figure 12 for Figure 1 Another enlarged view of the display panel in region S1 of the present application embodiment.

[0032] Figure 13 This is a schematic diagram of another layer structure of the display panel in the first edge region according to an embodiment of this application.

[0033] Figure 14 for Figure 1 A partial enlarged view of the display panel in region S3 of an embodiment of this application.

[0034] Figure 15 This is a schematic diagram of another layer structure of the display panel in the display area according to an embodiment of this application.

[0035] Figure 16 for Figure 1 A partial enlarged view of the display panel in region S4 of an embodiment of this application.

[0036] Figure 17 This is a plan view of a display device according to an embodiment of this application.

[0037] Figure label:

[0038] 1. Substrate;

[0039] 2. Display Function Layer; 21. Virtual Unit; 211. Virtual Circuit; 211a. First Inorganic Layer; 211b. First Insulating Layer; 211c. First Metal Layer; 211d. Second Insulating Layer; 212. Virtual Device; 212a. Second Metal Layer; 212b. First Organic Layer; 212c. Third Metal Layer; 22. Array Layer; 221. Driving Circuit; 222. Pixel Circuit; 22a. Thin Film Transistor; 22b. Active Layer; 22c. Gate Insulating Layer; 22d. Gate; 22e. Interlayer Insulating Layer; 23. Light Emitting Device Layer; 231. Light Emitting Device; 231a. Anode; 231b. Light Emitting Material Layer; 231c. Cathode;

[0040] 100. Display device; 200. Display panel;

[0041] DR1, First direction; DR2, Second direction; AA, Display area; NA, Non-display area; B1, First edge area; B2, Second edge area; BD, Binding area; B3, Third edge area. Detailed Implementation

[0042] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description in order to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples thereof.

[0043] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The embodiments will now be described in detail with reference to the accompanying drawings.

[0044] Relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0045] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0046] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0047] It should be understood that in the embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0048] The applicant discovered that display panels (such as organic light-emitting diode display panels) typically include display and non-display areas. The non-display areas contain regions for connecting to other circuit boards, such as bonding areas for flexible circuit boards. Considering that the shape of the flexible circuit board may be asymmetrical, the bonding area may not be located on the display panel's axis of symmetry, resulting in an asymmetrical structure. Due to this asymmetrical structure, the area of ​​the non-display area differs at the corners of the display panel, with a larger area at the corners closer to the bonding area. During the manufacturing process, the unequal areas at the corners of the non-display area cause non-uniformity in the display panel circuitry, including non-uniformity in the light-emitting devices and pixel circuits, thus leading to uneven display quality.

[0049] Based on the above analysis, the applicant proposes a display panel and a display device. The display panel includes a display area, a non-display area, a substrate, and a display functional layer. The display area of ​​the display panel has an axis along a first direction. A first edge area, a second edge area, and a bonding area of ​​the non-display area are located on the same side of the display area along the first direction. The first edge area and the second edge area are located on opposite sides of the display area along a second direction. The first edge area and the second edge area correspond to two corners of the side edge of the display panel where the bonding area is located. At least a portion of the area of ​​the second edge area after symmetry about the axis is located within the first edge area. The first edge area is larger than the second edge area, thus forming an asymmetrical structure for the display panel. The display functional layer located on one side of the substrate includes multiple virtual units. The virtual units are disposed within the first edge area. By disposing of virtual units within the first edge area, the fabrication process of the display functional layer within the first edge area is made similar to the fabrication process within the display area. This results in a more uniform circuit arrangement in the first edge area and the display area, thereby making the display effect of the display panel in the embodiments of this application more uniform.

[0050] Figure 1 This is a plan view of a display panel according to an embodiment of this application. Figure 2 for Figure 1 A partial enlarged view of the display panel in region S1 of this application embodiment. Figure 3 This is a schematic diagram of a layer structure of the display panel in the display area according to an embodiment of this application.

[0051] Please see Figure 3 This application provides a display panel 200, including: a display area AA having an axis along a first direction DR1; a non-display area NA at least partially surrounding the display area AA; the non-display area NA includes a first edge area B1, a second edge area B2, and a bonding area BD, the first edge area B1, the second edge area B2, and the bonding area BD being located on the same side of the display area AA along the first direction DR1, the first edge area B1 and the second edge area B2 being located on opposite sides of the display area AA along the second direction DR2, the first direction DR1 and the second direction DR2 intersecting; at least a portion of the area of ​​the second edge area B2 symmetrical about the axis is located within the first edge area B1; a substrate 1, at least a portion of the substrate 1 being located in the display area AA and at least a portion of the substrate 1 being located in the non-display area NA; a display functional layer 2 disposed on one side of the substrate 1; at least a portion of the display functional layer 2 being located in the display area AA and at least a portion of the display functional layer 2 being located in the non-display area NA; the display functional layer 2 includes a plurality of virtual units 21, at least a portion of the virtual units 21 being disposed in the first edge area B1.

[0052] In this embodiment, the first direction DR1 and the second direction DR2 intersect. When viewed from above, the first direction DR1 corresponds to the vertical direction of the viewing angle, and the second direction DR2 corresponds to the horizontal direction of the viewing angle. The display area AA has an axis along the first direction DR1, and at least a portion of the display area AA is symmetrical about this axis. The non-display area NA can be annular and at least partially surrounds the display area AA. The first edge area B1, the second edge area B2, and the bonding area BD of the non-display area NA are located on the same side of the display area AA along the first direction DR1, and the first edge area B1 and the second edge area B2 are respectively located on both sides of the display area AA along the second direction DR2. Therefore, on one side edge of the display panel 200 where the bonding area BD is provided, the first edge area B1 and the second edge area B2 respectively correspond to the two corners of that side edge of the display panel 200. At least a portion of the area of ​​the second edge region B2 after symmetry about the axis is located within the first edge region B1. That is, the area of ​​the second edge region B2 is smaller than that of the first edge region B1. Therefore, the structure within the first edge region B1 has a greater influence on the display uniformity of the display panel 200 of this embodiment than the structure within the second edge region B2.

[0053] The substrate 1 can be formed from polymeric materials such as glass, polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyaryl compounds (PAR), or glass fiber reinforced plastic (FRP). The substrate 1 can be transparent, translucent, or opaque.

[0054] The display functional layer 2 is disposed on one side of the substrate 1, with at least a portion of the display functional layer 2 located in the display area AA and at least a portion of the display functional layer 2 located in the non-display area NA. The display functional layer 2 is used for displaying light emission and includes an array layer 22 and a light-emitting device layer 23.

[0055] The light-emitting device layer 23 includes multiple light-emitting devices 231, which can be organic light-emitting diodes (OLEDs), miniature light-emitting diodes (Mini-LEDs), or micro-LEDs. For ease of explanation, this embodiment uses an organic light-emitting diode as an example. The light-emitting device 231 includes an anode 231a, a light-emitting material layer 231b, and a cathode 231c. The anode 231a, light-emitting material layer 231b, and cathode 231c are sequentially arranged along the direction away from the substrate 1. The light-emitting material layer 231b can be formed within the pixel definition opening of the pixel definition layer using methods such as inkjet printing, nozzle printing, or vapor deposition. The cathode 231c can be formed on the light-emitting material layer 231b by vapor deposition. For example, the light-emitting device 231 further includes a hole transport layer and an electron transport layer, wherein the hole transport layer is located on the side surface of the anode 231a away from the substrate, the organic light-emitting layer is located on the side surface of the hole transport layer away from the anode 231a, and is used to enhance the ability of the anode 231a to inject holes and transport them to the organic light-emitting layer, and the electron transport layer is located on the side surface of the organic light-emitting layer away from the hole transport layer, and is used to enhance the ability of the cathode 231c to inject electrons and transport them to the organic light-emitting layer.

[0056] The array layer 22 includes a plurality of thin film transistors (TFTs) 22a and a pixel circuit 222 and a driving circuit 221 formed by the TFTs 22a for controlling the light-emitting device 231. For ease of explanation, this embodiment of the application uses a top-gate type TFT 22a as an example. The array layer 22 includes an active layer 22b for forming the TFTs 22a. The active layer 22b includes a source region and a drain region formed by doping with N-type or P-type impurity ions, and a channel region between the source region and the drain region; a gate insulating layer 22c located on the active layer 22b; a gate 22d of the TFT 22a located on the gate insulating layer 22c; an interlayer insulating layer 22e located on the gate 22d; and the source electrode and drain electrode of the TFT 22a located on the interlayer insulating layer 22e. The source electrode and drain electrode are electrically connected (or bonded) to the source region and drain region, respectively, through contact holes.

[0057] It should be noted that the display function layer 2 includes multiple virtual units 21. The virtual unit 21 can be a virtual light-emitting device 231 or a virtual driving circuit 221. The virtual unit 21 is not used for display light emission, but the virtual unit 21 will form a corresponding circuit arrangement. When manufacturing the display panel 200 of this application embodiment, the virtual unit 21 is manufactured together with other structures of the display function layer 2, so that the manufacturing process and structure of the first edge area B1 and the display area AA are closer, thereby making the circuit arrangement of the first edge area B1 of the display panel 200 of this application embodiment closer to the circuit arrangement of the display area AA and other non-display areas NA, thereby improving the display uniformity of the display panel 200 of this application embodiment.

[0058] Further reading Figures 1 to 3 The distance from the end of the binding area BD along the second direction DR2 near the first edge area B1 to the axis is D1, and the distance from the end of the binding area BD along the second direction DR2 near the second edge area B2 to the axis is D2, where D1 > D2.

[0059] The distance D1 from the end of the bonding area BD closest to the first edge area B1 along the second direction DR2 to the axis is greater than the distance D2 from the end of the bonding area BD closest to the second edge area B2 along the second direction DR2 to the axis. In other words, compared to the second edge area B2, the bonding area BD is closer to the first edge area B1, making the area of ​​the first edge area B1 larger than the area of ​​the second edge area B2. Therefore, the structure within the first edge area B1 has a greater influence on the display uniformity of the display panel 200 in this embodiment than the structure within the second edge area B2. It is understood that the shape of the first edge area B1 is similar to that of the second edge area B2, and along the edge direction of the display area AA, the average width of the first edge area B1 is greater than the width of the second edge area B2.

[0060] Figure 4 for Figure 1 Another enlarged view of the display panel in region S1 of the present application embodiment. Figure 5 This is a schematic diagram of a layer structure of a display panel in the first edge region according to an embodiment of this application. Figure 6 for Figure 1 A partial enlarged view of the display panel in region S2 of this application embodiment. Figure 7 This is a schematic diagram of another layer structure of the display panel in the third edge region according to an embodiment of this application.

[0061] Further, please refer to Figures 4 to 7The display function layer 2 includes an array layer 22, which includes multiple driving circuits 221 located in the non-display area NA; the virtual unit 21 includes multiple virtual circuits 211, at least a portion of which is on the same layer as at least a portion of which is insulated from the driving circuits 221.

[0062] In this embodiment, the display functional layer 2 includes an array layer 22. The driving circuit 221 of the array layer 22 is located in the non-display area NA and is used to transmit the driving signal of the display panel 200 of this embodiment. Exemplarily, the driving circuit 221 is located at both edges of the display area AA along the second direction DR2. The virtual unit 21 includes a virtual circuit 211. At least a portion of the virtual circuit 211 is disposed on the same layer as the driving circuit 221. Exemplarily, the structure of the virtual circuit 211 can be the same as at least a portion of the structure of the driving circuit 221, and the virtual circuit 211 and the driving circuit 221 can be fabricated together in the same process steps. It is understood that the virtual circuit 211 and the driving circuit 221 are isolated to reduce the influence of the virtual circuit 211 on the driving signal of the driving circuit 221.

[0063] Further reading Figures 4 to 7 The driving circuit 221 includes a thin-film transistor 22a, and at least a portion of the virtual circuit 211 is disposed on the same layer as the thin-film transistor 22a.

[0064] The driving circuit 221 includes at least one thin-film transistor 22a. When manufacturing the display panel 200 of the present application embodiment, the thin-film transistor 22a and the virtual circuit 211 of the driving circuit 221 can be manufactured together in the same process steps.

[0065] Further reading Figures 4 to 7 The thin-film transistor 22a includes an active layer 22b, a gate insulating layer 22c, a gate 22d, and an interlayer insulating layer 22e stacked sequentially; the virtual circuit 211 includes a first inorganic layer 211a, a first insulating layer 211b, a first metal layer 211c, and a second insulating layer 211d stacked sequentially; the first inorganic layer 211a and the active layer 22b are disposed on the same layer, the first insulating layer 211b is disposed on the same layer as the gate insulating layer 22c, the first metal layer 211c is disposed on the same layer as the gate 22d, and the second insulating layer 211d is disposed on the same layer as the interlayer insulating layer 22e.

[0066] In this embodiment, a top-gate type thin-film transistor 22a is used as an example for description. The array layer 22 includes an active layer 22b for forming the thin-film transistor 22a. The active layer 22b includes a source region and a drain region formed by doping with N-type or P-type impurity ions, and a channel region between the source and drain regions. A gate insulating layer 22c is located on the active layer 22b. A gate 22d of the thin-film transistor 22a is located on the gate insulating layer 22c. An interlayer insulating layer 22e is located on the gate 22d. The source and drain electrodes of the thin-film transistor 22a are located on the interlayer insulating layer 22e. The source and drain electrodes are electrically connected (or bonded) to the source and drain regions respectively through contact holes. When fabricating the thin-film transistor 22a, the first inorganic layer 211a of the virtual circuit 211 can be fabricated together with the active layer 22b of the thin-film transistor 22a, the first insulating layer 211b of the virtual circuit 211 can be fabricated together with the gate insulating layer 22c of the thin-film transistor 22a, the first metal layer 211c of the virtual circuit 211 can be fabricated together with the gate 22d of the thin-film transistor 22a, and the second insulating layer 211d of the virtual circuit 211 can be fabricated together with the interlayer insulating layer 22e of the thin-film transistor 22a. Therefore, the virtual circuit 211 can contain an incomplete thin-film transistor 22a. Considering that both the virtual circuit 211 and the driving circuit 221 are located in the non-display area NA, the virtual circuit 211 containing the incomplete thin-film transistor 22a can reduce the impact on the signal transmission of the driving circuit 221.

[0067] Further reading Figures 4 to 7 The non-display area NA also includes a third edge area B3, which is located on one side of the display area AA along the second direction DR2. At least part of the driving circuit 221 is located in the third edge area B3. The number of driving circuits 221 per unit area in the third edge area B3 is n1, and the number of virtual circuits 211 per unit area in the first edge area B1 is n2, where n1 = n2.

[0068] In this embodiment, the third edge region B3 is located along the second direction DR2 of the display area AA. Therefore, the third edge region B3 and the first edge region B1 are located on the same side of the display area AA.

[0069] Alternatively, the third edge region B3 and the second edge region B2 are located on the same side of the display area AA, and the driving circuit 221 is disposed in the third edge region B3. The number n1 of driving circuits 221 per unit area in the third edge region B3 is equal to the number n2 of virtual circuits 211 per unit area in the first edge region B1, making the circuit layout of the first edge region B1 and the circuit layout of the third edge region B3 of the display panel 200 of this embodiment closer, thereby improving the display uniformity of the display panel 200 of this embodiment.

[0070] Figure 8 for Figure 1 Another enlarged view of the display panel in region S1 of the present application embodiment. Figure 9 This is a schematic diagram of another layer structure of the display panel in the first edge region according to an embodiment of this application. Figure 10 for Figure 1 A partial enlarged view of the display panel in region S3 of an embodiment of this application. Figure 11 This is a schematic diagram of another layer structure of the display panel in the display area according to an embodiment of this application.

[0071] Further, please refer to Figures 8 to 11 The display function layer 2 includes an array layer 22, which includes multiple pixel circuits 222 located in the display area AA; the virtual unit 21 includes multiple virtual circuits 211, at least a portion of which is on the same layer as at least a portion of which is isolated from the pixel circuits 222.

[0072] In this embodiment, the display functional layer 2 includes an array layer 22, and the pixel circuits 222 of the array layer 22 are located in the display area AA, used to transmit pixel signals of the display panel 200 of this embodiment. The virtual unit 21 includes a virtual circuit 211, at least a portion of which is disposed on the same layer as the pixel circuit 222. Exemplarily, the structure of the virtual circuit 211 may be at least partially the same as the structure of the pixel circuit 222, and the virtual circuit 211 and the pixel circuit 222 may be fabricated together in the same process steps. It is understood that the virtual circuit 211 and the pixel circuit 222 are isolated to reduce the influence of the virtual circuit 211 on the pixel signals of the pixel circuit 222.

[0073] Further reading Figures 8 to 11 The pixel circuit 222 includes a thin-film transistor 22a, and at least a portion of the virtual circuit 211 is disposed on the same layer as the thin-film transistor 22a.

[0074] The pixel circuit 222 includes at least one thin-film transistor 22a. When manufacturing the display panel 200 of the present application embodiment, the thin-film transistor 22a and the virtual circuit 211 of the pixel circuit 222 can be manufactured together in the same process steps.

[0075] Further reading Figures 8 to 11The thin-film transistor 22a includes an active layer 22b, a gate insulating layer 22c, a gate 22d, and an interlayer insulating layer 22e stacked sequentially; the virtual circuit 211 includes a first inorganic layer 211a, a first insulating layer 211b, a first metal layer 211c, and a second insulating layer 211d stacked sequentially; the first inorganic layer 211a and the active layer 22b are disposed on the same layer, the first insulating layer 211b is disposed on the same layer as the gate insulating layer 22c, the first metal layer 211c is disposed on the same layer as the gate 22d, and the second insulating layer 211d is disposed on the same layer as the interlayer insulating layer 22e.

[0076] In this embodiment, a top-gate type thin-film transistor 22a is used as an example for description. The array layer 22 includes an active layer 22b for forming the thin-film transistor 22a. The active layer 22b includes a source region and a drain region formed by doping with N-type or P-type impurity ions, and a channel region between the source and drain regions. A gate insulating layer 22c is located on the active layer 22b. A gate 22d of the thin-film transistor 22a is located on the gate insulating layer 22c. An interlayer insulating layer 22e is located on the gate 22d. The source and drain electrodes of the thin-film transistor 22a are located on the interlayer insulating layer 22e. The source and drain electrodes are electrically connected (or bonded) to the source and drain regions respectively through contact holes. When fabricating the thin-film transistor 22a, the first inorganic layer 211a of the virtual circuit 211 can be fabricated together with the active layer 22b of the thin-film transistor 22a, the first insulating layer 211b of the virtual circuit 211 can be fabricated together with the gate insulating layer 22c of the thin-film transistor 22a, the first metal layer 211c of the virtual circuit 211 can be fabricated together with the gate 22d of the thin-film transistor 22a, and the second insulating layer 211d of the virtual circuit 211 can be fabricated together with the interlayer insulating layer 22e of the thin-film transistor 22a. Therefore, the virtual circuit 211 can contain an incomplete thin-film transistor 22a. Considering that the virtual circuit 211 and the pixel circuit 222 are respectively located in the non-display area NA and the display area AA, the virtual circuit 211 containing the incomplete thin-film transistor 22a can reduce the impact on the signal transmission of the pixel circuit 222.

[0077] Further reading Figures 8 to 11 The number of pixel circuits 222 per unit area in the display area AA is n3, and the number of virtual circuits 211 per unit area in the first edge area B1 is n2, where n3 = n2.

[0078] The number n3 of pixel circuits 222 per unit area in the display area AA is equal to the number n2 of virtual circuits 211 per unit area in the first edge area B1, making the circuit layout of the first edge area B1 of the display panel 200 in this embodiment closer to the circuit layout of the display area AA, thereby improving the display uniformity of the display panel 200 in this embodiment.

[0079] Figure 12 for Figure 1 Another enlarged view of the display panel in region S1 of the present application embodiment. Figure 13 This is a schematic diagram of another layer structure of the display panel in the first edge region according to an embodiment of this application. Figure 14 for Figure 1 A partial enlarged view of the display panel in region S3 of an embodiment of this application. Figure 15 This is a schematic diagram of another layer structure of the display panel in the display area according to an embodiment of this application.

[0080] Further, please refer to Figures 12 to 15 The display function layer 2 includes a light-emitting device layer 23, which includes a plurality of light-emitting devices 231, which are located in the display area AA; the virtual unit 21 includes a plurality of virtual devices 212, at least a portion of which is on the same layer as at least a portion of which is insulated from the virtual device 212.

[0081] In this embodiment, the display functional layer 2 includes a light-emitting device layer 23, where the light-emitting devices 231 are located in the display area AA, and are used to realize the display illumination of the display panel 200 of this embodiment. The virtual unit 21 includes a virtual device 212, at least a portion of which is disposed on the same layer as the light-emitting device 231. Exemplarily, the structure of the virtual device 212 may be at least partially the same as the structure of the light-emitting device 231, and the virtual device 212 and the light-emitting device 231 may be fabricated together in the same process steps. It is understood that the virtual device 212 and the light-emitting device 231 are insulated to reduce the influence of pixel signals and / or driving signals of the virtual device 212 and the light-emitting device 231.

[0082] Further reading Figures 12 to 15 The light-emitting device 231 includes an anode 231a, a light-emitting material layer 231b, and a cathode 231c stacked in sequence. The virtual device 212 includes a second metal layer 212a, a first organic layer 212b, and a third metal layer 212c stacked in sequence. The anode 231a and the second metal layer 212a are disposed in the same layer, the light-emitting material layer 231b is disposed in the same layer as the first organic layer 212b, and the cathode 231c is disposed in the same layer as the second metal layer 212a.

[0083] The light-emitting device 231 can be an organic light-emitting diode (OLED), a miniature light-emitting diode (Mini-LED), or a micro-LED. For ease of explanation, this embodiment uses an organic light-emitting diode as an example. The light-emitting device 231 includes an anode 231a, a light-emitting material layer 231b, and a cathode 231c. The anode 231a, the light-emitting material layer 231b, and the cathode 231c are arranged sequentially along the direction away from the substrate 1. When fabricating the light-emitting device 231, the second metal layer 212a of the virtual device 212 can be fabricated together with the anode 231a of the light-emitting device 231, the first organic layer 212b of the virtual device 212 can be fabricated together with the light-emitting material layer 231b of the light-emitting device 231, the first metal layer 211c of the virtual device 212 can be fabricated together with the gate 22d of the light-emitting device 231, and the third metal layer 212c of the virtual device 212 can be fabricated together with the cathode 231c of the light-emitting device 231. Therefore, the virtual device 212 can include the complete light-emitting device 231. Considering that the virtual device 212 and the pixel circuit 222 are respectively located in the non-display area NA and the display area AA, the virtual device 212, which includes the complete light-emitting device 231, can reduce the impact on the signal transmission of the light-emitting device 231.

[0084] Further reading Figures 12 to 15 The number of light-emitting devices 231 per unit area in the display area AA is n4, and the number of virtual devices 212 per unit area in the first edge area B1 is n5, where n4 = n5.

[0085] The number n4 of light-emitting devices 231 per unit area in the display area AA is equal to the number n5 of virtual devices 212 per unit area in the first edge area B1, making the circuit layout of the first edge area B1 of the display panel 200 in this embodiment closer to the circuit layout of the display area AA, thereby improving the display uniformity of the display panel 200 in this embodiment.

[0086] Figure 16 for Figure 1 A partial enlarged view of the display panel in region S4 of an embodiment of this application.

[0087] Further, please refer to Figure 16At least a portion of the virtual units 21 are located in the second edge region B2, which makes the circuit layout of the second edge region B2 of the display panel 200 in this embodiment closer to the circuit layout of the display area AA and other non-display areas NA, thereby improving the display uniformity of the display panel 200 in this embodiment. Given that the structure in the first edge region B1 has a greater impact on the display uniformity of the display panel 200 in this embodiment than the structure in the second edge region B2, virtual units 21 need to be provided in the first edge region B1, while virtual units 21 may or may not be provided in the second edge region B2.

[0088] For ease of understanding, the virtual unit 21 in the subsequent embodiments of this application refers to the virtual unit 21 located in the second edge region B2.

[0089] Optionally, the display function layer 2 includes an array layer 22, which includes a plurality of driving circuits 221 located in the non-display area NA; the virtual unit 21 includes a plurality of virtual circuits 211, at least a portion of which is on the same layer as at least a portion of which is insulated from the driving circuits 221.

[0090] In this embodiment, the display functional layer 2 includes an array layer 22. The driving circuit 221 of the array layer 22 is located in the non-display area NA and is used to transmit the driving signal of the display panel 200 of this embodiment. Exemplarily, the driving circuit 221 is located at both edges of the display area AA along the second direction DR2. The virtual unit 21 includes a virtual circuit 211. At least a portion of the virtual circuit 211 is disposed on the same layer as the driving circuit 221. Exemplarily, the structure of the virtual circuit 211 can be the same as at least a portion of the structure of the driving circuit 221, and the virtual circuit 211 and the driving circuit 221 can be fabricated together in the same process steps. It is understood that the virtual circuit 211 and the driving circuit 221 are isolated to reduce the influence of the virtual circuit 211 on the driving signal of the driving circuit 221.

[0091] Optionally, the display function layer 2 includes an array layer 22, which includes a plurality of pixel circuits 222 located in the display area AA; the virtual unit 21 includes a plurality of virtual circuits 211, at least a portion of which is on the same layer as at least a portion of which is isolated from the pixel circuits 222.

[0092] In this embodiment, the display functional layer 2 includes an array layer 22, and the pixel circuits 222 of the array layer 22 are located in the display area AA, used to transmit pixel signals of the display panel 200 of this embodiment. The virtual unit 21 includes a virtual circuit 211, at least a portion of which is disposed on the same layer as the pixel circuit 222. Exemplarily, the structure of the virtual circuit 211 may be at least partially the same as the structure of the pixel circuit 222, and the virtual circuit 211 and the pixel circuit 222 may be fabricated together in the same process steps. It is understood that the virtual circuit 211 and the pixel circuit 222 are isolated to reduce the influence of the virtual circuit 211 on the pixel signals of the pixel circuit 222.

[0093] Optionally, the display function layer 2 includes a light-emitting device layer 23, which includes a plurality of light-emitting devices 231 located in the display area AA; the virtual unit 21 includes a plurality of virtual devices 212, at least a portion of which is on the same layer as at least a portion of which is insulated from the virtual device 212.

[0094] In this embodiment, the display functional layer 2 includes a light-emitting device layer 23, where the light-emitting devices 231 are located in the display area AA, and are used to realize the display illumination of the display panel 200 of this embodiment. The virtual unit 21 includes a virtual device 212, at least a portion of which is disposed on the same layer as the light-emitting device 231. Exemplarily, the structure of the virtual device 212 may be at least partially the same as the structure of the light-emitting device 231, and the virtual device 212 and the light-emitting device 231 may be fabricated together in the same process steps. It is understood that the virtual device 212 and the light-emitting device 231 are insulated to reduce the influence of pixel signals and / or driving signals of the virtual device 212 and the light-emitting device 231.

[0095] Therefore, in this embodiment of the application, by setting virtual units 21 in the first edge area B1 and the second edge area B2, the circuit arrangement of the display panel 200 in the first edge area B1 and the second edge area B2 is close to the circuit arrangement in the display area AA and other non-display areas NA, thereby making the circuit arrangement of the display panel 200 in the first edge area B1 and the display area AA more uniform, and thus making the display effect of the display panel 200 in this embodiment of the application more uniform.

[0096] Figure 17 This is a plan view of a display device according to an embodiment of this application.

[0097] Please see Figure 17This application also provides a display device 100, including the display panel 200 of the foregoing embodiments of this application. The display device 100 provided in this application can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0098] In summary, this application provides a display panel and a display device. The display panel includes a display area, a non-display area, a substrate, and a display functional layer. The display area of ​​the display panel has an axis along a first direction. The first edge area, the second edge area, and the bonding area of ​​the non-display area are located on the same side of the display area along the first direction. The first edge area and the second edge area are respectively located on opposite sides of the display area along a second direction. The first edge area and the second edge area correspond to the two corners of the side edge of the display panel where the bonding area is located. At least a portion of the area of ​​the second edge area after symmetry about the axis is located within the first edge area. The first edge area is larger than the second edge area, thus forming an asymmetrical structure for the display panel. The display functional layer located on one side of the substrate includes multiple virtual units. The virtual units are disposed within the first edge area. By disposing of virtual units within the first edge area, the fabrication process of the display functional layer within the first edge area is made similar to the fabrication process within the display area. This results in a more uniform circuit arrangement in the first edge area and the display area, thereby making the display effect of the display panel of this application embodiment more uniform.

[0099] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, include: The display area has an axis along a first direction; A non-display area, at least partially surrounding the display area; the non-display area includes a first edge area, a second edge area, and a binding area, wherein the first edge area, the second edge area, and the binding area are located on the same side of the display area along the first direction, and the first edge area and the second edge area are respectively located on opposite sides of the display area along the second direction, wherein the first direction and the second direction intersect; at least a portion of the area of ​​the second edge area symmetrical about the axis is located within the first edge area; A substrate, at least a portion of which is located in the display area and at least a portion of which is located in the non-display area; A display functional layer is disposed on one side of the substrate; at least a portion of the display functional layer is located in the display area, and at least a portion of the display functional layer is located in the non-display area; the display functional layer includes a plurality of virtual units, and at least a portion of the virtual units are disposed in the first edge area.

2. The display panel according to claim 1, characterized in that, The display function layer includes an array layer, which includes multiple driving circuits located in the non-display area; the virtual unit includes multiple virtual circuits, at least a portion of which is on the same layer as at least a portion of the driving circuits and is insulated from them. Preferably, the driving circuit includes a thin-film transistor, and at least a portion of the virtual circuit is disposed on the same layer as the thin-film transistor; Preferably, the thin-film transistor includes an active layer, a gate insulating layer, a gate, and an interlayer insulating layer stacked sequentially; the virtual circuit includes a first inorganic layer, a first insulating layer, a first metal layer, and a second insulating layer stacked sequentially; the first inorganic layer and the active layer are disposed on the same layer, the first insulating layer and the gate insulating layer are disposed on the same layer, the first metal layer and the gate are disposed on the same layer, and the second insulating layer and the interlayer insulating layer are disposed on the same layer.

3. The display panel according to claim 2, characterized in that, The non-display area further includes a third edge area, which is located on one side of the display area along the second direction, and at least a portion of the driving circuits are located in the third edge area; the number of driving circuits per unit area in the third edge area is n1, and the number of virtual circuits per unit area in the first edge area is n2, wherein n1 = n2.

4. The display panel according to claim 1, characterized in that, The display function layer includes an array layer, which includes multiple pixel circuits located in the display area; the virtual unit includes multiple virtual circuits, at least a portion of which is on the same layer as at least a portion of the pixel circuits and is insulated from them. Preferably, the pixel circuit includes a thin-film transistor, and at least a portion of the virtual circuit is disposed on the same layer as the thin-film transistor; Preferably, the thin-film transistor includes an active layer, a gate insulating layer, a gate, and an interlayer insulating layer stacked sequentially; the virtual circuit includes a first inorganic layer, a first insulating layer, a first metal layer, and a second insulating layer stacked sequentially; the first inorganic layer and the active layer are disposed on the same layer, the first insulating layer and the gate insulating layer are disposed on the same layer, the first metal layer and the gate are disposed on the same layer, and the second insulating layer and the interlayer insulating layer are disposed on the same layer.

5. The display panel according to claim 4, characterized in that, The number of pixel circuits per unit area in the display area is n3, and the number of virtual circuits per unit area in the first edge area is n2, where n3 = n2.

6. The display panel according to claim 1, characterized in that, The display function layer includes a light-emitting device layer, which includes a plurality of light-emitting devices located in the display area; The virtual unit includes multiple virtual devices, at least a portion of which are on the same layer as at least a portion of the virtual device and are insulated from each other.

7. The display panel according to claim 6, characterized in that, The number of light-emitting devices per unit area in the display area is n4, and the number of virtual devices per unit area in the first edge area is n5, where n4 = n5.

8. The display panel according to claim 1, characterized in that, The distance from the end of the binding area near the first edge area along the second direction to the axis is D1, and the distance from the end of the binding area near the second edge area along the second direction to the axis is D2, wherein D1 > D2.

9. The display panel according to claim 1, characterized in that, At least a portion of the virtual units are located in the second edge region.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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