Display device

Abstract

A display device according to the present disclosure includes a substrate including a plurality of subpixels, a light emitting device disposed in each subpixel, the light emitting device including a first electrode, a light emitting layer, and a second electrode, a fence disposed along an outer periphery of the subpixel, an end portion of the fence formed in an undercut shape, and a shield electrode on the fence, the shield electrode formed integrally with the first electrode, wherein the first electrode and the shield electrode are electrically disconnected by the undercut shape, and wherein a voltage is applied to the shield electrode.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, to a display device having improved light emission characteristics. Background Technology

[0002] Recently, with the development of multimedia, the importance of display devices has been increasing. In response, flat panel displays, such as liquid crystal displays, plasma displays, and organic light-emitting diode (OLED) displays, are being commercialized. Among these display devices, OLED displays are currently widely used due to their high response speed, high brightness, and wide viewing angle.

[0003] The descriptions provided in the background section should not be construed as prior art simply because they are mentioned in or associated with that section. The background section may include information describing one or more aspects of the subject matter art, and the descriptions in that section do not limit this disclosure. Summary of the Invention

[0004] To manufacture high-resolution display devices, it is typically necessary to minimize or reduce the gaps between subpixels. However, the inventors of this disclosure have realized that, in this case, when the gaps between adjacent subpixels are reduced, lateral leakage currents are more likely to occur between adjacent subpixels. This lateral leakage current can cause unwanted light emission within the pixel, a significant cause of defects in display devices.

[0005] The purpose of this disclosure is to provide a display device capable of preventing or reducing the mixing of light of a specific color output from adjacent pixels.

[0006] To achieve this objective, a display device according to one aspect of the present disclosure includes: a substrate including a plurality of sub-pixels; a light-emitting device disposed in each sub-pixel, the light-emitting device including a first electrode, a light-emitting layer and a second electrode; a fence disposed along the outer periphery of the sub-pixels, the ends of the fence being formed in an undercut shape; and a shielding electrode on the fence, the shielding electrode being integrally formed with the first electrode, wherein the first electrode and the shielding electrode are electrically disconnected by the undercut shape, and wherein a voltage is applied to the shielding electrode.

[0007] The shielding electrode and the second electrode can have the same potential.

[0008] The substrate can be made of at least one of wafers, plastic materials, and glass.

[0009] A thin-film transistor is disposed in each sub-pixel, a passivation layer is disposed above the thin-film transistor, and the thin-film transistor is electrically connected to a first electrode through a first contact hole formed in the passivation layer.

[0010] A reflective layer is disposed above a passivation layer, and a planarization layer is formed on the passivation layer. Shielding electrodes are electrically connected to the reflective layer through a second contact hole formed in the planarization layer and a third contact hole formed in the fence.

[0011] Grooves can be formed in areas corresponding to the undercut shape of the planarization layer.

[0012] External electrical voltage is supplied to the shielding electrodes through a reflective layer, and the electrical voltage can be a low potential voltage.

[0013] According to another aspect of this disclosure, a display device includes: a substrate including a plurality of R (red) sub-pixels, G (green) sub-pixels, and B (blue) sub-pixels; a light-emitting device disposed in each of the R, G, and B sub-pixels, the light-emitting device including a first electrode, a light-emitting layer, and a second electrode; a fence disposed along the outer periphery of the plurality of R, G, and B sub-pixels, the ends of the fence being formed in an undercut shape; and a shielding electrode on the fence, the shielding electrode being integrally formed with the first electrode, wherein the first electrode and the shielding electrode are electrically disconnected by the undercut shape, and wherein a voltage is applied to the shielding electrode.

[0014] Thin-film transistors are disposed in each of a plurality of R, G, and B sub-pixels. A passivation layer is disposed on the thin-film transistor, and a first reflective layer is disposed on the passivation layer in the R sub-pixel. In the G sub-pixel, a first planarization layer is disposed on the passivation layer, a first reflective layer is disposed on the passivation layer, and a second reflective layer is disposed on the first planarization layer. In the B sub-pixel, a second planarization layer is disposed on the first planarization layer, a second reflective layer is disposed on the first planarization layer, and a third reflective layer is disposed on the second planarization layer.

[0015] The first and second reflective layers can be respectively disposed on the passivation layer in the R and G sub-pixels, and the first planarization layer can be disposed on the passivation layer in the R sub-pixels and a portion of the G sub-pixels, with the first reflective layer disposed on the passivation layer. The second planarization layer can be disposed in multiple R, G, and B sub-pixels to cover the first planarization layer and the second reflective layer, and the third reflective layer can be disposed on the second planarization layer in the B sub-pixels.

[0016] The light-emitting devices of the R sub-pixel and G sub-pixel can be placed on the second planarization layer, and the light-emitting device of the B sub-pixel can be placed on the third reflective layer, so that the first electrode of the B sub-pixel is in direct contact with the third reflective layer.

[0017] The shielding electrode of the R sub-pixel can be electrically connected to the first reflective layer through a first contact hole formed in the first planarization layer, the second planarization layer, and the fence to apply voltage to the shielding electrode, and the shielding electrode of the G sub-pixel can be electrically connected to the second reflective layer through a second contact hole formed in the second planarization layer and the fence to apply voltage to the shielding electrode.

[0018] The voltage line is disposed on the first planarization layer in the B sub-pixel, and the shielding electrode of the B sub-pixel can be electrically connected to the voltage line through a third contact hole formed in the second planarization layer and the fence to apply voltage to the shielding electrode.

[0019] The first and second reflective layers can extend to a portion of the B sub-pixel, respectively, so that the shielding electrode of the B sub-pixel can be electrically connected to the first and second reflective layers to apply voltage to the shielding electrode.

[0020] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0021] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to illustrate the principles of the disclosure. In the drawings: Figure 1 This is a schematic block diagram of a display device according to the present disclosure.

[0022] Figure 2 It is a schematic block diagram of subpixels according to this disclosure.

[0023] Figure 3 This is a conceptual circuit diagram illustrating the sub-pixels of an organic light-emitting display device according to the present disclosure.

[0024] Figure 4 This is a cross-sectional view showing the structure of a display device according to a first embodiment of the present disclosure.

[0025] Figure 5 yes Figure 4 An enlarged cross-sectional view of region A.

[0026] Figure 6A This is a schematic view of a display device having a structure in which no shielding electrodes are provided.

[0027] Figure 6B This is a schematic view of a display device according to the present disclosure in which shielding electrodes are provided.

[0028] Figures 7A to 7FThis is a cross-sectional view showing a method for manufacturing a display device according to a first embodiment of the present disclosure.

[0029] Figure 8 This is a cross-sectional view showing the structure of a display device according to a second embodiment of the present disclosure.

[0030] Figure 9 This is a cross-sectional view showing the structure of a display device according to a third embodiment of the present disclosure.

[0031] Figure 10 This is a cross-sectional view showing the structure of a display device according to the fourth embodiment of the present disclosure.

[0032] Figure 11 This is a cross-sectional view showing the structure of a display device according to the fifth embodiment of the present disclosure. Detailed Implementation

[0033] The advantages and features of this disclosure, as well as the methods for implementing them, will become clear from the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art to which it pertains. This disclosure is limited only by the scope of the appended claims.

[0034] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings used to describe embodiments of this disclosure are illustrative, and therefore this disclosure is not limited to what is described. Throughout this disclosure, the same reference numerals denote the same parts. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies will be omitted where it is determined that such descriptions unnecessarily obscure the gist of this disclosure. When terms such as "comprising," "having," or "including" are used in this disclosure, additional parts may be added, unless the term "only" is used herein. When a part is indicated in the singular, the plural form is included unless otherwise stated.

[0035] When analyzing components, the error range is interpreted as included, even if it is not explicitly described.

[0036] When describing positional relationships, for example, when the positional relationship between two parts is described as "on," "above," "below," "beside," etc., if "exactly" or "directly" is not used, one or more other parts may be located between the two parts.

[0037] When describing temporal relationships, such as when the chronological order is described as "after", "following", "next", "before", etc., non-continuous situations may also be included if "immediately" or "directly" is not used.

[0038] Although the terms first, second, etc., are used to describe various components, these components are not substantially limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component described below can essentially be a second component within the technical concept of this disclosure.

[0039] When describing the components of this disclosure, terms such as first, second, A, B, (a), (b) may be used. These terms are used only to distinguish one component from another, and the nature, order, or number of components is not limited by these terms. When describing a component as being “connected” or “linked” to another component, it should be understood that the component may be directly connected or linked to another component; unless otherwise expressly stated, other components may be interposed between components, or components may be indirectly connected or linked via other components.

[0040] Any implementation described as an "example" in this article is not necessarily to be interpreted as preferred or superior to other implementations.

[0041] The term “at least one” should be understood to include any and all combinations of one or more of the associated listed items. For example, “at least one of the first element, the second element, and the third element” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element, the first element, the second element, or the third element.

[0042] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It should also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, the terms “part” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the functions described herein that would be understood by one of ordinary skill in the art.

[0043] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be joined or combined in part or in whole, and may interoperate and be technology-driven in various ways. Embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0044] As used herein, the term "apparatus" can include display apparatuses, such as liquid crystal modules (LCMs) including display panels and driving units for driving the display panels, and organic light-emitting display modules (OLED modules). Furthermore, the term "apparatus" can also include notebook computers, televisions, computer monitors, vehicle electronics including equipment for vehicles or other types of vehicles, and assemblies of electronic equipment or mobile electronic equipment such as smartphones or electronic pads, which are finished products (complete products or final products) including LCMs and OLED modules.

[0045] Therefore, the apparatus in this disclosure may include the display device itself, such as an LCM or OLED module, as well as application products including an LCM or OLED module, or complete sets of equipment as devices for end users.

[0046] The contents of this disclosure will be described in detail below with reference to the accompanying drawings.

[0047] Figure 1 This is a schematic block diagram of a sub-pixel of an organic light-emitting display device according to the present disclosure. Figure 2 This is a schematic block diagram of a sub-pixel of an organic light-emitting display device according to the present disclosure.

[0048] like Figure 1 As shown, the organic light-emitting display device 100 includes an image processing unit 102, a timing control unit 104, a gating drive unit 106, a data drive unit 107, a power supply unit 108, and a display panel 109.

[0049] The image processing unit 102 outputs image data provided from the outside and drive signals for driving various devices. For example, the drive signals from the image processing unit 102 may include data enable signals, vertical synchronization signals, horizontal synchronization signals, and clock signals.

[0050] Image data and drive signals are provided from image processing unit 102 to timing control unit 104. Based on the drive signals from image processing unit 102, timing control unit 104 writes and outputs gating timing control signal GDC for controlling the drive timing of gating drive unit 106 and data timing control signal DDC for controlling the drive timing of data drive unit 107.

[0051] The gating drive unit 106, in response to the gating timing control signal GDC provided from the timing control unit 104, outputs a scan signal to the display panel 109. The gating drive unit 106 outputs the scan signal through multiple gating lines GL1 to GLm. In this case, the gating drive unit 106 may be formed in the form of an integrated circuit (IC), but is not limited thereto.

[0052] The data driving unit 107, in response to the data timing control signal DDC input from the timing control unit 104, outputs a data voltage to the display panel 109. The data driving unit 107 samples and latches the digital data signal DATA provided from the timing control unit 104 to convert it into an analog data voltage based on the gamma voltage. The data driving unit 107 outputs the data voltage through multiple data lines DL1 to DLn. In this case, the data driving unit 107 can be mounted on the upper surface of the display panel 109 in the form of an integrated circuit (IC), but is not limited thereto.

[0053] Power supply unit 108 outputs high-potential voltage VDD and low-potential voltage VSS to supply to display panel 109. High-potential voltage VDD is supplied to display panel 109 via first power line EVDD, and low-potential voltage VSS is supplied to display panel 109 via second power line EVSS. At this time, the voltage from power supply unit 108 is applied to data drive unit 107 or gating drive unit 106 to drive them.

[0054] The display panel 109 displays images based on the data voltage from the data driving unit 108, the scan signal from the gating driving unit 106, and the power from the power supply unit 108.

[0055] The display panel (PAN) includes multiple subpixels (SPs) for displaying images. Subpixels (SPs) may include red, green, and blue subpixels. Additionally, subpixels (SPs) may include white, red, green, and blue subpixels. White, red, green, and blue subpixels may be formed in the same area or in different areas.

[0056] like Figure 2 As shown, a sub-pixel SP can be connected to the gating line GL1, the data line DL1, the first power line EVDD, and the second power line EVSS. The number of transistors and capacitors, as well as the driving method, in the sub-pixel SP are determined based on the pixel circuit configuration.

[0057] Figure 3 This is a circuit diagram showing the sub-pixel SP of the organic light-emitting display device 100 according to the present disclosure.

[0058] like Figure 3 As shown, the organic light-emitting display device 100 according to this disclosure includes a gate line GL, a data line DL, and a power line PL that intersect each other to define a sub-pixel SP. A switching thin-film transistor Ts, a driving thin-film transistor DT, a storage capacitor Cst, and an organic light-emitting device D are disposed in the sub-pixel SP.

[0059] The switching thin-film transistor Ts is connected to the gate line GL and the data line DL, and the driving thin-film transistor Td and the storage capacitor Cst are connected between the switching thin-film transistor Ts and the power line PL. The organic light-emitting device D is connected to the driving thin-film transistor Td.

[0060] In an organic light-emitting display device with this structure, when the switching thin-film transistor Ts is turned on according to the gating signal applied to the gating line GL, the data signal applied to the data line DL is applied to the gate of the driving thin-film transistor Td and one electrode of the storage capacitor Cst through the switching thin-film transistor Ts.

[0061] The driving thin-film transistor Td is turned on according to the data signal applied to the gate. As a result, a current proportional to the data signal is supplied from the power line PL through the driving thin-film transistor Td to the organic light-emitting device D, and then the organic light-emitting device D emits light with a brightness proportional to the current flowing through the driving thin-film transistor Td.

[0062] At this time, the storage capacitor Cst is charged with a voltage proportional to the data signal to keep the voltage of the gate of the driving thin-film transistor Td constant within a frame.

[0063] In this figure, only two thin-film transistors Td and Ts and one capacitor Cst are shown, but this disclosure is not limited thereto. This disclosure may provide three or more thin-film transistors and two or more capacitors.

[0064] Figure 4 This is a cross-sectional view showing the structure of a display device 100 according to a first embodiment of the present disclosure. The display device 100 includes a plurality of R, G, and B sub-pixels, but for ease of description, only one sub-pixel is shown in the figure.

[0065] like Figure 4 As shown, in the organic light-emitting display device 100 according to the first embodiment of the present disclosure, transistor T is disposed on the wafer substrate 140.

[0066] The wafer substrate 140 may be a single-crystal silicon wafer formed by growing single-crystal silicon (Si), but is not limited thereto, and may be a wafer formed from various semiconductor materials.

[0067] The thin-film transistor includes an active region 112 disposed inside a wafer substrate 140, a gate insulating layer 144 covering the active region 112, a gate 114 on the gate insulating layer 144, an interlayer insulating layer 146 covering the gate 114, and a source 115 and a drain 116 on the interlayer insulating layer 146.

[0068] The active region 112 can be formed on the inner side of the wafer substrate 140. The active region 112 of the wafer substrate 140 may include an undoped central channel region 112a, a source region 112b and a drain region 112c doped on both sides of the channel region 112a.

[0069] The gate insulating layer 144 may consist of a single layer or multiple layers made of inorganic materials (such as SiOx or SiNx), but is not limited thereto.

[0070] The gate 114 may be made of metal. For example, the gate 114 may be formed of a single layer or multiple layers, which may be made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu), but is not limited thereto.

[0071] The interlayer insulating layer 146 may be made of organic materials (such as photoacrylic resin), or it may be formed from a single layer or multiple layers of inorganic materials (such as SiOx or SiNx), but is not limited thereto. Furthermore, the interlayer insulating layer 146 may be formed from multiple layers of organic and inorganic materials, but is not limited thereto.

[0072] The source 115 and drain 116 are formed of a single layer or multiple layers, which are made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), but are not limited thereto. The source 115 and drain 116 can be contacted with the source region 112b and drain region 112c of the active region 112, respectively, through contact holes formed in the gate insulating layer 144 and the interlayer insulating layer 146.

[0073] Although not shown in the figure, a buffer layer can be disposed between the wafer substrate 140 and the gate insulating layer 144. The buffer layer 142 enhances the adhesion between the wafer substrate 140 and the layers thereon. Furthermore, the buffer layer 142 can block various types of defects, such as alkaline components flowing out from the substrate 140. Additionally, the buffer layer 142 can delay the diffusion of moisture or oxygen that has penetrated into the substrate 140. The buffer layer 142 can be a single layer made of silicon oxide (SiOx) or silicon nitride (SiNx), or multiple layers thereof. When the buffer layer 142 is composed of multiple layers, SiOx and SiNx can be formed alternately.

[0074] A passivation layer 148 is formed on a wafer substrate 140, and a transistor T is disposed on the wafer substrate 140. The passivation layer 148 may be formed of an organic material such as photoacrylic resin, but is not limited thereto, and may also be formed of multiple layers including inorganic and organic layers.

[0075] A reflective layer 160 is formed on the passivation layer 148. The reflective layer 160 may be made of a metal with good reflectivity (e.g., Ag or Al), but is not limited to this. In this case, the reflective layer 160 is floating, so that no signal is applied to it.

[0076] A planarization layer 150 is disposed on the passivation layer, and a reflective layer 160 is disposed on the passivation layer. The planarization layer 150 may be formed of an organic material (e.g., photopolymer acrylic resin), but is not limited thereto. The planarization layer 150 may include multiple layers, including inorganic and organic layers. Furthermore, the planarization layer 150 may be formed of the same material as the passivation layer 148, but may be formed of a different material.

[0077] The light-emitting device D is disposed in each sub-pixel SP1 and SP2 on the planarization layer 150. The light-emitting device D includes a first electrode 132, a light-emitting layer 134, and a second electrode 136.

[0078] The first electrode 132 is disposed on the planarization layer 150 and is electrically connected to the drain 116 of the thin-film transistor through the first contact hole H1 formed in the planarization layer 150.

[0079] Although the first contact hole H1 penetrates the reflective layer 160 in the figure, this is due to the characteristics of the cross-sectional view. Since the first contact hole H1 is formed in the planarization layer 150 in the area where the reflective layer 160 is not formed, the reflective layer 160 and the first electrode 132 are electrically insulated from each other.

[0080] The first electrode 132 can be made of a translucent conductive material that transmits light. For example, the first electrode 132 can be made of at least one or more alloys such as LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag, or LiF / Ca:Ag. Furthermore, the first electrode 132 can be made of a transparent metal oxide layer such as indium tin oxide (ITO) or indium zinc oxide (IZO). Since the display device 100 according to this disclosure is a top-emitting type, the first electrode 132 can be made of a transparent metal. However, in this disclosure, the luminous efficiency of the light-emitting device D can be improved by providing a reflective layer 160 at the lower part of the light-emitting device D to reflect light emitted from the light-emitting device D upwards.

[0081] Furthermore, the reflective layer 160 improves the light extraction efficiency of the light-emitting device D through a microcavity. The microcavity reflects light multiple times between the two reflective layers to achieve light resonance, thereby improving the light emission efficiency of the light-emitting device D.

[0082] Since the length of the microcavity depends on the wavelength of light, and the length of the microcavity varies depending on the thickness of the planarization layer 150 above the reflective layer 160, the thickness of the planarization layer 150 in this disclosure is different for sub-pixels. For example, since the wavelength of the R sub-pixel is the longest and the wavelength of the B sub-pixel is the shortest, the thickness of the planarization layer 150 for the R sub-pixel is the largest, and the thickness for the B sub-pixel is the smallest.

[0083] Furthermore, for each of the R, G, and B sub-pixels, the flattening layer 150 can be formed by a different number of layers. For example, the flattening layer 150 for the R sub-pixel can include three layers, the flattening layer 150 for the G sub-pixel can include two layers, and the flattening layer 150 for the B sub-pixel can include a single layer.

[0084] Furthermore, the planarization layer 150 can be formed as a single layer. In this case, in the R and G sub-pixels that output light with relatively long wavelengths, the reflective layer 160 can be disposed below the planarization layer 150, and in the B sub-pixel that outputs light with relatively short wavelengths, the reflective layer 160 can be disposed above the planarization layer 150, thereby maximizing or improving the microcavity effect. At this time, the first electrode 132 of the light-emitting device D can be directly disposed on the reflective layer 160 in the B sub-pixel, wherein the reflective layer 160 is disposed on the planarization layer 150.

[0085] A fence F is formed at the boundary between subpixels on the planarization layer 150. The fence F is formed to surround the subpixel to define the subpixel. Specifically, the fence F overlaps with a portion of the edge region of the first electrode 132 to divide each subpixel, such that light of a specific color output from the subpixel does not mix with light of a different color output from adjacent subpixels.

[0086] The fence F can be made of inorganic materials, such as SiOx or SiNx, but is not limited to these.

[0087] A light-emitting layer 134 is disposed in a sub-pixel surrounded by a fence F. The light-emitting layer 134 can be formed in R, G, and B pixels, and includes an R-light-emitting layer for emitting red light, a G-light-emitting layer for emitting green light, and a B-light-emitting layer for emitting blue light. For example, the light-emitting layer 134 can be an organic light-emitting layer, an inorganic light-emitting layer, a nanoscale material layer, a quantum dot layer, a micro-LED light-emitting layer, or a miniature LED light-emitting layer, but is not limited thereto.

[0088] The light-emitting layer 134 may also include an electron injection layer for injecting electrons into the light-emitting layer, a hole injection layer for injecting holes into the light-emitting layer, an electron transport layer for transporting injected electrons to the light-emitting layer, a hole transport layer for transporting injected holes to the light-emitting layer, an electron blocking layer, and a hole blocking layer, but is not limited thereto.

[0089] The second electrode 136 is disposed on the light-emitting layer 134 and can be formed of a single layer or multiple layers of metal or its alloy. Furthermore, the second electrode 136 can be made of a transparent metal oxide material such as ITO or IZO, but is not limited thereto.

[0090] Furthermore, the second electrode 136 can be made of a translucent conductive material that transmits light. For example, the second electrode 136 can be made of at least one or more alloys such as LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag, or LiF / Ca:Ag.

[0091] The light-emitting device D can be formed in a series structure. The series structure may include multiple organic light-emitting layers and a charge-generating layer disposed between the organic light-emitting layers. The charge-generating layer is provided to regulate the charge balance among the multiple organic light-emitting layers, and the charge-generating layer may be formed from multiple layers including a first charge-generating layer and a second charge-generating layer. The charge-generating layer may include an N-type charge-generating layer and a P-type charge-generating layer. In this case, the charge-generating layer may be formed from an organic layer doped with an alkali metal such as Li, Na, K, or Cs, or an alkaline earth metal such as Mg, Sr, Ba, or Ra, but is not limited thereto.

[0092] A shielding electrode 164 is formed on the fence F. The shielding electrode 164 is formed to surround the sub-pixel. The shielding electrode 164 is electrically connected to the reflective layer 160 through a second contact hole H2 formed in the fence F and the planarization layer 150. Although not shown in the figure, the reflective layer 160 can be connected to an external power supply to apply a low potential voltage VSS, thereby providing the low potential voltage VSS to the shielding electrode 164.

[0093] An encapsulation layer 180 is formed on the light-emitting device D to encapsulate the light-emitting device D. When the light-emitting device D is exposed to impurities such as moisture or oxygen, pixel shrinkage may occur, in which the light-emitting area shrinks, or defects such as dark spots appear in the light-emitting area. In addition, moisture or oxygen that permeates the light-emitting device D can oxidize the metal electrodes. The encapsulation layer 180 blocks impurities such as oxygen and moisture from the outside to prevent or reduce defects in the light-emitting device D and various electrodes.

[0094] The encapsulation layer 180 may be formed by a first encapsulation layer 182, a second encapsulation layer 184, and a third encapsulation layer 186, but is not limited thereto. The encapsulation layer 180 may be formed by two, four, or more layers.

[0095] The first encapsulation layer 182 and the third encapsulation layer 186 may be made of inorganic materials, such as SiOx or SiNx, but are not limited thereto. The second encapsulation layer 184 may be made of an organic insulating material such as epoxy resin.

[0096] As described above, in this disclosure, the shielding electrode 164 can be disposed on the fence F, and the shielding electrode 164 can be made of the same material as the first electrode 132 of the light-emitting device D. This will be described in more detail.

[0097] Figure 5 yes Figure 4 An enlarged cross-sectional view of region A. (See image below.) Figure 5 As shown, a reflective layer 160 is formed on a passivation layer 148, and a planarization layer 150 is formed on the reflective layer 160. A fence F is disposed on the planarization layer 150. The fence F is formed in the boundary region of the sub-pixels to define multiple sub-pixels.

[0098] The ends of the fence F can have an undercut shape or a hanging shape. The shielding electrode 164 is formed on the planarization layer 150 of the sub-pixels between the fence F and on the fence F between the sub-pixels.

[0099] As will be described later, the shielding electrode 164 and the first electrode 132 of the light-emitting device D are integrally formed by the same process, but are electrically disconnected from each other by the undercut shape ucut at the end of the fence F.

[0100] Furthermore, the light-emitting layer 134 is disposed on the shielding electrode 164 and the first electrode 132. In this case, the light-emitting layer 134 is formed integrally, but the light-emitting layer 134 on the shielding electrode 164 and the light-emitting layer 134 on the first electrode 132 are disconnected from each other by the undercut shape ucut at the end of the fence F. When the light-emitting layer 134 is disconnected, lateral leakage current does not flow through the light-emitting layer 134 between adjacent sub-pixels. Therefore, the following defects can be prevented or reduced: for example, crosstalk caused by lateral leakage current, line mura and edge mura manifested as abnormal color in lines or local areas, increased power consumption due to unnecessary current consumption, organic material degradation due to continuous leakage current, and image retention defects.

[0101] In this disclosure, a shielding electrode 164 is formed on the fence F for the following reasons: to provide a low potential voltage VSS to the shielding electrode 164 through the reflective layer 160.

[0102] like Figure 6A As shown, in a display device without shielding electrodes, a high potential voltage VDD is applied to the first electrode 132, and a low potential voltage VSS is applied to the second electrode 136. Therefore, an electric field E1 corresponding to the voltage difference VDD-VSS is generated between the first electrode 132 and the second electrode 136.

[0103] The light-emitting layer 134 emits light through an electric field E1, and the light is then output to the outside. When the light-emitting layer 134 in the boundary region of a sub-pixel emits light, light of a specific color from adjacent sub-pixels is mixed and then output to the outside. To prevent or reduce color mixing, a fence F is formed in the boundary region of each sub-pixel. The fence F is disposed between the first electrode 132 and the second electrode 136 to block the formation of the electric field E1 between the first electrode 132 and the second electrode 136, so that the light-emitting layer 134 does not emit light in that region.

[0104] Furthermore, recently, in order to manufacture high-resolution display devices, display devices 100 have been manufactured that minimize or reduce the spacing between sub-pixels. However, in this case, as the distance between adjacent sub-pixels decreases, lateral leakage current flows between adjacent sub-pixels. Since the lateral leakage current mainly flows to adjacent sub-pixels through the light-emitting layer 134, an electric field E2 is generated in the light-emitting layer 134 in the region where the lateral leakage current forms the fence F.

[0105] The intensity of the electric field E2 in the region forming the fence F can be less than the intensity of the electric field E1 in another region (E1>E2). However, since the light-emitting layer 134 emits light even through the small-intensity electric field E2, light is also output to the outside even in the region forming the fence F. As a result, light of different colors from adjacent sub-pixels is mixed, which degrades the image quality.

[0106] like Figure 6B As shown, in the display device 100 according to this disclosure, a shielding electrode 164 is formed on the grid F. A voltage can be applied to the shielding electrode 164 to increase the effect of the shielding electric field. A low potential voltage VSS applied to the second electrode 136 can be provided to the shielding electrode 164. For example, when an anode voltage of approximately 8V is applied to the first electrode 132 and a cathode voltage of approximately 0V is applied to the second electrode 136, no electric field is generated in the light-emitting layer 134 above the grid F (E3=0), and therefore the light-emitting layer in that region does not emit light.

[0107] Lateral leakage current between adjacent sub-pixels can be blocked by the undercut shape ucut of the fence F. However, since the light-emitting layer 134 cannot be completely disconnected by the undercut shape ucut of the fence F, a cathode voltage of approximately 0V is applied to the shielding electrode 164, causing the light-emitting layer 134 above the fence F to not emit light.

[0108] Furthermore, this structure also applies even when the organic light-emitting device D is formed in a series configuration. This series configuration includes multiple light-emitting layers and charge-generating layers located between them. For example, when an anode voltage of approximately 8V is applied to the first electrode 132 and a cathode voltage of 0V is applied to the second electrode 136, a voltage of approximately 4V is generated in the charge-generating layers disposed within the light-emitting layer 134, causing the light-emitting layers above and below the charge-generating layer disposed above the fence F to emit light. However, when a shielding voltage of 0V is applied to the shielding electrode 164, a voltage lower than the threshold voltage for light emission by the light-emitting layer is applied to the charge-generating layer, causing the light-emitting layer in that region to not emit light.

[0109] Therefore, since the light-emitting layer 134 on the shielding electrode 164 does not emit light, the mixing of different colors of light output from adjacent sub-pixels can be prevented or reduced.

[0110] Furthermore, in the display device 100 according to the first embodiment of this disclosure, a thin-film transistor T is formed on a wafer substrate 140 and a light-emitting device D is disposed thereon; however, this disclosure is not limited to this structure. In this disclosure, a rigid and transparent material (e.g., glass) or a flexible transparent material (e.g., plastic) is used as the substrate, and thin-film transistors can be formed by directly forming amorphous semiconductors, crystalline semiconductors, or oxide semiconductors on the substrate.

[0111] Figures 7A to 7F This is a cross-sectional view showing a method for manufacturing a display device 100 according to a first embodiment of the present disclosure.

[0112] First, such as Figure 7A As shown, a wafer substrate 140 is formed by growing monocrystalline silicon (Si) or polycrystalline silicon, and then impurities are doped in some regions within the wafer substrate 140 to form a channel region 112a, a source region 112b, and a drain region 112c. In this case, the source region 112b and the drain region 112c are doped with impurities, while the channel region 112a between the source region 112b and the drain region 112c is not doped with impurities.

[0113] Therefore, as Figure 7B As shown, a single or multiple layers of inorganic materials (such as SiOx or SiNx) are deposited to form a gate insulating layer 144, and then molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof are deposited and etched to form a gate 114. In this case, the gate 114 can be formed as a single layer or multiple layers.

[0114] Subsequently, organic materials such as photoacrylic resin or inorganic materials such as SiOx or SiNx are deposited to form an interlayer insulating layer 146 comprising a single layer or multiple layers.

[0115] Subsequently, the source 115 and drain 116 are formed by depositing and etching metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof on the interlayer insulating layer 146.

[0116] Subsequently, an organic material (e.g., photoacrylic resin) is deposited to form a passivation layer 148, and a reflective layer 160 is formed on the passivation layer 148 by depositing and etching a metal with good reflectivity (e.g., silver (Ag) or aluminum (Al)).

[0117] Subsequently, an organic material such as photopolymer acrylic resin is deposited to form a planarization layer 150 on the passivation layer 148, and a reflective layer 160 is disposed on the passivation layer 148. The planarization layer 150 may be formed of the same material as the passivation layer 148, or it may be formed of a different material.

[0118] Subsequently, an inorganic material such as SiOx or SiNx is deposited on the planarization layer 150 and etched to form a fence F in the boundary region of the sub-pixels on the planarization layer 150. In this case, a portion of the inorganic material is removed to expose the planarization layer 150 to the outside of the region between the fences F, and the fences F are over-etched to form an undercut shape or a cantilever shape.

[0119] In this case, a second contact hole H2 is formed in the passivation layer 148 and the planarization layer 150 above the reflective layer 160. The second contact hole H2 can be formed by etching the passivation layer 148 and the planarization layer 150 separately, or by etching the passivation layer 148 and the planarization layer 150 simultaneously.

[0120] Therefore, as Figure 7D As shown, at least one of the translucent alloys such as LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag, and LiF / Ca:Ag, or at least one of the transparent metal oxides such as ITO and IZO, are deposited on the entire substrate 140 to form a first electrode 132 on a planarization layer 150 in the exposed region between the gates F and a shielding electrode 164 on the gates F.

[0121] At this time, since the end of the fence F is formed in an undercut shape or a hanging shape, the first electrode 132 and the shielding electrode 164 formed in the same deposition process are disconnected from each other in the undercut shape or hanging shape.

[0122] In other words, in the display device 100 according to the present disclosure, metal is simply deposited to form a first electrode 132 and a shielding electrode 164 that are separate from each other, without the need for a separate masking process, thereby eliminating the need for masking processes for forming the first electrode 132 and for forming the shielding electrode 164.

[0123] Then, as Figure 7E As shown, the light-emitting layer 134 is deposited on the entire substrate 140. In this case, due to the undercut shape of the ends of the fence F, the light-emitting layer 134 can also be disconnected between adjacent sub-pixels.

[0124] After that, as Figure 7F As shown, the second electrode 136 is formed by depositing a metal oxide such as ITO or IZO on the light-emitting layer 134. In this case, the undercut shape of the end of the gate F is mitigated by the first electrode 132 and the light-emitting layer 134, so that the second electrode 136 can be integrally formed on the entire substrate 140 without being broken.

[0125] Subsequently, an encapsulation layer 180 comprising a first encapsulation layer 182, a second encapsulation layer 184, and a third encapsulation layer 186 is formed on the light-emitting device D. In this case, the first encapsulation layer 182 and the third encapsulation layer 186 can be formed by depositing inorganic materials, and the second encapsulation layer 184 can be formed by depositing organic materials.

[0126] As described above, in the display device 100 according to the present disclosure, since the first electrode 132 and the shielding electrode 164 of the light-emitting device D are formed by one process, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0127] Figure 8 This is a cross-sectional view showing the structure of a display device 200 according to a second embodiment of the present disclosure. In this case, for ease of description, only the reflective layer 260, the upper grille F, and the light-emitting device D are shown.

[0128] like Figure 8 As shown, the reflective layer 260 is formed on the passivation layer 248, and the planarization layer 250 is formed on the passivation layer 248.

[0129] The fence F is disposed in the region between adjacent sub-pixels on the planarization layer 250. In this case, the fence F is formed by etching an inorganic layer such as SiOx or SiNx, and the ends of the fence F are formed into an undercut shape or a cantilever shape by over-etching.

[0130] Furthermore, a groove C is formed in the planarization layer 250, corresponding to the end of the fence F. The groove C can be formed by etching a portion of the planarization layer 250 corresponding to the end of the fence F after the fence F is formed.

[0131] The fence F is formed around the sub-pixel, such that the planarization layer 250 within the sub-pixel is exposed to the outside through the area between the fences F. A first electrode 232 is formed on the exposed planarization layer 250 of the sub-pixel, and a shielding electrode 264 is formed on the fence F in the area between the sub-pixels.

[0132] The light-emitting layer 234 is formed on the shielding electrode 264, and the first electrode 232 and the second electrode 236 are formed on the light-emitting layer 234, so that the light-emitting device D is disposed in the sub-pixel.

[0133] Contact hole H2 is formed in planarization layer 250 and gate F, and shielding electrode 264 is electrically connected to reflective layer 260 through contact hole H2. In this case, since a low potential voltage VSS applied to second electrode 236 is provided to shielding electrode 264 through reflective layer 260, a voltage of the same potential is applied to shielding electrode 264 and second electrode 236. Therefore, since no electric field is generated between shielding electrode 264 and second electrode 236, light-emitting layer 234 on shielding electrode 264 does not emit light.

[0134] Therefore, even when lateral leakage current is introduced from adjacent sub-pixels, the emitting layer 234 does not emit light at the boundaries of the sub-pixels. This allows for more effective prevention or reduction of color mixing between adjacent sub-pixels.

[0135] The first electrode 232 and the shielding electrode 264 can be formed by depositing a semi-transparent or transparent metal and then etching the deposited metal using a single mask process. The groove C of the planarization layer 150 is aligned with the undercut shape ucut of the fence F, such that when the first electrode 232 and the shielding electrode 264 are formed, they are reliably disconnected at the groove C and the undercut shape ucut. As a result, different voltages (i.e., high-potential voltage and low-potential voltage) can be applied to the first electrode 232 and the shielding electrode 264 respectively to prevent or reduce the emission of the light-emitting layer 234 between sub-pixels.

[0136] Furthermore, since the light-emitting layer 234 is also disconnected at the groove C and the undercut shape ucut, the lateral leakage current will not flow through the light-emitting layer 234 to the adjacent sub-pixel.

[0137] An encapsulation layer 280 is formed on the light-emitting device D to complete the display device 200.

[0138] In the display device 200 of this embodiment, since the light-emitting layer 234 between adjacent sub-pixels is disconnected by the undercut shape ucut of the fence F and the groove C of the planarization layer 250, the flow of lateral leakage current through the light-emitting layer 234 to the adjacent sub-pixels can be minimized or reduced.

[0139] Furthermore, in the display device 200 of this embodiment, since no electric field is generated in the region between sub-pixels, the light-emitting layer does not emit light at the sub-pixel boundaries even when lateral leakage current flows from adjacent sub-pixels. Therefore, color mixing between adjacent sub-pixels can be prevented or reduced more effectively.

[0140] Figure 9 This is a cross-sectional view showing the structure of a display device 300 according to a third embodiment of the present disclosure. In this case, adjacent R, G, and B sub-pixels are shown in the drawing, and specifically, for ease of description, only the reflective layer 360, the fence F, and the light-emitting device D of each sub-pixel are shown.

[0141] like Figure 9 As shown, the display device 300 of this embodiment includes a plurality of R, G and B sub-pixels.

[0142] A first reflective layer 360R is disposed in sub-pixel R on passivation layer 348, and a first planarization layer 350a is formed on passivation layer 348 on which the first reflective layer 360R is disposed. A second reflective layer 360G is disposed in sub-pixel G on first planarization layer 350a, and a voltage line 366 is disposed in sub-pixel B on first planarization layer 350a. In this case, the voltage line 366 can be formed from the same metal using the same process as the second reflective layer 360G, but it can also be formed from a different metal using a different process.

[0143] Furthermore, voltage lines 366 can be formed on the passivation layer 348. In this case, voltage lines 366 can be made of the same metal using the same process as the first reflective layer 360R, but can be formed of different metals using different processes.

[0144] A second planarization layer 350b is formed on a first planarization layer 350a on which a second reflective layer 360G is disposed. A third reflective layer 360B is disposed in sub-pixel B on the second planarization layer 350b.

[0145] The first to third reflective layers 360R, 360G, and 360B can be made of a metal with good reflectivity (such as silver (Ag) or aluminum (Al)). In this case, all the first to third reflective layers 360R, 360G, and 360B can be made of the same material or different materials.

[0146] A fence F is disposed on the second planarization layer 350b in the region between sub-pixels R, G, and B, and extends into a portion of the R, G, and B sub-pixels. In this case, the ends of the fence F are over-etched to form an undercut shape or overhang structure. Since the third reflective layer 360B is disposed in the sub-pixels above the second planarization layer 350b, and the fence F is disposed between the sub-pixels, a portion of the fence F extends in the sub-pixel B onto the third reflective layer 360B, such that the third reflective layer 360B is exposed to the outside through the fence F.

[0147] A first electrode 332 is disposed in sub-pixels R, G, and B between the fences F, and a shielding electrode 364 is disposed on the fences F. In this case, the first electrode 332 is disposed on the second planarization layer 350b exposed between the fences F in the R and G sub-pixels, and the first electrode 332 is disposed on the third reflective layer 360B exposed between the fences F in the B sub-pixel. That is, in the B sub-pixel, the first electrode 332 and the third reflective layer 360B are in direct contact with each other.

[0148] A shielding electrode 364 disposed in sub-pixel R is electrically connected to the first reflective layer 360R through a first contact hole H1 formed in the first planarization layer 350a, the second planarization layer 350b, and the fence F. The shielding electrode 364 and the first electrode 332 are disconnected by the undercut shape of the end of the fence F, and a low potential voltage VSS is applied to the shielding electrode 364 through the first reflective layer 360R, while a high potential voltage is applied to the first electrode 332.

[0149] The shielding electrode 364 disposed in the G sub-pixel is electrically connected to the second reflective layer 360G through the second contact hole H2 formed in the second planarization layer 350b and the fence F, so that the low potential voltage VSS is applied to the shielding electrode 364 through the second reflective layer 360G.

[0150] The shielding electrode 364 disposed in sub-pixel B is electrically connected to the voltage line 366 through a third contact hole H3 formed in the second planarization layer 350b and the gate F, such that a low potential voltage VSS is applied to the shielding electrode 364 through the voltage line 366. When the voltage line 366 is formed on the passivation layer 348, the shielding electrode 364 can be electrically connected to the voltage line 366 through the contact hole formed in the first planarization layer 350a, the second planarization layer 350b and the gate F.

[0151] A low potential voltage VSS is applied to the shielding electrodes 364 of sub-pixels R and G through the first reflective layer 360R and the second reflective layer 360G, respectively. On the other hand, in sub-pixel B, since the third reflective layer 360B is electrically connected to the first electrode 332, a low potential voltage VSS, different from the high potential voltage VDD applied to the first electrode 332, is applied to the shielding electrode 364 through a separate voltage line 366.

[0152] The light-emitting layer 334 is formed on the shielding electrode 364, and the first electrode 332 and the second electrode 336 are formed on the light-emitting layer 334, such that the light-emitting device D is disposed in each of the R, G and B sub-pixels.

[0153] Since the low potential voltage VSS applied to the second electrode 336 is applied to the shielding electrode 364, a voltage of the same potential is applied to both the shielding electrode 364 and the second electrode 336. Therefore, since no electric field is generated between the shielding electrode 364 and the second electrode 336, the light-emitting layer 334 on the shielding electrode 364 does not emit light. Furthermore, since the light-emitting layer 334 is broken at the undercut, lateral leakage current does not flow through the light-emitting layer 334 to adjacent sub-pixels.

[0154] Figure 10 This is a cross-sectional view showing the structure of a display device 400 according to a fourth embodiment of the present disclosure. In this case, adjacent R, G, and B sub-pixels are shown in the drawing, and specifically, for ease of description, only the reflective layer 360, the fence F, and the light-emitting device D of each sub-pixel are shown.

[0155] like Figure 10 As shown, the display device 400 of this embodiment includes a plurality of R, G and B sub-pixels.

[0156] A first reflective layer 460R is disposed in sub-pixel R on passivation layer 448, and a first planarization layer 450a is formed on passivation layer 448 on which the first reflective layer 460R is disposed. A second reflective layer 460G is disposed in sub-pixel G on first planarization layer 450a. In this case, the first reflective layer 460R extends from sub-pixel R to a portion of sub-pixel B, while the second reflective layer 460G extends from sub-pixel G to a portion of sub-pixel B.

[0157] A second planarization layer 450b is formed on a first planarization layer 450a on which a second reflective layer 460G is disposed. A third reflective layer 460B is disposed in sub-pixel B on the second planarization layer 450b.

[0158] The first to third reflective layers 460R, 460G, and 460B can be made of a metal with good reflectivity (e.g., silver (Ag) or aluminum (Al)). In this case, all the first to third reflective layers 460R, 460G, and 460B can be made of the same material or different materials.

[0159] A fence F is disposed on the second planarization layer 450b in the region between sub-pixels R, G, and B, and extends into a portion of the R, G, and B sub-pixels. In this case, the ends of the fence F are over-etched to form an undercut shape or overhang structure. Since the third reflective layer 460B is disposed above the second planarization layer 450b in the sub-pixel, and the fence F is disposed between the sub-pixels, a portion of the fence F extends over the third reflective layer 460B in sub-pixel B, such that the third reflective layer 460B is exposed to the outside through the fence F.

[0160] A first electrode 432 is disposed in sub-pixels R, G, and B between the fences F, and a shielding electrode 464 is disposed on the fences F. In this case, the first electrode 432 is disposed on the second planarization layer 450b exposed between the fences F in the R and G sub-pixels, and the first electrode 432 is disposed on the third reflective layer 460B exposed between the fences F in the B sub-pixel. That is, in the B sub-pixel, the first electrode 432 and the third reflective layer 460B are in direct contact with each other.

[0161] A shielding electrode 464 disposed in sub-pixel R is electrically connected to the first reflective layer 460R through a first contact hole H1 formed in the first planarization layer 450a, the second planarization layer 450b, and the fence F. The shielding electrode 464 and the first electrode 432 are disconnected by the undercut shape of the end of the fence F, and a low potential voltage VSS is applied to the shielding electrode 464 through the first reflective layer 460R, while a high potential voltage is applied to the first electrode 432.

[0162] The shielding electrode 464 disposed in the G sub-pixel is electrically connected to the second reflective layer 460G through the second contact hole H2 formed in the second planarization layer 450b and the fence F, so that the low potential voltage VSS is applied to the shielding electrode 464 through the second reflective layer 460G.

[0163] The shielding electrode 464 adjacent to the R sub-pixel, located on both sides of the B sub-pixel, is electrically connected to the first reflective layer 460R extending to the B sub-pixel via a third contact hole H3 formed in the first planarization layer 450a, the second planarization layer 450b, and the gate F. Therefore, a low-potential voltage VSS is applied to the shielding electrode 464 through the first reflective layer 460R. Similarly, the shielding electrode 464 adjacent to the G sub-pixel, located on both sides of the B sub-pixel, is electrically connected to the second reflective layer 460G extending to the G sub-pixel via a fourth contact hole H4 formed in the second planarization layer 450b and the gate F. Therefore, a low-potential voltage VSS is applied to the shielding electrode 464 through the second reflective layer 460G.

[0164] The display device 400 of this embodiment and Figure 9 The differences between the display devices 300 of the third embodiment shown are as follows. In the display device 300 according to the third embodiment, the voltage line 366 is configured to apply a low-potential voltage VSS to the shielding electrode 364 of the sub-pixel B. On the other hand, in the display device 400 according to this embodiment, the low-potential voltage VSS is applied through the first reflective layer 460R and the second reflective layer 460G extending to the sub-pixel B. Therefore, in the display device 400 according to this embodiment, a voltage line for applying the low-potential voltage VSS is not required.

[0165] A light-emitting layer 434 is formed on a shielding electrode 464 and a first electrode 432, and a second electrode 436 is formed on a light-emitting layer 434, such that a light-emitting device D is disposed on each of the R, G and B sub-pixels.

[0166] In the display device 400 according to this embodiment, since the same low potential voltage VSS is applied to the shielding electrode 464 and the second electrode 436, no electric field is generated between the shielding electrode 464 and the second electrode 436, and as a result, the light-emitting layer 434 above the shielding electrode 464 does not emit light.

[0167] Figure 11 This is a cross-sectional view showing the structure of a display device 500 according to a fifth embodiment of the present disclosure. In this case, adjacent R, G, and B sub-pixels are shown in the drawing, and specifically, for ease of description, only the reflective layer 360, the fence F, and the light-emitting device D of each sub-pixel are shown.

[0168] In the display device 500 of this embodiment, such as Figure 11As shown, a first reflective layer 560R is disposed in the R sub-pixel, a second reflective layer 560G is disposed in the G sub-pixel, and a third reflective layer 560B is disposed in the B sub-pixel. In this case, the first reflective layer 560R is disposed in the R sub-pixel on the passivation layer 548, a first planarization layer 550a and a second planarization layer 550b are formed on the first reflective layer 560R, and the light-emitting device D is disposed on the second planarization layer 550b.

[0169] The second reflective layer 560G is also disposed on the passivation layer 548 in the G sub-pixel, the second planarization layer 550b is formed on the second reflective layer 560G, and the light-emitting device D is disposed on the second planarization layer 550b. That is, the first planarization layer 550a is formed in the R sub-pixel, but not in the G sub-pixel. Therefore, in the R sub-pixel that outputs relatively long wavelength light, the length of the microcavity is determined by the first planarization layer 550a and the second planarization layer 550b, while in the G sub-pixel that outputs relatively short wavelength light, the length of the microcavity is determined only by the second planarization layer 550b.

[0170] The first planarization layer 550a can be formed only in the R sub-pixels, and in some regions of the R and B sub-pixels, but not in the G sub-pixels.

[0171] A third reflective layer 560B is formed on the second planarization layer 550b in the B sub-pixel, and a light-emitting device is disposed on the third reflective layer 560B. A first reflective layer 560R extends from the R sub-pixel to a portion of the B sub-pixel, and a second reflective layer 560G extends from the G sub-pixel to a portion of the B sub-pixel.

[0172] The first to third reflective layers 560R, 560G, and 560B can be made of a metal with good reflectivity (e.g., silver (Ag) or aluminum (Al)). In this case, all the first to third reflective layers 560R, 560G, and 560B can be formed from the same material or different materials.

[0173] The fence F is positioned in the region between the R, G, and B subpixels on the second planarization layer 550b, and extends into a portion of the R, G, and B subpixels. In this case, the ends of the fence F are over-etched to form an undercut shape or a cantilever structure.

[0174] A shielding electrode 564 is disposed on the fence F. The shielding electrode 564 is formed simultaneously with the first electrode 532 of the light-emitting device D, but the shielding electrode 564 and the first electrode 532 are separated by the undercut shape of the fence F.

[0175] A shielding electrode 564 disposed in the R sub-pixel is electrically connected to the first reflective layer 560R through a first contact hole H1 formed in the first planarization layer 550a, the second planarization layer 550b, and the fence F. The shielding electrode 564 and the first electrode 532 are disconnected by an undercut shape at the end of the fence F, and a low potential voltage is applied to the shielding electrode 564 through the first reflective layer 560R, while a high potential voltage is applied to the first electrode 532.

[0176] The shielding electrode 564 disposed in the G sub-pixel is electrically connected to the second reflective layer 560G through the second contact hole H2 formed in the second planarization layer 550b and the fence F, so that the low potential voltage VSS is applied to the shielding electrode 564 through the second reflective layer 560G.

[0177] The shielding electrode 564 adjacent to the R sub-pixel, located on both sides of the B sub-pixel, is electrically connected to the first reflective layer 560R extending to the B sub-pixel via a third contact hole H3 formed in the first planarization layer 550a, the second planarization layer 550b, and the gate F. Therefore, a low-potential voltage VSS is applied to the shielding electrode 564 through the first reflective layer 560R. The shielding electrode 564 adjacent to the G sub-pixel, located on both sides of the B sub-pixel, is electrically connected to the second reflective layer 560G extending to the G sub-pixel via a fourth contact hole H4 formed in the second planarization layer 550b and the gate F. Therefore, a low-potential voltage VSS is applied to the shielding electrode 564 through the second reflective layer 560G.

[0178] A light-emitting layer 534 is formed on a shielding electrode 564 and a first electrode 532, and a second electrode 536 is formed on a light-emitting layer 534, such that a light-emitting device D is disposed on each of the R, G and B sub-pixels.

[0179] The above description and accompanying drawings are merely illustrative of the technical concept of this disclosure, and those skilled in the art to which this disclosure pertains can combine and configure them without departing from the basic characteristics of this disclosure. Various modifications or variations, such as separation, substitution, and alteration, are possible. Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical concept of this disclosure, but are for illustrative purposes, and the scope of the technical concept of this disclosure is not limited by these embodiments.

[0180] Cross-references to related applications

[0181] This application claims priority to Korean Patent Application No. 10-2025-0055984, filed in Korea on April 29, 2025, the entire contents of which are expressly incorporated herein by reference.

Claims

1. A display device, the display device comprising: A substrate, the substrate comprising a plurality of sub-pixels; A light-emitting device, wherein the light-emitting device is disposed in each of the plurality of sub-pixels, the light-emitting device comprising a first electrode, a light-emitting layer and a second electrode; A fence is provided along the outer periphery of each sub-pixel, and the ends of the fence are formed in an undercut shape; as well as A shielding electrode is provided on the fence and is integrally formed with the first electrode. Wherein, the first electrode and the shielding electrode are electrically disconnected through the undercut shape, and Voltage is applied to the shielding electrode.

2. The display device according to claim 1, wherein, The shielding electrode and the second electrode have the same potential.

3. The display device according to claim 1, wherein, The substrate is made of at least one of a wafer, a plastic material, and a glass, or a combination thereof.

4. The display device according to claim 1, further comprising: A thin-film transistor, wherein the thin-film transistor is disposed in each of the plurality of sub-pixels; as well as A passivation layer is provided above the thin-film transistor. The thin-film transistor is electrically connected to the first electrode through a first contact hole formed in the passivation layer.

5. The display device according to claim 4, further comprising: A reflective layer is provided on the passivation layer. as well as A planarization layer is formed to cover the reflective layer, and the light-emitting device is disposed on the planarization layer. The shielding electrode is electrically connected to the reflective layer through a second contact hole formed in the planarization layer and a third contact hole formed in the fence.

6. The display device according to claim 5, wherein, A groove is formed in the region corresponding to the undercut shape of the planarization layer.

7. The display device according to claim 5, wherein, The reflective layer supplies power voltage to the shielding electrode.

8. The display device according to claim 7, wherein, The power supply voltage is a low potential voltage.

9. A display device, the display device comprising: A substrate, the substrate comprising a plurality of sub-pixels, the plurality of sub-pixels including red sub-pixels, green sub-pixels, and blue sub-pixels; A light-emitting device, wherein the light-emitting device is disposed in each of the plurality of sub-pixels, the light-emitting device comprising a first electrode, a light-emitting layer and a second electrode; A fence, wherein the fence is disposed along the outer periphery of the plurality of sub-pixels, and the ends of the fence are formed in an undercut shape; as well as A shielding electrode is provided on the fence and is integrally formed with the first electrode. Wherein, the first electrode and the shielding electrode are electrically disconnected through the undercut shape, and Voltage is applied to the shielding electrode.

10. The display device according to claim 9, further comprising: A thin-film transistor, wherein the thin-film transistor is disposed in each of the plurality of sub-pixels; A passivation layer is provided above the thin-film transistor. A first reflective layer is located on the passivation layer in the red sub-pixel; A first planarization layer is disposed on the passivation layer, and a first reflective layer is disposed on the passivation layer; A second reflective layer is located on the first planarization layer in the green sub-pixel; A second planarization layer is disposed on the first planarization layer, and a second reflective layer is disposed on the first planarization layer; as well as A third reflective layer is located on the second planarization layer in the blue sub-pixel.

11. The display device according to claim 9, further comprising: A thin-film transistor, wherein the thin-film transistor is disposed in each of the plurality of sub-pixels; A passivation layer is provided above the thin-film transistor. A first reflective layer is located on the passivation layer in the red sub-pixel; A second reflective layer is located on the passivation layer in the green sub-pixel; A first planarization layer is disposed on the passivation layer in the red sub-pixel and a portion of the green sub-pixel, and a first reflection layer is disposed on the passivation layer; A second planarization layer is disposed within the plurality of sub-pixels to cover the first planarization layer and the second reflection layer, and A third reflective layer is located on the second planarization layer in the blue sub-pixel.

12. The display device according to claim 10, wherein, The light-emitting devices of the red sub-pixel and the green sub-pixel are disposed on the second planarization layer, and The light-emitting device of the blue sub-pixel is disposed on the third reflective layer, such that the first electrode of the blue sub-pixel is in direct contact with the third reflective layer.

13. The display device according to claim 12, wherein, The shielding electrode of the red sub-pixel is electrically connected to the first reflective layer through a first contact hole formed in the first planarization layer, the second planarization layer, and the fence, so as to apply voltage to the shielding electrode. The shielding electrode of the green sub-pixel is electrically connected to the second reflective layer through a second contact hole formed in the second planarization layer and the fence to apply a voltage to the shielding electrode.

14. The display device according to claim 13, further comprising voltage lines disposed on the first planarization layer in the blue sub-pixel. in, The shielding electrode of the blue sub-pixel is electrically connected to the voltage line through a third contact hole formed in the second planarization layer and the fence to apply the voltage to the shielding electrode.

15. The display device according to claim 13, wherein, The first reflective layer and the second reflective layer extend to a portion of the blue sub-pixel, such that the shielding electrode of the blue sub-pixel is electrically connected to the first reflective layer and the second reflective layer to apply the voltage to the shielding electrode.

16. The display device according to claim 9, wherein, The voltage applied to the shielding electrode has the same potential as the voltage applied to the second electrode.

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