Display device, method of manufacturing the same, and electronic device including the same

Abstract

The present disclosure relates to a display device, a method of manufacturing a display device, and an electronic device including the display device. The display device includes an active layer including a source region, a drain region, and a channel region on a base layer, a cover layer over the active layer, and a gate layer over the channel region, wherein the drain region includes a first region overlapping the cover layer in a plan view and a second region not overlapping the cover layer, and wherein the first region has a lower dopant concentration than the second region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefits, and all benefits derived therefrom, to Korean Patent Application No. 10-2025-0055539, filed on April 28, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a display device, a method of manufacturing a display device, and an electronic device including a display device. Background Technology

[0004] Recently, due to increased interest in information display, research and development of display devices has been ongoing.

[0005] Display devices include circuit elements such as transistors. If leakage current is generated in these circuit elements, the display quality of the display device may be negatively affected.

[0006] For example, when leakage current occurs in some transistors, signal interference (e.g., crosstalk) between circuit elements may increase, having an unintended effect on the image displayed on the display device. For example, a grayscale or degraded image may be displayed, which may reduce display reliability. Summary of the Invention

[0007] This disclosure provides a display device, a method for manufacturing a display device, and an electronic device including the display device, wherein the possibility of leakage current can be reduced, and the risk of display quality being impaired due to leakage current can be reduced.

[0008] This disclosure provides a display device capable of improving display quality, a method for manufacturing a display device, and an electronic device including a display device.

[0009] According to one or more embodiments of the present disclosure, a display device may include: an active layer on a base layer, the active layer including a source region, a drain region and a channel region; a capping layer above the active layer; and a gate layer above the channel region, wherein the drain region includes a first region overlapping the capping layer in a plan view and a second region not overlapping the capping layer, and wherein the first region has a lower dopant concentration than the second region.

[0010] The capping layer may include a material permeable to dopants doped into the drain region.

[0011] The capping layer may include amorphous silicon material.

[0012] The overburden layer can be formed across the first region and the channel region in the plan view.

[0013] The overlay layer can overlap with the entire first region in the plan view.

[0014] The overlay can be in a floating state.

[0015] The covering layer can have an isolated shape.

[0016] The overlay can have a polygonal shape or a curved shape.

[0017] The capping layer may further include: a first gate insulating layer on the active layer; and a second gate insulating layer on the capping layer and the first gate insulating layer, wherein the capping layer may have a thickness smaller than that of the first gate insulating layer and the second gate insulating layer, and may have a thickness of 10 Å to 1000 Å.

[0018] The second region can be formed on one side of the first region, and the channel region can be formed on the other side of the first region.

[0019] The capping layer can be non-overlapping with the source region in a planar diagram.

[0020] The capping layer can be set across the drain region, channel region and source region in the plan view, and the source region can include a third region that overlaps with the capping layer and a fourth region that does not overlap with the capping layer in the plan view.

[0021] The overlay may include a first overlay that overlaps with the first region in the plan view and a second overlay that overlaps with the source region.

[0022] The source region may include a third region that overlaps with the second capping layer and a fourth region that does not overlap with the second capping layer in the planar diagram, and the third region may have a lower dopant concentration than the fourth region.

[0023] According to one or more embodiments of the present disclosure, a method of manufacturing a display device may include: patterning a base active layer on a base layer; patterning a capping layer over the base active layer; patterning a gate layer over the base active layer and the capping layer; and obtaining an active layer by forming a source region, a drain region and a channel region on the base active layer, wherein the capping layer comprises an amorphous silicon material.

[0024] Obtaining an active layer may include performing a doping process on a base active layer, and performing the doping process may include forming a first region in a drain region that overlaps with the capping layer.

[0025] A patterned overlay may be formed at a location beneath a first region.

[0026] Patterned overlays can include regional patterned overlays formed beneath source, channel, and drain regions in a planar diagram.

[0027] The patterned overlay may include a first overlay patterned in a planar diagram that overlaps with the drain region and a second overlay patterned with the source region.

[0028] According to one or more embodiments of the present disclosure, the electronic device may include: a processor; a display module electrically connected to the processor, the display module including the above-described display device; and a power module that provides power to the display module. Attached Figure Description

[0029] The above and other features of the present invention will become more apparent from the description of embodiments of the invention in more detail with reference to the accompanying drawings, in which: Figure 1 This is a schematic plan view illustrating a display device according to one or more embodiments; Figure 2 and Figure 3 This is a schematic cross-sectional view showing a display device according to one or more embodiments; Figure 4 This is a schematic circuit diagram illustrating a pixel circuit according to one or more embodiments; Figures 5 to 10 This is a schematic diagram illustrating a pixel circuit layer including pixel circuits according to one or more embodiments; Figures 11 to 15 This is a schematic cross-sectional view illustrating the process steps of a method for manufacturing a display device according to one or more embodiments; Figure 16 It is a schematic block diagram of an electronic device according to one or more embodiments; and Figure 17 Schematic diagrams illustrating various embodiments of the electronic device are shown. Detailed Implementation

[0030] Because this disclosure allows for various modifications and multiple implementations, specific implementations will be shown in the accompanying drawings and described in detail in the written description. However, this is not necessarily intended to limit this disclosure to the practice of a particular mode, and it should be understood that all modifications, equivalents, and alternatives that do not depart from the spirit and technical scope of this disclosure are included herein.

[0031] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element discussed below may be referred to as a second element without departing from the scope of the invention. Similarly, a second element may also be referred to as a first element. In this disclosure, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise.

[0032] It will also be understood that, when used in this disclosure, the terms "comprise," "include," "have," etc., specify the presence of the stated features, integers, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. Furthermore, when a first portion, such as a layer, film, region, or plate, is disposed "on" a second portion, the first portion may not only be "directly" on the second portion, but a third portion may also be located between the first and second portions. Furthermore, when stated as a first portion, such as a layer, film, region, or plate, formed on a second portion, the surface of the second portion on which the first portion is formed is not necessarily limited to the upper surface of the second portion, but may include other surfaces of the second portion, such as side or lower surfaces. Conversely, when a first portion, such as a layer, film, region, or plate, is "below" a second portion, the first portion may not only be "directly" below the second portion, but a third portion may also be located between the first and second portions.

[0033] As used in this article, the phrase "at least one" preceding an element in a column modifies the entire column of elements, but does not modify any individual elements within the column. For example, the phrase "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0034] This disclosure relates to a display device, a method of manufacturing a display device, and an electronic device including a display device. Hereinafter, the display device, the method of manufacturing a display device, and the electronic device including a display device will be described with reference to the accompanying drawings.

[0035] Figure 1 This is a schematic plan view illustrating a display device according to one or more embodiments.

[0036] refer to Figure 1 The display device DD may include a base layer BSL and a plurality of pixels PXL disposed on the base layer BSL. The display device DD may also include driver circuitry (e.g., scan driver and data driver), wiring, and pads for driving the pixels PXL.

[0037] The display device DD (or base layer BSL) may include a display area DSA and a non-display area NDA. The non-display area NDA may refer to the area outside the display area DSA. The non-display area NDA may surround at least a portion of the display area DSA. For example, the non-display area NDA may surround the entire display area DSA in a plan view.

[0038] The base layer (BSL) can form the base surface of the display device (DD). According to one or more embodiments, the base layer (BSL) can be a lower substrate for housing the layers forming the display device (DD). The base layer (BSL) can be a rigid or flexible substrate or film. For example, the base layer (BSL) can include at least one of a glass material, a silicon-based material, and polyimide. However, this disclosure is not limited thereto.

[0039] The term "plane" as used herein may be defined relative to a plane on which a base layer BSL is disposed, extending in a first direction DR1 and a second direction DR2, each being horizontal. According to one or more embodiments, a third direction DR3, which is vertical, may be the thickness direction of the base layer BSL, and the third direction DR3 may be the emission direction of the display device DD.

[0040] The display area DSA can refer to the area where pixels PXL are located. The non-display area NDA can refer to the area where pixels PXL are not located. The non-display area NDA may include driver circuitry, wiring, and pads connected to the pixels PXL of the display area DSA.

[0041] In the embodiments described herein, pixel PXL (or sub-pixel SPX) can be based on stripes or pentiles. ® The array structure is configured, but this disclosure is not limited thereto. Various other implementation methods can be applied in this disclosure.

[0042] According to one or more embodiments, a pixel PXL (or sub-pixel SPX) may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be a sub-pixel SPX. The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may form a pixel unit capable of emitting light of various colors.

[0043] Each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can emit light of a single color.

[0044] For example, the first sub-pixel SPX1 could be a red pixel emitting red (i.e., the first color) light, the second sub-pixel SPX2 could be a green pixel emitting green (i.e., the second color) light, and the third sub-pixel SPX3 could be a blue pixel emitting blue (i.e., the third color) light. The red pixel can emit light in the wavelength band from 600nm to 750nm. The green pixel can emit light in the wavelength band from 480nm to 560nm. The blue pixel can emit light in the wavelength band from 370nm to 460nm.

[0045] Figure 2 and Figure 3 This is a schematic cross-sectional view showing a display device according to one or more embodiments. Figure 3 A portion of the display device DD in the display area DSA is shown. Figure 4 This is a schematic circuit diagram illustrating a pixel circuit according to one or more embodiments.

[0046] refer to Figures 2 to 4 The display device DD may include a pixel circuit layer (PCL) and a light-emitting element layer (LEL). The display device DD may also include an upper UL layer.

[0047] The pixel circuit layer (PCL) may include the base layer (BSL). The PCL may include pixel circuits (PXC). The PCL may be a backplane layer. The pixel circuits (PXC) may be formed on the base layer (BSL) and may drive light-emitting elements (LDs).

[0048] The pixel circuit (PXC) may include circuit elements. These circuit elements may include driving transistors and switching transistors, and may include additional transistors and capacitors.

[0049] The light-emitting element layer (LEL) can be disposed on the pixel circuit layer (PCL). The LEL can include multiple light-emitting elements (LDs). The LEL can also include a pixel definition layer (PDL) and a packaging layer (TFE).

[0050] The light-emitting element (LD) can be electrically connected to the pixel circuit (PXC). According to one or more embodiments, the LD may include an organic light-emitting diode (OLED) comprising organic materials. Optionally or additionally, according to one or more embodiments, the LD may include an inorganic light-emitting diode comprising inorganic materials. However, this disclosure is not limited to the specific examples.

[0051] A light-emitting element (LD) may include an anode AE, an emitting structure EL, and a cathode CE. According to one or more embodiments, the emitting structure EL may be disposed in a region defined by a pixel-defining layer PDL. For example, in a plan view, the emitting structure EL may be surrounded by the pixel-defining layer PDL. The pixel-defining layer PDL may be adjacent to the periphery of the emitting structure EL. One surface of the emitting structure EL may be electrically connected to the anode AE, and another surface of the emitting structure EL may be electrically connected to the cathode CE. The anode AE ​​and the cathode CE may each comprise one or more conductive materials.

[0052] An emission structure EL may include multiple layers. For example, an emission structure EL may include multiple emission structures, including a hole transport layer, a light-emitting layer (or light-generating layer), and an electron transport layer. Each of the layers forming the emission structure EL may include an organic material. According to one or more embodiments, each layer may also include an inorganic layer containing a metal compound or such as quantum dots.

[0053] A pixel defining layer (PDL) may be disposed on a pixel circuit layer (PCL) to define the location where an emission structure (EL) is disposed. The pixel defining layer (PDL) may comprise organic or inorganic materials. For example, the pixel defining layer (PDL) may comprise multiple layers, each comprising an inorganic material. However, this disclosure is not limited thereto.

[0054] The encapsulation layer TFE can be disposed on the light-emitting element LD (e.g., cathode CE). The encapsulation layer TFE can compensate for the step difference generated by the light-emitting element LD and the pixel defining layer PDL. The encapsulation layer TFE may include multiple insulating layers on the light-emitting element LD. For example, the insulating layers may cover the light-emitting element LD. According to one or more embodiments, the encapsulation layer TFE may include inorganic and organic layers. For example, the encapsulation layer TFE may have a structure comprising a first inorganic layer, an organic layer, and a second inorganic layer disposed sequentially. However, this disclosure is not limited thereto. According to one or more embodiments, the encapsulation layer TFE may be a thin-film encapsulation layer.

[0055] The upper UL layer can be disposed on the light-emitting element layer LEL. The upper UL layer can include various layers that transmit light, such as a cover window. According to one or more embodiments, the upper UL layer can include a color filter, a lens array layer, a polarizing layer, etc. However, this disclosure is not limited to the specific examples.

[0056] According to one or more embodiments, a sub-pixel SPX may include a pixel circuit PXC and a light-emitting element LD.

[0057] The light-emitting element (LD) can be electrically connected between a first power supply voltage node VDDN and a second power supply voltage node VSSN. The first power supply voltage node VDDN can be electrically connected to a first power line and receive a first power supply voltage, and the second power supply voltage node VSSN can be electrically connected to a second power line and receive a second power supply voltage. The first power supply voltage can have a higher voltage level than the second power supply voltage.

[0058] The anode AE ​​of the light-emitting element LD can be electrically connected to the first power supply voltage node VDDN via the pixel circuit PXC. For example, the anode AE ​​can be electrically connected to the first power supply voltage node VDDN via one or more transistors included in the pixel circuit PXC. The cathode CE of the light-emitting element LD can be electrically connected to the second power supply voltage node VSSN. The light-emitting element LD emits light in response to the current flowing from the anode AE ​​to the cathode CE.

[0059] The pixel circuit PXC can be electrically connected to the gate line GL and the data line DL. The pixel circuit PXC can control the light-emitting element LD in response to the gate signal received via the gate line GL, and can cause the light-emitting element LD to emit light in response to the data signal received via the data line DL.

[0060] In implementations, the transistors of the pixel circuit PXC may include field-effect transistors (FETs). The transistors of the pixel circuit PXC may include metal-oxide-semiconductor field-effect transistors (MOSFETs). The transistors of the pixel circuit PXC may include P-type transistors and / or N-type transistors. For ease of explanation, this implementation will be described based on the assumption that some of the transistors in the pixel circuit PXC are P-type transistors.

[0061] refer to Figures 5 to 10 This section will describe the pixel circuit (PXC) and surrounding structure according to one or more embodiments. For ease of explanation, details that may be redundant with the above will be described briefly or not repeated.

[0062] Figures 5 to 10 This is a schematic diagram illustrating a pixel circuit layer including pixel circuitry according to one or more embodiments. For ease of explanation, Figures 5 to 10 The pixel circuit layer (PCL) of the display device DD is shown only schematically. Figures 5 to 10 The active layer ACT and surrounding structures shown can form at least some of the transistors in a pixel circuit PXC.

[0063] Figure 5 This is a schematic plan view showing a pixel circuit layer according to one or more embodiments. Figure 6 It is along Figure 5 A schematic cross-sectional view taken by line A-A'. Figure 7 This is a schematic plan view illustrating a pixel circuit layer according to one or more other embodiments. Figure 8 It is along Figure 7 A schematic cross-sectional view taken by line B-B'. Figure 9 This is a schematic plan view illustrating a pixel circuit layer according to one or more other embodiments. Figure 10 It is along Figure 9 A schematic cross-sectional view taken by line C-C'.

[0064] First, refer to Figure 5 and Figure 6 The present invention will describe a pixel circuit layer PCL including pixel circuits PXC according to one or more embodiments.

[0065] According to one or more embodiments, the pixel circuit layer PCL may include an active layer ACT, a first gate insulating layer GI1, a capping layer CV, a second gate insulating layer GI2, a gate layer GAT, an interlayer insulating layer IL, a first contact portion CNT1, a second contact portion CNT2, a drain electrode DE, and a source electrode SE.

[0066] The active layer ACT can be disposed on the base layer BSL. According to one or more embodiments, a buffer layer comprising one or more inorganic materials can also be inserted between the base layer BSL and the active layer ACT.

[0067] The active layer ACT can include amorphous silicon semiconductor, monocrystalline silicon, polycrystalline silicon, or oxide semiconductor.

[0068] The active layer ACT can form at least a portion of the circuit elements of the pixel circuit PXC. For example, the active layer ACT can form at least one of the driving transistor, switching transistor, and other transistors of the pixel circuit PXC.

[0069] The active layer ACT can include the source region SA, the channel region CHA, and the drain region DA.

[0070] The source region SA and drain region DA can be doped with dopants. For example, when the transistor formed by the active layer ACT is a p-type metal-oxide-semiconductor (PMOS), the source region SA and drain region DA can be doped with p-type dopants.

[0071] The channel region CHA can be formed between the source region SA and the drain region DA, and can be a region that is essentially undoped.

[0072] According to one or more embodiments, the drain region DA may include a low-concentration drain region LDA.

[0073] The low-concentration drain region (LDA) can overlap with the capping layer (CV) either in a planar view or on a third-direction DR3. During the manufacturing process of the display device (DD), the low-concentration drain region (LDA) can be formed based on the capping layer CV. In this document, overlap between structural elements in a planar view can refer to overlap on a third-direction DR3, and therefore, overlap in a planar view and overlap on a third-direction DR3 are used interchangeably.

[0074] The low-concentration drain region LDA can be adjacent to the channel region CHA along a planar direction (e.g., a horizontal direction), wherein the base layer BSL is disposed in this planar direction. For example, the low-concentration drain region LDA can be directly adjacent to the channel region CHA. In the first direction DR1, different portions of the drain region DA, excluding the low-concentration drain region LDA, can be formed on one side of the low-concentration drain region LDA, and the channel region CHA can be formed on the other side of the low-concentration drain region LDA.

[0075] The concentration of dopant in the low-concentration drain region LDA can be less than the concentration of dopant in the drain region DA outside the low-concentration drain region LDA, and if the channel region CHA is doped with dopant, it is greater than the concentration of dopant in the channel region CHA.

[0076] Low-concentration drain region (LDA) can mitigate the relatively abrupt change in doping concentration between the drain region (DA) and the channel region (CHA). Therefore, low-concentration LDA can prevent electric field concentration between the drain region (DA) and the channel region (CHA), and can reduce the risk of leakage current in the active layer (ACT).

[0077] Low-concentration drain region (LDA) can reduce gate-induced drain leakage (GIDL) current that may be caused by the high electric field between the gate layer (GAT) and the drain region (DA).

[0078] According to one or more embodiments, two or more insulating layers may be interposed between the active layer ACT and the gate layer GAT. For example, at least one gate insulating layer may be provided, and the capping layer CV may be within at least one gate insulating layer.

[0079] A first gate insulating layer GI1 may be disposed on the base layer BSL and the active layer ACT. The first gate insulating layer GI1 may be disposed on the active layer ACT. The first gate insulating layer GI1 may comprise various inorganic materials. According to one or more embodiments, the first gate insulating layer GI1 may be formed as a single layer or multiple layers.

[0080] A second gate insulating layer GI2 may be disposed on the capping layer CV and the first gate insulating layer GI1. For example, the second gate insulating layer GI2 may be formed on the capping layer CV. The second gate insulating layer GI2 may comprise various inorganic materials. According to one or more embodiments, the second gate insulating layer GI2 may be formed as a single layer or multiple layers.

[0081] The capping layer CV can be disposed on top of the first gate insulating layer GI1.

[0082] The capping layer CV can overlap with the drain region DA in a planar plot. The capping layer CV can overlap with the low-concentration drain region LDA in a planar plot. The capping layer CV may not overlap with a portion of the drain region DA in a planar plot. The capping layer CV may completely overlap with the low-concentration drain region LDA in a planar plot.

[0083] The capping layer CV can be formed across the low-concentration drain region (LDA) and the channel region (CHA) in a planar view. At least a portion of the capping layer CV can overlap with the gate layer (GAT) in a planar view. The capping layer CV can overlap with at least a portion of the channel region (CHA) in a planar view.

[0084] According to one or more implementations, the capping layer CV may not overlap with the source region SA.

[0085] In the plan view, the capping layer CV may overlap with one end of the gate layer GAT in the first direction DR1, and may not overlap with the other end of the gate layer GAT in the first direction DR1.

[0086] The capping layer CV can be floating. The capping layer CV can have a floating state. For example, the capping layer CV may not be directly connected to other electrodes or wiring. A floating capacitance can be formed between the drain region DA and the gate layer GAT in the capping layer CV. Therefore, electrons can be more effectively trapped in the lower portion of the capping layer CV (e.g., the portion of the first gate insulating layer GI1 adjacent to the capping layer CV), and the gate-induced drain leakage current can be substantially reduced.

[0087] According to one or more embodiments, the overlay layer CV may have an isolated shape (e.g., an island shape) in a planar view. The overlay layer CV may have a polygonal shape or a shape with curvature (e.g., a circular shape or an elliptical shape). However, this disclosure is not limited to any particular example.

[0088] According to one or more embodiments, the capping layer CV may have a thickness smaller than that of the first gate insulating layer GI1 and the second gate insulating layer GI2. Therefore, as described below, low-concentration drain regions LDA may be suitably formed in some regions of the active layer ACT that overlap with the capping layer CV in a planar view.

[0089] For example, the capping layer CV can have a thickness of 10 Å to 1000 Å. The first gate insulating layer GI1 can have a thickness selected in the range of 100 Å to 1500 Å, which is greater than the thickness of the capping layer CV. The second gate insulating layer GI2 can have a thickness selected in the range of 100 Å to 1000 Å, which is greater than the thickness of the capping layer CV.

[0090] The capping layer CV can be used to form a low-concentration drain region LDA in a portion of the drain region DA during the manufacturing process of the display device DD.

[0091] For example, when performing a doping process to form a drain region DA, in a planar view, a portion of the drain region DA with a higher concentration of dopant than the low-concentration drain region LDA can be formed in a region that does not overlap with the capping layer CV, and a low-concentration drain region LDA can be formed in a region that overlaps with the capping layer CV.

[0092] As mentioned above, low-concentration drain region (LDA) can reduce the risk of leakage current in the active layer ACT.

[0093] The capping layer CV may include a material permeable by its dopant. For example, the capping layer CV may include an amorphous silicon material. During the doping process, the region overlapping the capping layer CV on the third-direction DR3 may be doped with a relatively low concentration of dopant, and a low-concentration drain region LDA may be formed. According to one or more embodiments, the capping layer CV may include an amorphous silicon material doped to be conductive.

[0094] According to one or more embodiments, due to the formation of the capping layer CV, electron trapping can occur to a greater extent on the lower portion of the capping layer CV, thereby reducing the gate-induced drain leakage current. Due to the low-concentration drain region LDA formed based on the capping layer CV, the leakage current can be substantially reduced.

[0095] It reduces the risk of display quality being compromised due to leakage current and can provide a display device with improved display performance and electrical signal reliability.

[0096] For example, in order to drive multiple pixels PXL in the display area DSA, a method can be used in which the pixel PXL emits light immediately even when the gate voltage is applied to the switching transistor in the pixel circuit PXC of each pixel PXL, and a method can also be used in which the pixel PXL emits light simultaneously after the gate voltage is applied to all the switching transistors of the pixel PXL formed in multiple columns.

[0097] Experimentally, when using these methods, there may be greater concerns about potential damage to display quality (such as the speckling effect of the DSA in the display area) when a cutoff current or leakage current is generated in each switching transistor.

[0098] However, in the implementation where the overlay CV is placed on the active layer ACT, the likelihood of leakage current being generated in the circuit elements of the pixel PXL can be reduced, thereby mitigating the aforementioned risks.

[0099] The gate layer GAT can be disposed on the second gate insulating layer GI2. The gate layer GAT can overlap with the channel region CHA in the planar view. The gate layer GAT can be electrically connected to the gate line GL and can receive the gate voltage to turn on the transistor.

[0100] The gate layer GAT can overlap with the capping layer CV in a planar view. For example, in a planar view, the gate layer GAT can overlap with one end of the capping layer CV in the first direction DR1, and can not overlap with the other end of the capping layer CV in the first direction DR1.

[0101] The gate layer (GAT) can comprise various conductive materials (e.g., various metals). The gate layer (GAT) can form the gate electrode of a transistor (e.g., a switching transistor) formed by the active layer (ACT).

[0102] The interlayer insulating layer IL may cover at least a portion of the gate layer GAT. The interlayer insulating layer IL may be disposed on the gate layer GAT and the second gate insulating layer GI2. The interlayer insulating layer IL may comprise inorganic or organic materials.

[0103] The drain electrode DE and the source electrode SE can be disposed on the interlayer insulating layer IL.

[0104] The drain electrode DE can be electrically connected to the active layer ACT via the first contact portion CNT1, which penetrates the interlayer insulating layer IL, the first gate insulating layer GI1, and the second gate insulating layer GI2. The first contact portion CNT1 can be connected to the region outside the low-concentration drain region LDA of the drain region DA.

[0105] The source electrode SE can be electrically connected to the active layer ACT via the second contact portion CNT2, which penetrates the interlayer insulating layer IL, the first gate insulating layer GI1, and the second gate insulating layer GI2. The second contact portion CNT2 can be connected to the source region SA.

[0106] In the following text, see references Figure 7 and Figure 8 This section will describe a pixel circuit layer PCL including pixel circuits (PXC) according to one or more other embodiments. For ease of explanation, redundant content relative to the foregoing embodiments will be briefly described or omitted.

[0107] The pixel circuit layer PCL according to this embodiment differs from the pixel circuit layer PCL according to the aforementioned embodiment in that the cover layer CV is disposed across the drain region DA, the channel region CHA, and the source region SA in the plan view.

[0108] The capping layer CV can overlap with the drain region DA, the channel region CHA, and the source region SA in a planar view. In a planar view, the capping layer CV can overlap with each of the two ends of the gate layer GAT in the first direction DR1.

[0109] The source region SA can include a low-concentration source region LSA. The capping layer CV can overlap with the drain region DA to form a low-concentration drain region LDA, and can overlap with the source region SA to form a low-concentration source region LSA.

[0110] A low-concentration source region LSA can be a portion doped with a lower concentration of dopant than other portions of the source region SA. According to one or more embodiments, since portions of the capping layer CV overlap with the source region SA during the doping process to form the source region SA, dopant can be provided at a lower concentration in some regions. Therefore, a low-concentration source region LSA can be formed within a portion of the source region SA.

[0111] In this embodiment, the capping layer CV, the low-concentration source region LSA, and the low-concentration drain region LDA can also reduce the risk of leakage current, etc.

[0112] In the following text, see references Figure 9 and Figure 10 This section will describe a pixel circuit layer PCL including pixel circuits (PXC) according to one or more other embodiments. For ease of explanation, redundant content relative to the foregoing embodiments will be briefly described or omitted.

[0113] The pixel circuit layer PCL according to this embodiment differs from the pixel circuit layer PCL according to the aforementioned embodiment in that the cover layer CV includes a first cover layer CV1 and a second cover layer CV2 that are spaced apart from each other.

[0114] The first cover layer CV1 can have the same characteristics as the above reference. Figure 5 and Figure 6 The described capping layer CV has essentially the same structural features. The second capping layer CV2 can overlap with the source region SA in the planar diagram and can form a low-concentration source region LSA.

[0115] The first capping layer CV1 and the second capping layer CV2 can be formed in the same process.

[0116] In this embodiment, the first capping layer CV1 and the second capping layer CV2, the low-concentration source region LSA, and the low-concentration drain region LDA can also reduce the risk of leakage current, etc.

[0117] refer to Figures 11 to 15This document describes a method for manufacturing a display device DD according to one or more embodiments. For ease of explanation, content that may overlap with the above will be described briefly or without repetition.

[0118] Figures 11 to 15 This is a schematic cross-sectional view illustrating the process steps of a method for manufacturing a display device according to one or more embodiments. For ease of explanation, Figures 11 to 15 The above reference is illustrated schematically. Figure 6 The cross-sectional structure of the pixel circuit layer PCL is described at each process step.

[0119] refer to Figure 11 The underlying active layer ACT_B can be patterned on the base layer BSL. For example, based on the material of the active layer ACT to be provided, an appropriate process can be performed. For example, when the active layer ACT includes a polycrystalline silicon semiconductor, a crystallization process can be performed in this process.

[0120] According to one or more embodiments, a conductive or insulating layer on a base layer (BSL) can be formed based on conventional processes used for manufacturing semiconductor devices. For example, the conductive or insulating layer on the base layer (BSL) can be formed by photolithography, etched by various methods (wet etching, dry etching, etc.), and deposited by various methods (sputtering, chemical vapor deposition, etc.). This disclosure is not necessarily limited to any particular example.

[0121] According to one or more implementations, a buffer layer can be set on the base layer BSL before patterning the base active layer ACT_B.

[0122] refer to Figure 12 A first gate insulating layer GI1 can be formed on the basic active layer ACT_B, and a basic capping layer CV_B can be formed on the first gate insulating layer GI1.

[0123] In this process, the first gate insulating layer GI1 can cover the entirety of the base active layer ACT_B. The base capping layer CV_B can be a layer used to obtain the capping layer CV, and can overlap at least a portion of the base active layer ACT_B in a planar view.

[0124] In this process, according to one or more embodiments, a base capping layer CV_B comprising amorphous silicon material can be provided. For example, the base capping layer CV_B can be formed by a chemical vapor deposition (CVD) method.

[0125] refer to Figure 13 It is possible to remove (e.g., etch) at least a portion of the base overlay CV_B and obtain the overlay CV.

[0126] In this process, a capping layer (CV) can be patterned at such a location, and a low-concentration drain electrode region (LDA) is formed below this location during subsequent processes.

[0127] According to one or more embodiments, refer to Figure 7 and Figure 8 A patterned capping layer CV can be formed beneath the source region SA, channel region CHA, and drain region DA in a planar diagram.

[0128] refer to Figure 9 and Figure 10 According to one or more embodiments, the capping layer CV can be patterned to include a first capping layer CV1 and a second capping layer CV2. In a plan view, the first capping layer CV1 overlaps with the location where the drain region DA is formed, and the second capping layer CV2 overlaps with the location where the source region SA is formed.

[0129] refer to Figure 14 A second gate insulating layer GI2 can be formed on the capping layer CV.

[0130] In this process, the second gate insulating layer GI2 can cover the entire capping layer CV. Therefore, multiple gate insulating structures can be formed for the active layer ACT according to one or more embodiments.

[0131] refer to Figure 15 The gate layer GAT can be patterned on the second gate insulating layer GI2, and a doping process can be performed.

[0132] In this process, after patterning the gate layer GAT, a doping process can be performed to form the drain region DA and the source region SA to obtain the active layer ACT.

[0133] In this process, since the capping layer CV overlaps with a portion of the drain region DA on the third-direction DR3, a low-concentration drain region LDA can be formed in some regions of the active layer ACT that overlap with the capping layer CV. For example, a higher amount of dopant can be provided in regions that do not overlap with the capping layer CV compared to regions that overlap with the capping layer CV on the third-direction DR3. For example, since the capping layer CV comprises amorphous silicon material, a predetermined amount of dopant can penetrate into the capping layer CV.

[0134] Subsequently, according to one or more embodiments, an interlayer insulating layer IL can be formed on the gate layer GAT, and a source electrode SE and a drain electrode DE can be formed to provide a pixel circuit layer PCL. Furthermore, a light-emitting element layer LEL including a light-emitting element LD can be formed on the pixel circuit layer PCL, an upper layer UL including various layers can be formed on the light-emitting element layer LEL, and a display device DD according to one or more embodiments can be provided.

[0135] As described above, the display device DD may include circuit elements that have a reduced risk of leakage current due to the cover layer CV and the resulting low concentration of drain electrode region LDA, and the display device DD may be configured to have excellent display quality.

[0136] The display device DD according to one or more embodiments can be applied to various types of electronic devices. In an embodiment, the electronic device 10 may include the aforementioned display device DD, and may also include other modules or devices with additional functions besides the display device DD.

[0137] Figure 16 This is a schematic block diagram of an electronic device according to one or more embodiments. (Reference) Figure 16 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0138] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. The processor 12 may be electrically connected to the display module 11.

[0139] The memory 13 can store data and / or information used to operate the processor 12 or the display module 11. When the processor 12 runs an application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11. The display module 11 can process the provided signals and output image information on the display screen.

[0140] The power module 14 may include a power source such as a power adapter or battery device, and a power converter. The power converter can convert the power supplied by the power source and generate electricity to operate the electronic device 10.

[0141] At least one of the aforementioned components of the electronic device 10 may be included in the display device DD according to the above embodiment. Functionally, some of the structural elements forming the electronic device 10 may be included in the display device DD, and other structural elements may be provided separately from the display device DD. For example, the display module 11 may be included in the display device DD, while the processor 12, memory 13, and power module 14 may not be included in the display device DD and are instead provided separately in the electronic device 10.

[0142] Figure 17 Schematic diagrams illustrating various embodiments of the electronic device are shown.

[0143] refer to Figure 17 Various types of electronic devices that employ the implementation of the display device DD may include electronic devices for displaying images, such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d and desktop monitors 10_1e; wearable electronic devices including display modules, such as smart glasses 10_2a, head-mounted displays (HMDs) 10_2b and smartwatches 10_2c; and automotive electronic devices including display modules, such as central information displays (CIDs) and rearview mirror displays located on the dashboard, center console, and instrument panel of a vehicle.

[0144] According to one or more embodiments of the present disclosure, a display device, a method of manufacturing a display device, and an electronic device including the display device can be provided, wherein the risk of generating leakage current can be reduced, and thus the risk of display quality being impaired due to leakage current can be reduced.

[0145] According to one or more embodiments of the present disclosure, a display device capable of improving display quality, a method of manufacturing a display device, and an electronic device including the display device can be provided.

[0146] Although this disclosure has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made in this disclosure without departing from the spirit or scope of the disclosure as defined by the appended claims.

[0147] Therefore, the scope of this disclosure should not be limited by the detailed description in this specification, but by the claims.

Claims

1. A display device, comprising: An active layer, on top of a base layer, includes a source region, a drain region, and a channel region. A cover layer, above the active layer; as well as Gate layer, above the channel region The drain region includes a first region and a second region. In a plan view, the first region overlaps with the capping layer, and the second region does not overlap with the capping layer. The first region has a lower dopant concentration than the second region.

2. The display device according to claim 1, wherein, The capping layer comprises a material permeable to dopants doped into the drain region.

3. The display device according to claim 2, wherein, The capping layer comprises amorphous silicon material.

4. The display device according to claim 1, wherein, The covering layer is formed across the first region and the channel region in the plan view.

5. The display device according to claim 4, wherein, The covering layer overlaps entirely with the first region in the plan view.

6. The display device according to claim 1, wherein, The covering layer is in a floating state.

7. The display device according to claim 1, further comprising at least one gate insulating layer, in, The cover layer is in at least one gate insulating layer.

8. The display device according to claim 1, further comprising: A first gate insulating layer is disposed on the active layer; as well as A second gate insulating layer is disposed on the cover layer and the first gate insulating layer. The capping layer has a thickness smaller than that of the first gate insulating layer and the second gate insulating layer, and has a thickness of 10 Å to 1000 Å.

9. The display device according to claim 1, wherein, The second region is formed on one side of the first region, and the channel region is formed on the other side of the first region.

10. The display device according to claim 9, wherein, The capping layer does not overlap with the source region in the plan view.

11. The display device according to claim 1, wherein, The capping layer is disposed across the drain region, the channel region, and the source region in the plan view, and The source region includes a third region and a fourth region. In the plan view, the third region overlaps with the cover layer, and the fourth region does not overlap with the cover layer.

12. The display device according to claim 1, wherein, The overlay includes a first overlay that overlaps with the first region in the plan view and a second overlay that overlaps with the source region.

13. The display device according to claim 12, wherein, The source region includes a third region overlapping the second capping layer in the plan view and a fourth region not overlapping the second capping layer, and The third region has a lower dopant concentration than the fourth region.

14. A display device, comprising: An active layer, on top of a base layer, includes a source region, a drain region, and a channel region. as well as Gate layer, above the channel region The drain region includes a first region and a second region. The first region is located between the second region and the channel region. The first region has a lower dopant concentration than the second region.

15. A method of manufacturing a display device, the method comprising: Pattern the base active layer on the base layer; A patterned overlay layer is applied above the base active layer; A gate layer is patterned above the base active layer and the capping layer; as well as An active layer is obtained by forming a source region, a drain region, and a channel region on the basic active layer. The covering layer includes amorphous silicon material.

16. The method according to claim 15, wherein, Obtaining the active layer includes performing a doping process on the base active layer, and The doping process includes forming a first region in the drain region that overlaps with the capping layer.

17. The method according to claim 16, wherein, The patterning of the overlay includes patterning the overlay at a location formed below the first region.

18. The method according to claim 16, wherein, The patterning of the capping layer includes patterning the capping layer in a planar view over a region formed beneath the source region, the channel region, and the drain region.

19. The method of claim 16, wherein, The patterned overlay includes a first overlay patterned in a planar diagram that overlaps with the drain region and a second overlay patterned with the source region.

20. An electronic device comprising: processor; A display module is configured to be electrically connected to the processor, the display module comprising the display device according to claim 1; as well as A power module is configured to provide power to the display module.

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