Display device

Abstract

A display device includes a substrate, a transistor provided over the substrate, a color filter provided over the transistor, a cover layer provided over the color filter and including a flat portion overlapping with the color filter and a protruding portion protruding from the flat portion, a reflective layer provided over the protruding portion of the cover layer, a pixel electrode provided over the flat portion of the cover layer, an emission layer provided over the pixel electrode and the reflective layer, and a common electrode provided over the emission layer.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0056479, filed on April 29, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device. Background Technology

[0003] With the advancement of the information society, the demand for various types of display devices for displaying images is increasing, and various types of display devices such as liquid crystal displays and organic light-emitting diode displays are already in use.

[0004] The image displayed in the display device can be a still image or a moving image. If the image is a moving image, it can be a variety of images such as sports images, game images, movies, etc. The display device may include multiple pixels and multiple switching elements for driving the pixels. Each of the multiple pixels may include a pixel defining layer configured to define an emission region through which the pixel emits light. However, the area of ​​the emission region is limited by the pixel defining layer, so the display device consumes more power to provide the desired brightness of the pixel. Summary of the Invention

[0005] The technical problem to be solved by this disclosure is to provide a display device that can increase the area of ​​the emission region and improve the light extraction efficiency.

[0006] The technical problems to be solved by this disclosure are not limited to those described above, and other unmentioned technical problems can be inferred from the embodiments provided below.

[0007] One embodiment is a display device comprising: a substrate; a transistor disposed on the substrate; a color filter disposed on the transistor; a cover layer disposed on the color filter and including a flat portion overlapping the color filter and a protrusion extending from the flat portion; a reflective layer disposed on the protrusion of the cover layer; a pixel electrode disposed on the flat portion of the cover layer; an emissive layer disposed on the pixel electrode and the reflective layer; and a common electrode disposed on the emissive layer.

[0008] Further details of the embodiments are included in the detailed description and accompanying drawings.

[0009] The display device according to embodiments of the present disclosure can increase the area of ​​the emission region and improve the light extraction efficiency by improving the aperture ratio.

[0010] The display device according to embodiments of the present disclosure can reduce power consumption by improving light extraction efficiency.

[0011] However, the effects that can be obtained by this disclosure are not limited to those described above, and other technical effects not described above will be readily understood by those skilled in the art to which this disclosure pertains based on the following description. Attached Figure Description

[0012] Figure 1 This is a plan view showing a display device according to an embodiment.

[0013] Figure 2 This is a block diagram illustrating a display device according to one embodiment.

[0014] Figure 3 This is a cross-sectional view showing a display device according to an embodiment.

[0015] Figures 4 to 6 This is a cross-sectional view used to describe a method of manufacturing a display device according to an embodiment.

[0016] Figure 7 This is a cross-sectional view showing a display device according to another embodiment.

[0017] Figures 8 to 10 This is a cross-sectional view used to describe a method of manufacturing a display device according to another embodiment.

[0018] Figure 11 This is a cross-sectional view showing a display device according to yet another embodiment.

[0019] Figures 12 to 14 This is a cross-sectional view used to describe a method of manufacturing a display device according to yet another embodiment.

[0020] Figure 15 This is a cross-sectional view showing a display device according to yet another embodiment.

[0021] Figures 16 to 17 This is a cross-sectional view used to describe a method of manufacturing a display device according to yet another embodiment. Detailed Implementation

[0022] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings. In this specification, when a component (or region, layer, portion, etc.) is referred to as "on (another component)," "connected to," or "combined to" another component, it means that the component may be directly located on, connected to, or combined to the other component, or a third component may be present therein.

[0023] The same reference numerals denote the same elements. Additionally, in the drawings, for the purpose of effective description, the thickness, scale, and dimensions of parts are exaggerated. "And / or" includes all or one or more combinations defined by the relevant parts.

[0024] It should be understood that when the terms “first” and “second” are used herein to describe various components, those components should not be limited by these terms. The terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component without departing from the scope of this disclosure, and vice versa. Unless the context clearly indicates otherwise, the singular expressions and terms used herein also cover or include the plural expressions and terms.

[0025] In addition, terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the structures shown in the figure. These terms are described as relative concepts based on the directions shown in the figure.

[0026] In various embodiments of this disclosure, the terms “comprising,” “including,” “including,” or “containing” specify a characteristic, fixed quantity, step, process, element, and / or component or combination thereof, but do not exclude the presence or addition of other characteristics, fixed quantities, steps, processes, elements, and / or components or combinations thereof.

[0027] Figure 1 This is a plan view showing a display device according to an embodiment.

[0028] Reference Figure 1 The display device 10 can be applied to portable electronic devices such as mobile phones, smartphones, tablet computers, mobile communication terminals, electronic managers, e-book readers, portable multimedia players (PMPs), navigation devices, ultra-mobile PCs (UMPCs), etc. For example, the display device 10 according to this embodiment can be used as a display unit for televisions, laptops, monitors, billboards, Internet of Things (IoT) devices, etc. As another example, the display device 10 can be applied to various wearable devices such as smartwatches, watch phones, glasses-like displays, head-mounted displays (HMDs), etc.

[0029] The display device 10 may include a display panel 100, a display driver 200, and a scan driver 220. The display panel 100 may include a main region MR, a sub-region SR, and a curved region BR located between the main region MR and the sub-region SR.

[0030] The main region MR may include a display region DA and a non-display region NDA. The planar shape of the display region DA may be rectangular. As another example, the planar shape of the display region DA may be square, circular, elliptical, or other polygonal shapes. For example, the display region DA may have a rectangular shape with rounded corners, but is not limited to this, and may also have a rectangular shape with sharp corners.

[0031] In the plan view, the first direction DR1 and the second direction DR2 may intersect perpendicularly, and the third direction DR3 may intersect perpendicularly with the plane including the first direction DR1 and the second direction DR2. In the following text, the first direction DR1 may correspond to the right side, and the direction opposite to the first direction DR1 may correspond to the left side; the second direction DR2 may correspond to the upper side, and the direction opposite to the second direction DR2 may correspond to the lower side; however, the arrangement of components is not limited to these directions.

[0032] The display area DA may include a plurality of pixels SP configured to display an image. Pixel SPs may emit light through an emitting region or an opening region. Pixel SPs may include pixel circuitry with switching elements, a pixel defining layer configured to define the emitting region, and a self-emissive element. For example, the self-emissive element may include at least one of the following: an organic light-emitting diode including an organic light-emitting layer, a quantum dot LED including a quantum dot light-emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED or nano LED, but is not limited thereto.

[0033] The display area DA may include a short side extending along a first direction DR1 and a long side extending along a second direction DR2. The non-display area NDA may be configured to surround the display area DA. The non-display area NDA may include a first side along the first direction DR1 of the display area DA, a second side along a direction opposite to the first direction DR1, a third side along the second direction DR2, and a fourth side along a direction opposite to the second direction DR2. Here, the first side of the non-display area NDA may be the right side, the second side may be the left side, the third side may be the upper side, and the fourth side may be the lower side.

[0034] Scan lines SL can extend along a first direction DR1 and can be spaced apart from each other along a second direction DR2. Scan lines SL can sequentially provide scan signals to multiple pixels SP.

[0035] The emission control lines EML can extend along the first direction DR1 and can be spaced apart from each other along the second direction DR2. The emission control lines EML can sequentially provide emission signals to multiple pixels SP.

[0036] Data lines DL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. Data lines DL can provide data voltage to pixels SP. The data voltage determines the brightness of each pixel SP.

[0037] The power lines VL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. The power lines VL can provide a power supply voltage to the pixel SP. Here, the power supply voltage can include, but is not limited to, a drive voltage, a low-level voltage, an initialization voltage, a reference voltage, and a bias voltage.

[0038] Scan driver 220 can be disposed on each of the first and second sides of the non-display area NDA. Scan driver 220 may include multiple transistors and can provide scan signals to multiple pixels SP. The scan signal of scan driver 220 can select the pixel SP to which it provides data voltage, and the selected pixel SP can receive the data voltage via a data line. Scan driver 220 can be disposed in the non-display area NDA in a gate-in-panel (GIP) configuration.

[0039] The low-potential line VSL can be disposed in the non-display area NDA and can surround the scan driver 220 and the display area DA. For example, the low-potential line VSL can extend from the flexible film FPCB, pass through the sub-region SR and the curved region DR, be disposed on the first to fourth sides of the non-display area NDA, and surround the scan driver 220 and the display area DA.

[0040] The curved region BR and the sub-region SR may extend from the underside of the main region MR. The curved region BR may be disposed between the sub-region SR and the main region MR. The curved region BR may be bent relative to a bending axis along a first direction DR1, and the main region MR and the sub-region SR may overlap in the thickness direction or a third direction DR3. The display panel 100 may be bent such that the lower surface of the main region MR and the upper surface of the sub-region SR face each other.

[0041] The sub-region SR may include a first pad region PA1 and a second pad region PA2. The first pad region PA1 may be located at the center of the sub-region SR and may allow the display driver 200 to be mounted therein. The first pad region PA1 includes multiple pad portions and may be electrically connected to the display driver 200. The display driver 200 may provide data voltage to the data lines of the display panel 100. The display driver 200 may be formed as an integrated circuit (IC). For example, the display driver 200 may be disposed in the first pad region PA1 in a chip-on-plastic or chip-on-glass manner. As another example, the display driver 200 may be disposed in a chip-on-film manner.

[0042] The second pad area PA2 can be located at the lower edge of the sub-area SR. The second pad area PA2 includes multiple pad portions and can be electrically connected to the flexible film FPCB. For example, the flexible film FPCB can electrically connect a timing controller, power supply unit, and memory to the display panel 100.

[0043] The crack sensing pattern CRP may surround the low-potential line VSL, the scan driver 220, and the display area DA. The crack sensing pattern CRP may be positioned on the first to fourth sides of the non-display area NDA and completely surround the display area DA. As another example, the crack sensing pattern CRP may not be positioned within a portion of the non-display area NDA. When an external impact is applied to the display device 10, the crack sensing pattern CRP may be damaged, and the damaged crack sensing pattern CRP may indicate the presence of a crack in the display device 10.

[0044] Figure 2 This is a block diagram illustrating a display device according to one embodiment.

[0045] Reference Figure 2 The display panel 100 may include a display area DA and a non-display area NDA. The display area DA may include multiple pixels SP, power lines VL connected to the pixels SP, scan lines SL and data lines DL.

[0046] Each of the multiple pixels SP can be connected to a scan line SL, a data line DL, and a power line VL. Each of the multiple pixels SP may include a transistor, a light-emitting diode, and a capacitor.

[0047] Scan lines SL can extend along a first direction DR1 and can be spaced apart from each other along a second direction DR2 that intersects the first direction DR1 perpendicularly. Scan lines SL can sequentially provide scan signals to multiple pixels SP.

[0048] The data lines DL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. The data lines DL can provide data voltage to the pixel SP. The data voltage determines the brightness of the pixel SP.

[0049] The power lines VL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. The power lines VL can provide power supply voltages to multiple pixels SP. The power supply voltages can include, but are not limited to, drive voltages, low-level voltages, initialization voltages, reference voltages, and bias voltages.

[0050] Scan driver 220 may include multiple transistors and can generate scan signals based on scan control signals SCS. Scan driver 220 may use a shift register to shift the scan signals and sequentially provide the shifted scan signals to scan lines SL. The scan signals of scan driver 220 can selectively supply data voltages to pixels SP, and the selected pixels SP can receive data voltages via data lines DL. Scan driver 220 may be positioned as a gate in panel (GIP) on one or both sides of the non-display area DNA.

[0051] The timing controller 500 can receive digital video data DATA and timing signals from a graphics device or a setting module. The timing controller 500 can generate a data control signal DCS based on the timing signals. The timing controller 500 can control the operating timing of the display driver 200 by providing the digital video data DATA and the data control signal DCS to the display driver 200. The display driver 200 can convert the digital video data DATA into analog data voltage and provide it to the data line DL. The timing controller 500 can generate a scan control signal SCS based on the timing signals. The timing controller 500 can control the operating timing of the scan driver 220 by providing the scan control signal SCS to the scan driver 220. The timing controller 500 can change the driving frequency of the display panel 100 based on the input frequency received from the graphics device.

[0052] The power supply unit 600 can provide a power supply voltage to the power line VL. The power supply voltage may include, but is not limited to, a drive voltage, a low-level voltage, an initialization voltage, a reference voltage, and a bias voltage. The power supply unit 600 can generate a drive voltage and provide it to the drive voltage line, generate an initialization voltage and provide it to the initialization voltage line, generate a bias voltage and provide it to the bias voltage line, generate a reference voltage and provide it to the reference voltage line, and generate a low-level voltage and provide it to the low-level line VSL.

[0053] Figure 3 This is a cross-sectional view showing a display device according to an embodiment.

[0054] Reference Figure 3 The display panel 100 can emit light in a bottom-emitting manner. The display panel 100 can emit light emitted from the light-emitting diode ED through the substrate SUB and the optical component POL. The display panel 100 may include the optical component POL, the substrate SUB, the first buffer layer BUF1, the metal layer MTL, the second buffer layer BUF2, the transistor TR, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the first connection electrode CE1, the second connection electrode CE2, the through-hole layer VIA, the color filter CF, the overcoat layer OC, the reflective layer RFL, the light-emitting diode ED, the embankment BNK, and the encapsulation layer TFE.

[0055] An optical component (POL) polarizes the light emitted from a light-emitting diode (ED). The POL may include a polarizing film or a phase retardation film. The POL reduces reflected light caused by external light and prevents color distortion caused by the reflection of external light.

[0056] The substrate SUB can be disposed on the optical component POL. The substrate SUB can be a base substrate or a base component. The substrate SUB can be a flexible substrate capable of being bent, folded, rolled, etc. For example, the substrate SUB can include a glass material. As another example, the substrate SUB can include a polymer resin, such as polyimide PI, but is not limited thereto.

[0057] A first buffer layer BUF1 may be disposed on a substrate SUB. The first buffer layer BUF1 may include an inorganic layer capable of preventing the penetration of air or moisture. For example, the first buffer layer BUF1 may include multiple inorganic layers stacked alternately.

[0058] A metal layer MTL may be disposed on the first buffer layer BUF1. The metal layer MTL may be disposed below the transistor TR and may overlap with the semiconductor region ACT. The metal layer MTL prevents light from passing through the semiconductor region ACT of the transistor TR. The metal layer MTL may contain at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), and copper (Cu), but is not limited thereto.

[0059] The second buffer layer BUF2 may be disposed on the metal layer MTL. The second buffer layer BUF2 may include an inorganic layer capable of preventing the penetration of air or moisture. For example, the second buffer layer BUF2 may include multiple inorganic layers stacked alternately.

[0060] A transistor TR can constitute the pixel circuit of a pixel SP. The transistor TR can provide drive current to a light-emitting diode ED. The semiconductor region ACT, drain electrode DE, and source electrode SE of the transistor TR can be disposed on a second buffer layer BUF2. For example, the semiconductor region ACT of the transistor TR can comprise a silicon-based material, and its drain electrode DE and source electrode SE can be formed by doping with p-type impurities. As another example, the semiconductor region ACT of the transistor TR can comprise an oxide-based material, and its drain electrode DE and source electrode SE can be formed by doping with n-type impurities. The drain electrode DE of the transistor TR can be connected to a first connection electrode CE1, and the source electrode SE of the transistor TR can be connected to a second connection electrode CE2.

[0061] A first gate insulating layer GI1 may be disposed on the semiconductor region ACT of the transistor TR. The first gate insulating layer GI1 can insulate the semiconductor region ACT and the gate electrode GE of the transistor TR from each other. The first gate insulating layer GI1 may include an inorganic material.

[0062] The gate electrode GE of transistor TR can be disposed on the first gate insulating layer GI1. The gate electrode GE of transistor TR can overlap with the semiconductor region ACT of transistor TR.

[0063] A second gate insulating layer GI2 may be disposed on the gate electrode GE of the transistor TR. The second gate insulating layer GI2 can insulate the gate electrode GE from the first connection electrode CE1 and the second connection electrode CE2. The second gate insulating layer GI2 may comprise an inorganic material.

[0064] An interlayer insulating layer (ILD) may be disposed on the second gate insulating layer (GI2). The ILD insulates the first connection electrode (CE1) and the second connection electrode (CE2) from the gate electrode (GE). The thickness of the ILD may be greater than the thickness of either the first gate insulating layer (GI1) or the second gate insulating layer (GI2). The ILD may include an inorganic layer capable of preventing the penetration of air or moisture.

[0065] A first connecting electrode CE1 and a second connecting electrode CE2 can be disposed on the interlayer insulating layer ILD. The first connecting electrode CE1 can be inserted into a contact hole penetrating the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1, and can be connected to the drain electrode DE of the transistor TR. The second connecting electrode CE2 can be inserted into a contact hole penetrating the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1, and can be connected to the source electrode SE of the transistor TR. The second connecting electrode CE2 electrically connects the pixel electrode AE ​​of the light-emitting diode ED to the source electrode SE of the transistor TR.

[0066] A via layer VIA may be disposed on the first connecting electrode CE1 and the second connecting electrode CE2. The via layer VIA insulates the first connecting electrode CE1 and the second connecting electrode CE2 from the color filter CF. The upper surface of the via layer VIA may be flat. The via layer VIA may comprise an organic insulating material such as polyimide (PI).

[0067] The color filter CF can be disposed on the via layer VIA. In bottom emission mode, the color filter CF can be disposed below the light-emitting diode ED. The color filter CF can selectively transmit light of a certain wavelength and block or absorb light of another wavelength.

[0068] An overlay layer OC can be disposed on a color filter CF. The upper surface of the overlay layer OC may include a flat portion and a protrusion PRT projecting upward from the flat portion. The flat portion of the overlay layer OC may overlap with the light-emitting diode ED and the color filter CF. The protrusion PRT of the overlay layer OC may overlap with the reflective layer RFL and the embankment BNK. The protrusion PRT may project from the flat portion in a triangular shape, but is not limited thereto. The protrusion PRT may include a first surface inclined from the flat portion and a second surface symmetrical to the first surface. For example, the overlay layer OC may be formed by an exposure process using a gradient half-tone mask, but is not limited thereto.

[0069] A reflective layer RFL may be disposed on the protrusion PRT of the cover layer OC. The reflective layer RFL may be disposed on each of the first and second surfaces of the protrusion PRT. The reflective layer RFL may not be disposed on the uppermost part of the protrusion PRT of the cover layer OC. The reflective layer RFL reflects light emitted from the light-emitting diode ED toward the encapsulation layer TFE. The reflective layer RFL may comprise a metallic material with high reflectivity.

[0070] A light-emitting diode (ED) may include a pixel electrode AE, an emitting layer EL, and a common electrode CAT. The pixel electrode AE ​​may be disposed on a capping layer OC and a reflective layer RFL. The pixel electrode AE ​​may be disposed on the capping layer OC in the emitting region EA and on the reflective layer RFL in the non-emitting region. The pixel electrode AE ​​may completely cover the reflective layer RFL. The pixel electrode AE ​​may be a transparent electrode and transmit light. The pixel electrode AE ​​may be inserted into a contact hole penetrating the capping layer OC and the via layer VIA, and may be connected to a second connection electrode CE2. The pixel electrode AE ​​may receive drive current from the pixel circuitry of the pixel SP. The pixel electrode AE ​​may be the first electrode of the light-emitting diode ED.

[0071] The dam portion (BNK) can be disposed on the pixel electrode (AE) and the protrusion (PRT) of the capping layer (OC). The dam portion (BNK) can define the emission region (EA). The dam portion (BNK) can overlap with the protrusion (PRT) of the capping layer (OC) and the reflective layer (RFL). The dam portion (BNK) can overlap with the transistor (TR) of the pixel (SP).

[0072] An emission layer EL can be disposed on the pixel electrode AE ​​and the embankment BNK. The emission layer EL can be disposed on the pixel electrode AE ​​in the emission region EA and on the embankment BNK in the non-emission region. The emission layer EL may not be divided for each pixel in a plurality of pixels SP and can be integrally formed in all pixels SP. For example, the emission layer EL can be an organic emission layer formed of an organic material, but is not limited thereto. When the emission layer EL corresponds to an organic emission layer, the pixel circuit of the pixel SP can apply a predetermined voltage to the pixel electrode AE, and when the common electrode CAT receives a common voltage or a cathode voltage, holes can move to the emission layer EL through the hole transport layer, and electrons can move to the emission layer EL through the electron transport layer. As holes and electrons couple with each other, light can be emitted.

[0073] A common electrode CAT can be disposed on the emitter layer EL. For example, the common electrode CAT may not be divided for each pixel in a plurality of pixels SP, and can be implemented as a common electrode for all pixels SP. The common electrode CAT can be electrically connected to the low potential line VSL and can receive a low potential voltage, a common voltage, or a cathode voltage. The common electrode CAT can be the second electrode of a light-emitting diode ED. The common electrode CAT can be formed of a metallic material with high reflectivity to reflect light toward the substrate SUB.

[0074] A TFE (Transmission Electrode Interior) layer can be disposed on a light-emitting diode (ED). The TFE layer can be disposed on a common electrode (CAT) and can cover multiple EDs. The TFE layer can comprise inorganic materials and prevent oxygen or moisture from penetrating the ED. Alternatively, the TFE layer can comprise organic materials and protect the ED from foreign matter such as dust.

[0075] Since the display device 10 includes a protrusion PRT of the cover layer OC and a reflective layer RFL disposed on the protrusion PRT, light emitted from the light-emitting diode ED can be reflected by the reflective layer RFL toward the encapsulation layer TFE, and then reflected by the common electrode CAT toward the substrate SUB. Therefore, the display device 10 can improve light extraction efficiency. The display device 10 can reduce power consumption by improving light extraction efficiency.

[0076] Figures 4 to 6 This is a cross-sectional view used to describe a method of manufacturing a display device according to one embodiment. For ease of description, the substrate SUB and optical component POL are not shown. Figure 3 The diagram shows the first buffer layer BUF1, metal layer MTL, second buffer layer BUF2, transistor TR, first gate insulating layer GI1, second gate insulating layer GI2, interlayer insulating layer ILD, first connection electrode CE1, second connection electrode CE2, and via layer GIA. Figures 4 to 6 The transistor layer (TRL) is defined and shown in the middle.

[0077] A color filter (CF) can be placed on the transistor layer (TRL). The color filter (CF) can selectively transmit light of a certain wavelength and block or absorb light of another wavelength.

[0078] An overlay layer OC can be disposed on a color filter CF. The upper surface of the overlay layer OC may include a flat portion and a protrusion PRT projecting upward from the flat portion. The protrusion PRT may project from the flat portion in a triangular shape, but is not limited thereto. The protrusion PRT may include a first surface inclined from the flat portion and a second surface symmetrical to the first surface. For example, the overlay layer OC can be formed by an exposure process using a gradient halftone mask, but is not limited thereto.

[0079] The reflective layer RFL can be deposited on the entire surface of the capping layer OC and can be patterned. The reflective layer RFL can be disposed on each of the first and second surfaces of the protrusion PRT. The reflective layer RFL may not be disposed on the topmost part of the protrusion PRT of the capping layer OC. The reflective layer RFL may comprise a metallic material with high reflectivity.

[0080] exist Figure 5 In this process, pixel electrodes (AEs) can be deposited on the entire surface of the capping layer (OC) and the reflective layer (RFL) and can be patterned. Pixel electrodes (AEs) may not be positioned on the top of the protrusion (PRT). Each of the pixel electrodes (AEs) of multiple pixels (SPs) can be insulated from each other. Pixel electrodes (AEs) can completely cover the reflective layer (RFL). Pixel electrodes (AEs) can be transparent electrodes and can transmit light.

[0081] The dam portion (BNK) can be disposed on the pixel electrode (AE). The dam portion (BNK) can define the emission region (EA). The dam portion (BNK) can overlap with the protrusion (PRT) of the cover layer (OC) and the reflective layer (RFL).

[0082] exist Figure 6 In this process, the emitter layer EL can be disposed on the pixel electrode AE ​​and the embankment BNK. The emitter layer EL can be disposed on the pixel electrode AE ​​in the emitter region EA, and can be disposed on the embankment BNK in the non-emitter region. The emitter layer EL does not need to be divided for each pixel in the multiple pixels SP, and can be integrally formed in all pixels SP.

[0083] The common electrode CAT can be set on the emitter layer EL. For example, the common electrode CAT may not be divided for each pixel in the multiple pixels SP, and can be implemented as a common electrode for all pixels SP.

[0084] The TFE encapsulation layer can be disposed on the light-emitting diode (ED). The TFE encapsulation layer can be disposed on the common electrode CAT and can cover multiple light-emitting diodes (ED).

[0085] Figure 7 This is a cross-sectional view showing a display device according to another embodiment. Figure 7 The display device in the middle has the same Figure 3 The protrusion PRT and the embankment BNK of the cover layer OC of the display device are configured differently, and the same components as described above can be briefly described or omitted.

[0086] Reference Figure 7The display panel 100 can emit light in a bottom-emitting manner. The display panel 100 can emit light emitted from the light-emitting diode ED through the substrate SUB and the optical component POL. The display panel 100 may include the optical component POL, the substrate SUB, the first buffer layer BUF1, the metal layer MTL, the second buffer layer BUF2, the transistor TR, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the first connection electrode CE1, the second connection electrode CE2, the through-hole layer GIA, the color filter CF, the cover layer OC, the reflective layer RFL, the light-emitting diode ED, the dam BNK, and the encapsulation layer TFE.

[0087] The color filter CF can be disposed on the via layer VIA. In bottom emission mode, the color filter CF can be disposed below the light-emitting diode ED. The color filter CF can selectively transmit light of a certain wavelength and block or absorb light of another wavelength.

[0088] An overlay layer OC can be disposed on a color filter CF. The upper surface of the overlay layer OC may include a flat portion and a protrusion PRT projecting upward from the flat portion. The flat portion of the overlay layer OC may overlap with the light-emitting diode ED and the color filter CF. The protrusion PRT of the overlay layer OC may overlap with the reflective layer RFL and the embankment BNK. The protrusion PRT may include a flat upper surface and a side surface sloping between the upper surface and the flat portion. For example, the overlay layer OC can be formed by an exposure process using a gradient halftone mask, but is not limited thereto.

[0089] A reflective layer RFL can be disposed on the side surface of the protrusion PRT and the embankment BNK of the cover layer OC. The lower portion of the reflective layer RFL can be disposed on the side surface of the protrusion PRT, and its upper portion can contact the embankment BNK, specifically, a portion of the embankment BNK disposed on the flat upper surface of the protrusion PRT. The reflective layer RFL can reflect light emitted from the light-emitting diode ED toward the encapsulation layer TFE. The reflective layer RFL may comprise a metallic material with high reflectivity.

[0090] A light-emitting diode (ED) may include a pixel electrode AE, an emitting layer EL, and a common electrode CAT. The pixel electrode AE ​​may be disposed on a capping layer OC and a reflective layer RFL. The pixel electrode AE ​​may be disposed on the capping layer OC in the emitting region EA and on the reflective layer RFL in the non-emitting region. The pixel electrode AE ​​may completely cover the reflective layer RFL. The pixel electrode AE ​​may be a transparent electrode and may transmit light.

[0091] The dam portion (BNK) can be disposed on the pixel electrode (AE) and the protrusion (PRT) of the capping layer (OC). The dam portion (BNK) can define the emission region (EA). The dam portion (BNK) can overlap with the protrusion (PRT) of the capping layer (OC) and the reflective layer (RFL). The dam portion (BNK) can overlap with the transistor (TR) of the pixel (SP).

[0092] The embankment BNK may include a recessed portion DNT that overlaps with the protrusion PRT of the capping layer OC. The recessed portion DNT can be formed by an exposure process using a halftone mask on the upper surface of the embankment BNK. The emitter layer EL and the common electrode CAT may not fill the recessed portion DNT. Therefore, the recessed portion DNT can form a gap GAP with the emitter layer EL and the common electrode CAT.

[0093] The emitter layer EL can be disposed on the pixel electrode AE ​​and the embankment BNK. The emitter layer EL can be disposed on the pixel electrode AE ​​in the emitter region EA, and can also be disposed on the embankment BNK in the non-emitter region. The emitter layer EL can be formed integrally within all pixels SP, without being divided for each pixel in a plurality of pixels SP. The emitter layer EL can be cut by a gap GAP formed by the recess DNT of the embankment BNK.

[0094] A common electrode CAT can be disposed on the emitter layer EL. For example, the common electrode CAT may not be divided for each pixel in the multiple pixels SP, and can be implemented as a common electrode for all pixels SP. The common electrode CAT can be formed of a metallic material with high reflectivity to reflect light toward the substrate SUB.

[0095] A TFE (Transmission Electrode Interior) layer can be disposed on a light-emitting diode (ED). The TFE layer can be disposed on a common electrode (CAT) and can cover multiple EDs. The TFE layer can comprise inorganic materials and prevent oxygen or moisture from penetrating the ED. Alternatively, the TFE layer can comprise organic materials and protect the ED from foreign matter such as dust.

[0096] Since the display device 10 includes a protrusion PRT of the cover layer OC and a reflective layer RFL disposed on the protrusion PRT and the embankment BNK, light emitted from the light-emitting diode ED can be reflected by the reflective layer RFL toward the encapsulation layer TFE, and then reflected by the common electrode CAT toward the substrate, thus improving the light extraction efficiency of the display device 10. The display device 10 can reduce power consumption by improving the light extraction efficiency. Since the embankment BNK includes a recess DNT, the emitting layer EL can be cut through the gap GAP formed by the recess DNT, thereby reducing light leakage and crosstalk.

[0097] Figures 8 to 10This is a cross-sectional view used to describe a method of manufacturing a display device according to another embodiment. For ease of description, the substrate SUB and optical component POL are not shown, and Figure 7 The diagram shows the first buffer layer BUF1, metal layer MTL, second buffer layer BUF2, transistor TR, first gate insulating layer GI1, second gate insulating layer GI2, interlayer insulating layer ILD, first connection electrode CE1, second connection electrode CE2, and via layer GIA. Figures 8 to 10 The transistor layer (TRL) is defined and shown in the middle.

[0098] A color filter (CF) can be placed on the transistor layer (TRL). The color filter (CF) can selectively transmit light of a certain wavelength and block or absorb light of another wavelength.

[0099] An overlay layer OC can be disposed on a color filter CF. The upper surface of the overlay layer OC may include a flat portion and a protrusion PRT projecting upward from the flat portion. Before the reflective layer RFL is formed, the protrusion PRT may project from the flat portion in a triangular shape. The protrusion PRT may include a first surface inclined from the flat portion and a second surface symmetrical to the first surface. For example, the overlay layer OC can be formed by an exposure process using a gradient halftone mask, but is not limited thereto.

[0100] The reflective layer RFL can be deposited on the entire surface of the capping layer OC and can be patterned. The reflective layer RFL can be disposed on each of the first and second surfaces of the protrusion PRT. The reflective layer RFL may not be disposed on the topmost part of the protrusion PRT of the capping layer OC. The reflective layer RFL may comprise a metallic material with high reflectivity.

[0101] Pixel electrodes (AEs) can be deposited on the entire surface of the capping layer (OC) and the reflective layer (RFL) and can be patterned. Pixel electrodes (AEs) do not necessarily need to be positioned on the top of the protrusion (PRT). Each of the pixel electrodes (AEs) of multiple pixels (SPs) can be insulated from each other. Pixel electrodes (AEs) can completely cover the reflective layer (RFL). Pixel electrodes (AEs) can be transparent electrodes and can transmit light.

[0102] After forming the reflective layer RFL and the pixel electrode AE, the upper part of the protrusion PRT of the capping layer OC can be etched to form a flat upper surface. Therefore, a portion of the reflective layer RFL and a portion of the pixel electrode AE ​​may not be supported by the protrusion PRT of the capping layer OC.

[0103] exist Figure 9 In this configuration, the dam portion (BNK) can be disposed on the pixel electrode (AE) and the protrusion (PRT) of the capping layer (OC). The dam portion (BNK) can define the emission region (EA). The dam portion (BNK) can overlap with the protrusion (PRT) of the capping layer (OC) and the reflective layer (RFL). The dam portion (BNK) can overlap with the transistor (TR) of the pixel (SP).

[0104] The embankment BNK may include recessed portions DNTs that overlap with the protrusions PRT of the cover layer OC. The recessed portions DNTs can be formed by an exposure process using a halftone mask on the upper surface of the embankment BNK.

[0105] exist Figure 10 In this structure, the emitter layer EL can be disposed on the pixel electrode AE ​​and the embankment BNK. The emitter layer EL can be disposed on the pixel electrode AE ​​in the emitter region EA, and can also be disposed on the embankment BNK in the non-emitter region. The emitter layer EL can not be divided for each pixel in a plurality of pixels SP, and can be integrally formed in all pixels SP. The emitter layer EL can be cut by a gap GAP formed by the recess DNT of the embankment BNK.

[0106] The common electrode CAT can be set on the emitter layer EL. For example, the common electrode CAT may not be divided for each pixel in the multiple pixels SP, and can be implemented as a common electrode for all pixels SP.

[0107] The emitter layer EL and the common electrode CAT may not be filled in the recessed portion DNT. Therefore, the gap GAP can be surrounded by the recessed portion DNT, the emitter layer EL, and the common electrode CAT.

[0108] The TFE encapsulation layer can be disposed on the light-emitting diode (ED). The TFE encapsulation layer can be disposed on the common electrode CAT and can cover multiple light-emitting diodes (ED).

[0109] Figure 11 This is a cross-sectional view showing a display device according to yet another embodiment. Figure 11 The display device in the middle has relative to Figure 7 The display device in the text omits the configuration of the embankment BNK, and the same components as those described above can be briefly described or omitted.

[0110] Reference Figure 11 The display panel 100 can emit light in a bottom-emitting manner. The display panel 100 can emit light emitted from the light-emitting diode ED through the substrate SUB and the optical component POL. The display panel 100 may include the optical component POL, the substrate SUB, the first buffer layer BUF1, the metal layer MTL, the second buffer layer BUF2, the transistor TR, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the first connection electrode CE1 and the second connection electrode CE2, the through-hole layer GIA, the color filter CF, the cover layer OC, the reflective layer RFL, the light-emitting diode ED, and the encapsulation layer TFE.

[0111] The color filter CF can be disposed on the via layer VIA. In bottom emission mode, the color filter CF can be disposed below the light-emitting diode ED. The color filter CF can selectively transmit light of a certain wavelength and block or absorb light of another wavelength.

[0112] A capping layer OC can be disposed on a color filter CF. The upper surface of the capping layer OC may include a flat portion and a protrusion PRT projecting upward from the flat portion. The flat portion of the capping layer OC may overlap with the light-emitting diode ED and the color filter CF. The protrusion PRT of the capping layer OC may overlap with the reflective layer RFL. The protrusion PRT may include a flat upper surface and a sloping side surface between the upper surface and the flat portion. For example, the capping layer OC can be formed by an exposure process using a gradient halftone mask, but is not limited thereto. The protrusion PRT of the capping layer OC, the reflective layer RFL, the emitting layer EL, and the common electrode CAT can form a gap GAP.

[0113] A light-emitting diode (ED) may include a pixel electrode AE, an emitter layer EL, and a common electrode CAT. The pixel electrode AE ​​may be disposed on a capping layer OC. The pixel electrode AE ​​may be disposed on a flat portion of the capping layer OC. The pixel electrode AE ​​may be a transparent electrode and may transmit light.

[0114] The reflective layer RFL can be disposed on the upper surface of the pixel electrode AE ​​and the side surface of the protrusion PRT of the capping layer OC. The lower part of the reflective layer RFL can be disposed on the upper surface of the pixel electrode AE ​​and the side surface of the protrusion PRT, and its upper part can form part of the gap GAP. The reflective layer RFL can perform... Figure 3 or Figure 7 The function of the embankment BNK in the LED is as follows: The reflective layer RF defines the emission region EA, thereby increasing the area of ​​the emission region EA compared to the area defined by the embankment. The reflective layer RFL reflects light emitted from the LED ED toward the TFE encapsulation layer. The reflective layer RFL may include a metallic material with high reflectivity.

[0115] An emitter layer (EL) can be disposed on a pixel electrode (AE) and a reflective layer (RFL). A portion of the emitter layer (EL) can be disposed on the pixel electrode (AE), while another portion can be disposed on the reflective layer (RFL). The emitter layer (EL) does not need to be divided for each pixel in a plurality of pixels (SPs) and can be integrally formed within all pixels (SPs). The emitter layer (EL) can be divided by gaps (GAPs) between the reflective layers (RFLs).

[0116] A common electrode CAT can be disposed on the emitter layer EL. For example, the common electrode CAT may not be divided for each pixel in the multiple pixels SP, and can be implemented as a common electrode for all pixels SP. The common electrode CAT can be formed of a metallic material with high reflectivity to reflect light toward the substrate SUB.

[0117] A TFE (Transmission Electrode Interior) layer can be disposed on a light-emitting diode (ED). The TFE layer can be disposed on a common electrode (CAT) and can cover multiple EDs. The TFE layer can comprise inorganic materials and prevent oxygen or moisture from penetrating the ED. Alternatively, the TFE layer can comprise organic materials and protect the ED from foreign matter such as dust.

[0118] Since the display device 10 includes a protrusion PRT of the cover layer OC and a reflective layer RFL disposed on the protrusion PRT and the pixel electrode AE, the reflective layer RFL can perform the function of a dam. The display device 10 can increase the area of ​​the emitting region EA by improving the aperture ratio, and the light emitted from the light-emitting diode ED can be reflected by the reflective layer RFL toward the encapsulation layer TFE, and then reflected by the common electrode CAT toward the substrate, thus improving the light extraction efficiency. The display device 10 can reduce power consumption by improving the light extraction efficiency. Since the emitting layer EL can be cut by the gap GAP between the reflective layers RFL, light leakage and crosstalk can be reduced.

[0119] Figures 12 to 14 This is a cross-sectional view used to describe a method of manufacturing a display device according to yet another embodiment. For ease of description, the substrate SUB and optical component POL are not shown, and Figure 11 The first buffer layer BUF1, metal layer MTL, second buffer layer BUF2, transistor TR, first gate insulating layer GI1, second gate insulating layer GI2, interlayer insulating layer ILD, first connection electrode CE1 and second connection electrode CE2, and via layer GIA are defined and shown as transistor layer TRL.

[0120] A color filter (CF) can be placed on the transistor layer (TRL). The color filter (CF) can selectively transmit light of a certain wavelength and block or absorb light of another wavelength.

[0121] An overlay layer OC can be disposed on a color filter CF. The upper surface of the overlay layer OC may include a flat portion and a protrusion PRT projecting upward from the flat portion. Before the reflective layer RFL is formed, the protrusion PRT may project from the flat portion in a triangular shape. The protrusion PRT may include a first surface inclined from the flat portion and a second surface symmetrical to the first surface. For example, the overlay layer OC can be formed by an exposure process using a gradient halftone mask, but is not limited thereto.

[0122] Pixel electrodes AE can be deposited on the entire surface of the capping layer OC and can be patterned. Pixel electrodes AE can be disposed on a flat portion of the capping layer OC. Each of the pixel electrodes AE of a plurality of pixels SP can be insulated from each other. Pixel electrodes AE can be transparent electrodes and can transmit light.

[0123] The reflective layer RFL can be deposited on the entire surface of the pixel electrode AE ​​and the capping layer OC and can be patterned. The reflective layer RFL can be disposed on each of the first and second surfaces of the pixel electrode AE ​​and the protrusion PRT. The reflective layer RFL may not be disposed on the topmost part of the protrusion PRT of the capping layer OC. The reflective layer RFL may comprise a metallic material with high reflectivity.

[0124] exist Figure 13 In this process, the upper part of the protrusion PRT of the capping layer OC can be etched after the reflective layer RFL is formed. Therefore, a portion of the reflective layer RFL may not be supported by the protrusion PRT of the capping layer OC.

[0125] exist Figure 14 In this structure, the emitter layer EL can be disposed on the pixel electrode AE ​​and the reflective layer RFL. A portion of the emitter layer EL can be disposed on the pixel electrode AE, while another portion of the emitter layer EL can be disposed on the reflective layer RFL. The emitter layer EL can not be divided for each pixel in a plurality of pixels SP, and can be integrally formed in all pixels SP. The emitter layer EL can be cut by gaps (GAPs) between the reflective layers RFL.

[0126] The common electrode CAT can be set on the emitter layer EL. For example, the common electrode CAT may not be divided for each pixel in the multiple pixels SP, and can be implemented as a common electrode for all pixels SP.

[0127] The protrusion PRT of the capping layer OC, the reflective layer RFL, the emitting layer EL, and the common electrode CAT can form a gap GAP.

[0128] The TFE encapsulation layer can be disposed on the light-emitting diode (ED). The TFE encapsulation layer can be disposed on the common electrode CAT and can cover multiple light-emitting diodes (ED).

[0129] Figure 15 This is a cross-sectional view showing a display device according to yet another embodiment. Figure 15 The display device in the middle has relative to Figure 3 The display device in the text omits the configuration of the embankment BNK, and the same components as those described above can be briefly described or omitted.

[0130] Reference Figure 15The display panel 100 can emit light in a bottom-emitting manner. The display panel 100 can emit light emitted from the light-emitting diode ED through the substrate SUB and the optical component POL. The display panel 100 may include the optical component POL, the substrate SUB, the first buffer layer BUF1, the metal layer MTL, the second buffer layer BUF2, the transistor TR, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the first connection electrode CE1 and the second connection electrode CE2, the through-hole layer GIA, the color filter CF, the cover layer OC, the reflective layer RFL, the light-emitting diode ED, and the encapsulation layer TFE.

[0131] The color filter CF can be disposed on the via layer VIA. In bottom emission mode, the color filter CF can be disposed below the light-emitting diode ED. The color filter CF can selectively transmit light of a certain wavelength and block or absorb light of another wavelength.

[0132] An overlay layer OC may be disposed on a color filter CF. The upper surface of the overlay layer OC may include a flat portion and a protrusion PRT projecting upward from the flat portion. The flat portion of the overlay layer OC may overlap with the light-emitting diode ED and the color filter CF. The protrusion PRT of the overlay layer OC may overlap with the reflective layer RFL. The protrusion PRT may project from the flat portion in a triangular shape, but is not limited thereto. The protrusion PRT may include a first surface inclined from the flat portion and a second surface symmetrical to the first surface. For example, the overlay layer OC may be formed by an exposure process using a gradient halftone mask, but is not limited thereto.

[0133] A light-emitting diode (ED) may include a pixel electrode AE, an emitter layer EL, and a common electrode CAT. The pixel electrode AE ​​may be disposed on a capping layer OC. The pixel electrode AE ​​may be disposed on a flat portion of the capping layer OC. The pixel electrode AE ​​may be a transparent electrode and may transmit light.

[0134] The reflective layer RFL can be disposed on the upper surface of the pixel electrode AE ​​and on each of the first and second surfaces of the protrusion PRT of the capping layer OC. The reflective layer RFL may not be disposed on the uppermost part of the protrusion PRT of the capping layer OC. The reflective layer RFL can perform... Figure 3 or Figure 7 The function of the embankment BNK in the LED is as follows: The reflective layer RF defines the emission region EA to increase the area of ​​the emission region EA compared to the area defined by the embankment. The reflective layer RFL reflects light emitted from the LED ED toward the TFE encapsulation layer. The reflective layer RFL may include a metallic material with high reflectivity.

[0135] An emitter layer (EL) can be disposed on a pixel electrode (AE) and a reflective layer (RFL). A portion of the emitter layer (EL) can be disposed on the pixel electrode (AE), while another portion can be disposed on the reflective layer (RFL). The emitter layer (EL) may not be divided for each pixel in a plurality of pixels (SPs) and can be integrally formed within all pixels (SPs). The emitter layer (EL) may or may not be cut off at the top of the reflective layer (RFL).

[0136] A common electrode CAT can be disposed on the emitter layer EL. For example, the common electrode CAT may not be divided for each pixel in the multiple pixels SP, and can be implemented as a common electrode for all pixels SP. The common electrode CAT can be formed of a metallic material with high reflectivity to reflect light toward the substrate SUB.

[0137] A TFE (Transmission Electrode Interior) layer can be disposed on a light-emitting diode (ED). The TFE layer can be disposed on a common electrode (CAT) and can cover multiple EDs. The TFE layer can comprise inorganic materials and prevent oxygen or moisture from penetrating the ED. Alternatively, the TFE layer can comprise organic materials and protect the ED from foreign matter such as dust.

[0138] Since the display device 10 includes a protrusion PRT of the cover layer OC and a reflective layer RFL disposed on the protrusion PRT and the pixel electrode AE, the reflective layer RFL can perform the function of a dam. The display device 10 can increase the area of ​​the emitting region EA by improving the aperture ratio, and the light emitted from the light-emitting diode ED can be reflected by the reflective layer RFL toward the encapsulation layer TFE, and then reflected by the common electrode CAT toward the substrate, thus improving the light extraction efficiency. The display device 10 can reduce power consumption by improving the light extraction efficiency. Since the emitting layer EL can be cut off at the top of the protrusion PRT, light leakage and crosstalk can be reduced.

[0139] Figures 16 to 17 This is a cross-sectional view used to describe a method of manufacturing a display device according to yet another embodiment. For ease of description, the substrate SUB and optical component POL are not shown, and Figure 15 The diagram shows the first buffer layer BUF1, metal layer MTL, second buffer layer BUF2, transistor TR, first gate insulating layer GI1, second gate insulating layer GI2, interlayer insulating layer ILD, first connection electrode CE1, second connection electrode CE2, and via layer GIA. Figures 16 to 17 The transistor layer (TRL) is defined and shown in the middle.

[0140] A color filter (CF) can be placed on the transistor layer (TRL). The color filter (CF) can selectively transmit light of a certain wavelength and block or absorb light of another wavelength.

[0141] An overlay layer OC can be disposed on a color filter CF. The upper surface of the overlay layer OC may include a flat portion and a protrusion PRT projecting upward from the flat portion. The protrusion PRT may project from the flat portion in a triangular shape, but is not limited thereto. The protrusion PRT may include a first surface inclined from the flat portion and a second surface symmetrical to the first surface. For example, the overlay layer OC can be formed by an exposure process using a gradient halftone mask, but is not limited thereto.

[0142] exist Figure 16 In this process, pixel electrodes AE can be deposited on the entire surface of the capping layer OC and can be patterned. Pixel electrodes AE can be disposed on flat portions of the capping layer OC. Each of the pixel electrodes AE of a plurality of pixels SP can be insulated from each other. Pixel electrodes AE can be transparent electrodes and can transmit light.

[0143] The reflective layer RFL can be deposited on the entire surface of the pixel electrode AE ​​and the capping layer OC and can be patterned. The reflective layer RFL can be disposed on each of the first and second surfaces of the pixel electrode AE ​​and the protrusion PRT. The reflective layer RFL may not be disposed on the topmost part of the protrusion PRT of the capping layer OC. The reflective layer RFL may comprise a metallic material with high reflectivity.

[0144] exist Figure 17 In this configuration, the emitter layer EL can be disposed on the pixel electrode AE ​​and the reflective layer RFL. A portion of the emitter layer EL can be disposed on the pixel electrode AE, while another portion of the emitter layer EL can be disposed on the reflective layer RFL. The emitter layer EL may not be divided for each pixel in a plurality of pixels SP, and may be integrally formed within all pixels SP. The emitter layer EL may or may not be cut off by the topmost part of the reflective layer RFL.

[0145] The common electrode CAT can be set on the emitter layer EL. For example, the common electrode CAT may not be divided for each pixel in the multiple pixels SP, and can be implemented as a common electrode for all pixels SP.

[0146] The TFE encapsulation layer can be disposed on the light-emitting diode (ED). The TFE encapsulation layer can be disposed on the common electrode CAT and can cover multiple light-emitting diodes (ED).

[0147] The display device 10 according to various embodiments of the present disclosure can be described as follows.

[0148] One embodiment is a display device comprising: a substrate; a transistor disposed on the substrate; a color filter disposed on the transistor; a cover layer disposed on the color filter and including a flat portion overlapping the color filter and a protrusion extending from the flat portion; a reflective layer disposed on the protrusion of the cover layer; a pixel electrode disposed on the flat portion of the cover layer; an emissive layer disposed on the pixel electrode and the reflective layer; and a common electrode disposed on the emissive layer.

[0149] The display device according to various embodiments of the present disclosure may further include a dam portion disposed on a protrusion of a pixel electrode and a cover layer and configured to define an emission region overlapping a color filter. The pixel electrode is disposed on a reflective layer, and the emission layer is disposed on the dam portion.

[0150] In the display device according to various embodiments of the present disclosure, the protrusion of the cover layer may include a first surface inclined from the flat portion and a second surface symmetrical to the first surface.

[0151] In the display device according to various embodiments of the present disclosure, a reflective layer may be disposed on each of a first surface and a second surface.

[0152] In the display device according to various embodiments of the present disclosure, the embankment may include a recess that overlaps with a protrusion of the cover layer.

[0153] In the display device according to various embodiments of the present disclosure, the protrusion of the cover layer may include a flat upper surface and a side surface inclined between the upper surface and the flat portion.

[0154] In the display device according to various embodiments of the present disclosure, a portion of the reflective layer may be disposed on the side surface of the protrusion, and the remaining portion of the reflective layer may contact the embankment.

[0155] In the display device according to various embodiments of the present disclosure, the recess, the emissive layer, and the common electrode may form a gap.

[0156] In the display device according to various embodiments of the present disclosure, a reflective layer may be disposed on a pixel electrode to define an emission area that overlaps with a color filter.

[0157] In the display device according to various embodiments of the present disclosure, the protrusions of the cover layer, the reflective layer, the emitting layer and the common electrode may form a gap.

[0158] In the display device according to various embodiments of the present disclosure, the protrusion of the cover layer may include a flat upper surface and a side surface inclined between the upper surface and the flat portion.

[0159] In the display device according to various embodiments of the present disclosure, a portion of the reflective layer may be disposed on the upper surface of the pixel electrode and the side surface of the protrusion, and the remaining portion of the reflective layer may form part of the gap.

[0160] In the display device according to various embodiments of the present disclosure, the emitting layer may be gapped.

[0161] In the display device according to various embodiments of the present disclosure, the protrusion of the cover layer may include a first surface inclined from the flat portion and a second surface symmetrical to the first surface.

[0162] In the display device according to various embodiments of the present disclosure, a reflective layer may be disposed on each of a first surface and a second surface.

[0163] In the display device according to various embodiments of the present disclosure, the emitting layer may be cut off from the uppermost part of the reflective layer.

[0164] Embodiments of this disclosure have been described with reference to the accompanying drawings. Those skilled in the art will recognize that this disclosure may be implemented in other specific forms without departing from the spirit or essential characteristics of this disclosure. The described embodiments are to be considered illustrative in all respects only and not restrictive. Therefore, the scope of this disclosure is defined by the appended claims, and not by the foregoing description. All variations falling within the meaning and scope of equivalents of the claims will be included within the scope of this disclosure.

Claims

1. A display device, comprising: substrate; A transistor is disposed on the substrate; A color filter is disposed on the transistor; A cover layer is disposed on the color filter and includes a flat portion that overlaps with the color filter and a protrusion that protrudes from the flat portion; A reflective layer is disposed on the protrusion of the cover layer; Pixel electrodes are disposed on the flat portion of the cover layer; An emitting layer is disposed on the pixel electrode and the reflective layer; as well as A common electrode is disposed on the emitter layer.

2. The display device according to claim 1, wherein, The display device further includes: A dam portion is disposed on the protrusion of the pixel electrode and the cover layer, and is configured to define an emission area that overlaps with the color filter; The pixel electrode is disposed on the reflective layer, and the emitting layer is disposed on the embankment.

3. The display device according to claim 2, wherein, The protrusion of the cover layer includes a first surface inclined from the flat portion and a second surface symmetrical to the first surface.

4. The display device according to claim 3, wherein, The reflective layer is disposed on each of the first surface and the second surface.

5. The display device according to claim 2, wherein, The embankment includes a recess that overlaps with the protrusion of the covering layer.

6. The display device according to claim 5, wherein, The protrusion of the cover layer includes a flat upper surface and a sloping side surface between the upper surface and the flat portion.

7. The display device according to claim 6, wherein, A portion of the reflective layer is disposed on the side surface of the protrusion, and the remaining portion of the reflective layer contacts the embankment.

8. The display device according to claim 5, wherein, The recess, the emission layer, and the common electrode form a gap.

9. The display device according to claim 1, wherein, The reflective layer is disposed on the pixel electrode to define an emission area that overlaps with the color filter.

10. The display device according to claim 9, wherein, The protrusion of the cover layer, the reflective layer, the emitting layer, and the common electrode form a gap.

11. The display device according to claim 9, wherein, The protrusion of the cover layer includes a flat upper surface and a sloping side surface between the upper surface and the flat portion.

12. The display device according to claim 11, wherein, A portion of the reflective layer is disposed on the upper surface of the pixel electrode and the side surface of the protrusion, and the remaining portion of the reflective layer forms part of the gap.

13. The display device according to claim 8 or 10, wherein, The emission layer is cut open by the gap.

14. The display device according to claim 9, wherein, The protrusion of the cover layer includes a first surface inclined from the flat portion and a second surface symmetrical to the first surface.

15. The display device according to claim 14, wherein, The reflective layer is disposed on each of the first surface and the second surface.

16. The display device according to claim 15, wherein, The emitting layer is cut off at the top of the reflective layer.

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