Display panel, manufacturing method of display panel, and display device

Abstract

The application relates to the technical field of display, in particular to a display panel, a manufacturing method of the display panel and a display device. The display panel comprises a substrate, a pixel definition layer, a light emitting device layer and a second electrode layer. The pixel definition layer is arranged on the side of the first electrode layer of the substrate, the pixel definition layer comprises a pixel limiting part and a pixel opening arranged in the pixel limiting part, a plurality of pixel openings are arranged at intervals, the orthogonal projection of the pixel opening on the planarization layer at least partially overlaps the orthogonal projection of the first electrode on the planarization layer, and the pixel limiting part is recessed to form an isolation groove towards the substrate. The light emitting device layer comprises a light emitting part, and the light emitting part is located in the pixel opening. The pixel limiting part comprises a first sublayer and a second sublayer arranged in a stacking mode in a direction away from the substrate, and the isolation groove is arranged in the second sublayer. When the isolation groove is etched, the first sublayer can be used as an etching endpoint stop layer to control the depth of the isolation groove and improve the use performance of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a method for manufacturing the display panel, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] This application provides a display panel, a method for manufacturing the display panel, and a display device, aiming to improve the performance of the display panel.

[0005] In a first aspect, this application provides a display panel, comprising: a substrate, including a planarization layer and a first electrode layer disposed on one side of the planarization layer, the first electrode layer including a plurality of spaced-apart first electrodes; a pixel defining layer, located on the same side of the planarization layer as the first electrode layer, the pixel defining layer including a pixel defining portion and a pixel opening formed in the pixel defining portion, the plurality of pixel openings being spaced-apart, and the orthographic projection of the pixel openings on the planarization layer at least partially overlapping the orthographic projection of the first electrodes on the planarization layer, the pixel defining portion being recessed toward the substrate to form an isolation groove; a light-emitting device layer, including a light-emitting portion located within the pixel opening; and a second electrode layer disposed on the side of the light-emitting device layer away from the substrate; wherein the pixel defining portion includes a first sub-layer and a second sub-layer stacked in a direction away from the substrate, and the isolation groove is disposed in the second sub-layer.

[0006] According to any of the foregoing embodiments of the first aspect of this application, the isolation trench is disposed through the second sublayer so that a portion of the first sublayer is exposed to the isolation trench.

[0007] According to any of the foregoing embodiments of the first aspect of this application, the material of the first sublayer includes inorganic materials; the material of the second sublayer includes organic materials.

[0008] According to any of the foregoing embodiments of the first aspect of this application, the first sublayer and the second sublayer are configured to have an etching selectivity ratio of 8:1 to 30:1 under the same etching conditions.

[0009] According to any of the foregoing embodiments of the first aspect of this application, the material of the first sublayer includes at least one of silicon nitride, silicon oxide, and aluminum oxide.

[0010] According to any of the foregoing embodiments of the first aspect of this application, the material of the first sublayer includes an inorganic material mixture layer composed of at least two of silicon nitride, silicon oxide, and aluminum oxide.

[0011] According to any of the foregoing embodiments of the first aspect of this application, the material of the first sub-layer includes a plurality of sub-parts, each sub-part including one of silicon nitride, silicon oxide and aluminum oxide, and the sub-parts are alternately stacked.

[0012] According to any of the foregoing embodiments of the first aspect of this application, an interface bonding structure is also included, wherein the first sub-layer and the second sub-layer are connected through the interface bonding structure.

[0013] According to any of the foregoing embodiments of the first aspect of this application, the interface bonding structure includes a recess and a protrusion that matches the recess, wherein the recess is located on the side of the first sublayer facing the second sublayer, and the protrusion is located on the side of the second sublayer facing the first sublayer.

[0014] According to any of the foregoing embodiments of the first aspect of this application, the light-emitting device layer further includes a redundant portion located within a partition groove.

[0015] According to any of the foregoing embodiments of the first aspect of this application, both the light-emitting part and the redundant part include a carrier layer and a light-emitting material layer.

[0016] According to any of the foregoing embodiments of the first aspect of this application, the light-emitting device layer is a single-layer light-emitting device and includes a first carrier layer, a light-emitting material layer and a second carrier layer stacked in a direction away from the substrate; or, the light-emitting device layer is a multilayer light-emitting device and includes a first carrier layer, a first light-emitting material layer, a second carrier layer, a charge-generating layer, a third carrier layer, a second light-emitting material layer and a fourth carrier layer stacked in a direction away from the substrate.

[0017] According to any of the foregoing embodiments of the first aspect of this application, along the first direction, the thickness of the first sublayer is greater than or equal to... and less than or equal to And / or, along the first direction, the thickness of the second sublayer is greater than or equal to 0.5 μm and less than or equal to 0.7 μm.

[0018] Secondly, this application provides a method for manufacturing a display panel, comprising:

[0019] A substrate is provided, the substrate including a planarization layer and a first electrode layer disposed on one side of the planarization layer;

[0020] A first submaterial layer and a second submaterial layer are sequentially formed on one side of the substrate;

[0021] A pixel opening is formed in the first sub-material layer and the second sub-material layer, penetrating the first sub-material layer and the second sub-material layer, and an isolation groove is formed in the second sub-material layer, so that the first sub-material layer and the second sub-material layer constitute a pixel definition layer;

[0022] A light-emitting device layer and a second electrode layer are formed on the side of the pixel definition layer away from the substrate.

[0023] According to any of the foregoing embodiments of the second aspect of this application, pixel openings penetrating the first and second sub-material layers are formed in the first and second sub-material layers, and an isolation groove is formed in the second sub-material layer, so that the first and second sub-material layers constitute a pixel definition layer, including:

[0024] The second sub-material layer is photolithographically etched using a mask to form a mask pattern;

[0025] Based on the mask pattern, the second sub-material layer and the first sub-material layer are sequentially etched using a dry etching process to form pixel openings.

[0026] According to any of the foregoing embodiments of the second aspect of this application, after the step of sequentially etching the second sub-material layer and the first sub-material layer using a dry etching process according to the mask pattern to form a pixel opening, the method further includes:

[0027] The second sub-material layer is patterned to form isolation grooves.

[0028] Thirdly, this application provides a display device including a display panel of any of the foregoing embodiments of the first aspect, or the display device includes a display panel formed from the display panel of any of the foregoing embodiments of the second aspect.

[0029] The display panel, manufacturing method of the display panel, and display device provided in this application include a substrate, a pixel definition layer, a light-emitting device layer, and a second electrode layer. The substrate includes a planarization layer and a first electrode layer disposed on one side of the planarization layer. The planarization layer provides a uniform and flat substrate for the first electrode layer and the pixel definition layer. The pixel definition layer includes a pixel defining portion and a pixel opening formed in the pixel defining portion. The light-emitting device layer includes a light-emitting portion located within the pixel opening. The orthographic projection of the pixel opening onto the planarization layer at least partially overlaps with the orthographic projection of the first electrode onto the planarization layer, allowing the first electrode to contact and connect with the light-emitting portion within the pixel opening. Multiple pixel openings are spaced apart and can accommodate light-emitting portions emitting different or the same color. An isolation groove is formed by recessing the pixel defining portion toward the substrate. The isolation groove isolates adjacent light-emitting portions to reduce the probability of optical crosstalk between adjacent light-emitting portions. The pixel defining portion includes a first sub-layer and a second sub-layer stacked in a direction away from the substrate. The isolation groove is disposed in the second sub-layer. The first sub-layer is located between the substrate and the second sub-layer, limiting the depth of the isolation groove. Therefore, when etching isolation trenches on the second sub-layer, the first sub-layer can act as an etching endpoint barrier layer, effectively increasing the etching process window, controlling the depth of the isolation trenches, and preventing the isolation trenches from being too deep or too shallow. This reduces the probability of cathode layer breakage or light emission crosstalk, thereby improving the performance of the display panel. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0032] Figure 2 for Figure 1 A magnified view of a section at point A in the middle;

[0033] Figure 3 A partial structural diagram of the light-emitting device layer provided in the embodiments of this application. Figure 1 ;

[0034] Figure 4 A partial structural diagram of the light-emitting device layer provided in the embodiments of this application. Figure 2 ;

[0035] Figure 5 A flowchart illustrating the method for manufacturing a display panel provided in this application embodiment. Figure 1 ;

[0036] Figure 6 A flowchart illustrating the method for manufacturing a display panel provided in this application embodiment. Figure 2 .

[0037] Explanation of reference numerals in the attached figures:

[0038] 100 - Substrate; 110 - Planarization layer; 120 - First electrode layer; 121 - First electrode;

[0039] 200 - Pixel definition layer; 200a - First sub-layer; 200b - Second sub-layer; 210 - Pixel limiting part; 220 - Pixel opening; 230 - Isolation groove;

[0040] 300 - Light-emitting device layer; 300a - Light-emitting part; 300b - Redundancy part; 311 - First carrier layer; 312 - Second carrier layer; 313 - Third carrier layer; 314 - Fourth carrier layer; 315 - Charge generation layer; 320 - Light-emitting material layer; 321 - First light-emitting material layer; 322 - Second light-emitting material layer;

[0041] 400 - Second electrode layer;

[0042] 500 - Interface bonding structure; 510 - Recessed portion; 520 - Protruding portion;

[0043] X - First direction.

[0044] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the preferred embodiments of this application will be described in more detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0046] It should be noted that in the description of the embodiments of this application, the terms "upper", "lower", "inner", "outer" and other terms indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of description, and do not indicate or imply that the device or component must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of this application.

[0047] Furthermore, it should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0048] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "fixation," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0049] In OLED structures, to address crosstalk between adjacent pixels, techniques typically involve etching isolation trench structures within the organic pixel definition layer. However, fluctuations in process parameters during etching can lead to uneven etching depth in the isolation trench structure.

[0050] When the depth is too deep, it can cause the cathode layer to break. When the depth is too shallow, it is difficult to completely isolate adjacent pixels, which can easily cause light emission crosstalk, affecting display uniformity and device reliability, thereby affecting the performance of OLED display products.

[0051] In view of the above, the display panel, the method for manufacturing the display panel, and the display device provided in this application include a substrate, a pixel definition layer, a light-emitting device layer, and a second electrode layer. The substrate includes a planarization layer and a first electrode layer disposed on one side of the planarization layer. The planarization layer provides a uniform and flat substrate for the first electrode layer and the pixel definition layer. The pixel definition layer includes a pixel defining portion and a pixel opening formed in the pixel defining portion. The light-emitting device layer includes a light-emitting portion located within the pixel opening. The orthographic projection of the pixel opening onto the planarization layer at least partially overlaps with the orthographic projection of the first electrode onto the planarization layer, allowing the first electrode to contact and connect with the light-emitting portion within the pixel opening. Multiple pixel openings are spaced apart and can accommodate light-emitting portions emitting different or the same color. The pixel defining portion is recessed towards the substrate to form an isolation groove, which isolates adjacent light-emitting portions to reduce the probability of optical crosstalk between adjacent light-emitting portions. The pixel defining portion includes a first sub-layer and a second sub-layer stacked in a direction away from the substrate, with the isolation groove disposed in the second sub-layer. The first sub-layer is located between the substrate and the second sub-layer, limiting the depth of the isolation groove. Therefore, when etching isolation trenches on the second sub-layer, the first sub-layer can act as an etching endpoint barrier layer, effectively increasing the etching process window, controlling the depth of the isolation trenches, and preventing the isolation trenches from being too deep or too shallow. This reduces the probability of cathode layer breakage or light emission crosstalk, thereby improving the performance of the display panel.

[0052] The present application will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0053] See Figure 1 This application provides a display panel, including a substrate 100, a pixel definition layer 200, a light-emitting device layer 300, and a second electrode layer 400. The substrate 100 includes a planarization layer 110 and a first electrode layer 120 disposed on one side of the planarization layer 110. The first electrode layer 120 includes a plurality of spaced-apart first electrodes 121. The pixel definition layer 200 and the first electrode layer 120 are located on the same side of the planarization layer 110. The pixel definition layer 200 includes a pixel defining portion 210 and a pixel opening 220 formed in the pixel defining portion 210. The plurality of pixel openings 220 are spaced-apart, and the orthographic projection of the pixel opening 220 onto the planarization layer 110 at least partially overlaps with the orthographic projection of the first electrode 121 onto the planarization layer 110. The pixel defining portion 210 is recessed towards the substrate 100 to form an isolation groove 230. The light-emitting device layer 300 includes a light-emitting portion 300a located within the pixel opening 220. The second electrode layer 400 is disposed on the side of the light-emitting device layer 300 facing away from the substrate 100. The pixel limiting portion 210 includes a first sub-layer 200a and a second sub-layer 200b stacked in a direction away from the substrate 100, and an isolation trench 230 is disposed in the second sub-layer 200b.

[0054] The substrate 100 serves as the supporting base for the display panel and includes a planarization layer 110 and a first electrode layer 120. The planarization layer 110 provides a uniform and flat substrate for the first electrode layer 120 and the pixel definition layer 200. The first electrode layer 120 may include a plurality of first electrodes 121 arranged at intervals.

[0055] When the orthographic projection of the pixel opening 220 on the planarization layer 110 at least partially overlaps with the orthographic projection of the first electrode 121, the effective contact area between the light-emitting part 300a and the first electrode 121 can be ensured, reducing driving voltage loss and improving the problem of light leakage or current distribution distortion caused by misalignment.

[0056] The light-emitting device layer 300 may include a light-emitting portion 300a and a redundant portion 300b. The light-emitting portion 300a is located within the pixel opening 220 and is the actual light-emitting area. The light-emitting portion 300a is typically made of organic light-emitting materials (such as red, green, and blue primary color materials). The light-emitting portion 300a drives the light-emitting material to emit light by forming an electric field with the first electrode 121 and the second electrode layer 400. In related technologies, the redundant portion 300b is deposited together with the light-emitting portion 300a on the side of the pixel definition layer 200 away from the substrate 100. Therefore, the redundant portion 300b may cause current connection between adjacent light-emitting portions 300a, forming light emission crosstalk. In this embodiment, the redundant portion 300b is located within the isolation trench 230. By setting the isolation trench 230, the redundant portion 300b and the light-emitting portion 300a can be effectively isolated, reducing the probability of crosstalk between adjacent light-emitting portions 300a.

[0057] The second electrode layer 400 and the first electrode layer 120 together form a path for the driving current. The second electrode layer 400 can uniformly cover the entire display panel and ensure good contact with the light-emitting device layer 300; that is, the second electrode layer 400 can be a surface electrode. One of the first electrode layer 120 and the second electrode layer 400 is an anode, and the other is a cathode. For example, the first electrode layer 120 can be an anode, and the second electrode layer 400 can be a cathode, so that the first electrode 121 of the first electrode layer 120 and the second electrode layer 400 can interact to drive the light-emitting part 300a to emit light.

[0058] It should be noted that the pixel definition layer 200 may include a first sub-layer 200a and a second sub-layer 200b, with the first sub-layer 200a located between the substrate 100 and the second sub-layer 200b. Optionally, the difference in physical or chemical properties between the first sub-layer 200a and the second sub-layer 200b can be used to limit the etching depth of the isolation trench 230, thereby increasing the etching process window. For example, increasing the etching process window can be understood as enabling the etching process to achieve the expected etching effect within the allowable fluctuation range of parameters (such as etching gas flow rate, RF power, time, temperature, etc.), reducing the dependence on the consistency of process conditions.

[0059] The first sublayer 200a can act as an etching barrier layer, effectively blocking the etching process of the isolation trench 230. The isolation trench 230 is formed within the second sublayer 200b through an etching process and is recessed towards the substrate 100. The first sublayer 200a acts as a physical barrier. Optionally, the first sublayer 200a can be made of a material with a higher etching selectivity than the second sublayer 200b. Utilizing the difference in etching rates between the first sublayer 200a and the second sublayer 200b under the same etching environment, the etching process terminates on the surface of the first sublayer 200a after penetrating the second sublayer 200b. Even if the etching time is slightly prolonged due to process fluctuations, the first sublayer 200a can still maintain its integrity, reducing the probability of over-etching the isolation trench 230 causing breakage of the second electrode layer 400 or damage to the substrate 100.

[0060] Furthermore, due to the difference in etching rates between the first sublayer 200a and the second sublayer 200b under the same etching environment, the etching process can terminate at the surface of the first sublayer 200a after penetrating the second sublayer 200b. Thus, etching can be stopped after penetrating the second sublayer 200b, thereby improving the situation where the isolation trench 230 is too shallow, causing adjacent light-emitting parts 300a to be connected through redundant parts 300b, thereby increasing the probability of light emission crosstalk and reducing display uniformity and device reliability.

[0061] Therefore, when etching the isolation trench 230 on the second sub-layer 200b, the first sub-layer 200a can serve as an etching endpoint barrier layer, effectively increasing the etching process window, controlling the depth of the isolation trench 230, and improving the performance of the display panel.

[0062] In some alternative embodiments, the isolation groove 230 may be a recess in the second sublayer 200b, the isolation groove 230 being formed by a recess in the surface of the second sublayer 200b away from the substrate, the bottom wall of the isolation groove 230 being spaced apart from the first sublayer 200a, and the second sublayer 200b completely covering the first sublayer 200a.

[0063] See Figure 1 In some embodiments, the isolation trench 230 is disposed through the second sublayer 200b so that a portion of the first sublayer 200a is exposed to the isolation trench 230.

[0064] Understandably, after the isolation trench 230 penetrates the second sub-layer 200b, an etch barrier interface is formed in the exposed area of ​​the first sub-layer 200a. Due to the difference in etching rates between the first sub-layer 200a and the second sub-layer 200b under the same etching environment, the reaction rate decreases when the etchant contacts the first sub-layer 200a, thereby precisely controlling the depth of the isolation trench 230. This design effectively reduces the risk of excessive etching caused by fluctuations in the etching process (such as etching gas flow rate, RF power, time, temperature, etc.), lowers the precision requirements of the etching process, and prevents insufficient etching depth, effectively reducing the probability of electrical connection between the redundant part 300b and the light-emitting part 300a. Therefore, it reduces the precision requirements of the etching equipment and ensures etching uniformity.

[0065] In some embodiments, the material of the first sublayer 200a comprises an inorganic material. The material of the second sublayer 200b comprises an organic material.

[0066] In these alternative embodiments, to achieve the blocking effect of the first sublayer 200a, the first sublayer 200a can be made of inorganic materials, and the second sublayer 200b can be made of organic materials. By utilizing the differences in physicochemical properties between inorganic and organic materials, a stacked structure with a large etching selectivity is formed. In the etching process of the isolation trench 230, when an etchant with a high etching rate for organic materials is used, the organic material of the second sublayer 200b can be efficiently removed. The inorganic material of the first sublayer 200a, however, exhibits lower reactivity to the same etchant, causing the etching process to slow down after penetrating the second sublayer 200b. The inorganic first sublayer 200a, acting as an etching barrier layer, can terminate the etching process, thereby limiting the depth of the isolation trench 230 to within the thickness range of the second sublayer 200b. Even if the etching process parameters fluctuate beyond the preset value, the inorganic material of the first sublayer 200a can still maintain its structural integrity, improve the excessive etching extension to the substrate 100, and prevent the cathode breakage problem caused by the excessive depth of the isolation trench 230.

[0067] In some embodiments, the first sublayer 200a and the second sublayer 200b are configured to have an etching selectivity ratio of 8:1 to 30:1 under the same etching conditions. For example, the first sublayer 200a and the second sublayer 200b are configured to have an etching selectivity ratio of 8:1, 9:1, 12:1, 15:1, or 20:1 under the same etching conditions.

[0068] In other words, the etching selectivity ratio of the inorganic material included in the first sublayer 200a and the organic material included in the second sublayer 200b can be set to any value within the range of 8:1 to 30:1, including the two extreme values ​​of 8:1 and 30:1. This ensures that the second sublayer 200b is efficiently etched to form the isolation trench 230, while also ensuring the blocking effect of the first sublayer 200a.

[0069] If the etching selectivity ratio is set to less than 8:1, such as 6:1, the etching efficiency of the first sublayer 200a is relatively high, which may not effectively prevent etching depth deviations caused by process fluctuations. When the etching selectivity ratio is set to greater than 30:1, such as 32:1, the material selectivity of the first sublayer 200a and the second sublayer 200b will be reduced, thus affecting compatibility and flexibility.

[0070] In some embodiments, the material of the first sublayer 200a includes at least one of silicon nitride, silicon oxide, and aluminum oxide.

[0071] Optionally, the material of the first sublayer 200a may include silicon nitride. During etching, the dense atomic structure of silicon nitride results in a low reaction rate to etching gases, thus acting as a barrier. As the etching depth approaches the silicon nitride layer, the etching rate decreases, effectively reducing the probability of over-etching the pixel definition layer 200 and ensuring depth control of the isolation trench 230.

[0072] It should also be noted that the material of the first sublayer 200a may also include silicon oxide. In the etching process, the etching rate of silicon oxide is lower than that of organic materials, allowing silicon oxide to act as a barrier layer, terminating the etching process after the organic materials are removed.

[0073] Furthermore, the material of the first sub-layer 200a may also include alumina. Alumina enhances the barrier effect through its high melting point and corrosion resistance, preventing over-etching due to process fluctuations. In addition, the lattice structure of alumina has a weak adsorption capacity for etchant molecules, further reducing the probability of over-etching of the pixel definition layer 200 when etching the isolation trench 230.

[0074] In some embodiments, the material of the first sublayer 200a includes an inorganic material mixture layer composed of at least two of silicon nitride, silicon oxide, and aluminum oxide.

[0075] It is understood that the material of the first sublayer 200a may include a mixed layer of inorganic materials of silicon nitride and silicon oxide, or a mixed layer of inorganic materials of aluminum oxide and silicon nitride or silicon oxide, or a mixed layer of inorganic materials of aluminum oxide, silicon nitride and silicon oxide.

[0076] Optionally, when silicon nitride and silicon oxide are mixed, the high hardness of silicon nitride can enhance the mechanical strength of the inorganic material mixture layer, while silicon oxide can enhance the corrosion resistance of the inorganic material mixture layer to etchants through its good insulation and chemical stability.

[0077] When alumina is mixed with silicon nitride or silicon oxide, the high melting point of alumina can improve the thermal stability of the inorganic material mixture layer. Simultaneously, the corrosion resistance of alumina can further enhance the tolerance of the inorganic material mixture layer to etching environments.

[0078] It should be noted that the physicochemical properties of the inorganic material mixture layer can be flexibly adjusted by regulating the proportions of each component, thereby meeting the requirements for etching selectivity.

[0079] In some embodiments, the material of the first sublayer 200a includes a plurality of sub-parts, each sub-part including one of silicon nitride, silicon oxide and aluminum oxide, and the sub-parts are stacked alternately.

[0080] It is understood that the first sublayer 200a may include a silicon nitride sublayer and a silicon oxide sublayer stacked together, or it may include an alumina sublayer and a silicon nitride sublayer or a silicon oxide sublayer stacked together, or it may include a silicon nitride sublayer, a silicon oxide sublayer and an alumina sublayer stacked together.

[0081] The sub-layers are stacked alternately, and the first sub-layer 200a is formed by periodic repetition or asymmetrical combination. This arrangement allows for flexible adjustment of the performance of the first sub-layer 200a, such as etching selectivity and stress distribution, to meet barrier requirements.

[0082] In the etching process, when the etchant penetrates the second sublayer 200b and contacts the first sublayer 200a, the interface between each sublayer can increase the tortuosity of the etching path through a physical blocking effect. For example, after penetrating the silicon nitride sublayer, the etchant needs to readjust its reaction direction to attack the silicon oxide sublayer. This process consumes the energy of the etching active species, thereby reducing the etching rate, so as to achieve the etching blocking effect of the first sublayer 200a and effectively prevent the isolation trench 230 from being too deep.

[0083] In addition, the alternating stacking design of each sub-component can optimize the interlayer stress distribution and reduce the risk of warping or peeling due to differences in thermal expansion coefficients.

[0084] See Figure 2 In some embodiments, an interface bonding structure 500 may also be included, through which the first sub-layer 200a and the second sub-layer 200b are connected.

[0085] Understandably, by setting the interface and combining structure 500, the interlayer bonding force between the first sub-layer 200a and the second sub-layer 200b can be increased. This prevents peeling between the first sub-layer 200a and the second sub-layer 200b during etching. Furthermore, by setting the interface and combining structure 500, the probability of warping between the first sub-layer 200a and the second sub-layer 200b can be effectively reduced, thereby ensuring the structural stability of the pixel definition layer 200.

[0086] In some embodiments, the interface bonding structure 500 includes a recess 510 and a protrusion 520 that matches the recess 510. The recess 510 is located on the side of the first sublayer 200a facing the second sublayer 200b, and the protrusion 520 is located on the side of the second sublayer 200b facing the first sublayer 200a.

[0087] Optionally, to enhance the stability and reliability of the interface bonding, the interface bonding structure 500 may include a recessed portion 510 and a protruding portion 520. The recessed portion 510 may be disposed on the side of the first sub-layer 200a facing the second sub-layer 200b.

[0088] Corresponding to the recessed portion 510, the protrusion 520 may be provided on the side of the second sublayer 200b facing the first sublayer 200a. When the protrusion 520 is embedded in the recessed portion 510, it can effectively prevent the first sublayer from peeling off from the second sublayer 200b in the direction perpendicular to the interface and in the direction parallel to the interface, thereby improving the strength and stability of the interface bonding.

[0089] In practice, reactive ion etching or plasma etching techniques can be used to selectively remove part of the first sublayer 200a material to form the recess 510. Then, a second sublayer 200b is deposited. During the deposition process, the side of the second sublayer 200b facing the first sublayer 200a will fill the recess 510 to form the recess 510.

[0090] See Figure 1 , Figure 3 and Figure 4 In some embodiments, both the light-emitting part 300a and the redundant part 300b include a carrier layer and a light-emitting material layer 320.

[0091] It should be noted that the charge carrier layer is used for charge transport and can effectively promote the directional transport of charge carriers within the light-emitting section 300a. For example, by selecting a material with high electron mobility to form the electron transport layer, the injection of electrons from the second electrode layer 400 to the light-emitting material layer 320 can be accelerated. By using a material with high hole mobility to form the hole transport layer, it is possible to ensure that holes migrate efficiently from the first electrode 121 to the light-emitting material layer 320. The light-emitting material layer 320 is made of a light-emitting material, which, after being excited by charge carrier injection and recombination, can generate photons and emit visible light.

[0092] In the light-emitting part 300a, the carrier layer and the light-emitting material layer 320 work together. Under the action of the carrier layer, the carriers are efficiently injected into the light-emitting material layer 320 and undergo radiative recombination within the light-emitting material layer 320, releasing photons and realizing the light-emitting function, thereby providing a clear and vivid image display for the display panel.

[0093] See Figure 3 In some embodiments, the light-emitting device layer 300 is a single-layer light-emitting device and includes a first carrier layer 311, a light-emitting material layer 320, and a second carrier layer 312 stacked in a direction away from the substrate 100. Alternatively, as... Figure 4 As shown, the light-emitting device layer 300 is a stacked light-emitting device and includes a first carrier layer 311, a first light-emitting material layer 321, a second carrier layer 312, a charge generation layer 315, a third carrier layer 313, a second light-emitting material layer 322 and a fourth carrier layer 314 stacked in a direction away from the substrate 100.

[0094] Optionally, the light-emitting device layer 300 is a single-layer light-emitting device. The first carrier layer 311 may include a hole injection layer, a hole transport layer, and an electron blocking layer. The first carrier layer 311 is used to transport carriers injected from the first electrode 121 and guide the carriers to the light-emitting material layer 320. The light-emitting material layer 320 is made of a material capable of emitting light of a specific wavelength when carriers recombine. By selecting different light-emitting materials, the emission color can be controlled to meet display requirements. The second carrier layer 312 may include a hole blocking layer, an electron transport layer, and an electron injection layer. The second carrier layer is used to transport carriers injected from the second electrode layer 400 to ensure effective recombination of carriers in the light-emitting material layer 320, thereby achieving efficient light emission of the light-emitting part 300a.

[0095] Furthermore, the light-emitting device layer 300 can also be a stacked light-emitting device. The first carrier layer 311 and the third carrier layer 313 can each include a hole injection layer, a hole transport layer, and an electron blocking layer. The second carrier layer 312 and the fourth carrier layer 314 can each include a hole blocking layer, an electron transport layer, and an electron injection layer. The charge generation layer 315 can generate new carriers under the action of an applied electric field, providing carrier injection for the light-emitting part 300a. By providing the charge generation layer 315, the stacked light-emitting device can achieve series emission of multiple light-emitting units at a lower driving voltage, thereby improving brightness and luminous efficiency. In addition, the charge generation layer 315 can also block the reverse transport of carriers, reducing carrier leakage and improving the stability of the light-emitting device layer 300.

[0096] In some embodiments, along the first direction X, the thickness of the first sublayer 200a is greater than or equal to and less than or equal to

[0097] It should be noted that the thickness of the first sub-layer 200a can be set to... to Within the scope, including These two endpoints. This setting ensures the blocking effect of the first sublayer 200a without excessively increasing film formation time and material consumption, thus helping to save production capacity and reduce production costs.

[0098] If the thickness of the first sublayer 200a is set to be less than For example When this happens, it will affect the film uniformity of the first sublayer 200a, and defects such as pinholes and cracks are likely to occur, reducing the reliability and stability of the first sublayer 200a.

[0099] If the thickness of the first sublayer 200a is set to be greater than For example If this is the case, a longer film-forming time is required to form the first sublayer 200a, which will not only reduce production efficiency but also waste production capacity.

[0100] In other embodiments, the thickness of the second sublayer 200b along the first direction X is greater than or equal to 0.5 μm and less than or equal to 0.7 μm.

[0101] Optionally, the thickness of the second sub-layer 200b can be set within the range of 0.5μm to 0.7μm, including both 0.5μm and 0.7μm. Therefore, since the isolation groove 230 penetrates the second sub-layer 200b, the depth of the isolation groove 230 can be controlled within the range of 0.5μm to 0.7μm, thereby effectively mitigating the adverse effects of an excessively deep or shallow isolation groove 230 on the performance of the display panel.

[0102] If the thickness of the second sublayer 200b is set to less than 0.5μm, such as 0.3μm, the depth of the isolation groove 230 will be too shallow. If the depth of the isolation groove 230 is too shallow, it will be difficult to disconnect the redundant part 300b from the light-emitting part 300a, resulting in adhesion between the redundant part 300b and the light-emitting part 300a, which will increase the probability of light emission crosstalk.

[0103] If the thickness of the second sub-layer 200b is set to be greater than 0.7μm, such as 0.9μm, the depth of the isolation trench 230 will be too deep. If the depth of the isolation trench 230 is too deep, the second electrode layer 400 may break at the isolation trench 230, thereby affecting the reliability and stability of the display panel.

[0104] See Figure 5 and Figure 6 Based on the above embodiments, this application provides a method for manufacturing a display panel, which can be referred to in conjunction with the above embodiments. Figures 5 to 6 The manufacturing methods for the display panel include:

[0105] S101: A substrate 100 is provided, the substrate 100 including a planarization layer 110 and a first electrode layer 120 disposed on one side of the planarization layer 110.

[0106] The planarization layer 110 is typically made of organic insulating material, which effectively prevents electrical short circuits between different functional layers in subsequent processes. To fabricate the planarization layer 110, a spin coating process is first used to coat the substrate. By controlling the spin coating speed and time, a film of uniform thickness is formed. Subsequently, the film is baked to cure and solidify, resulting in a planarization layer 110 with a smooth surface.

[0107] The first electrode layer 120 is disposed on one side of the planarization layer 110. The first electrode layer 120 can be made of a transparent conductive material. A uniform thin film is deposited on the surface of the planarization layer 110 by physical vapor deposition, and then patterned into the desired shape by photolithography, etching and other processes to obtain the first electrode layer 120.

[0108] S102: A first submaterial layer and a second submaterial layer are sequentially formed on one side of the substrate 100.

[0109] A first submaterial layer may be formed on one side of the substrate 100. The first submaterial layer may include an inorganic material, such as at least one of silicon nitride, silicon oxide, and aluminum oxide. A chemical vapor deposition method may be used to deposit and form a uniform and dense first submaterial layer on the surface of the substrate 100. After the first submaterial layer is formed, a second submaterial layer may be prepared. The second submaterial layer may include an organic material.

[0110] S103: A pixel opening 220 is formed through the first sub-material layer and the second sub-material layer, and an isolation groove 230 is formed in the second sub-material layer, so that the first sub-material layer and the second sub-material layer constitute a pixel definition layer 200.

[0111] Optionally, photoresist can be uniformly coated on the surface of the second sub-material layer first, and then exposed through a mask to cause a chemical reaction in the photoresist. After development, a pattern corresponding to the pixel opening 220 is formed on the photoresist. Then, the second sub-material layer and the first sub-material layer are etched to form the pixel opening 220 that penetrates the second sub-material layer and the first sub-material layer, so that the first electrode 121 can be exposed to the pixel opening 220.

[0112] Then, an isolation trench 230 can be formed on the second sub-material layer. Optionally, the position and shape of the isolation trench 230 can be defined using a photolithography process, and then the second sub-material layer can be selectively etched to form the isolation trench 230. The function of the isolation trench 230 is to separate adjacent light-emitting parts 300a, preventing adjacent light-emitting parts 300a from sticking together through redundant parts 300b, thereby increasing the probability of light emission crosstalk.

[0113] Understandably, the first sub-material layer and the second sub-material layer together constitute the pixel definition layer 200, providing a basis for the deposition of the light-emitting device layer 300.

[0114] S104: A light-emitting device layer 300 and a second electrode layer 400 are formed on the side of the pixel definition layer 200 away from the substrate 100.

[0115] Optionally, the light-emitting device layer 300 can be formed by vacuum evaporation. Organic light-emitting materials, such as red, green, and blue primary color light-emitting materials, are placed in different evaporation sources. By controlling the temperature and evaporation rate of the evaporation sources, the organic materials are deposited on the first electrode layer 120 exposed by the pixel definition layer 200 (corresponding to the pixel opening 220 position), forming a uniformly thick and patterned light-emitting part 300a.

[0116] After the light-emitting device layer 300 is fabricated, a second electrode layer 400 can be deposited on the surface of the light-emitting device layer 300 by means of vacuum evaporation or sputtering to ensure that electrons can be injected into the light-emitting device layer 300.

[0117] See Figure 6 In some embodiments, step S103 may include:

[0118] S1031: Photolithography is performed on the second sub-material layer using a mask to form a mask pattern.

[0119] It should be noted that photoresist is first uniformly coated onto the surface of the second sub-material layer. Then, a mask with a specific pattern is aligned and placed above the second sub-material layer coated with photoresist. The pattern on the mask corresponds to the position and shape of the pixel opening 220.

[0120] Then, the photomask and photoresist are exposed using a light source. After exposure, a development process is performed. Through selective dissolution with the developer, the exposed or unexposed areas of the photoresist are removed, thereby forming a photomask pattern consistent with the photomask pattern on the surface of the second submaterial layer.

[0121] S1032: Based on the mask pattern, the second sub-material layer and the first sub-material layer are sequentially etched using a dry etching process to form the pixel opening 220.

[0122] Based on the mask pattern, the second sub-material layer and the first sub-material layer can be etched using a dry etching process to form the pixel opening 220.

[0123] Dry etching can employ reactive ion etching or plasma etching techniques. A substrate 100 with a mask pattern is placed in a reaction chamber, and an etching gas is introduced into the chamber. It is understood that the type of etching gas can be selected based on the material properties of the first and second sub-material layers; this application does not impose any limitations on this selection. By controlling parameters such as the type of etching gas, its flow rate, chamber pressure, RF power, and etching time, the etching process is ensured to proceed along the contour of the mask pattern, and the etching depth is sufficient to penetrate both the second and first sub-material layers.

[0124] It should be noted that the first sub-material layer can include inorganic materials, and the second sub-material layer can include organic materials. The first and second sub-material layers can utilize the same photomask. A mask pattern is formed on the second sub-material layer, and then dry etching is performed on both layers. After the etching depth penetrates the second sub-material layer, the area of ​​the first sub-material layer exposed to the second sub-material layer can be etched by the corresponding etching gas to form pixel openings 220. The area of ​​the second sub-material layer covering the first sub-material layer can act as an etching barrier layer to prevent mis-etching. Therefore, a single photomask is sufficient for both the first and second sub-material layers, eliminating the need for additional photolithography processes, simplifying the process flow, improving alignment accuracy, and thus enhancing process stability.

[0125] Furthermore, when forming the isolation trench 230, the outline of the isolation trench 230 can be formed on the second sub-material layer using photolithography. Then, the etching gas can be selected according to the material properties of the second sub-material layer using dry etching to etch the second sub-material layer, thereby forming the isolation trench 230 that penetrates the second sub-material layer. The first sub-material layer can serve as an etching barrier layer for the isolation trench 230 to prevent over-etching and improve etching uniformity.

[0126] It is understood that the order of etching pixel openings 220 and etching isolation trenches 230 is not limited and can be set according to actual needs. This application does not impose any restrictions on this.

[0127] In these alternative embodiments, after step S1032, a patterning process may be performed on the second sub-material layer to form the isolation trench 230. That is, the pixel opening 220 may be etched first, and then the isolation trench 230 may be etched.

[0128] It should also be noted that during the etching of the isolation tank 230, the concentration of etching byproducts can be monitored in real time to track the etching progress. For example, if the byproduct concentration is detected to be increasing, it can be interpreted as continuous etching with increased byproduct release. If the byproduct concentration is detected to be decreasing, it can be interpreted as the etching process approaching its end, with reduced byproduct formation. This facilitates monitoring of the etching process, allowing for control over the etching endpoint and ensuring product quality. Furthermore, if the etching byproduct concentration is detected to be below the target concentration, the etching gas flow rate can be increased to improve the etching rate. Therefore, flexibly adjusting etching parameters according to the etching progress can improve process efficiency.

[0129] Based on the above embodiments, this application provides a display device including the display panel of any of the above embodiments.

[0130] The specific details of the display panel have been described in detail in the above embodiments and will not be repeated here. The display device may include devices with display functions such as mobile phones, computers, tablets, and televisions, and this application does not limit them.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, include: The substrate includes a planarization layer and a first electrode layer disposed on one side of the planarization layer, wherein the first electrode layer includes a plurality of first electrodes disposed at intervals. A pixel definition layer is located on the same side of the planarization layer as the first electrode layer. The pixel definition layer includes a pixel defining portion and a pixel opening formed in the pixel defining portion. A plurality of pixel openings are spaced apart, and the orthographic projection of the pixel openings on the planarization layer at least partially overlaps with the orthographic projection of the first electrode on the planarization layer. The pixel defining portion is recessed toward the substrate to form an isolation groove. A light-emitting device layer includes a light-emitting portion, the light-emitting portion being located within the pixel opening; The second electrode layer is disposed on the side of the light-emitting device layer opposite to the substrate; The pixel defining portion includes a first sub-layer and a second sub-layer stacked in a direction away from the substrate, and the isolation trench is disposed in the second sub-layer.

2. The display panel according to claim 1, characterized in that, The isolation trench extends through the second sublayer, thereby exposing a portion of the first sublayer to the isolation trench.

3. The display panel according to claim 1, characterized in that, The material of the first sublayer includes inorganic materials; The material of the second sublayer includes organic materials; Preferably, the first sublayer and the second sublayer are configured to have an etching selectivity ratio of 8:1 to 30:1 under the same etching conditions.

4. The display panel according to claim 3, characterized in that, The material of the first sublayer includes at least one of silicon nitride, silicon oxide, and aluminum oxide; Preferably, the material of the first sublayer comprises an inorganic material mixture layer composed of at least two of silicon nitride, silicon oxide, and aluminum oxide; Preferably, the material of the first sub-layer includes a plurality of sub-parts, each of which includes one of silicon nitride, silicon oxide, and aluminum oxide, and the sub-parts are stacked alternately.

5. The display panel according to any one of claims 1 to 4, characterized in that, It also includes an interface bonding structure, through which the first sub-layer and the second sub-layer are connected; Preferably, the interface bonding structure includes a recess and a protrusion that matches the recess, the recess being located on the side of the first sublayer facing the second sublayer, and the protrusion being located on the side of the second sublayer facing the first sublayer.

6. The display panel according to any one of claims 1 to 4, characterized in that, The light-emitting device layer also includes a redundant portion, which is located within the isolation groove; Preferably, both the light-emitting part and the redundant part include a carrier layer and a light-emitting material layer; Preferably, the light-emitting device layer is a single-layer light-emitting device and includes a first carrier layer, the light-emitting material layer and a second carrier layer stacked in a direction away from the substrate; Alternatively, the light-emitting device layer is a stacked light-emitting device and includes a first carrier layer, a first light-emitting material layer, a second carrier layer, a charge-generating layer, a third carrier layer, a second light-emitting material layer, and a fourth carrier layer stacked in a direction away from the substrate.

7. The display panel according to any one of claims 1 to 4, characterized in that, Along the first direction, the thickness of the first sublayer is greater than or equal to and less than or equal to And / or, along the first direction, the thickness of the second sublayer is greater than or equal to 0.5 μm and less than or equal to 0.7 μm.

8. A method for manufacturing a display panel, characterized in that, include: A substrate is provided, the substrate including a planarization layer and a first electrode layer disposed on one side of the planarization layer; A first sub-material layer and a second sub-material layer are sequentially formed on one side of the substrate; A pixel opening is formed in the first sub-material layer and the second sub-material layer, penetrating the first sub-material layer and the second sub-material layer, and an isolation groove is formed in the second sub-material layer, so that the first sub-material layer and the second sub-material layer constitute a pixel definition layer. A light-emitting device layer and a second electrode layer are formed on the side of the pixel definition layer opposite to the substrate.

9. The manufacturing method according to claim 8, characterized in that, The step of forming pixel openings penetrating the first and second sub-material layers and forming isolation grooves in the second sub-material layer, so that the first and second sub-material layers constitute a pixel definition layer, includes: The second sub-material layer is photolithographically etched using a mask to form a mask pattern; According to the mask pattern, the second sub-material layer and the first sub-material layer are sequentially etched using a dry etching process to form the pixel opening; Preferably, after the step of sequentially etching the second sub-material layer and the first sub-material layer using a dry etching process according to the mask pattern to form the pixel opening, the method further includes: The second sub-material layer is patterned to form the isolation groove.

10. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1 to 7, or the display device includes a display panel formed by any one of claims 8 or 9.

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