Display device

Abstract

Disclosed is a display device including: a substrate; an anode electrode formed on the substrate and patterned to correspond to a plurality of pixels; a bank formed on the substrate and exposing at least one area of the anode electrode; a light emitting layer formed on the anode electrode; a cathode electrode formed on the light emitting layer; and a metal cup structure layer disposed on the bank, a metal cup hole can be formed between two metal cup structure layers spaced apart from each other on the bank.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0056064, filed on April 29, 2025, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates to display devices. Background Technology

[0004] With the advancement of information-oriented society, the demand for various types of display devices for displaying images is increasing, and various types of display devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light-emitting diode displays (OLEDs) are already in use.

[0005] The organic light-emitting display device includes pixels, each pixel being formed by an organic light-emitting element and a control circuit configured to control the amount of current applied to the organic light-emitting element. An anode electrode, a light-emitting layer, and a cathode electrode are stacked within the organic light-emitting element. Such organic light-emitting elements are susceptible to external penetration such as moisture or oxygen, therefore, a problem exists where the organic light-emitting element may be easily damaged if external contaminants are not effectively blocked.

[0006] Recently, there has been a need for a display device that is implemented in an ultra-thin package and has high resolution and display quality. When display devices are miniaturized and their resolution is increased at the same time, electrical short circuits or current leakage may occur between adjacent pixels. Summary of the Invention

[0007] One embodiment provides a display device that uses an undercut metal cup structure layer to block the path of moisture or oxygen intrusion.

[0008] One embodiment provides a display device in which a metal cup hole is defined by a barrier layer and at least two metal cup structure layers, the barrier layer being a non-conductive inorganic layer formed on a barrier, and the at least two metal cup structure layers being spaced apart from each other on the barrier layer.

[0009] One embodiment provides a display device in which the cathode electrode is configured to receive a low-potential driving voltage through a metal cup structure layer.

[0010] One embodiment provides a display device in which a metal cup hole is formed by connecting electrodes and at least two metal cup structure layers, the connecting electrodes being formed on the same layer as the anode electrode, and the at least two metal cup structure layers being spaced apart from each other on a partition.

[0011] One embodiment provides a display device in which a metal cup structure layer is connected to a connecting electrode through a contact hole formed in a partition, and a cathode electrode is configured to receive a low-potential driving voltage through the metal cup structure layer and the connecting electrode.

[0012] One embodiment provides a display device that prevents moisture or oxygen from entering the light-emitting element by trapping moisture or oxygen within a metal cup hole.

[0013] One embodiment is a display device, comprising: a substrate; an anode electrode formed on the substrate and patterned to correspond to a plurality of pixels; a partition formed on the substrate and exposing at least one region of the anode electrode; a light-emitting layer formed on the anode electrode; a cathode electrode formed on the light-emitting layer; and a metal cup structure layer disposed on the partition.

[0014] Metal cup holes can be formed between two metal cup structural layers that are spaced apart on the dike.

[0015] The barrier layer can be formed in the form of a grid between two metal cup structure layers to surround each of the multiple pixels.

[0016] The display device may also include a barrier layer formed on the barrier and made of a non-conductive inorganic material.

[0017] The two metal cup structure layers can be formed to cover one area and the other area of ​​the barrier layer, respectively.

[0018] The metal cup aperture can be surrounded by a barrier layer and two metal cup structural layers.

[0019] The display device may also include spacers formed on a metal cup structure layer.

[0020] The spacer can extend from the upper surface of the metal cup structure layer to the upper surface of the dike.

[0021] The spacer can extend further from the upper surface of the dike to cover the side surface of the dike and the edge of the anode electrode.

[0022] The spacer can be further disposed between the spacer and the anode electrode, and formed as the upper surface of the circuit element layer that is not covered by the spacer and is exposed.

[0023] The metal cup structure layer can be electrically connected to a low potential driving voltage, and the cathode electrode can be formed such that at least one region of it is in contact with the metal cup structure layer in the metal cup hole.

[0024] The display device may also include connection electrodes formed on a substrate, and the metal cup structure layer may be electrically connected to the connection electrodes through contact holes formed in the partition.

[0025] The connecting electrode can be electrically connected to a low potential driving voltage, and the cathode electrode can be formed such that at least one region of it is in contact with the metal cup structure layer in the metal cup hole.

[0026] The display device may include a low-potential drive voltage line in the form of a shortening bar formed on one side of the substrate, and the metal cup structure layer or connecting electrode may be electrically connected to the low-potential drive voltage line in the form of a shortening bar on one side of the substrate.

[0027] The metal cup structure layer may include a lower layer formed on the dike and an upper layer formed on the lower layer, wherein the lower surface of the upper layer may protrude more outward than the upper surface of the lower layer, and the lower and upper layers may be formed of conductive inorganic materials.

[0028] The luminescent layer can extend into the metal cup hole and can be cut off around the edge of the upper layer.

[0029] The cathode electrode can extend into the metal cup hole and can be formed to contact at least one region of the upper and lower layers in the metal cup hole.

[0030] Another embodiment is a display device, comprising: a substrate having a plurality of pixels; a partition formed on the substrate and configured to define the plurality of pixels; and a metal cup structure layer disposed on the partition.

[0031] Metal cup holes can be formed between two adjacent metal cup structural layers on the dike.

[0032] The display device may also include a barrier layer formed on a partition, the barrier layer being formed in a grid pattern to surround each of the plurality of pixels, and two adjacent metal cup structure layers being formed to cover one area and the other area of ​​the barrier layer, respectively.

[0033] The metal cup aperture can be surrounded by a barrier layer and two adjacent metal cup structural layers.

[0034] The display device may also include connection electrodes formed on a substrate, and the metal cup structure layer may be electrically connected to the connection electrodes through contact holes formed in the partition.

[0035] The display device may also include spacers formed on the metal cup structure layer, the spacers extending from the upper surface of the metal cup structure layer to the upper surface of the partition.

[0036] The spacer can extend further from the upper surface of the barrier to the side surface of the barrier, and can be formed as the upper surface of the circuit element layer that is not covered by the barrier and is exposed.

[0037] According to the embodiment, the display device can prevent the light-emitting element from being damaged by moisture or oxygen intruding from the outside through the metal cup hole formed by the metal cup structure layer.

[0038] The display device according to the embodiment can prevent IR drop of the low potential driving voltage applied to the cathode electrode by increasing the surface contact between the metal cup structure layer and the cathode electrode, and improve device reliability and brightness deviation between pixels.

[0039] According to the embodiment, the display device can prevent leakage current on the side surfaces between adjacent pixel columns by providing a barrier layer and a metal cup structure layer between adjacent pixel columns. Attached Figure Description

[0040] Figure 1 This is a block diagram illustrating the structure of a display device according to an embodiment.

[0041] Figure 2 This is a circuit diagram of the pixel according to the implementation method.

[0042] Figure 3 This is a schematic plan view of the display panel according to the first embodiment.

[0043] Figure 4 It is along Figure 3 The implementation of the cross-sectional view taken by the I-I' line shown.

[0044] Figure 5 It is along Figure 3 Another embodiment of the cross-sectional view taken by the I-I' line shown.

[0045] Figure 6 This is a schematic plan view of the display panel according to the second embodiment.

[0046] Figure 7 It is along Figure 6 The embodiment of the cross-sectional view taken by line II-II' shown.

[0047] Figure 8 This is a schematic plan view of the display panel according to the third embodiment.

[0048] Figure 9 It is along Figure 8 The implementation of the cross-sectional view taken by line III-III' shown.

[0049] Figures 10A to 10F Show Figure 9 The manufacturing method of the display panel shown.

[0050] Figure 11 The electrical connection relationship of the low-potential drive voltage line according to the embodiment is shown. Detailed Implementation

[0051] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings. In this specification, when a component (or region, layer, portion, etc.) is referred to as "on another component," "connected to another component," or "combined to another component," it means that the component may be directly on another component, connected to another component, or combined to another component, or a third component may be present between them.

[0052] The same reference numerals denote the same elements. Additionally, in the drawings, for the purpose of effective description, the thickness, scale, and dimensions of the parts are exaggerated. "And / or" includes all of one or more combinations defined by the relevant parts.

[0053] It should be understood that when the terms “first” and “second” are used herein to describe various components, those components should not be limited by these terms. The terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component without departing from the scope of this disclosure, and vice versa. Unless the context clearly indicates otherwise, the singular expressions and terms used herein also cover or include plural expressions and terms.

[0054] Furthermore, terms such as “lower,” “lower side,” “upper,” and “upper side” are used to describe the relationships between the structures shown in the accompanying drawings. These terms are described as relative concepts based on the directions shown in the figures.

[0055] In various embodiments of this disclosure, the terms "comprising," "including," "containing," or "having" specify attributes, fixed quantities, steps, processes, elements, and / or components or combinations thereof, but do not exclude the presence or addition of other attributes, fixed quantities, steps, processes, elements, and / or components or combinations thereof.

[0056] Figure 1 This is a block diagram illustrating the structure of a display device according to an embodiment.

[0057] Reference Figure 1 The display device 1 may include a timing controller 10, a gate driver 20, a data driver 30, a power supply unit 40, and a display panel 50.

[0058] Depending on the installed device, the timing controller 10 can be coupled to various processors, such as microprocessors, mobile processors, application processors, etc.

[0059] The timing controller 10 can receive video signals RGB and control signals CS from an external host system, etc. The video signal RGB may include multiple grayscale data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a master clock signal.

[0060] The timing controller 10 processes the video signal RGB and the control signal CS to suit the operating conditions of the display panel 50, and can generate and output image data DATA, gate drive control signal GCS, data drive control signal DCS and power control signal PCS.

[0061] The gate driver 20 can be formed in such a way that the gate driver 20 is mounted in the display panel 50 as an in-panel gate. The gate driver 20 can be disposed on one side of the display panel 50 as shown, or on both sides of the display panel 50 (e.g., left and right). Depending on the driving method, panel design method, etc., the gate driver 20 can be disposed on both sides of the display panel 50 as shown (e.g., left and right), or it can be connected to two or more of the four side surfaces of the display panel 50.

[0062] The gate driver 20 can generate a scan signal based on the gate drive control signal GCS output from the timing controller 10. The gate driver 20 can provide the generated scan signal to the pixel PX through multiple gate lines GL.

[0063] In one implementation, a pixel PX can be configured to receive multiple scan signals with different waveforms. In such an implementation, the gate driver 20 can provide multiple scan signals to the pixel PX via gate lines GL corresponding to the pixel PX.

[0064] The data driver 30 can generate a data signal based on the data drive control signal DCS output from the timing controller 10 and the image data DATA. The data driver 30 can provide the generated data signal to the pixel PX through multiple data lines DL.

[0065] The power supply unit 40 can generate a high-level driving voltage ELVDD and a low-level driving voltage ELVSS based on the power control signal PCS to supply to the display panel 50. The power supply unit 40 can supply the generated high-level driving voltage ELVDD and low-level driving voltage ELVSS to the pixel PX through corresponding voltage lines PL1 and PL2. In addition, the power supply unit 40 can also generate reference voltages required to drive the pixel PX, and supply these voltages to the pixel PX through corresponding voltage lines.

[0066] The display panel 50 can be implemented as a transmissive or non-transmissive display panel. A transmissive display panel can be applied to a transparent display device that displays an image on a screen while the real background object is visible.

[0067] Display panel 50 can be manufactured as a flexible display panel. The flexible display panel can be realized as an OLED panel using a plastic substrate.

[0068] The display panel 50 may include a display area AA and a non-display area NA surrounding the display area AA. In one embodiment, the non-display area NA may be formed around the display area AA and may correspond to a border area, but is not limited thereto.

[0069] Multiple pixels PX (or sub-pixels) are arranged in the display area AA. Pixels PX can be arranged in the display area AA, for example, in a matrix. Pixels in a pixel row are connected to the same gate line GL, and pixels PX in a pixel column are connected to the same data line DL. Pixels PX can emit light of a certain brightness, which corresponds to the data signal and scan signal provided through the gate line GL and the data line DL.

[0070] Each pixel PX may include a light-emitting element and driving circuitry configured to drive the light-emitting element. The light-emitting element included in the pixel PX can display one of the colors red, green, and blue.

[0071] In another embodiment, the light-emitting element can display one of cyan, magenta, and yellow. In various embodiments, the light-emitting element can display one of red, green, blue, and white.

[0072] In this embodiment, a touch sensor may be further disposed on the display panel 50. Touch input can be sensed using the touch sensor or by pixels (PX). The touch sensor may be disposed on the display panel 50 as an on-cell or additional type, or it may be implemented as an in-cell touch sensor embedded in the display panel 50.

[0073] The timing controller 10, gate driver 20, data driver 30 and power supply unit 40 can be configured as separate integrated circuits (ICs), or at least some of their parts can be integrated together to form an integrated circuit.

[0074] Figure 2 This is a circuit diagram of the pixel according to the implementation method.

[0075] Reference Figure 2 According to the embodiments, the pixel PX may include a driving transistor DT, a light-emitting element LD connected to the driving transistor DT, and a control circuit configured to control the amount of driving current to be applied to the light-emitting element LD through the driving transistor DT. For example, the control circuit may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0076] The first electrode of the driving transistor DT is configured to receive a high-potential driving voltage ELVDD (connected to the high-potential driving voltage line PL1), and the second electrode of the driving transistor DT is connected to the light-emitting element LD through the second node N2. The gate electrode of the driving transistor DT is connected to the data line DL through the first node N1. The driving transistor DT can be turned on according to the voltage difference between the first node N1 and the second node N2 (i.e., the gate-source voltage), and the amount of driving current flowing to the light-emitting element LD can be controlled.

[0077] The first electrode of the first transistor T1 can be connected to the data line DL, and the second electrode of the first transistor T1 can be connected to the gate electrode of the driving transistor DT. The gate electrode of the first transistor T1 can be connected to the first gate line GL1 and can receive a first gate signal. The first gate signal is a scan signal SC, and can be a control signal applied to program the data voltage Vdata into the pixel PX.

[0078] The first transistor T1 can be turned on according to the scan signal SC applied to the first gate line GL1, and can transmit the data voltage Vdata applied to the data line DL to the first node N1. Such a first transistor T1 can be called a switching transistor.

[0079] The first electrode of the second transistor T2 is connected to the reference voltage line VrefL, and the second electrode of the second transistor T2 is connected to the second node N2. The gate electrode of the second transistor T2 can be connected to the second gate line GL2 and can receive a second gate signal. The second gate signal is a sensing signal SN, and can be a control signal applied to apply a reference voltage to pixel PX or to sense the electrical characteristics of pixel PX.

[0080] The second transistor T2 can be turned on according to the sensing signal SN applied to the second gate line GL2, and can electrically connect the reference voltage line VrefL and the second node N2 to each other. When the reference voltage Vref is applied to the reference voltage line VrefL, the reference voltage Vref can be applied to the second node N2 through the turned-on second transistor T2.

[0081] When the reference voltage line VrefL is not connected to the reference voltage Vref, the sensing signal (e.g., current, voltage) applied to the second node N2 can flow through the reference voltage line VrefL to be transmitted to the data driver 30. Figure 1 ) and / or timing controller 10 ( Figure 1 )wait.

[0082] The transmitted sensing signal can be used to sense the electrical characteristics of pixel PX. Such a second transistor T2 can be referred to as an initialization transistor and / or a sensing transistor.

[0083] The storage capacitor Cst is connected between the first node N1 and the second node N2. The storage capacitor Cst can store a voltage corresponding to the voltage difference between the first node N1 and the second node N2, and maintain the stored voltage during a frame period, thereby stabilizing the voltage of the gate electrode of the driving transistor DT (i.e., the first node N1).

[0084] The anode of the light-emitting element (LD) can be connected to the driving transistor DT through the second node N2, and the cathode of the LD can be connected to the low-potential driving voltage ELVSS (connected to the low-potential driving voltage line PL2). When the driving transistor DT is turned on, a current path is formed between the high-potential driving voltage ELVDD and the low-potential driving voltage ELVSS, allowing driving current to flow to the LD. The LD emits light with a brightness corresponding to the amount of applied driving current.

[0085] exist Figure 2 In the illustrated embodiment, pixel PX may include an oxide semiconductor transistor. The oxide semiconductor transistor includes a gate electrode, a source electrode, and a drain electrode. The oxide semiconductor transistor has an active layer formed of oxide semiconductor.

[0086] Here, the oxide semiconductor can be either amorphous or crystalline. Oxide semiconductor transistors can be constructed as n-type transistors. Oxide semiconductor transistors can be fabricated using low-temperature processes and exhibit lower charge mobility than LTPS transistors. These oxide semiconductor transistors possess excellent cutoff current characteristics.

[0087] In another embodiment, the pixel PX can be a hybrid type that further includes LTPS (low-temperature polysilicon) transistors.

[0088] An LTPS transistor includes a gate electrode, a source electrode, and a drain electrode. An LTPS transistor has an active layer formed of polysilicon. This LTPS transistor can be constructed as a P-type transistor or an N-type transistor. LTPS transistors have high electron mobility, thus exhibiting fast drive characteristics.

[0089] Figure 3 This is a schematic plan view of the display panel according to the first embodiment. Figure 3 The image shows the display area AA. Figure 1 The settings include pixels PX1, PX2, and PX3.

[0090] Reference Figure 3The display panel 50 according to an embodiment includes a plurality of unit pixels PXU. Each unit pixel PXU may include a plurality of pixels PX1, PX2, and PX3 configured to emit light of different colors from each other. In an embodiment, the plurality of pixels PX1, PX2, and PX3 may display one of the colors red, green, and blue. However, the embodiment is not limited to this.

[0091] In one embodiment, pixels PX1, PX2, and PX3, which form a unit pixel PXU and are configured to emit light of different colors from each other, can be alternately arranged along a first direction X. Furthermore, pixels PX1, PX2, and PX3, configured to emit light of the same color, can be arranged along a second direction Y, which is substantially perpendicular to the first direction.

[0092] Pixels PX1, PX2, and PX3 can each include their corresponding light-emitting regions EA1, EA2, and EA3. Each light-emitting region EA1, EA2, and EA3 can be a light-emitting element (LD). Figure 2 The area where the anode electrode, the light-emitting layer, and the cathode electrode are in contact with each other and stacked.

[0093] Each luminous region EA1, EA2, and EA3 can be surrounded by a partition 211 that defines the luminous regions EA1, EA2, and EA3. The partition 211 can be formed in the form of a grid surrounding each luminous region EA1, EA2, and EA3.

[0094] The partition 211 can be formed on the anode electrode and can include an opening that exposes a region of the anode electrode. The exposed regions of the anode electrode not covered by the partition 211 can be defined as light-emitting regions EA1, EA2, and EA3. The partition 211 can be formed to define individual pixels PX1, PX2, and PX3. That is, adjacent pixel rows and pixel columns can be divided by the partition 211.

[0095] The barrier layer 213 and the metal cup structure layer 310 can be formed on the dike 211.

[0096] The barrier layer 213 may be formed in at least one region of the dike 211. For example, the barrier layer 213 may extend along the dike 211 in the first direction X. Alternatively, the barrier layer 213 may have a grid-like form extending along the dike 211 in the first direction X and the second direction Y, but is not limited thereto.

[0097] The metal cup structure layer 310 can be formed on the dike 211 such that at least one region of it covers the barrier layer 213. For example, the metal cup structure layer 310 can be formed to cover at least a portion of the edge of the barrier layer 213 and expose the central region of the barrier layer 213.

[0098] In one embodiment, at least two metal cup structure layers 310 may be provided between adjacent pixel rows and / or pixel columns. The at least two metal cup structure layers 310 may be spaced apart from each other by a predetermined interval. In this case, each metal cup structure layer 310 may be configured such that at least one region of it covers the barrier layer 213. For example, the metal cup structure layers 310 may be configured such that one metal cup structure layer 310 covers at least a portion of the edge on one side of the barrier layer 213, and the other metal cup structure layer 310 covers at least a portion of the edge on the other side of the barrier layer 213. However, the embodiment is not limited to this.

[0099] The metal cup structure layer 310 may have a form that extends along a second direction Y between adjacent columns of pixels. Alternatively, the metal cup structure layer 310 may have a grid form that further extends along a first direction X between adjacent rows of pixels, but is not limited thereto.

[0100] The structure of the barrier layer 213 and the metal cup structure layer 310 will be described in detail below with reference to the accompanying drawings.

[0101] A portion of the upper surface of the partition 211 and a portion of the upper surface of the metal cup structure layer 310 may be covered by the spacer 320. In one embodiment, the spacer 320 may be positioned further away from each of the light-emitting regions EA1, EA2, and EA3 than the partition 211. However, the embodiment is not limited to this; in another embodiment, the spacer 320 may be positioned closer to each of the light-emitting regions EA1, EA2, and EA3 than the partition 211, and may be formed to surround each of the light-emitting regions EA1, EA2, and EA3.

[0102] Figure 4 It is along Figure 3 The implementation of the cross-sectional view taken by the I-I' line shown.

[0103] Reference Figure 4 According to the embodiment, the display panel 50 may include a substrate 101 and pixels PX1 and PX2 disposed on the substrate 101.

[0104] The substrate 101 supports various components of the display panel 50. The substrate 101 can be formed of a transparent insulating material such as glass or plastic. When the substrate 101 is formed of plastic, the substrate 101 can be referred to as a plastic film or a plastic substrate.

[0105] For example, substrate 101 may be a film comprising one of polyimide polymers, polyester polymers, silicone polymers, acrylic polymers, polyolefin polymers, and copolymers thereof, but embodiments of the present disclosure are not limited thereto. Furthermore, when substrate 101 is made of plastic, substrate 101 may be formed as a dual structure. For example, substrate 101 may have a dual structure with an adhesive layer between a first polyimide layer and a second polyimide layer. For example, substrate 101 may have a structure including an interlayer insulating layer formed of an inorganic insulating material and located between the first polyimide layer and the second polyimide layer.

[0106] When substrate 101 is made of glass, substrate 101 may be referred to as a glass substrate. For example, the glass substrate may include a shielding metal (not shown) and may be used to protect the device from external light or signal interference.

[0107] A circuit element layer (PCL) can be disposed on the substrate 101. Circuit elements, such as reference elements, can be disposed on the PCL. Figure 2 The description includes at least one transistor (DT, T1, T2) and a capacitor (Cst). For example, the circuit element layer PCL may include a semiconductor pattern forming the circuit element, conductive electrodes, and at least one insulating layer between them. Additionally, the circuit element layer PCL may include at least one barrier layer for protecting the circuit element from external intrusion and / or at least one planarization layer for planarizing the upper surface of the circuit element layer PCL. There are no specific limitations on the construction and structure of the circuit element layer PCL.

[0108] The light-emitting element layer containing the light-emitting element LD can be placed on the circuit element layer PCL.

[0109] More specifically, the first electrode can be patterned on the circuit element layer PCL. For example, the first electrode can be an anode electrode 201.

[0110] The anode electrode 201 can be formed of a metallic material such as chromium, titanium, gold, silver, copper, aluminum, etc. Alternatively, the anode electrode 201 may include a metallic material with high reflectivity, such as a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and indium tin oxide (ITO) (ITO / Al / ITO), and an APC alloy. The anode electrode 201 can be composed of a single layer or multiple layers, but the embodiments disclosed herein are not limited thereto.

[0111] Such an anode electrode 201 can be patterned to correspond to each pixel PX1 and PX2. Furthermore, the anode electrode 201 can be electrically connected to the transistors (e.g., driving transistors DT) of each pixel PX1 and PX2 disposed in the circuit element layer PCL via contact holes or the like.

[0112] The partition 211 can be formed on the anode electrode 201. The partition 211 can be formed on the substrate 101 with a relatively wide width.

[0113] The partition 211 may include an opening that overlaps with the anode electrode 201. For example, the opening may correspond to the central region of the anode electrode 201. In such an embodiment, the partition 211 may cover a region of the anode electrode 201, such as an edge, and expose the remaining regions, such as the central region, upward through the opening. The exposed regions of the anode electrode 201 not covered by the partition 211 may be defined as light-emitting regions EA1 and EA2. The light-emitting layer 202 and the cathode electrode 203, described below, may be sequentially stacked in the exposed regions of the anode electrode 201 and in direct contact with each other to form a light-emitting element LD.

[0114] The barrier 211 can be formed of an opaque material to prevent light interference between adjacent pixels. For example, the barrier 211 can be formed of an organic material such as benzocyclobutene resin, polyimide resin, acrylic resin, or photosensitive polymer.

[0115] Alternatively, the barrier 211 may comprise a black-based material and may include a light-shielding material (black barrier) formed from at least one of, for example, colored pigments (black pigments), black dyes, organic black, and carbon. When the barrier 211 is formed from a black-based material, it can shield external light, thereby further improving the brightness of the display panel 50. In this case, the barrier 211 can be used to absorb light reflected from the underside of the barrier 211 in externally incident light.

[0116] In embodiments, the barrier 211 can be a multilayer structure. For example, the barrier 211 may include an organic layer and an organic layer on which an inorganic coating or inorganic layer is disposed. The inorganic layer may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON) (or Si2N2O), magnesium fluoride (MgF2), or combinations thereof. Furthermore, in embodiments where the barrier 211 is formed as a multilayer structure, a portion of the multilayer of the barrier 211 (e.g., the lower layer) may include a black material, while the remaining portions (e.g., the upper layer) may include a transparent material.

[0117] A barrier layer 213 may be formed on the dike 211. The barrier layer 213 may be formed in at least one region of the dike 211, including the central region.

[0118] In this embodiment, the barrier layer 213 may be formed of a non-conductive inorganic material. For example, the non-conductive inorganic material may include an inorganic silicon-containing material. For example, the silicon-containing material may include, but is not limited to, silicon oxides or nitrides or combinations thereof.

[0119] The metal cup structure layer 310 can be further disposed on the dike 211. For example, the metal cup structure layer 310 can be disposed on the barrier layer 213.

[0120] At least two metal cup structure layers 310 can be disposed between adjacent pixels PX1 and PX2. The two metal cup structure layers 310 can be formed such that at least a portion of them overlaps with the barrier layer 213. That is, the two metal cup structure layers 310 can be spaced apart from each other by a predetermined interval to cover one side and the other side of the barrier layer 213.

[0121] In an embodiment, the metal cup structure layer 310 may include a lower layer 310A disposed adjacent to the dike 211 and the barrier layer 213, and an upper layer 310B disposed on the lower layer 310A. The lower layer 310A and the upper layer 310B may be formed of a conductive inorganic material. The conductive inorganic material may include a metal-containing material. For example, metal-containing materials include copper, titanium, aluminum, molybdenum, silver, indium tin oxide, indium zinc oxide, or combinations thereof. However, the material of the metal cup structure layer 310 is not limited to these.

[0122] Such a metal cup structure layer 310 can be configured to receive a low-potential drive voltage ELVSS ( Figure 2 For example, the metal cup structure layer 310 can be electrically connected to the low-potential drive voltage line PL2. Figure 2 For example, the metal cup structure layer 310 can be directly connected to the non-display area NA of the display panel 50. Figure 1 The low-potential drive voltage line PL2 is provided in the form of a shorting bar, or it can be indirectly connected to the low-potential drive voltage line PL2 through connecting electrodes, etc. The connection structure between the metal cup structure layer 310 and the low-potential drive voltage line PL2 can be described in more detail below with reference to the accompanying drawings.

[0123] The lower layer 310A of the metal cup structure layer 310 can be formed to cover at least one area of ​​the barrier layer 213. For example, the lower layer 310A can be formed to cover at least a portion of the edge of the barrier layer 213. In an embodiment, the lower layer 310A can be formed to further cover the portion of the upper surface of the dike 211 that is not covered by the barrier layer 213.

[0124] The upper layer 310B of the metal cup structure layer 310 can be formed to be wider than the lower layer 310A. For example, the lower surface of the upper layer 310B can be formed to be wider than the upper surface of the lower layer 310A. In such an embodiment, at least one region of the upper layer 310B can protrude more outward than the lower layer 310A and can form a shielding region SA for the underlying layer (e.g., barrier layer 213).

[0125] In other words, the metal cup structure layer 310 can have an inverted conical shape on its side surfaces. Such a metal cup structure layer 310 can be formed by depositing the constituent materials of a lower layer 310A and an upper layer 310B, and then patterning the lower layer 310A and the upper layer 310B into an inverted conical shape. Alternatively, the metal cup structure layer 310 can be formed by patterning the lower layer 310A and then patterning the upper layer 310B above the patterned lower layer 310A.

[0126] The barrier layer 213 and two adjacent metal cup structure layers 310 can form a metal cup aperture H surrounded by them. A region of the barrier layer 213 can be exposed upward within the metal cup aperture H. Such a metal cup aperture H can trap external materials such as oxygen and moisture that penetrate through the passivation film 102 described below, and prevent damage to the light-emitting element LD due to the intrusion of external materials.

[0127] Spacer 320 may be further formed on the metal cup structure layer 310. Spacer 320 may be provided to protect the light-emitting element LD by preventing external impacts from being directly transmitted to the light-emitting element LD. Spacer 320 may be formed of an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene resin, hexamethyldisiloxane resin, and phenolic resin, and may be formed as a single layer or multiple layers. Spacer 320 may be formed of the same material as spacer 211, but is not limited thereto.

[0128] The spacer 320 can be formed to cover at least one area of ​​the upper layer 310B of the metal cup structure layer 310. In an embodiment, the spacer 320 can also cover the upper surface of the dike 211 that is not covered by the barrier layer 213 and the metal cup structure layer 310. That is, the spacer 320 can extend from the upper surface of the metal cup structure layer 310 to the upper surface of the dike 211. In such an embodiment, the spacer 320 can cover the side surface of the metal cup structure layer 310 adjacent to the upper surface of the dike 211.

[0129] The spacer 320 may not be formed inside the metal cup hole H. Therefore, by making the passivation film 102, described below, in direct contact with the interior of the metal cup hole H, external materials that penetrate through the passivation film 102 are effectively trapped inside the metal cup hole H.

[0130] The light-emitting layer 202 can be formed on the anode electrode 201. The light-emitting layer 202 can be formed in at least one region of the partition 211 and in the exposed region of the anode electrode 201 not covered by the partition 211.

[0131] In this embodiment, the light-emitting layer 202 may extend through the light-emitting regions EA1 and EA2 to the non-light-emitting regions. For example, the light-emitting layer 202 may be further formed on the exposed areas of the spacer 320, the metal cup structure layer 310, and the barrier layer 213. In this case, due to the low step coverage, the light-emitting layer 202 may be cut off around the edge of the upper layer 310B of the metal cup structure layer 310. Therefore, the portion of the upper surface of the barrier layer 213 formed in the shielding region SA and the side surface of the metal cup structure layer 310 in contact with it are not covered by the light-emitting layer 202, but are exposed inside the metal cup hole H and can contact the cathode electrode 203 described below.

[0132] The light-emitting layer 202 can be formed of an organic material that emits light corresponding to the voltage applied to the anode electrode 201 and the cathode electrode 203 described below. In embodiments, the light-emitting layer 202 can emit light of one color—red, green, or blue—depending on the type of organic material. However, embodiments are not limited to this, and the light-emitting layer 202 can be configured to emit different colors of light, such as white.

[0133] In this embodiment, the common layer may be located between the anode electrode 201 and the light-emitting layer 202. The common layer is an organic layer, and may include, for example, a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and / or an electron injection layer (EIL), but is not limited thereto.

[0134] The second electrode can be formed on the light-emitting layer 202. The second electrode can be a cathode electrode 203. The cathode electrode 203 can include a metallic material with high reflectivity, such as a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and indium tin oxide (ITO) (ITO / Al / ITO), and an APC alloy. The cathode electrode 203 can be composed of a single layer or multiple layers, but the embodiments of this disclosure are not limited thereto.

[0135] The cathode electrode 203 can be formed relatively wide on the substrate 101. Unlike the light-emitting layer 202, due to the high step coverage, the cathode electrode 203 can be formed continuously without interruption around the edge of the upper layer 310B of the metal cup structure layer 310. Therefore, within the metal cup hole H, the cathode electrode 203 can be formed to contact the exposed upper surface of the barrier layer 213 not covered by the light-emitting layer 202 and the side surface of the metal cup structure layer 310 adjacent to the exposed upper surface of the barrier layer 213. Specifically, the cathode electrode 203 can be formed to cover the side surface of the lower layer 310A and the lower surface of the upper layer 310B of the metal cup structure layer 310.

[0136] Since the metal cup structure layer 310 is electrically connected to the low-potential driving voltage line PL2, the cathode electrode 203 can be electrically connected to the low-potential driving voltage line PL2 through the metal cup structure layer 310 and can receive the low-potential driving voltage ELVSS. In the structure where the cathode electrode 203 covers the side surface of the metal cup structure layer 310, the electrical contact area between the cathode electrode 203 and the metal cup structure layer 310 is very wide. Therefore, the low-potential driving voltage ELVSS can be effectively transmitted to the cathode electrode 203. Thus, the IR drop phenomenon generated when the low-potential driving voltage ELVSS is applied to the display panel 50 with a large area can be improved, and a low-potential driving voltage ELVSS of the same magnitude is stably provided to pixels PX1, PX2, and PX3, thereby improving the brightness uniformity among pixels PX1, PX2, and PX3.

[0137] The passivation film 102 can be formed on the cathode electrode 203. The passivation film 102 can be a local passivation layer disposed in the region of each pixel PX1 and PX2, or a corresponding layer thereto.

[0138] The passivation film 102 can be formed from organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, or inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3), but is not limited thereto. The passivation film 102 can have a structure formed of a single layer or multiple layers.

[0139] The passivation film 102 can cover the cathode electrode 203 and can extend along the inner surface of the metal cup aperture H. In such an embodiment, the intrusion path of external materials introduced via the passivation film 102 between adjacent pixels PX1 and PX2 can be blocked by the barrier layer 213 and the metal cup structure layer 310 as shown. That is, external materials such as harmful gases are trapped within the metal cup aperture H and will not be transmitted to the light-emitting element LD, thus preventing damage to the light-emitting element LD.

[0140] At the same time, Figure 3 In the stripe arrangement shown, the distance between adjacent pixel columns is relatively close, and the distance between adjacent pixel columns is further reduced in the display panel 50 with high image quality and high resolution. Therefore, lateral leakage current (LLC) may occur between pixels PX1, PX2, and PX3 arranged adjacent to each other.

[0141] exist Figure 4 In this embodiment, the barrier layer 213 disposed between the metal cup structure layers 310 is formed of a non-conductive inorganic material. Therefore, the path of the lateral leakage current flowing between adjacent pixels PX1 and PX2 is blocked, and electrical short circuits and damage between pixels PX1 and PX2 can be prevented.

[0142] In an embodiment, a first planarization layer 103 may be further provided. The first planarization layer 103 can planarize the step differences formed by the underlying layer and protect the components on the lower side. The first planarization layer 103 may be formed of an organic material, including, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The first planarization layer 103 may have a structure formed of a single layer or multiple layers.

[0143] In one embodiment, the inkjet layer, photoresist, color filter, or photosensitive monomer may be further disposed between the passivation film 102 and the first planarization layer 103, but the embodiment is not limited thereto.

[0144] Figure 5 It is along Figure 3 Another embodiment of the cross-sectional view taken by the I-I' line is shown. In the description... Figure 5 When implementing the method, with Figure 4 The same parts are given the same reference numerals, and their detailed descriptions will be omitted.

[0145] Reference Figure 5 A color filter layer can be further formed on the first planarization layer 103.

[0146] The color filter layer may include a buffer layer 401, a color filter 402, and a black matrix 403 formed on the first planarization layer 103. The color filter 402 can block or transmit a specific color of light emitted from the light-emitting region. The black matrix 403 may be disposed between the color filters 402, dividing individual pixels (PX) and preventing light interference between adjacent pixels (PX). For example, the color filter 402 may contact the side and top surfaces of the black matrix 403.

[0147] A second planarization layer 404 may be further disposed on the color filter layer. The second planarization layer 404 can be used to planarize the step differences formed by the color filter 402. For example, the second planarization layer 404 may include an organic insulating material.

[0148] A touch sensor layer can be formed on the second planarization layer 404.

[0149] More specifically, a touch buffer layer 501 may be formed on the second planarization layer 404. The touch buffer layer 501 may be located between the touch sensor metal including touch electrodes 502 and 503 and the cathode electrode 203 of the light-emitting element LD.

[0150] The touch buffer layer 501 prevents liquid chemicals (developer or etchant) used during the manufacturing process of the touch sensor metal disposed on the touch buffer layer 501, or external moisture, from penetrating the light-emitting layer 202 containing organic matter. Therefore, the touch buffer layer 501 prevents damage to the light-emitting layer 202, which is susceptible to liquid chemicals or moisture.

[0151] The touch buffer layer 501 can be formed of an organic insulating material that can be formed at a low temperature equal to or below a predetermined temperature (e.g., 100°C) and has a low dielectric constant of 1 to 3 to prevent damage to the light-emitting layer 202, which contains organic materials susceptible to high temperatures. For example, the touch buffer layer 501 can be formed of acrylic, epoxy, or siloxane-based materials. The touch buffer layer 501, formed of an organic insulating material and having planarization properties, can prevent damage to the second planarization layer 404 due to warping of the display device 1 and breakage of the touch sensor metal on the touch buffer layer 501.

[0152] According to the mutual capacitance-based touch sensor structure, touch electrodes 502 and 503 can be disposed on the touch buffer layer 501, and touch electrodes 502 and 503 can cross each other.

[0153] Touch electrode connection wires can be electrically connected between touch electrodes 502 and 503. Touch electrodes 502 and 503 can be electrically connected to touch drivers, etc., via touch electrode connection wires. A portion of the touch electrode connection wires can receive touch drive signals from the touch drive circuit and transmit touch drive signals to touch electrodes 502 and 503, and can also transmit touch sensing signals from touch electrodes 502 and 503 to the touch drive circuit.

[0154] The touch electrode connecting lines and touch electrodes 502 and 503 can be disposed in different layers separated by a touch insulating film. The touch electrode connecting lines can be configured to overlap with the barrier 211 to prevent a decrease in the aperture ratio. The touch electrode connecting lines can be formed by double lines, in which case each layer of the touch electrode connecting lines can be formed on the touch buffer layer 501 and the touch insulating film, respectively.

[0155] The touch protective film 504 can be disposed on the touch electrodes 502 and 503.

[0156] In the above embodiment, the touch sensor layer is disposed on the color filter layer. However, the embodiment is not limited to this. In various other embodiments, the color filter layer may be disposed on the touch sensor layer.

[0157] Figure 6 This is a schematic plan view of the display panel according to the second embodiment.

[0158] and Figure 3Compared to the implementation method, in Figure 6 In this embodiment, each light-emitting region EA1, EA2, and EA3 can be surrounded by spacers 320 that define the light-emitting regions EA1, EA2, and EA3. The spacers 320 can be formed in a grid pattern surrounding each light-emitting region EA1, EA2, and EA3.

[0159] The partition 211 can be formed such that at least one area of ​​it is covered by the spacer 320, and is spaced apart from the light-emitting areas EA1, EA2 and EA3. The partition 211 can be formed around the periphery of the light-emitting areas EA1, EA2 and EA3.

[0160] Figure 7 It is along Figure 6 The embodiment shown is a cross-sectional view taken along line II-II'. In the description... Figure 7 When implementing the method, with Figure 4 The same parts are given the same reference numerals, and their detailed descriptions will be omitted.

[0161] refer to Figure 7 The anode electrode 201 can be patterned to correspond to the respective light-emitting regions EA1 and EA2. The spacer 211 can be spaced apart from the anode electrode 201 on the circuit element layer PCL. Figure 4 Depending on the implementation method, the partition 211 may be formed not to cover the anode electrode 201. The partition 211 may be formed to surround the patterned anode electrode 201 on a plane, but is not limited thereto.

[0162] A barrier layer 213 may be formed on the dike 211. The barrier layer 213 may be formed in at least one region of the dike 211, including the central region of the dike 211.

[0163] Metal cup structure layer 310 can be formed on the partition 211 and the barrier layer 213. At least two metal cup structure layers 310 can be disposed between adjacent pixels PX1 and PX2. The two metal cup structure layers 310 can be spaced apart from each other by a predetermined interval on the barrier layer 213.

[0164] The barrier layer 213 and the two metal cup structure layers 310 can form a predetermined metal cup hole H around them. The metal cup hole H can trap external materials such as oxygen and moisture that penetrate through the passivation film 102, and prevent damage to the light-emitting element LD due to the intrusion of external materials.

[0165] Spacer 320 may be formed on metal cup structure layer 310. Spacer 320 may be formed to cover at least one region of upper layer 310B of metal cup structure layer 310. In an embodiment, spacer 320 may be formed to further cover the upper surface of barrier 211 not covered by barrier layer 213 and the side surface of metal cup structure layer 310 adjacent to the upper surface of barrier 211.

[0166] exist Figure 7 In some embodiments, the spacer 320 may be further formed to cover at least one region of the anode electrode 201. For example, the spacer 320 may be formed to cover the edge of the anode electrode 201 and expose the central region of the anode electrode 201 upwards. In this case, the exposed areas of the anode electrode 201 not covered by the spacer 320 may be defined as light-emitting regions EA1 and EA2.

[0167] In such an embodiment, the spacer 320 may be further formed to cover the spacer region between the partition 211 and the anode electrode 201, as well as the side surface of the partition 211 adjacent to the spacer region. In this way, when the partition 211 and the anode electrode 201 are spaced apart from each other and the spacer 320 is further provided between them, external materials that intrude through the partition 211 or the like can be more effectively blocked from entering the light-emitting element LD.

[0168] Figure 8 This is a schematic plan view of the display panel according to the third embodiment.

[0169] Reference Figure 8 The display panel 50 according to an embodiment includes a plurality of unit pixels PXU. Each unit pixel PXU may include a plurality of pixels PX1, PX2, and PX3 configured to emit light of different colors from each other. In an embodiment, the plurality of pixels PX1, PX2, and PX3 may display one of the colors red, green, and blue. However, the embodiment is not limited to this.

[0170] In one embodiment, pixels PX1, PX2, and PX3, configured to emit light of different colors from each other, can be alternately arranged along a first direction X. Furthermore, pixels PX1, PX2, and PX3, configured to emit light of the same color, can be arranged along a second direction Y, which is substantially perpendicular to the first direction.

[0171] Similar to Figure 3 Each pixel PX1, PX2, and PX3 can include its corresponding light-emitting region EA1, EA2, and EA3. Each light-emitting region EA1, EA2, and EA3 can be surrounded by a partition 211 that defines the light-emitting regions EA1, EA2, and EA3.

[0172] The connecting electrode 204 and the metal cup structure layer 310 can be formed on the dike 211.

[0173] The connecting electrode 204 may be formed in at least one region of the partition 211. For example, the connecting electrode 204 may have an elongated form extending along the partition 211 in the first direction X. Alternatively, the connecting electrode 204 may have a grid form extending along the partition 211 in the first direction X and the second direction Y, but is not limited thereto.

[0174] The connecting electrode 204 can be configured to electrically connect the cathode electrode 203 of the light-emitting element LD and the low-potential driving voltage line PL2. Figure 2 Therefore, the connecting electrode 204 can be electrically connected to the low-potential drive voltage line PL2.

[0175] In embodiments where the connecting electrode 204 has an elongated form, the electrical connection area between the connecting electrode 204 and the cathode electrode 203 is very wide. Therefore, the IR drop phenomenon that occurs when a low-potential driving voltage ELVSS is applied to the display panel 50 with a large area can be improved, and a low-potential driving voltage ELVSS of the same magnitude is stably provided to pixels PX1, PX2, and PX3, thereby improving the brightness uniformity among pixels PX1, PX2, and PX3.

[0176] The metal cup structure layer 310 can be formed on the dam 211 such that at least one region of it covers the connection electrode 204. For example, the metal cup structure layer 310 can be formed to cover at least a portion of the edge of the connection electrode 204 and expose the central region of the connection electrode 204.

[0177] In one embodiment, at least two metal cup structure layers 310 may be provided between adjacent pixel rows and / or pixel columns. The at least two metal cup structure layers 310 may be spaced apart from each other by a predetermined interval. In this case, each metal cup structure layer 310 may be configured such that at least one region of it covers the connection electrode 204. For example, the metal cup structure layers 310 may be configured such that one metal cup structure layer 310 covers at least a portion of the edge on one side of the connection electrode 204, and the other metal cup structure layer 310 covers at least a portion of the edge on the other side of the connection electrode 204. However, the embodiment is not limited to this.

[0178] The metal cup structure layer 310 may have a form that extends along a second direction Y between adjacent columns of pixels. Alternatively, the metal cup structure layer 310 may have a form that further extends along a first direction X between adjacent rows of pixels, but is not limited thereto.

[0179] Figure 9 It is along Figure 8 The embodiment shown is a cross-sectional view taken from line III-III'. In the description... Figure 9When implementing the method, with Figure 4 The same parts are given the same reference numerals, and their detailed descriptions will be omitted.

[0180] Reference Figure 9 The first electrode can be patterned on the circuit element layer PCL. Furthermore, the first electrode 201 is, for example, an anode electrode 201. The anode electrode 201 can be patterned to correspond to each pixel PX1 and PX2.

[0181] Furthermore, the connection electrode 204 can be further formed on the circuit element layer PCL. The connection electrode 204 can be formed of a conductive material. For example, the connection electrode 204 can be formed on the same layer as the anode electrode 201 and made of the same material as the anode electrode 201, but is not limited thereto.

[0182] Such a connection electrode 204 can be configured to receive a low-potential drive voltage ELVSS ( Figure 2 For example, connection electrode 204 can be electrically connected to the low-potential drive voltage line PL2. Figure 2 For example, the connecting electrode 204 can be directly connected to the non-display area NA of the display panel 50. Figure 1 The low-potential drive voltage line PL2 can be connected in the form of a short-circuit bar, or indirectly via an additional connecting electrode. The connection structure between the connecting electrode 204 and the low-potential drive voltage line PL2 can be described in more detail below with reference to the accompanying drawings.

[0183] A spacer 211 can be formed on the anode electrode 201. The spacer 211 can be configured to cover a region of the anode electrode 201, such as an edge, and expose the remaining regions, such as the central region of the anode electrode 201. The spacer 211 can be formed relatively wide on the substrate 101. The area of ​​the anode electrode 201 that is not covered by the spacer 211 and is exposed can be defined as the light-emitting region. The light-emitting layer 202 and the cathode electrode 203 can be sequentially stacked on the exposed region of the anode electrode 201 such that they are in direct contact with each other, thereby forming a light-emitting element LD.

[0184] The metal cup structure layer 310 can be disposed on the partition 211. At least two metal cup structure layers 310 can be disposed on adjacent pixels PX1 and PX2. Figure 8 Between the two metal cup structural layers 310, the two layers can be spaced apart from each other at a predetermined interval on the dike 211.

[0185] In an embodiment, the metal cup structure layer 310 may include a lower layer 310A disposed adjacent to the partition 211 and an upper layer 310B disposed on the lower layer 310A. The lower layer 310A and the upper layer 310B may be formed of a conductive inorganic material. The conductive inorganic material may include a metal-containing material. For example, metal-containing materials include copper, titanium, aluminum, molybdenum, silver, indium tin oxide, indium zinc oxide, or combinations thereof. However, the material of the metal cup structure layer 310 is not limited to these.

[0186] The lower layer 310A of the metal cup structure layer 310 may overlap with at least one region of the connecting electrode 204. For example, the lower layer 310A may be formed to overlap with at least a portion of the edge of the connecting electrode 204.

[0187] The upper layer 310B of the metal cup structure layer 310 can be formed to be wider than the lower layer 310A. For example, the lower surface of the upper layer 310B can be formed to be wider than the upper surface of the lower layer 310A. In such an embodiment, at least one region of the upper layer 310B can protrude more outward than the lower layer 310A and can form a shielding region SA for the underlying layer (e.g., the connecting electrode 204).

[0188] The metal cup structure layer 310 can contact the connection electrode 204 formed below the partition 211 through contact holes CT formed in the partition 211. In an embodiment, the contact holes CT can be formed in the form of dots or stripes. For example, corresponding to the form of the connection electrode 204 that extends and elongates in the second direction Y, the contact holes can be formed in the partition 211 in an elongated and extended form between adjacent pixel columns.

[0189] The connecting electrode 204 and two adjacent metal cup structure layers 310 can form a metal cup hole H surrounding them. A region of the connecting electrode 204 can be exposed upward within the metal cup hole H. Such a metal cup hole H can trap external materials such as oxygen and moisture that penetrate through the passivation film 102, and prevent damage to the light-emitting element LD due to the intrusion of external materials.

[0190] Spacer 320 may be further formed on the metal cup structure layer 310. Spacer 320 may be formed to cover at least one region of the upper layer 310B of the metal cup structure layer 310. In an embodiment, spacer 320 may be formed to further cover the upper surface of the partition 211 that is not covered by the metal cup structure layer 310. That is, spacer 320 may extend from the upper surface of the metal cup structure layer 310 to the upper surface of the partition 211. In such an embodiment, spacer 320 may cover the side surface of the metal cup structure layer 310 adjacent to the upper surface of the partition 211.

[0191] The spacer 320 is not formed inside the metal cup hole H. Therefore, by making the passivation film 102 directly contact the interior of the metal cup hole H, external materials that penetrate through the passivation film 102 are effectively trapped inside the metal cup hole H.

[0192] The light-emitting layer 202 can be formed on the anode electrode 201. The light-emitting layer 202 can be formed in at least one region of the partition 211 and in the region of the anode electrode 201 that is not covered by the partition 211 and is exposed.

[0193] In this embodiment, the light-emitting layer 202 may extend through the light-emitting regions EA1, EA2, and EA3 to the non-light-emitting regions. For example, the light-emitting layer 202 may be further formed on the spacer 320, the metal cup structure layer 310, and the exposed areas of the connecting electrode 204. In this case, due to the low step coverage, the light-emitting layer 202 may be cut off around the edge of the upper layer 310B of the metal cup structure layer 310. Therefore, the inner surface of the metal cup structure layer 310 is not covered by the light-emitting layer 202 but is exposed inside the metal cup hole H and can contact the cathode electrode 203.

[0194] The second electrode can be formed on the light-emitting layer 202. The second electrode can be a cathode electrode 203.

[0195] The cathode electrode 203 can be formed relatively wide on the substrate 101. Unlike the light-emitting layer 202, due to the high step coverage, the cathode electrode 203 can be formed continuously without interruption around the edge of the upper layer 310B of the metal cup structure layer 310. Therefore, within the metal cup hole H, the cathode electrode 203 can be formed to contact the exposed upper surface of the connecting electrode 204 that is not covered by the light-emitting layer 202 and the side surface of the metal cup structure layer 310 adjacent to the exposed upper surface of the connecting electrode 204. Specifically, the cathode electrode 203 can be formed to cover the side surface of the lower layer 310A and the lower surface of the upper layer 310B of the metal cup structure layer 310.

[0196] Since the metal cup structure layer 310 is electrically connected to the low-potential driving voltage line PL2 via the connecting electrode 204, the cathode electrode 203 can also be electrically connected to the low-potential driving voltage line PL2 via the metal cup structure layer 310 and can receive the low-potential driving voltage ELVSS. In the structure where the cathode electrode 203 covers the side surface of the metal cup structure layer 310, the electrical contact area between the cathode electrode 203 and the metal cup structure layer 310, as well as the electrical contact area between the metal cup structure layer 310 and the connecting electrode 204, is very wide. Therefore, the low-potential driving voltage ELVSS can be effectively transmitted to the cathode electrode 203. Thus, the IR drop phenomenon generated when the low-potential driving voltage ELVSS is applied to the display panel 50 with a large area can be improved, and a low-potential driving voltage ELVSS of the same magnitude is stably provided to pixels PX1, PX2, and PX3, thereby improving the brightness uniformity among pixels PX1, PX2, and PX3.

[0197] A passivation film 102 can be formed on the cathode electrode 203. The passivation film 102 can cover the cathode electrode 203 and can extend along the inner surface of the metal cup aperture H. In this embodiment, the intrusion path of external materials introduced via the passivation film 102 between adjacent pixels PX1 and PX2 can be blocked by the connecting electrode 204 and the metal cup structure layer 310 as shown. That is, external materials such as harmful gases are trapped within the metal cup aperture H and will not be transmitted to the light-emitting element LD, thus preventing damage to the light-emitting element LD.

[0198] Figures 10A to 10F Show Figure 9 The manufacturing method of the display panel shown.

[0199] Reference Figure 10A The anode electrode 201 can be formed on the circuit element layer PCL. The anode electrode 201 can be patterned to correspond to each pixel PX1 and PX2 ( Figure 8 (area).

[0200] In one embodiment, the connection electrode 204 may be further formed on the circuit element layer PCL. The connection electrode 204 may be configured to receive a low-potential drive voltage ELVSS. Figure 2 It can be electrically connected to the low-potential drive voltage line PL2 via, for example, a contact hole, the diagram of which is omitted.

[0201] refer to Figure 10BA barrier 211 can be formed on the anode electrode 201 and the connecting electrode 204. For example, the barrier material can be deposited on the circuit element layer PCL, and a portion of the barrier material can be controlled and patterned using a mask such as a photoresist. The barrier 211 can be patterned to cover the edge of the anode electrode 201 and expose the central region of the anode electrode 201. Alternatively, the barrier 211 can be patterned to have contact holes (CTs) that expose the edges of the connecting electrode 204. Patterning can be performed using photolithography, digital lithography, or laser ablation processes.

[0202] refer to Figure 10C and Figure 10D The metal cup structure layer 310 can be formed on the dam 211. The metal cup structure layer 310 can be formed such that at least a portion of it overlaps with the contact hole CT, and the metal cup structure layer 310 contacts the connection electrode 204 exposed upward through the contact hole CT.

[0203] More in detail, such as Figure 10C As shown, the lower and upper layers can be deposited on the dike 211. Furthermore, as... Figure 10D As shown, the lower and upper layers can be removed from the area other than the area around the contact hole CT using a mask such as photoresist.

[0204] In this configuration, the lower layer 310A can be patterned to expose at least one area, such as the central region of the connection electrode 204 formed below it, and the upper layer 310B can be patterned to be wider than the upper surface of the lower layer 310A to form a shielding area.

[0205] In one embodiment, a portion of the upper layer material can be removed using a dry etching process or the like, thereby forming the upper layer 310B. Furthermore, a portion of the lower layer material can be removed using a wet etching process or the like, thereby forming the lower layer 310A. In this embodiment, the photoresist can be a positive or negative photoresist. In this case, the etching selectivity and etching process of the upper and lower layers can be appropriately selected so that an overhang can be formed between the upper layer 310B and the lower layer 310A.

[0206] refer to Figure 10E Spacer 320 may be formed on the dike 211 and the metal cup structure layer 310. Spacer 320 may be formed to cover at least one region of the upper layer 310B of the metal cup structure layer 310. In an embodiment, spacer 320 may be patterned to further cover the upper surface of the dike 211 not covered by the metal cup structure layer 310 and the side surface of the metal cup structure layer 310 adjacent to the upper surface of the dike 211.

[0207] refer to Figure 10FThe light-emitting layer 202, the cathode electrode 203, and the passivation film 102 can be formed on the anode electrode 201, the spacer 211, the spacer 320, the metal cup structure layer 310, and the connecting electrode 204. In this embodiment, the cathode electrode 203, formed of ITO or the like, can be formed by a sputtering process.

[0208] Due to the low step coverage, the light-emitting layer 202 is cut off around the shielded area of ​​the metal cup structure layer 310. Due to the high step coverage, the cathode electrode 203 and the passivation film 102 can be formed to cover the side surface of the metal cup structure layer 310 and extend along the interior of the metal cup hole H.

[0209] exist Figures 10A to 10F In the embodiment shown, the manufacturing method of the display panel forms a pixel PX. Figures 10A to 10F The operation shown can be repeated for other pixels and can be further formed into three or more pixels.

[0210] Figure 11 The electrical connection relationship of the low-potential drive voltage line according to the embodiment is shown.

[0211] Reference Figure 11 The display panel 50 may include a display area AA with pixels PX and a non-display area NA surrounding the display area AA. The display area AA may be generally quadrilateral or rectangular, but is not limited thereto. The non-display area NA may be configured to surround the display area AA, but is not limited thereto.

[0212] On the side of the non-display area NA, it is possible to configure the data drive 30 ( Figure 1 One or more source driver integrated circuits (SDICs) are included in the source film SF. Each source driver integrated circuit (SDIC) can be mounted in the source film SF, and one side of the source film SF can be electrically connected to the display panel 50. In addition, a line for electrically connecting the source driver integrated circuit (SDIC) and the display panel 50 can be provided on the upper part of the source film SF.

[0213] The display device 1 may include at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) for mounting control components and various electronic devices.

[0214] The other side of the source film SF, on which the source driver integrated circuit SDIC is mounted, can be connected to at least one source printed circuit board SPCB. That is, one side of the source film SF can be electrically connected to the display panel 50, and the other side of the source film SF can be electrically connected to the source printed circuit board SPCB.

[0215] The timing controller 10 and the power supply unit 40 can be mounted in the control printed circuit board (CPCB). The control printed circuit board (CPCB) can be electrically connected to the source printed circuit board (SPCB) via a flexible flat cable (FFC) or a flexible printed circuit.

[0216] The drive voltage output from the power supply unit 40 can be applied to the display panel 50 via the control printed circuit board (CPCB), flexible flat cable (FFC), source printed circuit board (SPCB), and lines formed on the source film (SF). For this purpose, the input portion of the drive voltage can be located on the display panel 50 near the source driver integrated circuit (SDIC).

[0217] Voltage lines electrically connected to the power supply unit 40 can be provided on the display panel 50. For example, the voltage lines may include a low-potential drive voltage line PL2 that receives a low-potential drive voltage ELVSS. The low-potential drive voltage line PL2 may be formed in the non-display area NA, for example, in the form of a shortening bar. For example, in the non-display area NA adjacent to the source driver integrated circuit SDIC, the low-potential drive voltage line PL2 may be formed as a strip that extends and elongates along one side surface of the display panel 50.

[0218] Multiple metal cup structure layers 310 can be formed on the display panel 50. Each metal cup structure layer 310 can have a linear shape that extends and elongates beyond the display area AA.

[0219] One side of the metal cup structure layer 310 can be electrically connected to the low-potential drive voltage line PL2, which is provided in the form of a shorting bar. When the metal cup structure layer 310 and the low-potential drive voltage line PL2 are disposed in different layers, they can be electrically connected through a contact hole that penetrates one or more insulating layers between them. The metal cup structure layer 310 and the low-potential drive voltage line PL2 can be connected through one or more connecting electrodes between them.

[0220] In one embodiment, the low-potential drive voltage line PL2 can be formed by multiple shorting bars. In such an embodiment, the metal cup structure layers 310 can be grouped when one or more metal cup structure layers 310 are connected to a shorting bar.

[0221] In one embodiment, the other side of the metal cup structure layer 310 can be interconnected via at least one shorting bar on the other side corresponding to the low-potential drive voltage line PL2. However, the embodiment is not limited to this.

[0222] In the illustrated embodiment, instead of the metal cup structure layer 310, the connecting electrode 204 can be electrically connected to the low-potential drive voltage line PL2. Similar to the illustrated metal cup structure layer 310, the connecting electrode 204 can have a linear shape that extends and elongates beyond the display area AA. One side of the connecting electrode 204 can be electrically connected to the low-potential drive voltage line PL2, which is provided in the form of a shorting bar.

[0223] In this embodiment, the metal cup structure layer 310 can be electrically connected to the connection electrode 204 via contact holes. The metal cup structure layer 310 can also be electrically connected to the low-potential drive voltage line PL2 via the connection electrode 204 formed in the display area AA.

[0224] Embodiments of this disclosure have been described with reference to the accompanying drawings. Those skilled in the art will recognize that this disclosure may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered illustrative in all respects and not restrictive. Therefore, the scope of this disclosure is indicated by the appended claims rather than by the foregoing description. All changes within the equivalent meaning and scope of the claims are to be included within the scope of this disclosure.

Claims

1. A display device, comprising: substrate; Anode electrodes are formed on the substrate and patterned to correspond to multiple pixels; A dam formed on the substrate and exposing at least one region of the anode electrode; A light-emitting layer is formed on the anode electrode; A cathode electrode is formed on the light-emitting layer; and The metal cup structure layer is installed on the dike. Metal cup holes are formed between two spaced-apart metal cup structural layers on the dike.

2. The display device according to claim 1, further comprising: A barrier layer formed on the dike and made of non-conductive inorganic material. The two metal cup structure layers are formed to cover one region and the other region of the barrier layer, respectively.

3. The display device according to claim 2, in, The barrier layer is formed in a mesh pattern between the two metal cup structure layers to surround each of the plurality of pixels.

4. The display device according to claim 2, in, The metal cup hole is surrounded by the barrier layer and the two metal cup structural layers.

5. The display device according to claim 1, further comprising: Spacers formed on the metal cup structure layer, The spacer extends from the upper surface of the metal cup structure layer to the upper surface of the dike.

6. The display device according to claim 5, in, The spacer extends further from the upper surface of the dike to cover the side surface of the dike and the edge of the anode electrode.

7. The display device according to claim 6, in, The spacer is further disposed between the barrier and the anode electrode, and is formed as an exposed upper surface of the circuit element layer that is not covered by the barrier.

8. The display device according to claim 1, in, The metal cup structure layer is electrically connected to a low-potential driving voltage. The cathode electrode is formed such that at least one region thereof is in contact with the metal cup structure layer in the metal cup hole.

9. The display device according to claim 1, further comprising: Connection electrodes formed on the substrate, The metal cup structure layer is electrically connected to the connecting electrode through contact holes formed in the partition.

10. The display device according to claim 9, in, The connecting electrode is electrically connected to a low-potential driving voltage. The cathode electrode is formed such that at least one region thereof is in contact with the metal cup structure layer in the metal cup hole.

11. The display device according to claim 8 or 10, comprising: A low-potential drive voltage line in the form of a short-circuit strip is formed on one side of the substrate. The metal cup structure layer or the connecting electrode is electrically connected to the low-potential driving voltage line in the form of a short-circuit strip on one side of the substrate.

12. The display device according to claim 1, in, The metal cup structure layer includes: The lower layer formed on the dike; and The upper layer formed on the lower layer, The lower surface of the upper layer protrudes outward more than the upper surface of the lower layer. The lower layer and the upper layer are formed of conductive inorganic materials.

13. The display device according to claim 12, in, The light-emitting layer extends into the hole of the metal cup and is cut off around the edge of the upper layer.

14. The display device according to claim 13, in, The cathode electrode extends into the metal cup aperture and is formed to contact at least one region of the upper and lower layers in the metal cup aperture.

15. A display device, comprising: A substrate with multiple pixels; Formed on the substrate and configured to define the plurality of pixels; and The metal cup structure layer is installed on the dike. Metal cup holes are formed between two adjacent metal cup structural layers on the dike.

16. The display device according to claim 15, further comprising: A barrier layer is formed on the dike, the barrier layer being formed in a grid pattern to surround each of the plurality of pixels. The two adjacent metal cup structure layers are formed to cover one region and the other region of the barrier layer, respectively. The metal cup hole is surrounded by the barrier layer and the two adjacent metal cup structural layers.

17. The display device according to claim 15, further comprising: Connection electrodes formed on the substrate, The metal cup structure layer is electrically connected to the connecting electrode through contact holes formed in the partition.

18. The display device according to claim 15, further comprising: Spacers formed on the metal cup structure layer, The spacer extends from the upper surface of the metal cup structure layer to the upper surface of the dike.

19. The display device according to claim 18, in, The spacer extends further from the upper surface of the barrier to the side surface of the barrier, and is formed as an exposed upper surface of the circuit element layer that is not covered by the barrier.

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