Display panel and display device

Abstract

The application discloses a display panel and a display device, wherein the display panel comprises a substrate, a bottom shielding layer, an active layer and a multilayer conductive layer; the active layer and the multilayer conductive layer constitute at least one gate drive circuit; the gate drive circuit comprises a first output transistor and a second output transistor; the bottom shielding layer comprises a first shielding layer and a second shielding layer which are in the same layer and not connected; the first shielding layer covers at least part of the normal projection of the channel region of the first output transistor on the substrate; the second shielding layer covers at least part of the normal projection of the channel region of the second output transistor on the substrate; the first gate of the first output transistor and the second output transistor is located in the first conductive layer and is connected to the first shielding layer and the second shielding layer, thereby reducing the threshold voltage Vth offset of the output transistor in the gate drive circuit, improving the output stability of the gate drive circuit and the display effect of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] OLED (Organic Light Emitting Diode) display technology, with its advantages of being thin and light, self-emissive, having a wide viewing angle, fast response speed, low brightness, and low power consumption, has been widely used in the field of high-performance displays.

[0003] Among them, the GIP circuit is an important auxiliary circuit in the display panel, but the GIP circuit still has the problem of unstable output, which affects the display effect of the display panel. Summary of the Invention

[0004] The present invention provides a display panel and display device that reduces the threshold voltage Vth offset of the output transistor in the gate driving circuit, improves the output stability of the gate driving circuit, and thus improves the display effect of the display panel.

[0005] In a first aspect, embodiments of the present invention provide a display panel, comprising:

[0006] Substrate;

[0007] A bottom shielding layer is disposed on one side of the substrate; the bottom shielding layer includes a first shielding layer and a second shielding layer, the first shielding layer and the second shielding layer are located in the same layer and are not connected;

[0008] A multilayer conductive layer is disposed on the side of the bottom shielding layer away from the substrate, the multilayer conductive layer including a first conductive layer; the first conductive layer is located on the side of the first shielding layer away from the substrate;

[0009] An active layer is located between the bottom shielding layer and the first conductive layer;

[0010] The active layer and the multilayer conductive layer constitute at least one gate driving circuit; the gate driving circuit includes a first output transistor and a second output transistor.

[0011] Wherein, the first shielding layer orthogonally projects onto the substrate at least partially covering the orthogonal projection of the channel region of the first output transistor onto the substrate; the second shielding layer orthogonally projects onto the substrate at least partially covering the orthogonal projection of the channel region of the second output transistor onto the substrate; the first gate of the first output transistor and the first gate of the second output transistor are located in the first conductive layer, the first gate of the first output transistor is connected to the first shielding layer, and the first gate of the second output transistor is connected to the second shielding layer.

[0012] Optionally, the active layer includes a first active layer; the first active layer extends along a first direction, and the channel regions of the first output transistor and the second output transistor are located in the first active layer;

[0013] Optionally, the orthographic projection of the first gate of the first output transistor on the substrate at least partially covers the orthographic projection of the channel region of the first output transistor on the substrate; the orthographic projection of the first gate of the second output transistor on the substrate at least partially covers the orthographic projection of the channel region of the second output transistor on the substrate.

[0014] Optionally, the channel regions of the first output transistor and the second output transistor are arranged along the first direction.

[0015] Optionally, the bottom shielding layer further includes a third shielding layer, which is on the same layer as the first shielding layer and the second shielding layer but not connected to them;

[0016] Optionally, the active layer includes a second active layer; the second active layer is on the same layer as the first active layer but not connected; the gate driving circuit further includes a plurality of control transistors;

[0017] The channel regions of the plurality of control transistors are located in the second active layer, and the third shielding layer at least partially covers the orthographic projection of the channel regions of the plurality of control transistors onto the substrate.

[0018] Preferably, the third shielding layer is connected to a signal with a constant voltage;

[0019] Optionally, the first shielding layer includes a first conductive portion extending along a first direction and a plurality of second conductive portions extending along a second direction, the second conductive portions being spaced apart along the first direction; one end of each of the second conductive portions is connected to the first conductive portion.

[0020] The second conductive portion projects onto the substrate in a positive projection that at least partially covers the positive projection of the channel region of the first output transistor onto the substrate; the second direction intersects the first direction;

[0021] Preferably, the second shielding layer includes a third conductive portion extending along a first direction and a plurality of fourth conductive portions extending along a second direction, the fourth conductive portions being spaced apart along the first direction; one end of each fourth conductive portion is connected to the third conductive portion.

[0022] The orthographic projection of the fourth conductive portion onto the substrate at least partially covers the orthographic projection of the channel region of the second output transistor onto the substrate.

[0023] Optionally, the first conductive layer includes a first sub-conductive layer and a second sub-conductive layer; the first sub-conductive layer and the second sub-conductive layer are on the same layer and are not connected; the first gate of the first output transistor is located in the first sub-conductive layer, and the first gate of the second output transistor is located in the second sub-conductive layer;

[0024] Optionally, the first sub-conductive layer includes a fifth conductive portion extending along the first direction and a plurality of sixth conductive portions extending along the second direction, the sixth conductive portions being spaced apart along the first direction; one end of each sixth conductive portion is connected to the fifth conductive portion.

[0025] The orthographic projection of the sixth conductive portion onto the substrate at least partially covers the orthographic projection of the channel region of the first output transistor onto the substrate;

[0026] Optionally, the second sub-conductive layer includes a seventh conductive portion extending along the first direction and a plurality of eighth conductive portions extending along the second direction, the eighth conductive portions being spaced apart along the first direction; one end of each eighth conductive portion is connected to the seventh conductive portion.

[0027] The eighth conductive portion projects onto the substrate in a positive projection that at least partially covers the positive projection of the channel region of the second output transistor onto the substrate.

[0028] Optionally, the first shielding layer further includes a first extension, which is connected to the first conductive portion or the second conductive portion; the first sub-conductive layer further includes a second extension, which is connected to the fifth conductive portion or the sixth conductive portion.

[0029] Wherein, the orthographic projection of the first extension on the substrate does not overlap with the orthographic projection of the first active layer on the substrate, the orthographic projection of the second extension on the substrate does not overlap with the orthographic projection of the first active layer on the substrate, and the first extension is connected to the second extension through a first via; the orthographic projection of the first via on the substrate overlaps at least with the orthographic projection of the first extension on the substrate, and the orthographic projection of the first via on the substrate overlaps at least with the orthographic projection of the second extension on the substrate;

[0030] Optionally, the second shielding layer further includes a third extension, which is connected to the third conductive portion or the fourth conductive portion; the second sub-conductive layer further includes a fourth extension, which is connected to the seventh conductive portion or the eighth conductive portion.

[0031] Wherein, the orthographic projection of the third extension on the substrate does not overlap with the orthographic projection of the first active layer on the substrate, the orthographic projection of the fourth extension on the substrate does not overlap with the orthographic projection of the first active layer on the substrate, the third extension is connected to the fourth extension through a second via, the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the third extension on the substrate at least, and the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the fourth extension on the substrate at least.

[0032] Optionally, the first extension extends along the first direction or the second direction, and the orthographic projection of the first extension on the substrate and the orthographic projection of the second extension on the substrate at least partially overlap.

[0033] Optionally, the first shielding layer further includes a first extension, which is connected to the first conductive portion or the second conductive portion; the first sub-conductive layer further includes a second extension, which is connected to the fifth conductive portion or the sixth conductive portion.

[0034] The multilayer conductive layer further includes a second conductive layer located on the side of the first conductive layer away from the substrate; the second conductive layer includes a first connecting line; a first end of the first connecting line is connected to the first extension through a third via; a second end of the first connecting line is connected to the second extension through a fourth via.

[0035] Wherein, the orthographic projection of the third via on the substrate overlaps with the orthographic projection of the first extension on the substrate; the orthographic projection of the fourth via on the substrate overlaps with the orthographic projection of the second extension on the substrate;

[0036] Optionally, the first extension extends along the first direction or the second direction, and the orthographic projection of the first extension on the substrate and the orthographic projection of the second extension on the substrate do not overlap at least partially.

[0037] Optionally, the second shielding layer further includes a third extension, which is connected to the third conductive portion or the fourth conductive portion; the second sub-conductive layer further includes a fourth extension, which is connected to the seventh conductive portion or the eighth conductive portion.

[0038] The second conductive layer further includes a second connecting line; a first end of the second connecting line is connected to the third extension through a fifth via; a second end of the second connecting line is connected to the fourth extension through a sixth via.

[0039] Wherein, the orthographic projection of the fifth via on the substrate overlaps with the orthographic projection of the third extension on the substrate; the orthographic projection of the sixth via on the substrate overlaps with the orthographic projection of the fourth extension on the substrate;

[0040] Optionally, the third extension extends along the first direction or the second direction, and the orthographic projection of the third extension on the substrate and the orthographic projection of the fourth extension on the substrate do not overlap at least partially.

[0041] Optionally, the overlapping area of ​​the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first active layer on the substrate at least covers the overlapping area of ​​the orthographic projection of the sixth conductive portion on the substrate and the orthographic projection of the first active layer on the substrate.

[0042] The overlapping area of ​​the orthographic projection of the fourth conductive part on the substrate and the orthographic projection of the first active layer on the substrate at least covers the overlapping area of ​​the orthographic projection of the eighth conductive part on the substrate and the orthographic projection of the first active layer on the substrate.

[0043] Secondly, embodiments of the present invention provide a display device, including the display panel described in any embodiment of the present invention.

[0044] The technical solution provided by this invention provides a first shielding layer and a second shielding layer at corresponding positions of the first and second output transistors. These layers block downward light, reducing the impact of light irradiation on device characteristics. Furthermore, the first gate of the first output transistor is connected to the first shielding layer, which serves as the second gate of the first output transistor, forming a double-gate structure. Similarly, the first gate of the second output transistor is connected to the second shielding layer, which serves as the second gate of the second output transistor, also forming a double-gate structure. This double-gate structure reduces the threshold voltage Vth offset of the first and second output transistors, improving electron mobility and thus enhancing the output stability of the gate driving circuit and improving the display effect of the display panel. Attached Figure Description

[0045] Figure 1 This is a top view structural diagram of a display panel provided in an embodiment of the present invention;

[0046] Figure 2 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention;

[0047] Figure 3 This is a top view of the bottom shielding layer in a display panel according to an embodiment of the present invention.

[0048] Figure 4for Figure 1 A partial top view of the first conductive layer in the middle;

[0049] Figure 5 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention;

[0050] Figure 6 for Figure 1 A top view of a portion of the bottom shielding layer;

[0051] Figure 7 A top view of another display panel provided in an embodiment of the present invention;

[0052] Figure 8 A cross-sectional structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0053] Figure 9 A cross-sectional structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0054] Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] In gate drive circuits, transistor devices often have a bottom shield metal (BSM) structure. In TFT devices with a BSM, connecting the BSM to a DC potential can shield the transistor from the effects of static electricity. However, connecting the BSM to a DC potential increases the electric field, forming a depletion layer at the bottom of the channel. This reduces the current path and mobility, leading to a negative bias in the threshold voltage Vth. Even when the BSM is connected to 0V, the negative bias of Vth still exists, causing unstable output of the Gip circuit and affecting the display effect of the display panel.

[0057] In view of this, embodiments of the present invention provide a display panel that improves the stability of circuit output by optimizing the layout of the gate driving circuit. Figure 1 This is a top view schematic diagram of a display panel provided in an embodiment of the present invention. Figure 2 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention, specifically... Figure 1 The cross-sectional structure of the display panel shown is obtained along the cutting line aa' or cutting line bb', for reference. Figures 1-2 The display panel provided in this embodiment of the invention includes:

[0058] Substrate 11;

[0059] A bottom shielding layer 12 is disposed on one side of the substrate 11; the bottom shielding layer 12 includes a first shielding layer 121 and a second shielding layer 122, the first shielding layer 121 and the second shielding layer 122 are located in the same layer and are not connected.

[0060] A multilayer conductive layer is disposed on the side of the bottom shielding layer 12 away from the substrate 11. The multilayer conductive layer includes a first conductive layer 13. The first conductive layer 13 is located on the side of the first shielding layer 121 away from the substrate 11.

[0061] The active layer 14 is located between the bottom shielding layer 12 and the first conductive layer 13;

[0062] The active layer 14 and the multilayer conductive layers constitute at least one gate driving circuit; the gate driving circuit includes a first output transistor Q1 and a second output transistor Q2.

[0063] The first shielding layer 121 projects onto the substrate 11 in a positive projection that at least partially covers the projection of the channel region T1 of the first output transistor Q1 onto the substrate 11; the second shielding layer 122 projects onto the substrate 11 in a positive projection that at least partially covers the projection of the channel region T2 of the second output transistor Q2 onto the substrate 11; the first gate G1 of the first output transistor Q1 and the first gate G1 of the second output transistor Q2 are located in the first conductive layer 13, the first gate G1 of the first output transistor Q1 is connected to the first shielding layer 121, and the first gate G1 of the second output transistor Q2 is connected to the second shielding layer 122.

[0064] Specifically, the substrate 11 can provide protection and support for the array substrate. The substrate 11 can be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET), or a rigid substrate formed of materials such as glass. A bottom shielding layer 12 (BSM) is disposed on one side of the substrate 11. The bottom shielding layer 12 can shield the channel region of the transistor device in the gate drive circuit and block external light from below the device, reducing the influence of light on the characteristics of the transistor device. Multiple conductive layers are disposed on the side of the bottom shielding layer 12 away from the substrate 11. Insulating layers are disposed between the multiple conductive layers and the bottom shielding layer 12, and the multiple conductive layers are isolated from each other by insulating layers. An active layer 14 is disposed between the first shielding layer 121 and the first conductive layer 13. For example, a first insulating layer 15 is disposed between the active layer 14 and the bottom shielding layer 12, and a second insulating layer 16 is disposed between the active layer 14 and the first conductive layer 13.

[0065] The active layer 14 and the multilayer conductive layers can form multiple gate driving circuits. These gate driving circuits output gate control signals from the pixel driving circuits to control the operation of the pixel driving circuits in the display panel. The gate driving circuits can be any of the following: 7T2C, 9T2C, 12T3C, and 16T4C. In the gate driving circuit, the first terminal of the first output transistor Q1 is connected to the first signal line, the second terminal of the first output transistor Q1 is connected to the first terminal of the second output transistor Q2, and the second terminal of the second output transistor Q2 is connected to the second signal line. The first signal line provides the first signal PVGH, and the second signal line provides the second signal PVGL. The second terminals of the first output transistor Q1 and the first terminals of the second output transistor Q2 are connected to the output signal line GOUT. The gate driving circuit also includes multiple control transistors and multiple capacitors. The first output transistor Q1, in conjunction with the control transistors and capacitors at the front end, outputs the first signal PVGH, or the second output transistor Q2, in conjunction with the control transistors and capacitors at the front end, outputs the second signal PVGL.

[0066] In this embodiment of the invention, the bottom shielding layer 12 includes a first shielding layer 121 and a second shielding layer 122. The first shielding layer 121 and the second shielding layer 122 are disposed on the same layer but not connected. The orthographic projection of the first shielding layer 121 onto the substrate 11 at least covers the orthographic projection of the channel region T1 of the first output transistor Q1 onto the substrate 11. That is, the first shielding layer 121 can shield the channel region T1 of the first output transistor Q1, thereby blocking light from below the first output transistor Q1 and reducing the impact of light on the device characteristics. The orthographic projection of the second shielding layer 122 onto the substrate 11 at least covers the orthographic projection of the channel region T2 of the second output transistor Q2 onto the substrate 11. That is, the second shielding layer 122 can shield the channel region T2 of the second output transistor Q2, thereby blocking light from below the second output transistor Q2 and reducing the impact of light on the device characteristics.

[0067] The first gate G1 of the first output transistor Q1 is connected to the first shielding layer 121. The first gate G1 and the first shielding layer 121 are located on different conductive layers and can be electrically connected via vias. A short circuit is formed between the first gate G1 and the first shielding layer 121, ensuring they have the same potential. The first shielding layer 121 can serve as the second gate of the first output transistor Q1, forming a dual-gate structure, which reduces the threshold voltage Vth offset of the first output transistor Q1. Furthermore, when the channel of the first output transistor Q1 is turned on, the bottom region of the channel also becomes conductive, thereby improving electron mobility. Therefore, while meeting mobility requirements, the device size of the first output transistor Q1 can be optimized and reduced, which is beneficial for narrow bezel designs.

[0068] Similarly, the first gate G1 of the second output transistor Q2 is connected to the second shielding layer 122. The first gate G1 and the second shielding layer 122 are located on different conductive layers, and an electrical connection can be achieved between them vias. A short circuit is formed between the first gate G1 and the second shielding layer 122, and they have the same potential. The second shielding layer 122 can serve as the second gate of the second output transistor Q2, forming a dual-gate structure, which reduces the threshold voltage Vth offset of the second output transistor Q2. Furthermore, when the channel of the second output transistor Q2 is turned on, the bottom region of the channel also becomes conductive, thereby improving electron mobility. Therefore, while meeting mobility requirements, the device size of the second output transistor Q2 can be optimized and reduced, which is beneficial for narrow bezel designs.

[0069] The technical solution provided by this invention provides a first shielding layer 121 and a second shielding layer 122 respectively at corresponding positions of the first output transistor Q1 and the second output transistor Q2. The first shielding layer 121 and the second shielding layer 122 can block the light from below, reducing the impact of light irradiation on the device characteristics. Furthermore, the first gate G1 of the first output transistor Q1 is connected to the first shielding layer 121, using the first shielding layer 121 as the second gate of the first output transistor Q1, forming a double-gate structure. Similarly, the first gate G1 of the second output transistor Q2 is connected to the second shielding layer 122, using the second shielding layer 122 as the second gate of the second output transistor Q2, also forming a double-gate structure. This double-gate structure reduces the threshold voltage Vth offset of the first output transistor Q1 and the second output transistor Q2, improving electron mobility and thus enhancing the output stability of the gate driving circuit and improving the display effect of the display panel.

[0070] See also Figure 1 The active layer 14 includes a first active layer 141; the first active layer 141 extends along a first direction X, and the channel region T1 of the first output transistor Q1 and the channel region T2 of the second output transistor Q2 are located in the first active layer 141.

[0071] Specifically, the first active layer 141 has a channel region T1 for a first output transistor Q1 and a channel region T2 for a second output transistor Q2. The channel region T1 of the first output transistor Q1 has its first electrode and second electrode on either side in the first direction X, respectively. Similarly, the channel region T2 of the second output transistor Q2 has its first electrode and second electrode on either side in the first direction X, respectively. By placing the channel regions T1 and T2 of the first and second output transistors on the same first active layer 141, the connection trace between the second electrode of the first output transistor Q1 and the first electrode of the second output transistor Q2 can be omitted, thus simplifying the wiring layout.

[0072] Optionally, the channel region T1 of the first output transistor Q1 and the channel region T2 of the second output transistor Q2 are arranged along the first direction X, which can reduce the width in the second direction Y. For example, when the second direction Y is the extension direction of the bezel width, it can be beneficial for the narrow bezel design of the display panel.

[0073] See also Figure 2 Optionally, the first gate G1 of the first output transistor Q1 is projected onto the substrate 11 in a positive projection that at least partially covers the positive projection of the channel region T1 of the first output transistor Q1 onto the substrate 11; the first gate G1 of the second output transistor Q2 is projected onto the substrate 11 in a positive projection that at least partially covers the positive projection of the channel region T2 of the second output transistor Q2 onto the substrate 11.

[0074] Specifically, to ensure the control capability of the first gate G1 of the first output transistor Q1 over the channel region T1 of the first output transistor Q1, the first gate G1 of the first output transistor Q1 at least covers the channel region T1 of the first output transistor Q1 in the orthogonal projection direction. In some embodiments, the orthogonal projection of the first gate G1 of the first output transistor Q1 on the substrate 11 may exceed a certain length of the orthogonal projection of the channel region T1 of the first output transistor Q1 on the substrate 11, further improving the control capability of the first gate G1 over the channel region.

[0075] Similarly, the first gate G1 of the second output transistor Q2 can cover the channel region T2 of the second output transistor Q2 in the orthogonal projection direction. In some embodiments, the orthogonal projection of the first gate G1 of the second output transistor Q2 on the substrate 11 can exceed a certain length of the orthogonal projection of the channel region T2 of the second output transistor Q2 on the substrate 11, further improving the control capability of the first gate G1 over the channel region.

[0076] Figure 3 This is a top view schematic diagram of the bottom shielding layer in a display panel according to an embodiment of the present invention. See also: Figure 3 The bottom shielding layer 12 also includes a third shielding layer 123, which is on the same layer as the first shielding layer 121 and the second shielding layer 122 but not connected; the third shielding layer 123 orthogonally projects onto the substrate 11 to at least partially cover the orthogonal projection of the channel regions of the plurality of control transistors onto the substrate 11.

[0077] Specifically, the active layer 14 also includes a second active layer; the second active layer is on the same layer as the first active layer 141 but not connected; the channel regions of the multiple control transistors are located in the second active layer, which is disposed on one side of the first active layer 141; the third shielding layer 123 can be used to shield the channel regions of the multiple control transistors, thereby blocking the light below each control transistor and reducing the impact of light irradiation on device characteristics. The third shielding layers 123 corresponding to each control transistor can be interconnected, and the third shielding layers 123 can be connected to a constant potential, such as around 0V, thereby reducing the static charge accumulated in the substrate 11, shielding the impact of static electricity on each control transistor, and further improving the output stability of the gate drive circuit.

[0078] Combination Figure 1 , Figure 4 for Figure 1 A partial top view of the first conductive layer is shown in the diagram. Figure 4The first conductive layer 13 includes a first sub-conductive layer 131 and a second sub-conductive layer 132; the first sub-conductive layer 131 and the second sub-conductive layer 132 are on the same layer but not connected; the first gate G1 of the first output transistor Q1 is located on the first sub-conductive layer 131, and the first gate G1 of the second output transistor Q2 is located on the second sub-conductive layer; that is, the first gate G1 of the first output transistor Q1 is disposed on the first sub-conductive layer 131, and the first gate G1 of the second output transistor Q2 is disposed on the second sub-conductive layer 132.

[0079] Optionally, the first sub-conductive layer 131 includes a fifth conductive portion 21 extending along the first direction X and a plurality of sixth conductive portions 22 extending along the second direction Y, the sixth conductive portions 22 being spaced apart along the first direction X; one end of the sixth conductive portion 22 is connected to the fifth conductive portion 21.

[0080] The sixth conductive portion 22 is projected onto the substrate 11 in a positive projection that at least partially covers the positive projection of the channel region T1 of the first output transistor Q1 onto the substrate 11.

[0081] Specifically, multiple conductive strips extending along the second direction Y serve as sixth conductive portions 22, and these sixth conductive portions 22 are arranged at intervals along the first direction X, forming a comb-like structure. One end of each sixth conductive portion 22 can be connected to a fifth conductive portion 21 extending along the first direction X. The fifth conductive portion 21 and the sixth conductive portion 22 can be an integral structure or separate structures; no specific limitation is made here. Figure 5 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention, specifically... Figure 1 The cross-sectional structure of the display panel shown is obtained along the cutting line cc' or dd', combined with... Figure 4 See Figure 5Each sixth conductive portion 22 intersects with the first active layer 141 in the orthographic projection direction. The channel region T1 of the first output transistor Q1 can be disposed on the first active layer 141 below the sixth conductive portion 22. The sixth conductive portion 22 can serve as the first gate G1 of the first output transistor Q1. By setting multiple sixth conductive portions 22 to form a comb-like structure, the overall width-to-length ratio of the channel region T1 of the first output transistor Q1 can be improved, providing better conductivity and conduction speed, which is beneficial to improving the performance of the first output transistor Q1. For example, one end of each sixth conductive portion 22 on the same side is connected to the fifth conductive portion 21. The fifth conductive portion 21 can be provided with an extension region 211 of a certain size in the direction away from the sixth conductive portion 22. The extension region 211 of the fifth conductive portion 21 can be reused as one plate of a capacitor connected to the first output transistor Q1 in the gate drive circuit. The other plate of the capacitor can be disposed in the third conductive layer, wherein the third conductive layer is located on the side of the first conductive layer 13 away from the substrate 11. When referring to the second conductive layer below, the third conductive layer can be disposed between the first conductive layer 13 and the second conductive layer.

[0082] Combination Figure 1 See also Figure 4 and Figure 5 Optionally, the second sub-conductive layer 132 includes a seventh conductive portion 23 extending along the first direction X and a plurality of eighth conductive portions 24 extending along the second direction Y, the eighth conductive portions 24 being spaced apart along the first direction X; one end of the eighth conductive portion 24 is connected to the seventh conductive portion 23.

[0083] The eighth conductive portion 24 is projected onto the substrate 11 in a positive projection that at least partially covers the positive projection of the channel region T2 of the second output transistor Q2 onto the substrate 11.

[0084] Specifically, multiple conductive strips extending along the second direction Y serve as eighth conductive portions 24, and these eighth conductive portions 24 are spaced apart along the first direction X, forming a comb-like structure. One end of each eighth conductive portion 24 can be connected to a seventh conductive portion 23 extending along the first direction X. Depending on layout design requirements, multiple segments of the seventh conductive portion 23 can also be provided. In this embodiment, one seventh conductive portion 23 can be connected to one end of a portion of the eighth conductive portion 24, and another seventh conductive portion 23 can be connected to the other end of another portion of the eighth conductive portion 24. Two segments of the seventh conductive portion 23 are connected to a common eighth conductive portion 24, thereby allowing the seventh conductive portion 23 and the eighth conductive portion 24 to form an integrated conductive structure. The seventh conductive portion 23 and the eighth conductive portion 24 can be an integrated structure or separate structures; no specific limitation is made here. Each of the eighth conductive portions 24 intersects with the first active layer 141 in the orthographic projection direction. The channel region T2 of the second output transistor Q2 can be disposed on the first active layer 141 below the eighth conductive portion 24, and the eighth conductive portion 24 can serve as the first gate G1 of the second output transistor Q2. By setting multiple eighth conductive portions 24 to form a comb-like structure, the overall width-to-length ratio of the channel region T2 of the second output transistor Q2 can be improved, providing better conductivity and conduction speed, which is beneficial to improving the performance of the second output transistor Q2.

[0085] Figure 6 for Figure 1 A top-view structural diagram of a portion of the bottom shielding layer, combined with... Figure 1 and Figure 4 See Figure 6 Optionally, the first shielding layer 121 includes a first conductive portion 31 extending along a first direction X and a plurality of second conductive portions 32 extending along a second direction Y, the second conductive portions 32 being spaced apart along the first direction X; one end of the second conductive portion 32 is connected to the first conductive portion 31.

[0086] The second conductive portion 32 is projected onto the substrate 11 in a positive projection that at least partially covers the positive projection of the channel region T1 of the first output transistor Q1 onto the substrate 11; the second direction Y intersects the first direction X;

[0087] Specifically, multiple conductive strips extending along the second direction Y serve as second conductive portions 32, and these second conductive portions 32 are spaced apart in the first direction X, similarly forming a comb-like structure. The orthographic projection of the second conductive portions 32 onto the substrate 11 at least partially covers the orthographic projection of the channel region T1 of the first output transistor Q1 onto the substrate 11, thereby using the second conductive portions 32 to block external light. In some embodiments, to avoid process deviations and ensure effective blocking by the second conductive portions 32, the overlapping area of ​​the orthographic projection of the second conductive portion 32 onto the substrate 11 and the orthographic projection of the first active layer 141 onto the substrate 11 can at least cover the overlapping area of ​​the orthographic projection of the sixth conductive portion 22 onto the substrate 11 and the orthographic projection of the first active layer 141 onto the substrate 11. In this embodiment of the invention, the width dimension of the second conductive portion 32 in the first direction X is at least greater than or equal to the width dimension of the sixth conductive portion 22 in the first direction X, thereby ensuring effective blocking of the channel region T1 of the first output transistor Q1 by the second conductive portion 32.

[0088] One end of the second conductive part 32 on the same side is connected to the first conductive part 31, so that the first conductive part 31 and the second conductive part 32 can form an integral conductive structure. The first conductive part 31 and the second conductive part 32 can be an integral structure or a separate structure, and there is no specific limitation. In some embodiments, the first shielding layer 121 may also be provided with two sets of first conductive parts 31, which are respectively provided at both ends of the second conductive part 32, so that the second conductive parts 32 are connected in parallel, thereby reducing the overall line resistance of the first shielding layer 121.

[0089] Optionally, the second shielding layer 122 includes a third conductive portion 33 extending along the first direction X and a plurality of fourth conductive portions 34 extending along the second direction Y, the fourth conductive portions 34 being spaced apart along the first direction X; one end of the fourth conductive portion 34 is connected to the third conductive portion 33.

[0090] The fourth conductive portion 34 is projected onto the substrate 11 in a positive projection that at least partially covers the positive projection of the channel region T2 of the second output transistor Q2 onto the substrate 11.

[0091] Specifically, multiple conductive strips extending along the second direction Y serve as fourth conductive portions 34, and these fourth conductive portions 34 are spaced apart in the first direction X, similarly forming a comb-like structure. The orthographic projection of the fourth conductive portion 34 onto the substrate 11 at least partially covers the orthographic projection of the channel region T2 of the second output transistor Q2 onto the substrate 11, thereby using the fourth conductive portion 34 to block external light. In some embodiments, to avoid process deviations and ensure effective blocking by the fourth conductive portion 34, the overlapping area of ​​the orthographic projection of the fourth conductive portion 34 onto the substrate 11 and the orthographic projection of the first active layer 141 onto the substrate 11 can at least cover the overlapping area of ​​the orthographic projection of the eighth conductive portion 24 onto the substrate 11 and the orthographic projection of the first active layer 141 onto the substrate 11. In this embodiment of the invention, the width dimension of the fourth conductive portion 34 in the first direction X is at least greater than or equal to the width dimension of the eighth conductive portion 24 in the first direction X, thereby ensuring effective blocking of the channel region T2 of the second output transistor Q2 by the fourth conductive portion 34.

[0092] One end of the fourth conductive part 34 on the same side is connected to the third conductive part 33, so that the third conductive part 33 and the fourth conductive part 34 can form an integral conductive structure. The third conductive part 33 and the fourth conductive part 34 can be an integral structure or a separate structure, without specific limitation. In some embodiments, the first shielding layer 121 may also be provided with two sets of third conductive parts 33, which are respectively provided at both ends of the fourth conductive part 34, so that the fourth conductive parts 34 are connected in parallel, thereby reducing the overall line resistance of the second shielding layer 122.

[0093] Figure 7 This is a top view structural diagram of another display panel provided in an embodiment of the present invention, combined with... Figure 4 and Figure 6 See Figure 7 Optionally, the first shielding layer 121 further includes a first extension 35, which is connected to the first conductive part 31 or the second conductive part 32; the first sub-conductive layer 131 further includes a second extension 25, which is connected to the fifth conductive part 21 or the sixth conductive part 22.

[0094] Wherein, the orthographic projection of the first extension 35 on the substrate 11 does not overlap with the orthographic projection of the first active layer 141 on the substrate 11, and the orthographic projection of the second extension 25 on the substrate 11 does not overlap with the orthographic projection of the first active layer 141 on the substrate 11. The first extension 35 is connected to the second extension 25 through a first via. The orthographic projection of the first via on the substrate 11 overlaps at least with the orthographic projection of the first extension 35 on the substrate 11, and the orthographic projection of the first via on the substrate 11 overlaps at least with the orthographic projection of the second extension 25 on the substrate 11.

[0095] Specifically, the first extension 35 can be connected to the first conductive part 31, or the first extension 35 can be connected to the second conductive part 32. In this embodiment of the invention, based on the wiring spacing and the requirement of not affecting the narrow bezel design, the first extension 35 can be configured to be connected to the first conductive part 31, and the first extension 35, the first conductive part 31, and the second conductive part 32 form a conductive structure. For the second extension 25, it can be connected to the fifth conductive part 21, or it can be connected to the sixth conductive part 22, and the second extension 25, the fifth conductive part 21, and the sixth conductive part 22 form a conductive structure. In this embodiment of the invention, the second extension 25 is configured to be connected to the fifth conductive part 21. The first extension 35 and the second extension 25 are configured as different layers, and the first extension 35 and the second extension 25 are electrically connected through the first via 41. To prevent the first via 41 from passing through the first active layer 141, the orthographic projection of the first extension 35 on the substrate 11 does not overlap with the orthographic projection of the first active layer 141 on the substrate 11, and the orthographic projection of the second extension 25 on the substrate 11 does not overlap with the orthographic projection of the first active layer 141 on the substrate 11. In other words, the first active layer 141 is not provided between the first extension 35 and the second extension 25, and the first via 41 can be provided in the insulating layer between the first extension 35 and the second extension 25, so that the first extension 35 and the second extension 25 can be connected.

[0096] It should be noted that the extension direction of the first extension 35 can be either the first direction X or the second direction Y, and the orthographic projection of the first extension 35 on the substrate 11 at least partially overlaps with the orthographic projection of the second extension 25 on the substrate 11. A first via 41 can be correspondingly disposed at the overlapping position to ensure that the first extension 35 and the second extension 25 can be connected. In this embodiment of the invention, both the first extension 35 and the second extension 25 extend along the second direction Y.

[0097] Combination Figure 4 , Figure 6 and Figure 7 Optionally, the second shielding layer 122 further includes a third extension 36, which is connected to the third conductive part 33 or the fourth conductive part 34; the second sub-conductive layer 132 further includes a fourth extension 26, which is connected to the seventh conductive part 23 or the eighth conductive part 24.

[0098] Wherein, the orthographic projection of the third extension 36 on the substrate 11 does not overlap with the orthographic projection of the first active layer 141 on the substrate 11, the orthographic projection of the fourth extension on the substrate 11 does not overlap with the orthographic projection of the first active layer 141 on the substrate 11, the third extension 36 is connected to the fourth extension 26 through the second via, the orthographic projection of the second via on the substrate 11 overlaps with the orthographic projection of the third extension 36 on the substrate 11 at least, and the orthographic projection of the second via on the substrate 11 overlaps with the orthographic projection of the fourth extension 26 on the substrate 11 at least.

[0099] Specifically, the third extension 36 can be connected to the third conductive part 33, or the third extension 36 can be connected to the fourth conductive part 34. In this embodiment of the invention, based on the wiring spacing and the requirement of not affecting the narrow bezel design, the third extension 36 can be configured to be connected to the third conductive part 33, and the third extension 36, the third conductive part 33, and the fourth conductive part 34 form a conductive structure. For the fourth extension 26, it can be connected to the seventh conductive part 23, or it can be connected to the eighth conductive part 24, and the fourth extension 26, the seventh conductive part 23, and the eighth conductive part 24 form a conductive structure. In this embodiment of the invention, the fourth extension 26 is configured to be connected to the seventh conductive part 23. The third extension 36 and the fourth extension 26 are configured on different layers, and the third extension 36 and the fourth extension 26 are electrically connected through the second via 42. To prevent the second via 42 from passing through the first active layer 141, the orthographic projection of the third extension 36 on the substrate 11 does not overlap with the orthographic projection of the first active layer 141 on the substrate 11, and the orthographic projection of the fourth extension 26 on the substrate 11 does not overlap with the orthographic projection of the first active layer 141 on the substrate 11. In other words, the first active layer 141 is not provided between the third extension 36 and the fourth extension 26, and the second via 42 can be provided in the insulating layer between the third extension 36 and the fourth extension 26, so that the third extension 36 and the fourth extension 26 can be connected.

[0100] It should be noted that the extension direction of the third extension 36 can be either the first direction X or the second direction Y, and the orthographic projection of the third extension 36 on the substrate 11 at least partially overlaps with the orthographic projection of the fourth extension 26 on the substrate 11. The second via 42 can be correspondingly disposed at the overlapping position to ensure that the third extension 36 and the fourth extension 26 can be connected. In this embodiment of the invention, both the third extension 36 and the fourth extension 26 extend along the fourth direction.

[0101] Figure 8 This is a cross-sectional structural diagram of another display panel provided in an embodiment of the present invention, specifically... Figure 1 The cross-sectional structure of the display panel shown is obtained along the cutting line ee', combined with Figure 1 , Figure 4 and Figure 6 See Figure 8 The multilayer conductive layer also includes a second conductive layer, which is located on the side of the first conductive layer 13 away from the substrate 11; the second conductive layer includes a first connecting line 51; the first end of the first connecting line 51 is connected to the first extension 35 through a third via 43; the second end of the first connecting line 51 is connected to the second extension 25 through a fourth via 44.

[0102] Among them, the orthographic projection of the third via 43 on the substrate 11 overlaps with the orthographic projection of the first extension 35 on the substrate 11; the orthographic projection of the fourth via 44 on the substrate 11 overlaps with the orthographic projection of the second extension 25 on the substrate 11.

[0103] Specifically, the second conductive layer includes multiple connecting lines for wiring connections between various control transistors, multiple capacitors, the first output transistor Q1, and the second output transistor Q2. Among the multiple connecting lines is a first connecting line 51. A third via 43 and a fourth via 44 are respectively provided on the insulating layer between the first extension 35 and the second extension 25. The third via 43 can expose a portion of the first extension 35, and the fourth via 44 can expose a portion of the second extension 25. The two ends of the first connecting line 51 can be connected to the first extension 35 and the second extension 25 through the third via 43 and the fourth via 44, respectively.

[0104] The orthographic projection of the first extension 35 on the substrate 11 and the orthographic projection of the first active layer 141 on the substrate 11 do not overlap at least partially. The third via 43 can be disposed on the insulating layer at the corresponding non-overlapping position, thereby preventing the third via 43 from passing through the first active layer 141. To reduce the bridging trace length of the first connecting line 51, the extension directions of the first extension 35 and the second extension 25 can be the same, and the orthographic projection of the first extension 35 on the substrate 11 and the orthographic projection of the second extension 25 on the substrate 11 do not overlap at least partially. The third via 43 can be disposed on the insulating layer at the corresponding non-overlapping position. Corresponding to the position of the second extension 25, a fourth via 44 can be disposed on the insulating layer between the second extension 25 and the first connecting line 51, thereby achieving the bridging of the first extension 35 and the second extension 25 through the first connecting line 51. In terms of fabrication process, only the corresponding vias need to be added, and each film layer can still be fabricated according to the original process without affecting the original fabrication process flow.

[0105] Figure 9 This is a cross-sectional structural diagram of another display panel provided in an embodiment of the present invention, specifically... Figure 1 The cross-sectional structure of the display panel shown is obtained along the cutting line ff', combined with Figure 1 , Figure 4 and Figure 6 See Figure 9The second conductive layer also includes a second connecting line 52; the first end of the second connecting line 52 is connected to the third extension 36 through the fifth via 45; the second end of the second connecting line 52 is connected to the fourth extension 26 through the sixth via 46.

[0106] Among them, the orthographic projection of the fifth via 45 on the substrate 11 overlaps with the orthographic projection of the third extension 36 on the substrate 11; the orthographic projection of the sixth via 46 on the substrate 11 overlaps with the orthographic projection of the fourth extension 26 on the substrate 11.

[0107] Specifically, the multiple connecting lines also include a second connecting line 52. A fifth via 45 and a sixth via 46 are respectively provided on the insulating layer between the third extension 36 and the fourth extension 26. The fifth via 45 can expose a portion of the third extension 36, and the sixth via 46 can expose a portion of the fourth extension 26. The two ends of the second connecting line 52 can be connected to the third extension 36 and the fourth extension 26 through the fifth via 45 and the sixth via 46 respectively.

[0108] The orthographic projection of the third extension 36 on the substrate 11 does not overlap with the orthographic projection of the first active layer 141 on the substrate 11 at least partially. The fifth via 45 can be disposed on the insulating layer at the corresponding non-overlapping position, thereby preventing the fifth via 45 from passing through the first active layer 141. To reduce the bridging trace length of the second connecting line 52, the extension directions of the third extension 36 and the fourth extension 26 can be the same, and the orthographic projection of the third extension 36 on the substrate 11 does not overlap with the orthographic projection of the fourth extension 26 on the substrate 11 at least partially. The fifth via 45 can be disposed on the insulating layer at the non-overlapping position. Corresponding to the position of the fourth extension 26, a sixth via 46 can be disposed on the insulating layer between the fourth extension 26 and the second connecting line 52, thereby achieving the bridging of the third extension 36 and the fourth extension 26 through the second connecting line 52. In terms of fabrication process, only the corresponding vias need to be added, and each film layer can still be fabricated according to the original process without affecting the original fabrication process flow.

[0109] Optionally, embodiments of the present invention also provide a display device, which includes the display panel provided in any embodiment of the present invention. Therefore, the display device also has the beneficial effects described in any of the above embodiments. Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. In this embodiment, the display device 200 can be a mobile phone or any electronic product with display function, including but not limited to the following categories: display panels in products such as televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, and touch interactive terminals. The present invention does not impose any special limitations on these.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: Substrate; A bottom shielding layer is disposed on one side of the substrate; the bottom shielding layer includes a first shielding layer and a second shielding layer, the first shielding layer and the second shielding layer are located in the same layer and are not connected; A multilayer conductive layer is disposed on the side of the bottom shielding layer away from the substrate, the multilayer conductive layer including a first conductive layer; The first conductive layer is located on the side of the first shielding layer away from the substrate; An active layer is located between the bottom shielding layer and the first conductive layer; The active layer and the multilayer conductive layer constitute at least one gate driving circuit; the gate driving circuit includes a first output transistor and a second output transistor. Wherein, the first shielding layer orthogonally projects onto the substrate at least partially covering the orthogonal projection of the channel region of the first output transistor onto the substrate; the second shielding layer orthogonally projects onto the substrate at least partially covering the orthogonal projection of the channel region of the second output transistor onto the substrate; the first gate of the first output transistor and the first gate of the second output transistor are located in the first conductive layer, the first gate of the first output transistor is connected to the first shielding layer, and the first gate of the second output transistor is connected to the second shielding layer.

2. The display panel according to claim 1, characterized in that, The active layer includes a first active layer; the first active layer extends along a first direction, and the channel regions of the first output transistor and the second output transistor are located in the first active layer; Preferably, the orthographic projection of the first gate of the first output transistor onto the substrate at least partially covers the orthographic projection of the channel region of the first output transistor onto the substrate; The first gate of the second output transistor is projected onto the substrate in a positive projection that at least partially covers the positive projection of the channel region of the second output transistor onto the substrate. Preferably, the channel regions of the first output transistor and the second output transistor are arranged along the first direction.

3. The display panel according to claim 2, characterized in that, The bottom shielding layer also includes a third shielding layer, which is on the same layer as the first shielding layer and the second shielding layer but not connected to them; Preferably, the active layer includes a second active layer; the second active layer is on the same layer as the first active layer but not connected; the gate driving circuit further includes a plurality of control transistors; The channel regions of the plurality of control transistors are located in the second active layer, and the third shielding layer at least partially covers the orthographic projection of the channel regions of the plurality of control transistors onto the substrate. Preferably, the third shielding layer is connected to a signal with a constant voltage; Preferably, the first shielding layer includes a first conductive portion extending along a first direction and a plurality of second conductive portions extending along a second direction, the second conductive portions being spaced apart along the first direction; One end of the second conductive part is connected to the first conductive part; The second conductive portion projects onto the substrate in a positive projection that at least partially covers the positive projection of the channel region of the first output transistor onto the substrate. The second direction intersects with the first direction; Preferably, the second shielding layer includes a third conductive portion extending along a first direction and a plurality of fourth conductive portions extending along a second direction, the fourth conductive portions being spaced apart along the first direction; one end of each fourth conductive portion is connected to the third conductive portion. The orthographic projection of the fourth conductive portion onto the substrate at least partially covers the orthographic projection of the channel region of the second output transistor onto the substrate.

4. The display panel according to claim 3, characterized in that, The first conductive layer includes a first sub-conductive layer and a second sub-conductive layer; the first sub-conductive layer and the second sub-conductive layer are on the same layer and are not connected; the first gate of the first output transistor is located in the first sub-conductive layer, and the first gate of the second output transistor is located in the second sub-conductive layer; Preferably, the first sub-conductive layer includes a fifth conductive portion extending along the first direction and a plurality of sixth conductive portions extending along the second direction, the sixth conductive portions being spaced apart along the first direction; one end of each sixth conductive portion is connected to the fifth conductive portion. The orthographic projection of the sixth conductive portion onto the substrate at least partially covers the orthographic projection of the channel region of the first output transistor onto the substrate; Preferably, the second sub-conductive layer includes a seventh conductive portion extending along the first direction and a plurality of eighth conductive portions extending along the second direction, the eighth conductive portions being spaced apart along the first direction; one end of each eighth conductive portion is connected to the seventh conductive portion. The eighth conductive portion projects onto the substrate in a positive projection that at least partially covers the positive projection of the channel region of the second output transistor onto the substrate.

5. The display panel according to claim 4, characterized in that, The first shielding layer further includes a first extension, which is connected to the first conductive portion or the second conductive portion; the first sub-conductive layer further includes a second extension, which is connected to the fifth conductive portion or the sixth conductive portion; Wherein, the orthographic projection of the first extension on the substrate does not overlap with the orthographic projection of the first active layer on the substrate, and the orthographic projection of the second extension on the substrate does not overlap with the orthographic projection of the first active layer on the substrate. The first extension is connected to the second extension through a first via. The orthographic projection of the first via on the substrate overlaps at least with the orthographic projection of the first extension on the substrate, and the orthographic projection of the first via on the substrate overlaps at least with the orthographic projection of the second extension on the substrate. Preferably, the second shielding layer further includes a third extension, which is connected to the third conductive portion or the fourth conductive portion; the second sub-conductive layer further includes a fourth extension, which is connected to the seventh conductive portion or the eighth conductive portion. Wherein, the orthographic projection of the third extension on the substrate does not overlap with the orthographic projection of the first active layer on the substrate, the orthographic projection of the fourth extension on the substrate does not overlap with the orthographic projection of the first active layer on the substrate, the third extension is connected to the fourth extension through a second via, the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the third extension on the substrate at least, and the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the fourth extension on the substrate at least.

6. The display panel according to claim 5, characterized in that, The first extension extends along the first direction or the second direction, and the orthographic projection of the first extension on the substrate and the orthographic projection of the second extension on the substrate at least partially overlap.

7. The display panel according to claim 4, characterized in that, The first shielding layer further includes a first extension, which is connected to the first conductive portion or the second conductive portion; the first sub-conductive layer further includes a second extension, which is connected to the fifth conductive portion or the sixth conductive portion; The multilayer conductive layer further includes a second conductive layer located on the side of the first conductive layer away from the substrate; the second conductive layer includes a first connecting line; a first end of the first connecting line is connected to the first extension through a third via; a second end of the first connecting line is connected to the second extension through a fourth via. Wherein, the orthographic projection of the third via on the substrate overlaps with the orthographic projection of the first extension on the substrate; the orthographic projection of the fourth via on the substrate overlaps with the orthographic projection of the second extension on the substrate; Preferably, the first extension extends along the first direction or the second direction, and the orthographic projection of the first extension on the substrate and the orthographic projection of the second extension on the substrate do not overlap at least partially.

8. The display panel according to claim 7, characterized in that, The second shielding layer further includes a third extension, which is connected to the third conductive portion or the fourth conductive portion; the second sub-conductive layer further includes a fourth extension, which is connected to the seventh conductive portion or the eighth conductive portion; The second conductive layer further includes a second connecting line; a first end of the second connecting line is connected to the third extension through a fifth via; a second end of the second connecting line is connected to the fourth extension through a sixth via. Wherein, the orthographic projection of the fifth via on the substrate overlaps with the orthographic projection of the third extension on the substrate; the orthographic projection of the sixth via on the substrate overlaps with the orthographic projection of the fourth extension on the substrate; Preferably, the third extension extends along the first direction or the second direction, and the orthographic projection of the third extension on the substrate and the orthographic projection of the fourth extension on the substrate do not overlap at least partially.

9. The display panel according to any one of claims 4-8, characterized in that, The overlapping area of ​​the orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first active layer on the substrate at least covers the overlapping area of ​​the orthographic projection of the sixth conductive portion on the substrate and the orthographic projection of the first active layer on the substrate. The overlapping area of ​​the orthographic projection of the fourth conductive part on the substrate and the orthographic projection of the first active layer on the substrate at least covers the overlapping area of ​​the orthographic projection of the eighth conductive part on the substrate and the orthographic projection of the first active layer on the substrate.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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