Display panel and display device

Abstract

The application provides a display panel and a display device, and relates to the technical field of display. The display panel comprises a substrate, a semiconductor device, a light-emitting device layer and a plurality of conductive layers. The semiconductor device is located on one side of the substrate. The plurality of conductive layers are sequentially and spacedly arranged along the thickness direction of the substrate, and the plurality of conductive layers are located between the substrate and the light-emitting device layer. One of the plurality of conductive layers closer to the light-emitting device layer comprises a first power line extending in a first direction, a second power line and a data line. Along a second direction, the data line is located between the first power line and the second power line. The first direction is perpendicular to the second direction. Both the first direction and the second direction are perpendicular to the thickness direction of the substrate. The data line comprises a first bridging point for connecting a gate electrode. The orthographic projection of the first bridging point on the substrate is located in the orthographic projection of the data line on the substrate. The display panel provided by the application can solve the problem of poor conductivity.

Description

Technical Field

[0001] This application belongs to the field of display technology, and more specifically, relates to a display panel and a display device. Background Technology

[0002] The conductive layer near the light-emitting device layer in the display panel includes multiple conductive lines, with etched gaps between adjacent conductive lines.

[0003] In related technologies, metal residue can easily remain in the gap between two adjacent conductive lines, resulting in poor conductivity. Summary of the Invention

[0004] The purpose of this application is to provide a display panel and a display device to solve the problem of poor conductivity.

[0005] To achieve the above objectives, the technical solution adopted in this application is as follows:

[0006] In a first aspect, this application provides a display panel, including a substrate, a semiconductor device, a light-emitting device layer, and multiple conductive layers. The semiconductor device is located on one side of the substrate and includes a source electrode, a drain electrode, and a gate electrode. The light-emitting device layer is located on one side of the substrate and is electrically connected to the source electrode and the drain electrode, respectively. The multiple conductive layers are sequentially spaced along the thickness direction of the substrate and are located between the substrate and the light-emitting device layer. One of the multiple conductive layers closer to the light-emitting device layer includes a first power line, a second power line, and a data line. The first power line, the second power line, and the data line all extend along a first direction. Along a second direction, the data line is located between the first power line and the second power line. The first direction is perpendicular to the second direction, and both the first direction and the second direction are perpendicular to the thickness direction of the substrate. The data line includes a first bridging point for connecting to the gate electrode, and the orthographic projection of the first bridging point on the substrate lies within the orthographic projection of the data line on the substrate.

[0007] Understandably, in order to connect to the gate electrode, the data cable is usually provided with a protruding tab on the side facing the first power line, and the data cable connects to the gate electrode through the tab.

[0008] In the technical solution of this application, the orthographic projection of the first bridging point on the substrate is located within the orthographic projection of the data line on the substrate. The data line can be connected to the gate electrode through the first bridging point, eliminating the need to provide a protruding ear on the side facing the first power line. This can increase the distance between the data line and the first power line to a certain extent, thereby reducing the risk of metal residue in the gap between the data line and the first power line, which can help solve the problem of poor conductivity.

[0009] Therefore, the display panel provided in this application can at least partially solve the problem of poor conductivity.

[0010] In some embodiments, the first power line is electrically connected to the drain electrode, the second power line is electrically connected to the source electrode, and the data line includes a bent section protruding towards the first power line, with a first bridging point located at the bent section. This increases the distance between the bent section and the second power line, reducing the risk of metal residue in the gap between the data line and the second power line, thereby helping to solve the problem of poor conductivity.

[0011] Optionally, the light-emitting device layer includes a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit with different light-emitting colors, and the drain electrode includes a first drain electrode, a second drain electrode, and a third drain electrode. The first light-emitting unit is electrically connected to the first drain electrode, the second light-emitting unit is electrically connected to the second drain electrode, and the third light-emitting unit is electrically connected to the third drain electrode.

[0012] Optionally, there are multiple first power lines, one of two adjacent first power lines is electrically connected to the first drain electrode and the second drain electrode, and the other of two adjacent first power lines is electrically connected to the second drain electrode and the third drain electrode.

[0013] Optionally, the display panel provided in this application includes a pixel definition layer, which is located on the side of the plurality of conductive layers that is closer to the light-emitting device layer and away from the substrate. The pixel definition layer includes a pixel opening, and at least a portion of the light-emitting device layer is located in the pixel opening.

[0014] Optionally, the display panel provided in this application includes an isolation structure located on the side of the pixel definition layer away from the substrate. The isolation structure encloses and forms an isolation opening, which is connected to the pixel opening.

[0015] In some embodiments, the first power line includes a bridging portion and a main body connected to the bridging portion. Along the second direction, the size of the bridging portion is larger than the size of the main body, and the bent section corresponds to the bridging portion. In this way, the first power line is divided into a bridging portion and a main body. The first power line can be bridged through the larger bridging portion, which helps improve reliability. Furthermore, the size of the main body of the first power line can be reduced, thereby increasing the distance between the main body and the data line. This helps reduce the risk of metal residue in the gap between the data line and the main body, and thus helps solve the problem of poor conductivity.

[0016] In some implementations, the bridging portion has a notch on the side facing the data cable, with the bent section corresponding to the notch. This notch in the bridging portion increases the distance between the bent section and the bridging portion, reducing the risk of metal residue remaining in the gap between the data cable and the bridging portion, thus helping to solve the problem of poor conductivity.

[0017] In some implementations, along the second direction, the distance between the data line and the first power line is 'a', and the value of 'a' ranges from 2.5μm to 15μm.

[0018] Optionally, the value of a can be in the range of 4.5μm≤a≤15μm.

[0019] Optionally, the value of a can be in the range of 2.5μm≤a≤10μm.

[0020] Optionally, the value of a can be in the range of 4.5μm≤a≤10μm.

[0021] In this way, the distance between the data line and the first power line is between 2.5μm and 15μm, which helps to reduce the risk of metal residue in the gap between the data line and the first power line, and thus helps to solve the problem of poor conductivity.

[0022] Optionally, along the second direction, the spacing between the data line and the second power line is b, where b ranges from 2.5μm to 10μm. This spacing, between the data line and the second power line, is between 2.5μm and 10μm, which helps reduce the risk of metal residue in the gap between them, thus helping to solve the problem of poor conductivity.

[0023] Optionally, the value of b can be in the range of 3.5μm≤b≤10μm.

[0024] In some embodiments, the data line includes a main body segment connected to the bend segment, and along the second direction, the second power line is spaced apart from the main body segment by a distance b1, wherein the value of b1 is in the range of 2.5μm≤b1≤10μm.

[0025] In this way, the distance between the second power line and the main body is between 2.5μm and 10μm, which helps to reduce the risk of metal residue in the gap between the main body and the second power line, and thus helps to solve the problem of poor conductivity.

[0026] Optionally, along the second direction, the distance between the second power line and the bend is b2, where b2 ranges from 3.5μm to 10μm. This distance, between the second power line and the bend, is between 3.5μm and 10μm, which helps reduce the risk of metal residue in the gap between the bend and the second power line, thus helping to solve the problem of poor conductivity.

[0027] In some implementations, along the second direction, the spacing between the data line and the cable body is a1, where a1 ranges from 2.5μm to 15μm. This spacing, between 2.5μm and 15μm, helps reduce the risk of metal residue in the gap between the data line and the cable body, thus helping to solve the problem of poor conductivity.

[0028] Optionally, along the second direction, the spacing between the data line and the bridging part is a2, where a2 ranges from 4.5μm ≤ a2 ≤ 15μm; or 2.5μm ≤ a2 ≤ 10μm. This spacing between the data line and the bridging part, between 2.5μm and 10μm or between 4.5μm and 15μm, helps reduce the risk of metal residue remaining in the gap between the data line and the line body, thus helping to solve the problem of poor conductivity.

[0029] In some implementations, along the second direction, the distance between the data line and the notch is a3, and the value of a3 ranges from 4.5μm to 10μm.

[0030] This arrangement, with the data line and the notch spaced between 4.5μm and 10μm, helps reduce the risk of metal residue in the gap between the data line and the notch, thus helping to solve the problem of poor conductivity.

[0031] In some implementations, along the second direction, the size of the data line is d1, and the value of d1 ranges from 1.5μm to 4μm.

[0032] And / or, along the second direction, the size of the line body is d2, and the value of d2 is in the range of: 1.5μm≤d2≤4μm, or 2.5μm≤d2≤10μm;

[0033] And / or, along the second direction, the dimension of the second power line is d3, and the value of d3 is in the range of 1.5μm≤d3≤4μm;

[0034] And / or, along the first direction, the size of the bridging portion is d4, and the value of d4 is in the range of 10μm≤d4≤30μm.

[0035] This can improve the reliability of the data cable and / or the first power cable and / or the second power cable.

[0036] Secondly, this application provides a display device that includes the display panel of any of the above embodiments. The display device provided by this application has the same or similar technical effects as the display panel of any of the above embodiments, and will not be described again here. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the planar structure of the display panel provided in an embodiment of this application;

[0039] Figure 2 for Figure 1 A magnified view of a portion of point A in the middle;

[0040] Figure 3 For along Figure 2 One of the cross-sectional structural diagrams of the middle BB line;

[0041] Figure 4 For along Figure 2 Sectional view of the middle BB line, part two;

[0042] Figure 5 This is one of the schematic diagrams of the first power line, the second power line, and the data line in related technologies;

[0043] Figure 6 One of the schematic diagrams of the first power line, second power line, and data line provided in the embodiments of this application;

[0044] Figure 7 A second schematic diagram of the structure of the first power line, the second power line, and the data line provided in the embodiments of this application;

[0045] Figure 8 A third schematic diagram of the structure of the first power line, the second power line, and the data line provided in the embodiments of this application;

[0046] Figure 9 Fourth schematic diagram of the structure of the first power line, the second power line, and the data line provided in the embodiments of this application;

[0047] Figure 10 Fifth schematic diagram of the structure of the first power line, the second power line, and the data line provided in the embodiments of this application;

[0048] Figure 11 This is the sixth schematic diagram of the structure of the first power line, the second power line, and the data line provided in the embodiments of this application.

[0049] The following are the labeling elements in the figure:

[0050] 100 - Display panel; 110 - Display area; 120 - Non-display area;

[0051] 1-Substrate; 2-First gate dielectric layer; 3-Capacitor dielectric layer; 4-Buffer layer; 5-Second gate dielectric layer; 6-Interlayer dielectric layer; 7-First planarization layer; 8-Second planarization layer; 9-Pixel definition layer; 91-Isolation structure;

[0052] 10-Light-emitting device layer; 101-First electrode layer; 102-Light-emitting layer; 103-Second electrode layer; 11-Bottom light-shielding layer; 12-First active layer; 13-First conductive layer; 14-Second conductive layer; 15-Second active layer; 16-Third conductive layer; 17-Fourth conductive layer; 18-Fifth conductive layer; 191-First inorganic encapsulation layer; 192-Organic encapsulation layer; 193-Second inorganic encapsulation layer;

[0053] 21-First power cable; 2101-Notch; 211-Bridging section; 212-Cable body; 22-Second power cable; 23-Data cable; 2301-Ear; 2302-First bridging point; 231-Bending section; 232-Main body section. Detailed Implementation

[0054] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0055] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0056] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0058] The conductive layer in the display panel 100 near the light-emitting device layer 10 includes multiple conductive lines, and there are etched gaps between two adjacent conductive lines.

[0059] In related technologies, metal residue can easily remain in the gap between two adjacent conductive lines, resulting in poor conductivity.

[0060] Please see Figure 1 This application provides a display panel 100, which has a display area 110 (Active Area, AA) and a non-display area 120 (Non Display Area, NA).

[0061] Optionally, the non-display area 120 includes a package area (PA) connected to the display area 110 and a surrounding area (SA) surrounding the package area.

[0062] Optionally, the non-display area 120 can be the area of ​​the display area 110 near the border, and at least a portion of the non-display area 120 surrounds the display area 110.

[0063] Optionally, the non-display area 120 can also be a hole area.

[0064] Please refer to the following: Figure 2 , Figure 3 and Figure 4 The display panel 100 provided in this application embodiment includes a substrate 1 and a semiconductor device, wherein the semiconductor device is located on the substrate 1 in the thickness direction (e.g., ...). Figure 3 One side of the Z direction (in the middle).

[0065] Optionally, the substrate 1 can be a flexible substrate 1.

[0066] Optionally, the semiconductor device includes a source electrode, a drain electrode, and a gate electrode.

[0067] Optionally, the display panel 100 provided in this application embodiment includes a driving device layer, which includes a first active layer 12 (Polysilicon, PSI), a first conductive layer 13 (M1), a second conductive layer 14 (M2), a second active layer 15 (Indium Gallium Zinc Oxide, IGZO), a third conductive layer 16 (M3), and a fourth conductive layer 17 (M4) that are sequentially stacked and insulated from each other along a direction away from the substrate 1.

[0068] Optionally, the driving device layer further includes a fifth conductive layer 18 (M5) located on the side of the fourth conductive layer 17 away from the substrate 1, the fifth conductive layer 18 being insulated from the fourth conductive layer 17.

[0069] Optionally, the driving device layer includes semiconductor devices.

[0070] The display panel 100 provided in this application embodiment further includes a plurality of insulating film layers, which include a first gate dielectric layer 2 (GL1), a capacitor dielectric layer 3 (CI), a buffer layer 4, a second gate dielectric layer 5 (GL2), an inter-layer dielectric layer 6 (ILD), a first planarization layer 7 (PLN1), a second planarization layer 8 (PLN2), and a pixel definition layer 9 (PDL) arranged sequentially along the direction away from the substrate 1.

[0071] The first conductive layer 13 is disposed between the first gate dielectric and the capacitor dielectric layer 3, the second conductive layer 14 is disposed between the capacitor dielectric layer 3 and the buffer layer 4, the third conductive layer 16 is disposed between the second gate dielectric layer 5 and the interlayer dielectric layer 6, the fourth conductive layer 17 is disposed between the interlayer dielectric layer 6 and the first planarization layer 7, and the fifth conductive layer 18 is disposed between the first planarization layer 7 and the second planarization layer 8.

[0072] In addition, the first active layer 12 is disposed between the substrate 1 and the first gate dielectric layer 2, the second active layer 15 is disposed between the buffer layer 4 and the second gate dielectric layer 5, the first electrode layer 101 is disposed between the second planarization layer 8 and the pixel definition layer 9, and the pixel definition layer 9 is provided with a pixel opening that exposes a portion of the first electrode layer 101.

[0073] Optionally, the substrate 1 is provided with a bottom light-shielding layer 11 opposite to the first active layer 12.

[0074] Please continue reading. Figure 2 , Figure 3 and Figure 4 Optionally, the display panel 100 provided in this application embodiment further includes a light-emitting device layer 10, which is located on one side of the substrate 1 and is electrically connected to the source electrode and the drain electrode respectively.

[0075] Please continue reading. Figure 3 , Figure 4 and Figure 5 Multiple conductive layers are arranged along the thickness direction of substrate 1 (e.g., Figure 3The conductive layers are arranged sequentially at intervals in the Z direction, and multiple conductive layers are located between the substrate 1 and the light-emitting device layer 10. Among the multiple conductive layers, the one closer to the light-emitting device layer 10 includes the first power line 21, the second power line 22, and the data line 23.

[0076] Optionally, the conductive layer closer to the light-emitting device layer 10 among the multiple conductive layers can be the fourth conductive layer 17. That is, the first power line 21, the second power line 22, and the data line 23 can be disposed on the fourth conductive layer 17.

[0077] Optionally, the conductive layer closer to the light-emitting device layer 10 among the multiple conductive layers can be the fifth conductive layer 18. That is, the first power line 21, the second power line 22, and the data line 23 can be disposed on the fifth conductive layer 18.

[0078] Optionally, the conductive layers are all metallic layers. For example, the material of the conductive layer may include molybdenum (Mo). Alternatively, the material of the conductive layer may include molybdenum (Mo), aluminum (Al), and titanium (Ti). For example, a conductive layer may include three film layers, the materials of which may be molybdenum (Mo), aluminum (Al), and titanium (Ti), respectively.

[0079] Please refer to the following: Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 The first power line 21, the second power line 22, and the data line 23 are all along the first direction (e.g., Figure 6 Extend along the Y direction. Along the second direction (e.g., Figure 6 The data line 23 is located between the first power line 21 and the second power line 22 (in the X direction), with the first direction perpendicular to the second direction, and both the first and second directions perpendicular to the thickness direction of the substrate 1. The data line 23 includes a first bridging point 2302 for connecting the gate electrode, and the orthographic projection of the first bridging point 2302 on the substrate 1 lies within the orthographic projection of the data line 23 on the substrate 1.

[0080] The inventor discovered this; please refer to [link / reference]. Figure 5 In order to connect to the gate electrode, the data line 23 is usually provided with a protruding ear 2301 on the side facing the first power line 21, and the data line 23 is connected to the gate electrode through the ear 2301.

[0081] In the technical solution of this application embodiment, the orthographic projection of the first bridging point 2302 on the substrate 1 is located within the orthographic projection of the data line 23 on the substrate 1. The data line 23 can be connected to the gate electrode through the first bridging point 2302. There is no need to provide a protruding ear 2301 on the side facing the first power line 21. This can increase the distance between the data line 23 and the first power line 21 to a certain extent, thereby reducing the risk of metal residue in the gap between the data line 23 and the first power line 21 to a certain extent, which can help solve the problem of poor conductivity.

[0082] Therefore, the display panel 100 provided in this application can at least partially solve the problem of poor conductivity.

[0083] Please refer to the following: Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 In some embodiments, the first power line 21 is electrically connected to the drain electrode, the second power line 22 is electrically connected to the source electrode, and the data line 23 includes a bent section 231 protruding towards the first power line 21, with a first bridging point 2302 disposed at the bent section 231. This increases the distance between the bent section 231 and the second power line 22, which helps reduce the risk of metal residue in the gap between the data line 23 and the second power line 22, thereby helping to solve the problem of poor conductivity.

[0084] Optionally, the light-emitting device layer 10 includes multiple light-emitting units with different emitting colors, including a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit with different emitting colors. That is, the light-emitting device layer 10 includes a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit with different emitting colors.

[0085] The drain electrode includes a first drain electrode, a second drain electrode, and a third drain electrode. The first light-emitting unit is electrically connected to the first drain electrode, the second light-emitting unit is electrically connected to the second drain electrode, and the third light-emitting unit is electrically connected to the third drain electrode.

[0086] Optionally, the light-emitting unit includes a first electrode layer 101, a light-emitting layer 102, and a second electrode layer 103 sequentially stacked along a direction away from the substrate 1. The first electrode layer 101 is electrically connected to the drain electrode, and the second electrode layer 103 is electrically connected to the source electrode.

[0087] Optionally, the first electrode layer 101 may include a plurality of first electrodes. Optionally, the second electrode layer 103 may include a plurality of second electrodes. Optionally, the second electrode layer 103 may be filled with second electrodes deposited over its entire surface.

[0088] Optionally, the first electrode can be an anode and the second electrode can be a cathode.

[0089] Optionally, there are multiple first power lines 21, one of two adjacent first power lines 21 is electrically connected to the first drain electrode and the second drain electrode, and the other of two adjacent first power lines 21 is electrically connected to the second drain electrode and the third drain electrode.

[0090] Understandably, the driver circuit (IC) is electrically connected to the first power line 21, the second power line 22, and the data line 23. The electrical signal from the driver circuit (IC) is transmitted to the drain electrode via the first power line 21, and the drain electrode transmits the electrical signal to the first electrode. The electrical signal from the driver circuit (IC) is also transmitted to the source electrode via the second power line 22, and the source electrode transmits the electrical signal to the second electrode. The electrical signal from the driver circuit (IC) is also transmitted to the gate electrode via the data line 23.

[0091] In this way, one of the two adjacent first power lines 21 is electrically connected to the first and second drain electrodes, allowing electrical signals to be transmitted to both electrodes. The first drain electrode can then transmit the electrical signals to the first electrode of the first light-emitting unit, and the second drain electrode can also transmit the electrical signals to the first electrode of the second light-emitting unit. The other of the two adjacent first power lines 21 is electrically connected to both the second and third drain electrodes, allowing electrical signals to be transmitted to both electrodes. The second drain electrode can then transmit the electrical signals to the first electrode of the second light-emitting unit, and the third drain electrode can also transmit the electrical signals to the first electrode of the third light-emitting unit.

[0092] Optionally, please refer to Figure 3 and Figure 4 The display panel 100 provided in this application embodiment includes a pixel definition layer 9. The pixel definition layer 9 is located on the side of the plurality of conductive layers that is closer to the light-emitting device layer 10 and away from the substrate 1. The pixel definition layer 9 includes a pixel opening, and at least a portion of the light-emitting device layer 10 is located in the pixel opening.

[0093] Optionally, please refer to Figure 4 The display panel 100 provided in this application embodiment includes an isolation structure 91. The isolation structure 91 is located on the side of the pixel definition layer 9 away from the substrate 1. The isolation structure 91 encloses and forms an isolation opening, which is connected to the pixel opening.

[0094] Optionally, the material of the isolation structure 91 may include a metallic material.

[0095] Optionally, the isolation structure 91 may include a first layer and a second layer, with the second layer located on the side of the first layer away from the substrate 1. The material of the first layer may include aluminum (Al), and the material of the second layer may include titanium (Ti).

[0096] Optionally, the isolation structure 91 may further include a third layer located on the side of the first layer facing the substrate. Exemplarily, the material of the third layer may include titanium (Ti). Exemplarily, the material of the third layer may include molybdenum (Mo).

[0097] To seal the light-emitting unit, in some embodiments, the display panel 100 provided in this application further includes a first inorganic encapsulation layer 191, an organic encapsulation layer 192, and a second inorganic encapsulation layer 193 sequentially stacked along a direction away from the substrate 1. The first inorganic encapsulation layer 191 is located on the side of the light-emitting unit facing away from the substrate 1. That is, the organic encapsulation layer 192 covers the first inorganic encapsulation layer 191, and the second inorganic encapsulation layer 193 covers the organic encapsulation layer 192.

[0098] Optionally, the first inorganic encapsulation layer 191 can be an inorganic encapsulation layer formed by chemical vapor deposition (CVD) and patterning.

[0099] Alternatively, the organic encapsulation layer 192 can be fabricated by inkjet printing (IJP).

[0100] Alternatively, the second inorganic encapsulation layer 193 may be an inorganic encapsulation layer formed by chemical vapor deposition (CVD).

[0101] Please continue reading. Figure 6 In some embodiments, the first power line 21 includes a bridging portion 211 and a wire body 212 connected to the bridging portion 211. Along the second direction, the size of the bridging portion 211 is larger than the size of the wire body 212, and the bent section 231 corresponds to the bridging portion 211.

[0102] It is understandable that the first power line 21 is divided into a bridging part 211 and a main body 212. The first power line 21 can be bridged through the larger bridging part 211, which is beneficial to improving reliability.

[0103] In addition, the first power line 21 can reduce the size of the main body 212, which helps to increase the distance between the main body 212 and the data line 23, and helps to reduce the risk of metal residue in the gap between the data line 23 and the main body 212, thereby helping to solve the problem of poor conductivity.

[0104] Optionally, in the first power line 21, the bridging portion 211 can be connected to multiple line bodies 212. For example, each of the four corners of the bridging portion 211 is connected to a line body 212.

[0105] Please see Figure 7 , Figure 8 , Figure 9 and Figure 10 In some embodiments, the bridging portion 211 has a notch 2101 on the side facing the data line 23, and the bent section 231 corresponds to the notch 2101. In this way, providing the notch 2101 in the bridging portion 211 can increase the spacing between the bent section 231 and the bridging portion 211, which helps to reduce the risk of metal residue in the gap between the data line 23 and the bridging portion 211, and thus helps to solve the problem of poor conductivity.

[0106] Alternatively, the shape of the notch 2101 can be rectangular, trapezoidal, etc.

[0107] Please see Figure 11 Optionally, the bridging part 211 may not have a notch 2101.

[0108] Optionally, the bridging portion 211 is connected to two line bodies 212 at its two ends in the first direction, respectively.

[0109] In some embodiments, along the second direction, the distance between the data line 23 and the first power line 21 is a, and the value of a can be in the range of 2.5μm≤a≤15μm.

[0110] Optionally, the value of a can be in the range of: 4.5μm≤a≤15μm.

[0111] Optionally, the value of a can be in the range of: 2.5μm≤a≤10μm.

[0112] Optionally, the value of a can be in the range of: 4.5μm≤a≤10μm.

[0113] For example, the value of a can be: 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm m, 9μm, 9.5μm, 10μm, 10.5μm, 11μm, 11.5μm, 12μm, 12.5μm, 13μm, 13.5μm, 14μm, 14.5μm, 15μm, etc.

[0114] In this way, the distance between the data line 23 and the first power line 21 is between 2.5μm and 15μm, which helps to reduce the risk of metal residue in the gap between the data line 23 and the first power line 21, and thus helps to solve the problem of poor conductivity.

[0115] Optionally, along the second direction, the spacing between the data line 23 and the second power line 22 is b, where b can be in the range of 2.5μm ≤ b ≤ 10μm. This spacing, between the data line 23 and the second power line 22, is between 2.5μm and 10μm, which helps reduce the risk of metal residue in the gap between them, thus helping to solve the problem of poor conductivity.

[0116] Optionally, the value of b can be in the range of 3.5μm≤b≤10μm.

[0117] For example, the value of b can be: 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm, 10μm, etc.

[0118] Please refer to the following: Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 In some embodiments, the data line 23 includes a main body segment 232 connected to the bent segment 231. Along the second direction, the distance between the second power line 22 and the main body segment 232 is b1, and the value of b1 can be in the range of 2.5μm≤b1≤10μm.

[0119] In this way, the distance between the second power line 22 and the main body segment 232 is between 2.5μm and 10μm, which helps to reduce the risk of metal residue in the gap between the main body segment 232 and the second power line 22, and thus helps to solve the problem of poor conductivity.

[0120] Optionally, the value of b1 can be in the range of 2.5μm≤b1≤5μm.

[0121] Optionally, the value of b1 can be in the range of: 5μm≤b1≤10μm.

[0122] For example, the value of b1 can be: 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm, 10μm, etc.

[0123] Optionally, along the second direction, the distance between the second power line 22 and the bent section 231 is b2, and the value of b2 can be in the range of 3.5μm≤b2≤10μm.

[0124] Optionally, the value of b2 can be in the range of 3.5μm≤b2≤6μm.

[0125] Optionally, the value of b2 can be in the range of: 6μm≤b2≤10μm.

[0126] For example, the value of b2 can be: 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm, 10μm, etc.

[0127] In this way, the distance between the second power line 22 and the bending section 231 is between 3.5μm and 10μm, which helps to reduce the risk of metal residue in the gap between the bending section 231 and the second power line 22, and thus helps to solve the problem of poor conductivity.

[0128] Please refer to the following: Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 In some embodiments, along the second direction, the distance between the data line 23 and the line body 212 is a1, and the value of a1 can be in the range of 2.5μm≤a1≤15μm.

[0129] Optionally, the value range of a1 can be: 4.5μm≤a1≤15μm.

[0130] Optionally, the value range of a1 can be: 2.5μm≤a1≤10μm.

[0131] Optionally, the value range of a1 can be: 4.5μm≤a1≤10μm.

[0132] For example, the value of a1 can be: 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm, 10μm, 10.5μm, 11μm, 11.5μm, 12μm, 12.5μm, 13μm, 13.5μm, 14μm, 14.5μm, 15μm, etc.

[0133] In this way, the distance between the data line 23 and the line body 212 is between 2.5μm and 15μm, which helps to reduce the risk of metal residue in the gap between the data line 23 and the line body 212, and thus helps to solve the problem of poor conductivity.

[0134] Please see Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10In some embodiments, along the second direction, the distance between the data line 23 and the bridging portion 211 is a2, and the value of a2 can be in the range of 4.5μm≤a2≤15μm.

[0135] For example, the value of a2 can be: 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm, 10μm, 10.5μm, 11μm, 11.5μm, 12μm, 12.5μm, 13μm, 13.5μm, 14μm, 14.5μm, 15μm, etc.

[0136] In this way, the distance between the data line 23 and the bridging part 211 is between 4.5μm and 15μm, which helps to reduce the risk of metal residue in the gap between the data line 23 and the line body 212, and thus helps to solve the problem of poor conductivity.

[0137] Please see Figure 11 In some other embodiments, along the second direction, the distance between the data line 23 and the bridging portion 211 is a2, and the value of a2 can be in the range of 2.5μm≤a2≤10μm.

[0138] For example, the value of a2 can be: 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm, 10μm, etc.

[0139] In this way, the distance between the data line 23 and the bridging part 211 is between 2.5μm and 10μm, which helps to reduce the risk of metal residue in the gap between the data line 23 and the line body 212, and thus helps to solve the problem of poor conductivity.

[0140] Please refer to the following: Figure 7 , Figure 8 , Figure 9 and Figure 10 In some embodiments, along the second direction, the distance between the data line 23 and the notch 2101 is a3, and the value of a3 can be in the range of 4.5μm≤a3≤10μm.

[0141] For example, the value of a3 can be: 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm, 10μm, etc.

[0142] In this way, the distance between the data line 23 and the notch 2101 is between 4.5μm and 10μm, which helps to reduce the risk of metal residue in the gap between the data line 23 and the notch 2101, and thus helps to solve the problem of poor conductivity.

[0143] Please refer to the following: Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 In some embodiments, along the second direction, the size of the data line 23 is d1, and the value range of d1 can be: 1.5μm≤d1≤4μm.

[0144] For example, the value of d1 can be: 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2μm, 2.1μm, 2.2μm, 2.3μm, 2.4μm, 2.5μm, 2.6μm, 2.7μm, 2.8μm, 2.9μm, 3μm, 3.1μm, 3.2μm, 3.3μm, 3.4μm, 3.5μm, 3.6μm, 3.7μm, 3.8μm, 3.9μm, 4μm, etc.

[0145] In this way, the size d1 of the data line 23 can be between 1.5μm and 4μm, making the data line 23 less prone to breakage and thus improving its reliability.

[0146] Please refer to the following: Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 In some embodiments, along the second direction, the size of the line body 212 is d2, and the value of d2 can be in the range of 1.5μm≤d2≤4μm.

[0147] For example, the values ​​of d2 can be: 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2μm, 2.1μm, 2.2μm, 2.3μm, 2.4μm, 2.5μm, 2.6μm m, 2.7μm, 2.8μm, 2.9μm, 3μm, 3.1μm, 3.2μm, 3.3μm, 3.4μm, 3.5μm, 3.6μm, 3.7μm, 3.8μm, 3.9μm, 4μm, etc.

[0148] In this way, the size d2 of the wire body 212 can be between 1.5μm and 4μm, making the wire body 212 less prone to breakage, thereby improving the reliability of the wire body 212.

[0149] Please see Figure 11In other embodiments, along the second direction, the size of the line body 212 is d2, and the value of d2 can be in the range of 2.5μm≤d2≤10μm.

[0150] For example, the values ​​of d2 can be: 2.5 μm, 2.6 μm, 2.7 μm, 2.8 μm, 2.9 μm, 3 μm, 3.1 μm, 3.2 μm, 3.3 μm, 3.4 μm, 3.5 μm, 3.6 μm, 3.7 μm, 3.8 μm, 3.9 μm, 4 μm, 4.1 μm, 4. 2μm, 4.3μm, 4.4μm, 4.5μm, 4.6μm, 4.7μm, 4.8μm, 4.9μm, 5μm, 5.1μm, 5.2μm, 5.3μm, 5.4μm, 5.5μm, 5.6μm, 5.7μm, 5.8μm, 5.9μm, 6μm, 6.1μm, 6.2μm, 6.3μm, 6.4μm, 6.5μm, 6.6μm, 6.7μm, 6.8μm, 6.9μm, 7μm, 7.1μm, 7.2μm, 7.3μm, 7.4μm, 7.5μm, 7.6μm, 7.7μm, 7.8μm, 7.9μm, 8μm, 8.1μm m.

[0151] In this way, the size d2 of the wire body 212 can be between 2.5μm and 10μm, making the wire body 212 less prone to breakage, thereby improving the reliability of the wire body 212.

[0152] Please refer to the following: Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 In some embodiments, along the second direction, the size of the second power line 22 is d3, and the value of d3 can be in the range of 1.5μm≤d3≤4μm.

[0153] For example, the values ​​of d3 can be: 1.5μm, 1.6μm, 1.7μm, 1.8μm, 1.9μm, 2μm, 2.1μm, 2.2μm, 2.3μm, 2.4μm, 2.5μm, 2.6μm m, 2.7μm, 2.8μm, 2.9μm, 3μm, 3.1μm, 3.2μm, 3.3μm, 3.4μm, 3.5μm, 3.6μm, 3.7μm, 3.8μm, 3.9μm, 4μm, etc.

[0154] In this way, the size d3 of the second power line 22 can be between 1.5μm and 4μm, making the second power line 22 less prone to breakage, thereby improving the reliability of the second power line 22.

[0155] Please refer to the following: Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 Along the first direction, the size of the bridging part 211 is d4, and the value of d4 can be in the range of 10μm≤d4≤30μm.

[0156] For example, the value of d4 can be: 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, 24μm, 25μm, 26μm, 27μm, 28μm, 29μm, 30μm, etc.

[0157] In this way, the size d4 of the bridging part 211 can be between 10μm and 30μm, and the bridging part 211 is not easy to break, thereby improving the reliability of the bridging part 211.

[0158] In some embodiments, this application also provides a display device, which includes the display panel 100 of any of the above embodiments. The display device provided in this application has the same or similar technical effects as the display panel 100 of any of the above embodiments, and will not be described again here.

[0159] Optionally, the display device can be a mobile phone, television, tablet computer, laptop computer, desktop computer, in-vehicle display terminal, wearable device, advertising display device, etc.

[0160] Optionally, the display panel 100 provided in this application embodiment can be an organic light-emitting diode (OLED) display panel 100 or a micro light-emitting diode (Micro LED / μLED) display panel 100.

[0161] The display panel 100 provided in this embodiment can employ low-temperature polycrystalline oxide (LTPO) technology, resulting in better energy efficiency. However, the performance and process performance of the OLED display device provided in this embodiment need further improvement.

[0162] The above are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, include: substrate; A semiconductor device, located on one side of the substrate, includes a source electrode, a drain electrode, and a gate electrode; A light-emitting device layer is located on the side of the semiconductor device away from the substrate and is electrically connected to the source electrode and the drain electrode, respectively. Multiple conductive layers are arranged sequentially at intervals along the thickness direction of the substrate and located between the substrate and the light-emitting device layer. One of the multiple conductive layers closer to the light-emitting device layer includes a first power line, a second power line, and a data line. The first power line, the second power line, and the data line all extend along a first direction. Along a second direction, the data line is located between the first power line and the second power line. The first direction is perpendicular to the second direction, and both the first direction and the second direction are perpendicular to the thickness direction of the substrate. The data line includes a first bridging point for connecting the gate electrode, wherein the orthographic projection of the first bridging point on the substrate lies within the orthographic projection of the data line on the substrate.

2. The display panel as described in claim 1, characterized in that, The first power line is electrically connected to the drain electrode, the second power line is electrically connected to the source electrode, and the data line includes a bent section protruding toward the first power line, with the first bridging point disposed on the bent section. Preferably, the light-emitting device layer includes a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit with different light-emitting colors, and the drain electrode includes a first drain electrode, a second drain electrode, and a third drain electrode. The first light-emitting unit is electrically connected to the first drain electrode, the second light-emitting unit is electrically connected to the second drain electrode, and the third light-emitting unit is electrically connected to the third drain electrode. Preferably, there are multiple first power lines, one of two adjacent first power lines is electrically connected to the first drain electrode and the second drain electrode, and the other of two adjacent first power lines is electrically connected to the second drain electrode and the third drain electrode. Preferably, the display panel includes a pixel definition layer located on the side of the plurality of conductive layers closer to the light-emitting device layer that is away from the substrate, the pixel definition layer including a pixel opening, and at least a portion of the light-emitting device layer being located in the pixel opening; Preferably, the display panel includes an isolation structure located on the side of the pixel definition layer opposite to the substrate, the isolation structure forming an isolation opening, and the isolation opening communicating with the pixel opening.

3. The display panel as described in claim 2, characterized in that, The first power cord includes a bridging portion and a main body connected to the bridging portion. Along the second direction, the size of the bridging portion is larger than the size of the main body, and the bent section corresponds to the bridging portion.

4. The display panel as described in claim 3, characterized in that, The bridging section has a notch on the side facing the data line, and the bent section corresponds to the notch.

5. The display panel as described in claim 1, characterized in that, Along the second direction, the distance between the data line and the first power line is a, and the value of a ranges from 2.5μm to 15μm. Preferably, the value range of a is: 4.5μm≤a≤15μm; Preferably, the value range of a is: 2.5μm≤a≤10μm; Preferably, the value range of a is: 4.5μm≤a≤10μm; And / or, along the second direction, the distance between the data line and the second power line is b, where the value of b ranges from 2.5 μm to 10 μm. Preferably, the value of b is in the range of 3.5μm≤b≤10μm.

6. The display panel as described in claim 2, characterized in that, The data line includes a main body segment connected to the bent section. Along the second direction, the distance between the second power line and the main body segment is b1, and the value of b1 is in the range of 2.5μm≤b1≤10μm. Preferably, along the second direction, the distance between the second power line and the bent section is b2, and the value of b2 is in the range of 3.5μm≤b2≤10μm.

7. The display panel as described in claim 3, characterized in that, Along the second direction, the distance between the data line and the line body is a1, and the value of a1 is in the range of 2.5μm≤a1≤15μm; Preferably, along the second direction, the distance between the data line and the bridging portion is a2, and the value of a2 is in the range of: 4.5μm≤a2≤15μm; or, 2.5μm≤a2≤10μm.

8. The display panel as described in claim 4, characterized in that, Along the second direction, the distance between the data line and the notch is a3, and the value of a3 is in the range of 4.5μm≤a3≤10μm.

9. The display panel as described in claim 3, characterized in that, Along the second direction, the size of the data line is d1, and the value range of d1 is: 1.5μm≤d1≤4μm; And / or, along the second direction, the size of the line body is d2, and the value of d2 is in the range of: 1.5μm≤d2≤4μm, or 2.5μm≤d2≤10μm; And / or, along the second direction, the dimension of the second power line is d3, and the value of d3 is in the range of 1.5μm≤d3≤4μm; And / or, along the first direction, the size of the bridging portion is d4, and the value of d4 is in the range of 10μm≤d4≤30μm.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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