Array substrate, display module and display device
Patent Information
- Application Number
- CN202510570441.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-30
- Publication Date
- 2026-10-30
AI Technical Summary
[0003]但是，现有显示屏的性能有待提升
[0039]与现有技术相比，本申请提供的阵列基板，其数据线包括第一数据线和第二数据线，第一数据线在衬底上的正投影位于栅极驱动电路靠近显示区的一侧，第二数据线在衬底上的正投影位于栅极驱动电路远离显示区的一侧，第二电源线至少部分覆盖第二数据线，通过将部分数据线走第二电源线的下方，有利于减少边框占用，实现更窄边框，提升产品性能。
Smart Images
Figure CN123022047A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to an array substrate, a display module, and a display device. Background Technology
[0002] OLED (Organic Light-Emitting Diode) is an active-matrix light-emitting device with a sandwich structure consisting of multiple organic layers and electrodes on both sides. Currently, AMOLED (Active-matrix organic light-emitting diode) displays have been commercialized in fields such as smartphones, watches, and laptops.
[0003] However, the performance of existing displays needs to be improved. Summary of the Invention
[0004] In view of this, the purpose of this application is to propose an array substrate that is beneficial for narrowing the bezel and improving the display effect.
[0005] To achieve the above objectives, this application provides an array substrate having a display area and a non-display area, wherein the non-display area at least partially surrounds the display area, and the non-display area includes a border area; the array substrate further includes:
[0006] Substrate;
[0007] A data line is disposed on one side of the substrate, and the data line is located in the border area;
[0008] A gate driving circuit is disposed on one side of the substrate, and the gate driving circuit is located in the border area;
[0009] A second power line is disposed on one side of the substrate, and the second power line is located in the border area;
[0010] The data line includes a first data line and a second data line. The orthographic projection of the first data line on the substrate is located on the side of the gate driving circuit closer to the display area, and the orthographic projection of the second data line on the substrate is located on the side of the gate driving circuit away from the display area. The second power line at least partially covers the second data line.
[0011] In one embodiment, the second data line is located between the second power line and the substrate, and the orthographic projection of the second data line on the substrate is located within the orthographic projection of the second power line on the substrate.
[0012] Preferably, the second power line includes a first part of the power line and a second part of the power line, the first data line is located between the first part of the power line and the substrate, and the orthographic projection of the first data line on the substrate is located within the orthographic projection of the first part of the power line on the substrate.
[0013] The second data line is located between the second portion of the power line and the substrate, and the orthographic projection of the second data line on the substrate is within the orthographic projection of the second portion of the power line on the substrate.
[0014] In one embodiment, the orthographic projection of the gate drive circuit on the substrate is located between the orthographic projection of the first portion of the power line on the substrate and the orthographic projection of the second portion of the power line on the substrate.
[0015] In one embodiment, the array substrate further includes:
[0016] A first conductor layer is disposed on one side of the substrate;
[0017] A second conductor layer is disposed on the side of the first conductor layer away from the substrate;
[0018] The first data line is partially located in the first conductor layer and partially located in the second conductor layer; the second data line is partially located in the first conductor layer and partially located in the second conductor layer.
[0019] Preferably, an insulating layer is provided between the first conductor layer and the second conductor layer.
[0020] In one embodiment, the array substrate further includes:
[0021] A third conductor layer is disposed on the side of the second conductor layer away from the substrate;
[0022] The first portion of the power line and the second portion of the power line are located in the third conductor layer;
[0023] Preferably, an insulating layer is provided between the third conductor layer and the second conductor layer.
[0024] In one embodiment, the array substrate further includes:
[0025] A fourth conductor layer is disposed on the side of the third conductor layer away from the substrate;
[0026] The gate drive circuit is partially located in the first conductor layer, partially located in the second conductor layer, partially located in the third conductor layer, and partially located in the fourth conductor layer;
[0027] Preferably, an insulating layer is provided between the fourth conductor layer and the third conductor layer.
[0028] In one embodiment, the non-display area further includes a bending area located on the side of the border area away from the display area; the array substrate further includes:
[0029] The first connecting line is partially located in the bending area and partially located in the border area, connecting to the first data line.
[0030] The second connecting line is partially located in the bending area and partially located in the border area, connecting to the second data line.
[0031] Preferably, the first connecting line is partially located in the first conductor layer and partially located in the second conductor layer; the second connecting line is partially located in the first conductor layer and partially located in the second conductor layer.
[0032] Preferably, the array substrate further includes a third connecting line, which is partially located in the bending area and partially located in the border area and connected to the first part of the power line;
[0033] Preferably, the array substrate further includes a fourth connecting line, the fourth connecting line being partially located in the bending area and partially located in the border area and connected to the second part of the power line;
[0034] Preferably, the third connecting line is located in the third conductor layer, and the fourth connecting line is located in the third conductor layer;
[0035] Preferably, the array substrate further includes a fifth connection line, which is partially located in the bending region and partially located in the border region and connected to the gate driving circuit.
[0036] In one embodiment, the gate driving circuit includes a light-emitting control circuit and a scanning circuit.
[0037] Based on the same inventive concept, this application also discloses a display module, which includes an array substrate as described in any one of the above, a control unit and a flexible circuit board, wherein the control unit is electrically connected to the flexible circuit board, the array substrate is electrically connected to the flexible circuit board, and the control unit provides electrical signals to the array substrate through the flexible circuit board.
[0038] Based on the same inventive concept, this application also discloses a display device, which includes the display module described above.
[0039] Compared with the prior art, the array substrate provided in this application includes a first data line and a second data line. The orthographic projection of the first data line on the substrate is located on the side of the gate driving circuit closer to the display area, and the orthographic projection of the second data line on the substrate is located on the side of the gate driving circuit away from the display area. The second power line at least partially covers the second data line. By running part of the data line under the second power line, it is beneficial to reduce the bezel occupation, achieve a narrower bezel, and improve product performance. Attached Figure Description
[0040] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0041] Figure 1 This is a schematic diagram of a related array substrate;
[0042] Figure 2 This is a schematic diagram of the structure of region A of the array substrate in one embodiment of the application;
[0043] Figure 3 This is a schematic diagram of the film layer structure of the array substrate in one embodiment of this application;
[0044] Figure 4 This is a schematic diagram of the structure of region A of the array substrate in another embodiment of this application;
[0045] Figure 5 This is a schematic diagram of the film structure of the array substrate in another embodiment of this application;
[0046] Figure 6 This is a schematic diagram of the film structure of the array substrate in another embodiment of this application;
[0047] Figure 7 This is a schematic diagram of the array substrate in another embodiment of this application;
[0048] Figure 8 This is a schematic diagram of the structure of region B of the array substrate in another embodiment of this application;
[0049] Figure 9 This is a schematic diagram of the structure of region B of the array substrate in another embodiment of this application.
[0050] Marker explanation:
[0051] 100. Array substrate; A. First region; B. Second region; 110. Display area; 120. Non-display area; 121. Border area; 122. Bending area; M1. First conductor layer; M2. Second conductor layer; M3. Third conductor layer; M4. Fourth conductor layer;
[0052] 10. Substrate;
[0053] 20. Data cable; 21. First data cable; 22. Second data cable;
[0054] 30. Gate drive circuit;
[0055] 40. Second power cord; 41. First power cord; 42. Second power cord;
[0056] 51. First connecting line; 52. Second connecting line; 53. Third connecting line; 54. Fourth connecting line; 55. Fifth connecting line. Detailed Implementation
[0057] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.
[0058] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0059] Please refer to Figure 1 As shown, a related array substrate 100 includes a display area 110 and a bezel area 121 surrounding the display area 110. The bezel area 121 has traces such as data lines 20, gate driving circuits 30, and second power lines 40, resulting in a relatively large width of the bezel area 121, which is not conducive to achieving a narrow bezel.
[0060] Based on this, this application provides an array substrate solution to solve the above problems.
[0061] Please refer toFigures 1-3 As shown, an array substrate 100 is provided in an embodiment of this application. The array substrate 100 has a display area 110 and a non-display area 120. The non-display area 120 at least partially surrounds the display area 110 and includes a border area 121. The array substrate 100 also includes a substrate 10, a data line 20, a gate driving circuit 30, and a second power line 40.
[0062] Data line 20 is disposed on one side of substrate 10 and is located in border area 121; gate drive circuit 30 is disposed on one side of substrate 10 and is located in border area 121; second power line 40 is disposed on one side of substrate 10 and is located in border area 121.
[0063] The data line 20 includes a first data line 21 and a second data line 22. The orthographic projection of the first data line 21 on the substrate 10 is located on the side of the gate driving circuit 30 closer to the display area 110, and the orthographic projection of the second data line 22 on the substrate 10 is located on the side of the gate driving circuit 30 away from the display area 110. The second power line 40 at least partially covers the second data line 22.
[0064] The array substrate 100 provided in this embodiment has a data line 20 including a first data line 21 and a second data line 22. The orthographic projection of the first data line 21 on the substrate 10 is located on the side of the gate driving circuit 30 closer to the display area 110, and the orthographic projection of the second data line 22 on the substrate 10 is located on the side of the gate driving circuit 30 away from the display area 110. The second power line 40 at least partially covers the second data line 22. By routing part of the data line 20 below the second power line 40, it is beneficial to reduce the bezel occupancy, achieve a narrower bezel, and improve product performance.
[0065] Preferably, the second signal line 3 is used to transmit the negative power supply signal (ELVSS).
[0066] Optionally, the display area 110 can be circular, rectangular, or chamfered rectangular. The border area 121 can include annular, rectangular, and / or curved corner areas, etc. In this embodiment, the array substrate 100 can reduce the width of the border area 121.
[0067] It should be noted that the display area 110 also has data lines. The data lines in the display area 110 are electrically connected to the data lines 20 in the border area, and are used to transmit signals to each pixel unit in the display area 110.
[0068] Furthermore, the data line 20 includes multiple first data lines 21 and multiple second data lines 22.
[0069] Please continue to refer to Figure 2 and 3As shown, in one embodiment, the second data line 22 is located between the second power line 40 and the substrate 10, and the orthographic projection of the second data line 22 on the substrate 10 lies within the orthographic projection of the second power line 40 on the substrate 10. Since the second data line 22 is completely covered by the second power line 40, the bezel can be further reduced, achieving a narrower bezel.
[0070] Please refer to Figure 4 and 5 As shown, in one embodiment, the second power line 40 includes a first power line 41 and a second power line 42. The first data line 21 is located between the first power line 41 and the substrate 10, and the orthographic projection of the first data line 21 on the substrate 10 is within the orthographic projection of the first power line 41 on the substrate 10. The second data line 22 is located between the second power line 42 and the substrate 10, and the orthographic projection of the second data line 22 on the substrate 10 is within the orthographic projection of the second power line 42 on the substrate 10, ensuring that the environments of the first data line 21 and the second data line 22 are similar and their loading is consistent.
[0071] At the same time, it helps to increase the overall width of the second power line 40, thereby reducing the current density in the second power line 40, avoiding overheating due to excessive current density, reducing the risk of screen burn-in caused by high current, and improving reliability. Specifically, the overall width of the second power line 40 is the sum of the widths of the first part of the power line 41 and the second part of the power line 42. The larger the overall width, the larger the cross-sectional area and the lower the current density.
[0072] Reference Figure 2 As shown, in one embodiment, the orthographic projection of the gate drive circuit 30 on the substrate 10 is located between the orthographic projection of the first portion of the power line 41 on the substrate 10 and the orthographic projection of the second portion of the power line 42 on the substrate 10, thereby reducing signal interference between the gate drive circuit 30 and the second power line 40.
[0073] Reference Figure 6 As shown, in one embodiment, the array substrate 100 further includes a first conductor layer M1 and a second conductor layer M2. The first conductor layer M1 is disposed on one side of the substrate 10, and the second conductor layer M2 is disposed on the side of the first conductor layer M1 away from the substrate 10. A first data line 21 is partially located on the first conductor layer M1 and partially on the second conductor layer M2; a second data line 22 is partially located on the first conductor layer M1 and partially on the second conductor layer M2. The fact that the first data line 21 and the second data line 22 both run through the first conductor layer M1 and the second conductor layer M2 helps to further reduce the bezel and achieve a narrower bezel. This also improves the reliability and stability of the entire array substrate 100 and reduces the risk of display defects due to a single line failure.
[0074] Preferably, an insulating layer is provided between the first conductor layer M1 and the second conductor layer M2 to isolate the first conductor layer M1 from the second conductor layer M2, thereby preventing short circuits and interference between different signals.
[0075] Reference Figure 6 As shown, in one embodiment, the array substrate 100 further includes a third conductor layer M3, which is disposed on the side of the second conductor layer M2 away from the substrate 10; a first power line 41 and a second power line 42 are located on the third conductor layer M3, so that the first power line 41 can cover the first data line 21 and the second power line 42 can cover the second data line 22.
[0076] Preferably, an insulating layer is provided between the third conductor layer M3 and the second conductor layer M2 to isolate the second conductor layer M2 from the third conductor layer M3, thereby preventing short circuits and interference between different signals.
[0077] Reference Figure 6 As shown, in one embodiment, the array substrate 100 further includes a fourth conductor layer M4, which is disposed on the side of the third conductor layer M3 away from the substrate 10. The gate drive circuit 30 is partially located in the first conductor layer M1, partially in the second conductor layer M2, partially in the third conductor layer M3, and partially in the fourth conductor layer M4, which helps to further reduce the bezel and achieve a narrower bezel. This also improves the reliability and stability of the entire array substrate 100.
[0078] Preferably, an insulating layer is provided between the fourth conductor layer M4 and the third conductor layer M3 to isolate the fourth conductor layer M4 from the third conductor layer M3, thereby preventing short circuits and interference between different signals.
[0079] Reference Figure 7 and 8 As shown, in one embodiment, the non-display area 120 further includes a bending area 122, which is located on the side of the bezel area 121 away from the display area 110. The array substrate 100 also includes a first connecting line 51 and a second connecting line 52. The first connecting line 51 is partially located in the bending area 122 and partially located in the bezel area 121, connecting to the first data line 21. The second connecting line 52 is partially located in the bending area 122 and partially located in the bezel area 121, connecting to the second data line 22. Both the first connecting line 51 and the second connecting line 52 are connected to the driver chip to transmit signals to the second data line 22 and the first data line 21. The bonding area is bent to the back side of the array substrate 100 through the bending area 122, which allows components such as the driver chip and flexible circuit board to be located on the non-light-emitting side of the array substrate 100, effectively reducing the bezel size and increasing the screen-to-body ratio.
[0080] Preferably, the first connecting line 51 is partially located in the first conductor layer M1 and partially located in the second conductor layer M2; the second connecting line 52 is partially located in the first conductor layer M1 and partially located in the second conductor layer M2.
[0081] Preferably, the array substrate 100 further includes a third connection line 53, which is partially located in the bending region 122 and partially located in the border region 121 and connected to the first power line 41. The third connection line 53 is connected to the driver chip to transmit signals to the first power line 41.
[0082] Preferably, the array substrate 100 further includes a fourth connection line 54, which is partially located in the bending region 122 and partially located in the border region 121, connecting to the second power line 42. The fourth connection line 54 is connected to the driver chip to transmit signals to the second power line 42.
[0083] Preferably, the third connecting line 53 is located in the third conductor layer M3, and the fourth connecting line 54 is located in the third conductor layer M3.
[0084] Reference Figure 9 As shown, in one embodiment, the array substrate 100 further includes a fifth connection line 55, which is partially located in the bending region 122 and partially located in the border region 121 and connected to the gate driving circuit 30. The fifth connection line 55 is connected to the driving chip to transmit signals to the gate driving circuit 30.
[0085] It should be noted that when different traces on the same layer cross each other, they need to be connected through vias on other layers.
[0086] In one embodiment, the gate driving circuit 30 includes a light-emitting control circuit and a scanning circuit. The light-emitting control circuit is used to implement the light-emitting control function, and the scanning circuit is used to implement the scanning function.
[0087] Specifically, the main function of the light-emitting control circuit is to control the light-emitting time and intensity of OLED pixels. Working in conjunction with other circuits on the display panel, it precisely controls the on and off times of each pixel based on input image and control signals, thereby adjusting image brightness and color. For example, when displaying an image of a dark scene, the light-emitting control circuit reduces the pixel's light-emitting time or lowers its intensity to achieve energy saving and accurate image display.
[0088] The main function of the scanning circuit is to scan the pixels on the display panel row by row or column by column according to a certain sequence and frequency. It generates scanning signals, sequentially selecting pixels in each row or column, enabling them to receive image signals from the data lines and emit light accordingly. The performance of the scanning circuit directly affects the refresh rate and stability of the displayed image. For example, a higher scanning frequency can achieve a higher refresh rate, resulting in smoother images and reduced flickering and ghosting.
[0089] Based on the same inventive concept, another embodiment of this application discloses a display module, which includes the array substrate 100 in the above embodiment, a control unit, and a flexible circuit board. The control unit is electrically connected to the flexible circuit board, and the array substrate is electrically connected to the flexible circuit board. The control unit provides electrical signals to the array substrate through the flexible circuit board. The data lines 20 in the array substrate 100 include a first data line 21 and a second data line 22. The orthographic projection of the first data line 21 on the substrate 10 is located on the side of the gate driving circuit 30 closer to the display area 110. The orthographic projection of the second data line 22 on the substrate 10 is located on the side of the gate driving circuit 30 away from the display area 110. The second power line 40 at least partially covers the second data line 22. By routing part of the data line 20 below the second power line 40, it is beneficial to reduce bezel occupancy, achieve a narrower bezel, and improve product performance.
[0090] Based on the same inventive concept, another embodiment of this application discloses a display device, which includes the display module in the above embodiments. Furthermore, the display device includes mobile phones, VR devices, computers, televisions, in-vehicle display devices, etc.
[0091] This embodiment provides a display device whose display module includes an array substrate 100. Its data lines 20 include a first data line 21 and a second data line 22. The orthographic projection of the first data line 21 on the substrate 10 is located on the side of the gate driving circuit 30 near the display area 110. The orthographic projection of the second data line 22 on the substrate 10 is located on the side of the gate driving circuit 30 away from the display area 110. The second power line 40 at least partially covers the second data line 22. By routing part of the data line 20 below the second power line 40, it is beneficial to reduce the bezel occupancy, achieve a narrower bezel, and improve product performance.
[0092] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description.
[0093] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0094] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.
Claims
1. An array substrate, characterized in that, The array substrate has a display area and a non-display area, the non-display area at least partially surrounding the display area, the non-display area including a border area, and the array substrate further includes: Substrate; A data line is disposed on one side of the substrate, and the data line is located in the border area; A gate driving circuit is disposed on one side of the substrate, and the gate driving circuit is located in the border area; A second power line is disposed on one side of the substrate, and the second power line is located in the border area; The data line includes a first data line and a second data line. The orthographic projection of the first data line on the substrate is located on the side of the gate driving circuit closer to the display area, and the orthographic projection of the second data line on the substrate is located on the side of the gate driving circuit away from the display area. The second power line at least partially covers the second data line.
2. The array substrate according to claim 1, characterized in that, The second data line is located between the second power line and the substrate, and the orthographic projection of the second data line on the substrate is located within the orthographic projection of the second power line on the substrate; Preferably, the second power line includes a first part of the power line and a second part of the power line, the first data line is located between the first part of the power line and the substrate, and the orthographic projection of the first data line on the substrate is located within the orthographic projection of the first part of the power line on the substrate. The second data line is located between the second portion of the power line and the substrate, and the orthographic projection of the second data line on the substrate is within the orthographic projection of the second portion of the power line on the substrate.
3. The array substrate according to claim 2, characterized in that, The orthographic projection of the gate drive circuit on the substrate lies between the orthographic projections of the first portion of the power lines on the substrate and the orthographic projections of the second portion of the power lines on the substrate.
4. The array substrate according to claim 2, characterized in that, The array substrate further includes: A first conductor layer is disposed on one side of the substrate; A second conductor layer is disposed on the side of the first conductor layer away from the substrate; The first data line is partially located in the first conductor layer and partially located in the second conductor layer; the second data line is partially located in the first conductor layer and partially located in the second conductor layer. Preferably, an insulating layer is provided between the first conductor layer and the second conductor layer.
5. The array substrate according to claim 4, characterized in that, The array substrate further includes: A third conductor layer is disposed on the side of the second conductor layer away from the substrate; The first portion of the power line and the second portion of the power line are located in the third conductor layer; Preferably, an insulating layer is provided between the third conductor layer and the second conductor layer.
6. The array substrate according to claim 5, characterized in that, The array substrate further includes: A fourth conductor layer is disposed on the side of the third conductor layer away from the substrate; The gate drive circuit is partially located in the first conductor layer, partially located in the second conductor layer, partially located in the third conductor layer, and partially located in the fourth conductor layer; Preferably, an insulating layer is provided between the fourth conductor layer and the third conductor layer.
7. The array substrate according to claim 6, characterized in that, The non-display area further includes a bending area, which is located on the side of the border area away from the display area; the array substrate further includes: The first connecting line is partially located in the bending area and partially located in the border area, connecting to the first data line. The second connecting line is partially located in the bending area and partially located in the border area, connecting to the second data line. Preferably, the first connecting line is partially located in the first conductor layer and partially located in the second conductor layer; the second connecting line is partially located in the first conductor layer and partially located in the second conductor layer. Preferably, the array substrate further includes a third connecting line, which is partially located in the bending area and partially located in the border area and connected to the first part of the power line; Preferably, the array substrate further includes a fourth connecting line, the fourth connecting line being partially located in the bending area and partially located in the border area and connected to the second part of the power line; Preferably, the third connecting line is located in the third conductor layer, and the fourth connecting line is located in the third conductor layer; Preferably, the array substrate further includes a fifth connection line, which is partially located in the bending region and partially located in the border region and connected to the gate driving circuit.
8. The array substrate according to claim 1, characterized in that, The gate driving circuit includes a light-emitting control circuit and a scanning circuit.
9. A display module, characterized in that, The system includes an array substrate as described in any one of claims 1-8, a control unit, and a flexible circuit board, wherein the control unit is electrically connected to the flexible circuit board, the array substrate is electrically connected to the flexible circuit board, and the control unit provides electrical signals to the array substrate through the flexible circuit board.
10. A display device, characterized in that, Includes the display module as described in claim 9.