Display device and electronic device

Abstract

A display device including a display panel and an electronic device are provided. The display panel includes a display area and a non-display area. The display area includes a corner portion. The display device includes: a plurality of pixels disposed in the display area and arranged in a grid defined by rows in a first direction and columns in a second direction, a first group of pixels among the plurality of pixels arranged in the corner portion and disposed in a stepped manner to define a shape of the corner portion; a power connection line disposed in the non-display area in the first direction, extending from the non-display area to the corner portion in the second direction, and delivering a power voltage to the plurality of pixels; and a connection pattern electrically connecting the power connection line and extending in a direction away from a pixel of the plurality of pixels adjacent to the connection pattern in the second direction.

Description

Technical Field

[0001] This disclosure relates to a display device for displaying images and an electronic device including the display device. Background Technology

[0002] The display device includes pixels that emit light and drivers that transmit drive signals to the pixels. Each pixel includes a pixel drive circuit containing transistors and a light-emitting element electrically connected to the pixel drive circuit. When a pulse potential caused by electrostatic discharge (ESD) generated in the lines that transmit drive signals to the pixel is introduced into the pixel, the device characteristics of the transistors included in the pixel drive circuit may change, thereby degrading the quality of the image displayed on the display device.

[0003] Accordingly, there is a need for display devices with improved image quality. Summary of the Invention

[0004] This disclosure aims to solve various problems, including those related to image quality. This disclosure describes a display device with improved image quality, as well as an electronic device including the conceived display device.

[0005] However, the aspects of this disclosure are not limited to those set forth herein. These and other aspects of the disclosure will become apparent to those skilled in the art upon reference to the detailed description of the disclosure given below.

[0006] According to some aspects, a display device is provided, comprising: a display panel including a display area and a non-display area adjacent to the display area, the display area including a corner portion; a plurality of pixels disposed in the display area and arranged in a grid defined by rows in a first direction and columns in a second direction intersecting the first direction; power connection lines disposed in the non-display area in the first direction, extending from the non-display area to the corner portion in the second direction, and transmitting power voltage to the plurality of pixels; and a connection pattern electrically connecting the power connection lines and extending in a direction away from pixels of the plurality of pixels adjacent to the connection pattern in the second direction. In the corner portion, a first group of pixels of the plurality of pixels is disposed in a stepped manner to define the shape of the corner portion.

[0007] In some aspects, the power connection line includes: a first power connection line transmitting a first power voltage; a second power connection line transmitting the first power voltage; and a third power connection line transmitting a first initialization voltage. In some aspects, a connection pattern is connected to the first power connection line and the second power connection line, and the connection pattern at least partially overlaps with each of the first power connection line, the second power connection line, and the third power connection line.

[0008] In some aspects, the display device further includes a power connection pattern adjacent to the power connection line in a second direction. In some aspects, the connection pattern electrically connects the power connection line to the power connection pattern.

[0009] In some aspects, the connection pattern includes a first connection pattern and a second connection pattern disposed in different layers.

[0010] In some aspects, the first connection pattern is connected to the power connection pattern, and the second connection pattern is connected to the power connection line and the first connection pattern.

[0011] In some aspects, each of the plurality of pixels includes: an active pattern; a first gate electrode disposed on the active pattern; a capacitor electrode disposed on the first gate electrode; a second gate electrode disposed on the capacitor electrode; and a source electrode disposed on the second gate electrode. In some aspects, a first connection pattern and the first gate electrode are disposed in the same layer. In some aspects, a second connection pattern and the source electrode are disposed in the same layer.

[0012] In some aspects, each of the plurality of pixels includes: an active pattern; a first gate electrode disposed on the active pattern; a capacitor electrode disposed on the first gate electrode; a second gate electrode disposed on the capacitor electrode; and a source electrode disposed on the second gate electrode. In some aspects, the connecting pattern and the second gate electrode are disposed in the same layer.

[0013] In some aspects, the connecting pattern has a shape that bends in a direction opposite to the second direction. For example, the connecting pattern has a U-shaped bend in a direction opposite to the second direction.

[0014] In some aspects, at the corner portion, the first group of pixels includes: a first pixel, disposed in the first row; a second pixel, disposed in the second row; and a third pixel, disposed in the third row. In some aspects, the power connection line extends into the third row, and the power connection line is spaced apart from the second row.

[0015] In some aspects, the display device may further include: gate connection lines extending in a first direction from a display area to a non-display area, the gate connection lines transmitting gate signals to a plurality of pixels. The gate connection lines may include: a first gate connection line electrically connected to a first pixel; a second gate connection line electrically connected to a second pixel; and a third gate connection line electrically connected to a third pixel. The second gate connection line may extend further into the non-display area than the third gate connection line.

[0016] In some aspects, the ends of the first gate connection line and the second gate connection line can be positioned in a second direction.

[0017] In some aspects, a display device is provided, comprising: a display panel including a display area and a non-display area adjacent to the display area, the display area including a corner portion; a plurality of pixels arranged in the display area in a grid defined by rows in a first direction and columns in a second direction intersecting the first direction; and power connection lines arranged in the non-display area in the first direction, transmitting power voltage to the plurality of pixels. In the corner portion, a first group of pixels of the plurality of pixels is arranged in a stepped manner to define the shape of the corner portion, and includes a first pixel arranged in a first row, a second pixel arranged in a second row, and a third pixel arranged in a third row. The power connection lines extend in the second direction from the non-display area to the third row of the corner portion.

[0018] In some cases, the power connection lines are spaced apart from the second row.

[0019] In some aspects, the display device further includes a gate connection line that extends from the display area to the non-display area in a first direction and transmits gate signals to a plurality of pixels.

[0020] In some aspects, the gate connection line includes: a first gate connection line electrically connected to a first pixel, a second gate connection line electrically connected to a second pixel, and a third gate connection line electrically connected to a third pixel. The second gate connection line extends further into the non-display area compared to the third gate connection line, which extends into the non-display area.

[0021] In some aspects, the ends of the first gate connection line and the ends of the second gate connection line are arranged in a second direction.

[0022] In some aspects, the display device further includes a connection pattern that electrically connects the power connection lines.

[0023] In some aspects, the connecting pattern extends in a direction away from the pixels adjacent to the connecting pattern in a second direction in a plurality of pixels.

[0024] In some aspects, the power connection line includes: a first power connection line transmitting a first power voltage; a second power connection line transmitting the first power voltage; and a third power connection line transmitting a first initialization voltage. In some aspects, a connection pattern is connected to the first power connection line and the second power connection line, and the connection pattern at least partially overlaps with each of the first power connection line, the second power connection line, and the third power connection line.

[0025] In some aspects, an electronic device is provided, comprising: the display device described above; and a processor that provides control signals and input image data to the display device.

[0026] In some aspects, the display device includes power connection lines that transmit electrical voltage to pixels and connection patterns that electrically connect the power connection lines. In some aspects, the connection patterns extend in a direction away from pixels in corner portions. In some aspects, the power connection lines are arranged to be spaced apart from pixels in corner portions. Therefore, the introduction of pulse potentials caused by electrostatic discharge generated in the power connection lines into the pixels is reduced, thereby reducing or preventing malfunctions in the pixel driving circuit. Thus, the display quality of the display device is improved.

[0027] The advantages of the display device disclosed herein are not limited to those mentioned above, and various other effects will be described in the following detailed description. Attached Figure Description

[0028] The above and other aspects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0029] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0030] Figure 2 It is shown in the figure. Figure 1 A plan view of the display device;

[0031] Figure 3 The diagram shows what is included. Figure 1 The equivalent circuit diagram of a pixel in a display device;

[0032] Figure 4 The diagram shows what is included. Figure 1 A cross-sectional view of the display panel in the display device;

[0033] Figure 5 It is shown in the figure. Figure 2 An enlarged plan view of area A;

[0034] Figures 6 to 8 It is shown in the figure. Figure 5 An enlarged plan view of area B;

[0035] Figure 9 This is a plan view illustrating a display device according to an embodiment of the present disclosure;

[0036] Figure 10 This is a plan view illustrating a display device according to an embodiment of the present disclosure;

[0037] Figure 11 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure; and

[0038] Figure 12This is a schematic diagram illustrating an electronic device according to various embodiments of the present disclosure. Detailed Implementation

[0039] Although specific embodiments are illustrated in the accompanying drawings and described in detail below, this disclosure can be modified in various ways and implemented in many different forms. Accordingly, it should be understood that this disclosure is not limited to the specific form disclosed and should be construed as including all modifications, equivalents, or substitutions contained within the spirit and scope of this disclosure.

[0040] In the accompanying drawings, the dimensions and relative dimensions of individual components, layers, and regions may be exaggerated or reduced for clarity. For example, the dimensions and thicknesses of each component shown in the drawings are arbitrarily illustrated for ease of explanation, and therefore, current embodiments of the teachings of this disclosure are not necessarily limited to those shown. When described with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals, and redundant descriptions thereof are omitted.

[0041] Various modifications and forms may be made in this disclosure, and specific embodiments will be illustrated in the accompanying drawings and described in detail in the text. However, this is not intended to limit the subject matter to the specific disclosed embodiments, and those skilled in the art will understand that various changes, equivalents, or substitutions are thus possible.

[0042] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure. Similarly, the second element may also be referred to as the first element.

[0043] As used herein, the term “and / or” includes any and all combinations of one or more of the related listed items. For example, in this disclosure, “A and / or B” means A or B, or A and B, and “at least one of A and B” indicates that it is either A or B, or both A and B.

[0044] It should also be understood that when an element is referred to as being "on" another element, "connected to," or "coupled to" another element, it can be directly disposed on, directly connected to, or coupled to that other element, or there can be an intervening element between them. Conversely, when an element is referred to as being "directly on" another element, "directly connected to," or "directly coupled to" another element, there is no intervening element. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" and "directly between," "adjacent" and "directly adjacent," etc.).

[0045] Furthermore, the terms “approximately,” “generally,” and “basically” are intended, and would be understood by a person of ordinary skill, to mean that slight deviations from absolute values ​​are included within the scope of the terms so modified.

[0046] The first direction DR1, the second direction DR2, and the third direction DR3 are not limited to directions corresponding to the three axes in an orthogonal coordinate system, and can be interpreted in a broad sense that includes them. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be orthogonal to each other, but they can also refer to different directions that are not orthogonal to each other.

[0047] In some aspects, the display device can be included in various electronic devices. In some aspects, the electronic device includes the display device described above, and may further include modules or devices with additional functions in addition to the display device.

[0048] Furthermore, the terms "overlapping" or "overlapping" mean that the first object may be on top of, below, or to the side of the second object, and vice versa. Additionally, the term "overlapping" may include layering, stacking, facing or oriented towards, extending over, covering or partially covering, or any other suitable term that will be understood and appreciated by one of ordinary skill in the art.

[0049] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to limit the inventive concept.

[0050] As used herein, singular expressions such as “a” and “the (said)” are intended to include plural expressions unless the context clearly indicates otherwise.

[0051] It should also be further understood that the terms “including / comprise” and / or variations thereof, when used in this specification, indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or groups thereof.

[0052] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another illustrated in the accompanying drawings. It should be understood that these relative terms are intended to cover different orientations of the device other than those depicted in the drawings. For example, if the device in one of the drawings is flipped, the element described as being “below” the other element will be oriented “above” the other element. Thus, depending on the specific orientation of the drawing, the term “below” can encompass both “below” and “above” orientations. Similarly, if the device in one of the drawings is flipped, the element described as being “below” or “under” the other element will be positioned “above” the other element. Thus, the terms “below” or “under” can encompass both “above” and “below” orientations.

[0053] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will be further understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense, unless expressly so specified herein.

[0054] In the following description, various embodiments will be illustrated with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and redundant descriptions of the same parts will be omitted.

[0055] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0056] refer to Figure 1 The display device DD1 may include a display panel DP and a driver for driving the display panel DP. The driver may include a controller CON, a gate driver GDV, a transmit driver EDV, and a data driver DDV.

[0057] The display panel (DP) can include pixels (PX), gate lines (GL), emitter lines (EML), and data lines (DL). Each pixel (PX) can be electrically connected to the gate driver (GDV), emitter driver (EDV), and data driver (DDV), and can generate light according to the drive signal.

[0058] The gate driver GDV can receive the gate control signal GCTRL from the controller CON. The gate driver GDV can generate the gate signal GS based on the gate control signal GCTRL. The gate driver GDV can then provide the gate signal GS to the pixel PX via the gate line GL.

[0059] The transmit driver EDV can receive the transmit control signal ECTRL from the controller CON. The transmit driver EDV can generate the transmit signal EM based on the transmit control signal ECTRL. The transmit driver EDV can then provide the transmit signal EM to the pixel PX via the transmit line EML.

[0060] The data driver DDV can receive the data control signal DCTRL and output image data ODAT from the controller CON. The data driver DDV can generate a data voltage DATA based on the data control signal DCTRL and the output image data ODAT. The data driver DDV can supply the data voltage DATA to the pixel PX via the data line DL.

[0061] The controller CON can be controlled from external devices (e.g., Figure 11 The processor 12) receives the control signal CTRL and the input image data IDAT. The controller CON can generate the gate control signal GCTRL, the transmit control signal ECTRL, the data control signal DCTRL, and the output image data ODAT based on the control signal CTRL and the input image data IDAT. The controller CON can control the gate driver GDV, the transmit driver EDV, and the data driver DDV.

[0062] Figure 2 It is shown in the figure. Figure 1 A plan view of the display device.

[0063] refer to Figure 1 and Figure 2 The display device DD1 may include a display panel DP, a gate driver GDV, a transmit driver EDV, a data driver DDV, a power transmission line VTL, and pads PD. The display panel DP may include a display area DA and a non-display area NDA.

[0064] The display area DA can be an area capable of displaying an image. Pixels PX can be disposed in the display area DA. The display area DA can include a plurality of pixels PX disposed in the display area DA. The plurality of pixels PX can be arranged in a grid defined by rows on a first direction DR1 and columns on a second direction DR2 intersecting the first direction DR1. A first group of pixels PX among the plurality of pixels PX can be arranged in a corner portion DAc and arranged in a stepped manner to define the shape of the corner portion DAc (described below). For example, pixels PX can be repeatedly disposed on the first direction DR1 and the second direction DR2 intersecting the first direction DR1. When each of the pixels PX emits light, the display area DA can display an image. For example, the display area DA can display an image on a third direction DR3 intersecting each of the first direction DR1 and the second direction DR2.

[0065] In this embodiment, the display area DA may have a planar shape, but not a rectangular planar shape with right-angled corners. For example, the display area DA may have a rectangular planar shape with rounded corners. For example, the display area DA may have a rectangular planar shape with rounded corners, wherein the long side extends in a first direction DR1 and the short side extends in a second direction DR2. However, the embodiment is not limited to this, and the display area DA may have various planar shapes with curved portions.

[0066] In an embodiment, in a plan view, the display area DA may include a first side DA1, a second side DA2, a third side DA3, a fourth side DA4, and a corner portion DAc with a rounded shape. The first side DA1 and the third side DA3 may be opposite to each other and may each extend in a first direction DR1. The second side DA2 and the fourth side DA4 may be opposite to each other and may each extend in a second direction DR2.

[0067] Each corner section DAc can be defined between two adjacent sides among the first side DA1, the second side DA2, the third side DA3, and the fourth side DA4. The corner section DAc can connect the first side DA1 to the second side DA2, the second side DA2 to the third side DA3, the third side DA3 to the fourth side DA4, and the fourth side DA4 to the first side DA1.

[0068] The non-display area NDA can be an area where no image is displayed. The non-display area NDA can be adjacent to the display area DA. For example, in a plan view, the non-display area NDA can surround the display area DA. Drivers can be located in the non-display area NDA. For example, the gate driver GDV, transmit driver EDV, data driver DDV, power transfer line VTL, and pad PD can be located in the non-display area NDA.

[0069] For example, the gate driver GDV can be located in the non-display area NDA adjacent to the second side DA2 (e.g., the left side) of the display area DA, and the emitter driver EDV can be located in the non-display area NDA adjacent to the fourth side DA4 (e.g., the right side) of the display area DA. The gate driver GDV can output a gate signal GS to the gate line GL, and the gate signal GS can be applied to the pixel PX through the gate line GL. The emitter driver EDV can output an emitter signal EM to the emitter line EML, and the emitter signal EM can be applied to the pixel PX through the emitter line EML.

[0070] Figure 2The figure shows a gate driver (GDV) disposed on a first side portion of a display device DD1 and a transmitter driver (EDV) disposed on a second side portion of the display device DD1, but the embodiment is not limited thereto. For example, the gate driver (GDV) and the transmitter driver (EDV) may be disposed together on either the first or second side portion of the display device DD1. For example, the gate driver (GDV) and the transmitter driver (EDV) may be integrally formed.

[0071] For example, the data driver DDV can be located in the non-display area NDA adjacent to the first side DA1 (e.g., the lower side) of the display area DA. The data driver DDV can output the data voltage DATA to the data line DL, and the data voltage DATA can be applied to the pixel PX through the data line DL.

[0072] For example, a power transmission line (VTL) can be located in a non-display area (NDA) adjacent to the first side (DA1) of the display area (DA), for example, the lower side. In a plan view, the power transmission line (VTL) can be located between the display area (DA) and the data driver (DDV).

[0073] A power transmission line (VTL) can output a power voltage (e.g., a constant voltage) to a power line, and this power voltage can be applied to a pixel (PX) through the power line. In an embodiment, the power transmission line (VTL) may include multiple power transmission lines. For example, the power transmission line (VTL) may include a line to which a first power voltage (e.g., ...) is applied. Figure 3 The first power transmission line (with a first power voltage ELVDD) is subjected to a second power voltage (e.g., Figure 3 The second power transmission line of the second power voltage (ELVSS), to which a first initialization voltage (e.g., Figure 3 The third power transmission line with the first initialization voltage VINT) and the second initialization voltage applied to it (e.g., Figure 3 The fourth power transmission line is the second initialization voltage (VAINT).

[0074] In the non-display area NDA, the power transmission line VTL can extend along the planar contour of the display area DA. In an embodiment, the end of the power transmission line VTL can extend along the corner portion DAc. To provide power voltage to the pixel PX disposed in the area adjacent to the corner portion DAc, the end of the power transmission line VTL can extend along the corner portion DAc between the gate driver GDV and the display area DA or between the emitter driver EDV and the display area DA. That is, the power transmission line VTL can have a shape in which the end bends along the planar shape (e.g., a rounded planar shape) of the corner portion DAc. For example, a first end of the power transmission line VTL can extend along the rounded planar shape of the corner portion DAc defined between the first side DA1 and the second side DA2, and a second end of the power transmission line VTL can extend along the rounded planar shape of the corner portion DAc defined between the first side DA1 and the fourth side DA4.

[0075] For example, pad PD can be located in a non-display area NDA adjacent to the first side DA1 (e.g., the lower side) of display area DA. Pad PD can be electrically connected to the gate driver GDV, transmit driver EDV, data driver DDV, and power transmission line VTL.

[0076] Figure 3 The diagram shows what is included. Figure 1 The equivalent circuit diagram of a pixel in a display device.

[0077] refer to Figure 3 A pixel PX may include a light-emitting element LE and a pixel driving circuit PC electrically connected to the light-emitting element LE. The pixel driving circuit PC can generate a driving current, and the light-emitting element LE can generate light based on the driving current.

[0078] The pixel driving circuit PC may include at least one transistor and at least one capacitor. In an embodiment, the pixel driving circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C1.

[0079] The pixel driving circuit PC can be connected to a first power line VL1, a second power line VL2, a third power line VL3, and a fourth power line VL4. The first power line VL1 can transmit a first power voltage ELVDD, and the second power line VL2 can transmit a second power voltage ELVSS. The voltage level of the first power voltage ELVDD can be higher than the voltage level of the second power voltage ELVSS. The third power line VL3 can transmit a first initialization voltage VINT, and the fourth power line VL4 can transmit a second initialization voltage VAINT.

[0080] The first transistor T1 may include a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first transistor T1 can provide drive current to the light-emitting element LE. For example, the first transistor T1 may be referred to as a drive transistor.

[0081] The second transistor T2 may include a gate electrode for receiving a first gate signal GW, a first electrode for receiving a data voltage DATA, and a second electrode connected to the second node N2. The second transistor T2 may supply the data voltage DATA to the second node N2 in response to the first gate signal GW. For example, the second transistor T2 may be referred to as a write transistor.

[0082] The third transistor T3 may include a gate electrode for receiving the second gate signal GC, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The third transistor T3 may connect the first transistor T1 diode in response to the second gate signal GC. The third transistor T3 may form a path to compensate for the threshold voltage of the first transistor T1. For example, the third transistor T3 may be referred to as a compensation transistor.

[0083] The fourth transistor T4 may include a gate electrode receiving a third gate signal GI, a first electrode receiving a first initialization voltage VINT, and a second electrode connected to the first node N1. The fourth transistor T4 may provide the first initialization voltage VINT to the first node N1 in response to the third gate signal GI. The fourth transistor T4 may also provide the first initialization voltage VINT to the gate electrode of the first transistor T1 to initialize the voltage of the gate electrode of the first transistor T1. For example, the fourth transistor T4 may be referred to as a gate initialization transistor.

[0084] The fifth transistor T5 may include a gate electrode for receiving the transmit signal EM, a first electrode for receiving the first power voltage ELVDD, and a second electrode connected to the second node N2. The fifth transistor T5 may supply the first power voltage ELVDD to the second node N2 in response to the transmit signal EM. For example, the fifth transistor T5 may be referred to as the first emitter control transistor.

[0085] The sixth transistor T6 may include a gate electrode for receiving the emission signal EM, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The sixth transistor T6 may electrically connect the second electrode of the first transistor T1 to the first electrode of the light-emitting element LE in response to the emission signal EM. For example, the sixth transistor T6 may be referred to as the second emission control transistor.

[0086] Figure 3The figure shows that the fifth transistor T5 and the sixth transistor T6 are driven substantially simultaneously by a single transmit signal EM, but the embodiment is not limited to this. For example, the fifth transistor T5 and the sixth transistor T6 can be driven independently by different transmit signals.

[0087] The seventh transistor T7 may include a gate electrode receiving a fourth gate signal GB, a first electrode receiving a second initialization voltage VAINT, and a second electrode connected to a fourth node N4. The seventh transistor T7 may provide the second initialization voltage VAINT to the fourth node N4 in response to the fourth gate signal GB. The seventh transistor T7 may also provide the second initialization voltage VAINT to the first electrode of the light-emitting element LE to initialize the voltage of the first electrode of the light-emitting element LE. For example, the seventh transistor T7 may be referred to as an anode initialization transistor.

[0088] Capacitor C1 may include a first electrode that receives a first electrical voltage ELVDD and a second electrode connected to a first node N1. For example, capacitor C1 may be referred to as a storage capacitor.

[0089] The light-emitting element LE may include a first electrode connected to the fourth node N4 and a second electrode receiving a second electrical voltage ELVSS. The light-emitting element LE can produce light with a brightness corresponding to the driving current.

[0090] Figure 3 The figure shows that each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 is a p-type transistor, and each of the third transistor T3 and the fourth transistor T4 is an n-type transistor, but the embodiment is not limited thereto. For example, all the transistors in the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be p-type transistors, or at least one of the transistors in the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be an n-type transistor.

[0091] also, Figure 3 The figure shows a pixel driving circuit PC comprising seven transistors and a capacitor, but the embodiment is not limited thereto.

[0092] Figure 4 The diagram shows what is included. Figure 1 A cross-sectional view of the display panel in a display device.

[0093] refer to Figure 4The display panel DP may include a substrate SUB, a buffer layer BUF, a first transistor TR1, a first gate insulating layer GI1, a second gate insulating layer GI2, a capacitor electrode CAPE, a second transistor TR2, a first interlayer insulating layer ILD1, a third gate insulating layer GI3, a second interlayer insulating layer ILD2, a first through-hole insulating layer VIA1, a connection electrode LCE, a second through-hole insulating layer VIA2, a light-emitting element LE, a pixel limiting layer PDL, and a packaging layer TFE.

[0094] The first transistor TR1 may include a first lower electrode BME1, a first active pattern ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1. The second transistor TR2 may include a second lower electrode BME2, a second active pattern ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2. The light-emitting element LE may include a pixel electrode PE, an emitter layer EL, and a common electrode CE.

[0095] The first transistor TR1 can be a transistor connected to the light-emitting element LE via a connection electrode LCE. For example, the first transistor TR1 can be... Figure 3 The sixth transistor T6, and the second transistor TR2 can be Figure 3 The third transistor T3 or the fourth transistor T4.

[0096] The substrate SUB can form the base of the display panel DP. The substrate SUB can include transparent or opaque materials. For example, the substrate SUB can include plastic, glass, quartz, or silicon.

[0097] The first lower electrode BME1 can be disposed on the substrate SUB. The first lower electrode BME1 can include a conductive material such as a metal, alloy, conductive metal nitride, conductive metal oxide, or transparent conductive oxide. In an embodiment, the first lower electrode BME1 can be omitted.

[0098] A buffer layer BUF can be disposed on the first lower electrode BME1 and can cover the first lower electrode BME1. The buffer layer BUF can include materials such as silicon oxide (SiO2). x Silicon nitride (SiN) x ) or silicon oxynitride (SiO) x N y Inorganic insulating materials such as (e.g., buffer layer BUF). In the embodiments, the buffer layer BUF can be omitted.

[0099] A first active pattern ACT1 may be disposed on a buffer layer BUF. In a planar view, the first active pattern ACT1 may at least partially overlap with the first lower electrode BME1. The first active pattern ACT1 may include a first source region, a first drain region, and a first channel region between the first source region and the first drain region. The first active pattern ACT1 may include a semiconductor material such as silicon semiconductor material or oxide semiconductor material. Examples of silicon semiconductor materials may include amorphous silicon or polycrystalline silicon. Examples of oxide semiconductor materials may include indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO). In an embodiment, the first active pattern ACT1 may include a silicon semiconductor material.

[0100] The first gate insulating layer GI1 may be disposed on the first active pattern ACT1 and may cover the first active pattern ACT1. The first gate insulating layer GI1 may include an inorganic insulating material.

[0101] A first gate electrode GE1 may be disposed on a first gate insulating layer GI1. In a plan view, the first gate electrode GE1 may overlap with a first channel region of a first active pattern ACT1. The first gate electrode GE1 may include a conductive material.

[0102] The second gate insulating layer GI2 can be disposed on the first gate electrode GE1 and can cover the first gate electrode GE1. The second gate insulating layer GI2 may include an inorganic insulating material.

[0103] The capacitor electrode CAPE and the second lower electrode BME2 can be disposed on the second gate insulating layer GI2. In a plan view, the capacitor electrode CAPE can overlap with the first gate electrode GE1. For example, the capacitor electrode CAPE and the first gate electrode GE1 can form a... Figure 3 The capacitor C1. The capacitor electrode CAPE and the second lower electrode BME2 may include conductive material. In an embodiment, the second lower electrode BME2 may be omitted.

[0104] The first interlayer insulating layer ILD1 can be disposed on the capacitor electrode CAPE and the second lower electrode BME2, and can cover the capacitor electrode CAPE and the second lower electrode BME2. The first interlayer insulating layer ILD1 may include inorganic insulating material.

[0105] A second active pattern ACT2 may be disposed on the first interlayer insulating layer ILD1. In a plan view, the second active pattern ACT2 may at least partially overlap with the second lower electrode BME2. The second active pattern ACT2 may include a second source region, a second drain region, and a second channel region between the second source region and the second drain region. The second active pattern ACT2 may include a semiconductor material. In an embodiment, the second active pattern ACT2 may include an oxide semiconductor material.

[0106] The third gate insulating layer GI3 can be disposed on the second active pattern ACT2 and can cover the second active pattern ACT2. The third gate insulating layer GI3 may include an inorganic insulating material.

[0107] The second gate electrode GE2 can be disposed on the third gate insulating layer GI3. In a plan view, the second gate electrode GE2 can overlap with the second channel region of the second active pattern ACT2. The second gate electrode GE2 may include a conductive material.

[0108] The second interlayer insulating layer ILD2 can be disposed on the second gate electrode GE2 and can cover the second gate electrode GE2. The second interlayer insulating layer ILD2 may include an inorganic insulating material.

[0109] The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 can be disposed on the second interlayer insulating layer ILD2.

[0110] The first source electrode SE1 can be electrically connected to the first source region of the first active pattern ACT1 through a first contact hole penetrating the insulating layers disposed thereunder (e.g., the first gate insulating layer GI1, the second gate insulating layer GI2, and the third gate insulating layer GI3, as well as the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2). The first drain electrode DE1 can be electrically connected to the first drain region of the first active pattern ACT1 through a second contact hole penetrating the insulating layers disposed thereunder (e.g., the first gate insulating layer GI1, the second gate insulating layer GI2, and the third gate insulating layer GI3, as well as the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2).

[0111] The second source electrode SE2 can be electrically connected to the second source region of the second active pattern ACT2 through a third contact hole that penetrates the insulating layer (e.g., the third gate insulating layer GI3 and the second interlayer insulating layer ILD2) disposed below it. The second drain electrode DE2 can be electrically connected to the second drain region of the second active pattern ACT2 through a fourth contact hole that penetrates the insulating layer (e.g., the third gate insulating layer GI3 and the second interlayer insulating layer ILD2) disposed below it.

[0112] Accordingly, a first transistor TR1 defined by a first lower electrode BME1, a first active pattern ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1, and a second transistor TR2 defined by a second lower electrode BME2, a second active pattern ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2 can be disposed in the display area DA and on the substrate SUB.

[0113] The first through-hole insulating layer VIA1 can be disposed on the first source electrode SE1, the second source electrode SE2, the first drain electrode DE1, and the second drain electrode DE2, and can cover the first source electrode SE1, the second source electrode SE2, the first drain electrode DE1, and the second drain electrode DE2. The first through-hole insulating layer VIA1 can include organic insulating materials such as phenolic resin, acrylic resin, polyimide resin, polyamide resin, silicone resin, or epoxy resin.

[0114] The connection electrode LCE can be disposed on the first via insulating layer VIA1. The connection electrode LCE can be electrically connected to the first source electrode SE1 or the first drain electrode DE1 through a contact hole penetrating the insulating layer (e.g., the first via insulating layer VIA1) disposed therebelow. Accordingly, the connection electrode LCE can electrically connect the first transistor TR1 to the light-emitting element LE. The connection electrode LCE may include a conductive material.

[0115] The second through-hole insulating layer VIA2 can be disposed on the connecting electrode LCE and can cover the connecting electrode LCE. The second through-hole insulating layer VIA2 may include an organic insulating material.

[0116] The pixel electrode PE can be disposed on the second via insulating layer VIA2. The pixel electrode PE can be electrically connected to the connection electrode LCE through a contact hole penetrating the insulating layer (e.g., the second via insulating layer VIA2) disposed beneath it. The pixel electrode PE can include a conductive material. For example, the pixel electrode PE can be used as… Figure 3 The first electrode of the light-emitting element (LE) is used to perform its function.

[0117] A pixel defining layer (PDL) may be disposed on the second via insulating layer (VIA2). The PDL may cover the edge portion of the pixel electrode (PE) and may define an opening that exposes at least a portion of the upper surface of the pixel electrode (PE). The PDL may comprise an organic insulating material or an inorganic insulating material.

[0118] An emitting layer EL can be disposed on a pixel electrode PE. The emitting layer EL can be disposed on the upper surface of the pixel electrode PE exposed by the pixel defining layer PDL. The emitting layer EL can include a material that emits light of a predetermined color. For example, the emitting layer EL can include a material that emits light in the red, green, or blue bands, but the embodiments are not limited thereto.

[0119] A common electrode CE can be disposed on the pixel-defining layer PDL and the emitter layer EL. The common electrode CE may include a conductive material. For example, the common electrode CE can be used as… Figure 3 The second electrode of the light-emitting element (LE) is used to perform its function.

[0120] Accordingly, a light-emitting element LE, defined by a pixel electrode PE, an emitting layer EL, and a common electrode CE, can be disposed in the display area DA and on the substrate SUB. The light-emitting element LE can be electrically connected to a first transistor TR1 and can generate light corresponding to the driving current supplied from the first transistor TR1.

[0121] The encapsulation layer TFE can be disposed on the common electrode CE. The encapsulation layer TFE can prevent or reduce the penetration of impurities or moisture from the outside into the light-emitting element LE. The encapsulation layer TFE may include at least one inorganic encapsulation layer containing inorganic insulating material and at least one organic encapsulation layer containing organic insulating material.

[0122] Figure 5 It is shown in the figure. Figure 2 Enlarged plan view of area A. Figure 5 The diagram can illustrate the pixel PX, the gate driver GDV, and the power transmission line VTL located in the area adjacent to the corner portion DAc.

[0123] refer to Figure 2 and Figure 5 In the corner portion DAc, pixels PX can be set in a stepped manner. Pixels PX can be set in a stepped manner to define the corner portion DAc of the display area DA, which has a rounded planar shape.

[0124] The gate driver GDV can transmit gate signals to pixels PX via gate lines GL. For example, the gate signals may include... Figure 3 The first gate signal GW, the second gate signal GC, the third gate signal GI, and the fourth gate signal GB. The data driver DDV can connect via the data line DL. Figure 3 The data voltage DATA is transmitted to the pixel PX.

[0125] In the plan view, the end of the power transmission line VTL can extend between the gate driver GDV and the corner portion DAc. For example, the gate driver GDV and the power transmission line VTL can extend along the corner portion DAc. The power transmission line VTL can transmit electrical voltage to the pixel PX through the power line VL. For example, the power line VL can include... Figure 3 The first power line VL1, the second power line VL2, the third power line VL3, and the fourth power line VL4, and the power voltage may include Figure 3 The first power voltage ELVDD and the second power voltage ELVSS, as well as the first initialization voltage VINT and the second initialization voltage VAINT.

[0126] Figure 5The figure illustrates that in the corner portion DAc, pixel PX is arranged in a stepped manner, consisting of one pixel PX on the first direction DR1 and four pixels PX on the second direction DR2, but the embodiment is not limited to this. The number of pixels PX arranged in a stepped manner in the corner portion DAc can be varied depending on the embodiment.

[0127] The structure in which the pixel PX in the corner portion DAc connecting the first side DA1 and the second side DA2 is connected to the gate driver GDV and the power transmission line VTL can be similar to and symmetrical to the structure in which the pixel PX in the corner portion DAc connecting the first side DA1 and the fourth side DA4 is connected to the transmit driver EDV and the power transmission line VTL.

[0128] Figures 6 to 8 It is shown in the figure. Figure 5 Enlarged plan view of area B. Figures 6 to 8 The outermost region of the corner section DAc can be illustrated.

[0129] refer to Figures 2 to 4 as well as Figures 6 to 8 The display device DD1 may include multiple lines for transmitting data voltage DATA, power voltage and gate signal GS to pixel PX in the display area DA and the non-display area NDA.

[0130] In an embodiment, the display device DD1 may include a first data connection line DCL1, a second data connection line DCL2, a third data connection line DCL3, a first power connection line VCL1, a second power connection line VCL2, a third power connection line VCL3, a fourth power connection line VCL4, a fifth power connection line VCL5, a sixth power connection line VCL6, and a gate connection line GCL. For example, each of the first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3, as well as the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3, may extend in a second direction DR2, and each of the fourth power connection line VCL4, the fifth power connection line VCL5, the sixth power connection line VCL6, and the gate connection line GCL may extend in a first direction DR1.

[0131] Pixel PX may include a first pixel PX1 located in the nth row (where n is a natural number greater than 0), a second pixel PX2 located in the (n+1)th row, and a third pixel PX3 located in the (n+2)th row. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be arranged sequentially in the display area DA in the direction opposite to the second direction DR2. Since the pixels PX are arranged in a stepped manner in the corner portion DAc, the first pixel PX1 may be configured to protrude more than the second pixel PX2 and the third pixel PX3 in the direction opposite to the first direction DR1.

[0132] The first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3 can be electrically connected to the data driver DDV and can be included in the data line DL. The first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3 can transmit the data voltage DATA to the pixel PX. The first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3 can be located in the non-display area NDA.

[0133] In this embodiment, the first data connection line DCL1, the third data connection line DCL3, and the capacitor electrode CAPE can be disposed in the same layer, and the second data connection line DCL2 and the first gate electrode GE1 can be disposed in the same layer. The first data connection line DCL1, the third data connection line DCL3, and the capacitor electrode CAPE can comprise the same material and can be formed using the same process. The second data connection line DCL2 and the first gate electrode GE1 can comprise the same material and can be formed using the same process. However, the embodiment is not limited thereto, and the layer in which the first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3 are disposed can be changed depending on the embodiment.

[0134] The first power connection line VCL1, the second power connection line VCL2, the third power connection line VCL3, the fourth power connection line VCL4, the fifth power connection line VCL5, and the sixth power connection line VCL6 can be electrically connected to the power transmission line VTL and can be included in the power line VL. The first power connection line VCL1, the second power connection line VCL2, the third power connection line VCL3, the fourth power connection line VCL4, the fifth power connection line VCL5, and the sixth power connection line VCL6 can transmit power voltage to the pixel PX.

[0135] In this embodiment, the first power connection line VCL1 and the second power connection line VCL2 can receive a first power voltage ELVDD and transmit the first power voltage ELVDD to the pixel PX. The third power connection line VCL3 and the sixth power connection line VCL6 can receive a first initialization voltage VINT and transmit the first initialization voltage VINT to the pixel PX. The fourth power connection line VCL4 can receive a second power voltage ELVSS and transmit the second power voltage ELVSS to the pixel PX. The fifth power connection line VCL5 can receive a second initialization voltage VAINT and transmit the second initialization voltage VAINT to the pixel PX.

[0136] The first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3 can be disposed in the non-display area NDA, and the fourth power connection line VCL4, the fifth power connection line VCL5, and the sixth power connection line VCL6 can be disposed in the display area DA. For example, the fourth power connection line VCL4, the fifth power connection line VCL5, and the sixth power connection line VCL6 can extend from the display area DA to the non-display area NDA. For example, the fourth power connection line VCL4 can include a fourth-first power connection line VCL41, a fourth-second power connection line VCL42, and a fourth-third power connection line VCL43 that respectively transmit power voltage to the first pixel PX1, the second pixel PX2, and the third pixel PX3. The fifth power connection line VCL5 can include a fifth-first power connection line VCL51, a fifth-second power connection line VCL52, and a fifth-third power connection line VCL53 that respectively transmit power voltage to the first pixel PX1, the second pixel PX2, and the third pixel PX3. The sixth power connection line VCL6 may include a sixth-first power connection line VCL61, a sixth-second power connection line VCL62, and a sixth-third power connection line VCL63 that respectively transmit power voltage to the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0137] In the embodiment, reference Figure 6 The first power connection line VCL1, the second power connection line VCL2, the third power connection line VCL3, and the second gate electrode GE2 can be disposed in the same layer. The first power connection line VCL1, the second power connection line VCL2, the third power connection line VCL3, and the second gate electrode GE2 can include the same material and can be formed by the same process.

[0138] In the embodiment, reference Figure 7The first power connection line VCL1, the second power connection line VCL2, the third power connection line VCL3, and the capacitor electrode CAPE can be disposed in the same layer. The first power connection line VCL1, the second power connection line VCL2, the third power connection line VCL3, and the capacitor electrode CAPE can include the same material and can be formed by the same process.

[0139] In the embodiment, reference Figure 8 The first power connection line VCL1, the second power connection line VCL2, the third power connection line VCL3, and the first source electrode SE1 can be disposed in the same layer. The first power connection line VCL1, the second power connection line VCL2, the third power connection line VCL3, and the first source electrode SE1 can include the same material and can be formed by the same process.

[0140] In this embodiment, the fourth power connection VCL4 and the first source electrode SE1 can be disposed in the same layer, the fifth power connection VCL5 and the second gate electrode GE2 can be disposed in the same layer, and the sixth power connection VCL6 and the capacitor electrode CAPE can be disposed in the same layer. The fourth power connection VCL4 and the first source electrode SE1 can comprise the same material and can be formed using the same process. The fifth power connection VCL5 and the second gate electrode GE2 can comprise the same material and can be formed using the same process. The sixth power connection VCL6 and the capacitor electrode CAPE can comprise the same material and can be formed using the same process. However, the embodiment is not limited to this, and the layer in which the first power connection VCL1, the second power connection VCL2, the third power connection VCL3, the fourth power connection VCL4, the fifth power connection VCL5, and the sixth power connection VCL6 are disposed can be varied depending on the embodiment.

[0141] In an embodiment, the display device DD1 may include a connection pattern CP that electrically connects the first power connection line VCL1 and the second power connection line VCL2. Furthermore, the display device DD1 may further include a power connection pattern VCP that is adjacent to and electrically connected to the first power connection line VCL1 and the second power connection line VCL2 in a second direction DR2, and the connection pattern CP may electrically connect the first power connection line VCL1, the second power connection line VCL2, and the power connection pattern VCP. In a plan view, the connection pattern CP may overlap with each of the first power connection line VCL1, the second power connection line VCL2, and the power connection pattern VCP. The connection pattern CP may be connected to each end of the first power connection line VCL1 and the second power connection line VCL2 that transmits the same power voltage (e.g., a first power voltage ELVDD).

[0142] In the following text, reference will be made to Figure 6 and Figure 7 To describe the connection pattern CP.

[0143] In an embodiment, a connection pattern CP can be defined as multiple patterns. The connection pattern CP may include a first connection pattern CP1 and a second connection pattern CP2. For example, the first connection pattern CP1 can be connected to a power connection pattern VCP via contact holes, and the second connection pattern CP2 can be connected to a first power connection line VCL1, a second power connection line VCL2, and the first connection pattern CP1 via contact holes, respectively. The first connection pattern CP1 and the second connection pattern CP2 can be disposed in different layers.

[0144] In this embodiment, the first connection pattern CP1 and the first gate electrode GE1 may be disposed in the same layer, and the second connection pattern CP2 and the first source electrode SE1 may be disposed in the same layer. The first connection pattern CP1 and the first gate electrode GE1 may comprise the same material and may be formed by the same process. The second connection pattern CP2 and the first source electrode SE1 may comprise the same material and may be formed by the same process. However, the embodiment is not limited thereto, and the layer in which the first connection pattern CP1 and the second connection pattern CP2 are disposed may be changed depending on the embodiment.

[0145] In an embodiment, each of the first connection pattern CP1 and the second connection pattern CP2 may extend in a direction away from the pixel PX adjacent to the first connection pattern CP1 and the second connection pattern CP2 in the second direction DR2. Each of the first connection pattern CP1 and the second connection pattern CP2 may have a shape extending in a direction away from the first pixel PX1 (e.g., the first pixel PX1 located at the outermost edge of the corner portion DAc). Each of the first connection pattern CP1 and the second connection pattern CP2 may have a shape that curves in a direction opposite to the second direction DR2. For example, each of the first connection pattern CP1 and the second connection pattern CP2 may have a U-shaped planar shape. For example, in a planar view, the first connection pattern CP1 may at least partially overlap with each of the third power connection line VCL3 and the third data connection line DCL3, and the second connection pattern CP2 may at least partially overlap with each of the first power connection line VCL1, the second power connection line VCL2, and the second data connection line DCL2.

[0146] Since the connection pattern CP, which electrically connects the first power connection line VCL1 and the second power connection line VCL2, is formed away from the first pixel PX1, the introduction of pulse potentials caused by electrostatic discharge in the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3 into the first pixel PX1 can be reduced. Furthermore, since the connection pattern CP is defined by the first connection pattern CP1 and the second connection pattern CP2, and the first connection pattern CP1 and the second connection pattern CP2 are formed in different layers spaced apart on the third-direction DR3, the introduction of pulse potentials caused by electrostatic discharge in the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3 into the first pixel PX1 can be further reduced.

[0147] In the following text, reference will be made to Figure 8 To describe the connection pattern CP.

[0148] In this embodiment, the connection pattern CP can be defined as a single pattern. For example, the connection pattern CP can be connected to the first power connection line VCL1, the second power connection line VCL2, and the power connection pattern VCP respectively through each contact hole.

[0149] In this embodiment, the connection pattern CP and the second gate electrode GE2 may be disposed in the same layer. The connection pattern CP and the second gate electrode GE2 may comprise the same material and may be formed by the same process. However, the embodiment is not limited thereto, and the layer in which the connection pattern CP is disposed may vary depending on the embodiment.

[0150] In an embodiment, the connection pattern CP may extend in a direction away from the pixel PX adjacent to the connection pattern CP in the second direction DR2. The connection pattern CP may have a shape extending in a direction away from the first pixel PX1 (e.g., the first pixel PX1 located at the outermost edge of the corner portion DAc). The connection pattern CP may have a shape that curves in a direction opposite to the second direction DR2. For example, the connection pattern CP may have a W-shaped planar shape. For example, in a planar view, the connection pattern CP may at least partially overlap with each of the first power connection line VCL1, the second power connection line VCL2, the third power connection line VCL3, the second data connection line DCL2, and the third data connection line DCL3.

[0151] Since the connection pattern CP that electrically connects the first power connection line VCL1 and the second power connection line VCL2 is formed away from the first pixel PX1, the pulse potential caused by electrostatic discharge generated in the first power connection line VCL1, the second power connection line VCL2 and the third power connection line VCL3 can be reduced from being introduced into the first pixel PX1.

[0152] Refer again Figures 2 to 4 as well as Figures 6 to 8 The first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3, as well as the first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3, can be positioned adjacent to the corner portion DAc in which the pixel PX is arranged in a stepped manner. The first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3, as well as the first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3, can extend to the outermost edge of the corner portion DAc. In the plan view of the non-display area NDA, a portion (e.g., an end) of each of the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3, as well as the first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3, can be arranged with a stepped difference, which is formed by the stepped arrangement of the pixel PX in the corner portion DAc. The first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3, as well as the first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3, can extend to the area where the first pixel PX1 protrudes more than the second pixel PX2 and the third pixel PX3.

[0153] The ends of the first power connection line VCL1, the second power connection line VCL2, the third power connection line VCL3, the first data connection line DCL1, the second data connection line DCL2, the third data connection line DCL3, the power connection pattern VCP, and the second pixel PX2 can be arranged in the same row (i.e., the (n+1)th row). The ends of the first data connection line DCL1, the first power connection line VCL1, the second data connection line DCL2, the second power connection line VCL2, the third data connection line DCL3, the third power connection line VCL3, the power connection pattern VCP, and the second pixel PX2 can be arranged on the first direction DR1.

[0154] In this embodiment, the first data connection line DCL1, the first power connection line VCL1, the second data connection line DCL2, the second power connection line VCL2, the third power connection line VCL3, and the third data connection line DCL3 can be sequentially arranged on the first direction DR1. However, the embodiment is not limited to this, and the arrangement of the lines can be changed depending on the embodiment.

[0155] A gate connection line (GCL) can be electrically connected to the gate driver (GDV) and can be included in a gate line (GL). The gate connection line (GCL) can transmit the gate signal (GS) to the pixel (PX). The gate connection line (GCL) can be located in the display area (DA). For example, the gate connection line (GCL) can extend from the display area (DA) to the non-display area (NDA). For example, the gate connection line (GCL) can include a first gate connection line (GCL1), a second gate connection line (GCL2), and a third gate connection line (GCL3) that respectively transmit the gate signal (GS) to the first pixel (PX1), the second pixel (PX2), and the third pixel (PX3). The gate signal (GS) can include a first gate signal (GW), a second gate signal (GC), a third gate signal (GI), and a fourth gate signal (GB), and the gate connection line (GCL) can include multiple lines that transmit the first gate signal (GW), the second gate signal (GC), the third gate signal (GI), and the fourth gate signal (GB) to the pixel (PX).

[0156] In one embodiment, the gate connection line GCL may be disposed in the same layer as the first source electrode SE1. The gate connection line GCL may be made of the same material as the first source electrode SE1 and may be formed by the same process. However, the embodiment is not limited thereto, and the layer in which the gate connection line GCL is disposed may be changed depending on the embodiment.

[0157] The display device DD1 according to an embodiment may include a first power connection line VCL1, a second power connection line VCL2, and a third power connection line VCL3 that transmit power voltage to the pixel PX, and a connection pattern CP that electrically connects the first power connection line VCL1 and the second power connection line VCL2. Since the connection pattern CP extends away from the pixel PX located in the corner portion DAc, the introduction of pulse potentials caused by electrostatic discharge generated in the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3 into the pixel PX can be reduced. Accordingly, malfunctions of the pixel driving circuit PC can be reduced, and the display quality of the display device DD1 can be improved.

[0158] Figure 9 This is a plan view of a display device according to an embodiment. Figure 9 It can correspond to Figures 6 to 8 . Figure 9 The outermost region of the corner section DAc can be illustrated.

[0159] In the following text, in conjunction with the above references Figures 1 to 8 The repeated descriptions of the display device DD1 may be omitted or simplified.

[0160] refer to Figure 9The display device DD2 may include a first data connection line DCL1, a second data connection line DCL2 and a third data connection line DCL3 that transmit data voltage to the pixel PX, a first power connection line VCL1, a second power connection line VCL2 and a third power connection line VCL3 that transmit power voltage to the pixel PX, a first power connection line VCL1, a second power connection line VCL2 and a third power connection line VCL3, a fourth power connection line VCL4, a fifth power connection line VCL5 and a sixth power connection line VCL6 that transmit gate signals to the pixel PX, and a connection pattern CP that electrically connects the first power connection line VCL1 and the second power connection line VCL2.

[0161] For example, each of the first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3, as well as the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3, can extend in the second direction DR2, and each of the fourth power connection line VCL4, the fifth power connection line VCL5, the sixth power connection line VCL6, and the gate connection line GCL can extend in the first direction DR1.

[0162] Pixel PX may include a first pixel PX1 located in the nth row, a second pixel PX2 located in the (n+1)th row, and a third pixel PX3 located in the (n+2)th row. Pixels PX may be arranged in a stepped manner in the corner portion DAc of the display area DA, and the first pixel PX1 may be configured to protrude more than the second pixel PX2 and the third pixel PX3 in a direction opposite to the first direction DR1.

[0163] The first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3, as well as the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3, can be located in the non-display area NDA. Furthermore, the fourth power connection line VCL4, the fifth power connection line VCL5, and the sixth power connection line VCL6, as well as the gate connection line GCL, can extend from the display area DA to the non-display area NDA.

[0164] The first power connection line VCL1 and the second power connection line VCL2 can transmit the first power voltage, the third power connection line VCL3 and the sixth power connection line VCL6 can transmit the first initialization voltage, the fourth power connection line VCL4 can transmit the second power voltage, and the fifth power connection line VCL5 can transmit the second initialization voltage.

[0165] In this embodiment, the ends of the first power connection line VCL1, the second power connection line VCL2, the third power connection line VCL3, the first data connection line DCL1, the second data connection line DCL2, the third data connection line DCL3, and the third pixel PX3 can be disposed in the same row (i.e., row n+2). The first power connection line VCL1, the second power connection line VCL2, the third power connection line VCL3, and the first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3 can extend from the non-display area NDA to the row where the third pixel PX3 is disposed (i.e., row n+2), and may not be disposed in the row where the second pixel PX2 is disposed (i.e., row n+1). The first power connection line VCL1, the second power connection line VCL2, the third power connection line VCL3, and the first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3 can be spaced apart from the row where the second pixel PX2 is disposed. The ends of the first data connection line DCL1, the first power connection line VCL1, the second data connection line DCL2, the second power connection line VCL2, the third data connection line DCL3, the third power connection line VCL3, and the third pixel PX3 can be set on the first direction DR1.

[0166] In other words, the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3, as well as the first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3, can be spaced apart from adjacent pixels PX (e.g., the first pixel PX1) in the second direction DR2 by one pixel row. Since the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3 are formed to be spaced apart from the first pixel PX1, the pulse potential caused by electrostatic discharge generated in the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3 can be reduced from being introduced into the first pixel PX1.

[0167] The fourth power connection line VCL4 may include fourth-to-first power connection lines VCL41, fourth-to-second power connection lines VCL42, and fourth-to-third power connection lines VCL43, which respectively transmit power voltage to the first pixel PX1, the second pixel PX2, and the third pixel PX3. The fifth power connection line VCL5 may include fifth-to-first power connection lines VCL51, fifth-to-second power connection lines VCL52, and fifth-to-third power connection lines VCL53, which respectively transmit power voltage to the first pixel PX1, the second pixel PX2, and the third pixel PX3. The sixth power connection line VCL6 may include sixth-to-first power connection lines VCL61, sixth-to-second power connection lines VCL62, and sixth-to-third power connection lines VCL63, which respectively transmit power voltage to the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0168] In this embodiment, the fourth-first power connection VCL41, the fourth-second power connection VCL42, the fifth-first power connection VCL51, the fifth-second power connection VCL52, the sixth-first power connection VCL61, and the sixth-second power connection VCL62 may extend further in a direction opposite to the first direction DR1 than the fourth-third power connection VCL43, the fifth-third power connection VCL53, and the sixth-third power connection VCL63. The ends of the fourth-first power connection VCL41, the fifth-first power connection VCL51, the sixth-first power connection VCL61, the fourth-second power connection VCL42, the fifth-second power connection VCL52, and the sixth-second power connection VCL62 may be positioned in the second direction DR2. The ends of the fourth-third power connection line VCL43, the fifth-third power connection line VCL53, and the sixth-third power connection line VCL63 can be disposed on the second direction DR2. The column containing the ends of the fourth-first power connection line VCL41, the fifth-first power connection line VCL51, the sixth-first power connection line VCL61, the fourth-second power connection line VCL42, the fifth-second power connection line VCL52, and the sixth-second power connection line VCL62 can be spaced apart on the first direction DR1 from the column containing the ends of the fourth-third power connection line VCL43, the fifth-third power connection line VCL53, and the sixth-third power connection line VCL63.

[0169] The fourth-second power connection line VCL42, the fifth-second power connection line VCL52, and the sixth-second power connection line VCL62 may extend further into the non-display area NDA than the fourth-third power connection line VCL43, the fifth-third power connection line VCL53, and the sixth-third power connection line VCL63. In an embodiment, the fourth-second power connection line VCL42, the fifth-second power connection line VCL52, and the sixth-second power connection line VCL62 electrically connected to the second pixel PX2 may extend one pixel column further than the fourth-third power connection line VCL43, the fifth-third power connection line VCL53, and the sixth-third power connection line VCL63 electrically connected to the third pixel PX3.

[0170] The gate connection line GCL may include a first gate connection line GCL1, a second gate connection line GCL2, and a third gate connection line GCL3 that respectively transmit gate signals to the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0171] In an embodiment, the first gate connection line GCL1 and the second gate connection line GCL2 may extend further than the third gate connection line GCL3 in a direction opposite to the first direction DR1. The ends of the first gate connection line GCL1 and the second gate connection line GCL2 may be disposed in the second direction DR2. The column in which the ends of the third gate connection line GCL3 are disposed may be spaced apart from the column in which the ends of the first gate connection line GCL1 and the second gate connection line GCL2 are disposed in the first direction DR1.

[0172] The second gate connection line GCL2 may extend further into the non-display area NDA than the third gate connection line GCL3. In an embodiment, the second gate connection line GCL2, which is electrically connected to the second pixel PX2, may extend further by one pixel column than the third gate connection line GCL3, which is electrically connected to the third pixel PX3.

[0173] The connection pattern CP can be connected to the ends of the first power connection line VCL1 and the second power connection line VCL2 respectively through contact holes. In an embodiment, the connection pattern CP can extend closer to the adjacent pixel PX in the second direction DR2. The connection pattern CP can have a shape extending closer to the first pixel PX1 (e.g., the first pixel PX1 located at the outermost edge of the corner portion DAc). The connection pattern CP can have a curved shape in the second direction DR2. For example, the connection pattern CP can have an M-shaped planar shape. For example, the connection pattern CP may not overlap with the second data connection line DCL2, the third data connection line DCL3, and the third power connection line VCL3 in a planar view.

[0174] The display device DD2 according to an embodiment may include a first power connection line VCL1, a second power connection line VCL2, and a third power connection line VCL3 that transmit power voltage to the pixel PX. Since the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3 are spaced apart from the pixel PX disposed in the corner portion DAc, the introduction of pulse potentials caused by electrostatic discharge generated in the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3 into the pixel PX can be reduced. Accordingly, malfunctions in the pixel driving circuit can be reduced, and the display quality of the display device DD2 can be improved.

[0175] Figure 10 This is a plan view of a display device according to an embodiment. Figure 10 It can correspond to Figures 6 to 8 . Figure 10 The outermost region of the corner section DAc can be illustrated.

[0176] The following is for reference Figure 10 The described display device DD3 can be a display device that combines the structures of the display devices DD1 and DD2 described above. In the following text, it will be referred to as above. Figures 1 to 8 The described display device DD1 and the above reference Figure 9 The repeated descriptions of the display device DD2 may be omitted or simplified.

[0177] refer to Figure 10 The display device DD3 may include a first data connection line DCL1, a second data connection line DCL2 and a third data connection line DCL3 that transmit data voltage to the pixel PX, a first power connection line VCL1, a second power connection line VCL2 and a third power connection line VCL3 that transmit power voltage to the pixel PX, a fourth power connection line VCL4, a fifth power connection line VCL5 and a sixth power connection line VCL6 that transmit gate signals to the pixel PX, and a connection pattern CP that electrically connects the first power connection line VCL1 and the second power connection line VCL2.

[0178] Pixel PX may include a first pixel PX1 located in the nth row, a second pixel PX2 located in the (n+1)th row, and a third pixel PX3 located in the (n+2)th row. Pixels PX may be arranged in a stepped manner in the corner portion DAc of the display area DA, and the first pixel PX1 may be configured to protrude more than the second pixel PX2 and the third pixel PX3 in a direction opposite to the first direction DR1.

[0179] The first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3, as well as the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3, can be located in the non-display area NDA. Furthermore, the fourth power connection line VCL4, the fifth power connection line VCL5, and the sixth power connection line VCL6, as well as the gate connection line GCL, can extend from the display area DA to the non-display area NDA.

[0180] In this embodiment, the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3, as well as the first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3, can be located in the row where the third pixel PX3 is located (i.e., the (n+2)th row), and may not be located in the row where the second pixel PX2 is located (i.e., the (n+1)th row). That is, the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3, as well as the first data connection line DCL1, the second data connection line DCL2, and the third data connection line DCL3, can be located one pixel away from the first pixel PX1.

[0181] The fourth power connection line VCL4 may include fourth-to-first power connection lines VCL41, fourth-to-second power connection lines VCL42, and fourth-to-third power connection lines VCL43, which respectively transmit power voltage to the first pixel PX1, the second pixel PX2, and the third pixel PX3. The fifth power connection line VCL5 may include fifth-to-first power connection lines VCL51, fifth-to-second power connection lines VCL52, and fifth-to-third power connection lines VCL53, which respectively transmit power voltage to the first pixel PX1, the second pixel PX2, and the third pixel PX3. The sixth power connection line VCL6 may include sixth-to-first power connection lines VCL61, sixth-to-second power connection lines VCL62, and sixth-to-third power connection lines VCL63, which respectively transmit power voltage to the first pixel PX1, the second pixel PX2, and the third pixel PX3. The gate connection line GCL may include a first gate connection line GCL1, a second gate connection line GCL2, and a third gate connection line GCL3 that respectively transmit gate signals to the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0182] In the embodiment, the fourth-first power connection line VCL41, the fourth-second power connection line VCL42, the fifth-first power connection line VCL51, the fifth-second power connection line VCL52, the sixth-first power connection line VCL61, the sixth-second power connection line VCL62, the first gate connection line GCL1, and the second gate connection line GCL2 may extend further in a direction opposite to the first direction DR1 than the fourth-third power connection line VCL43, the fifth-third power connection line VCL53, the sixth-third power connection line VCL63, and the third gate connection line GCL3.

[0183] The fourth-second power connection line VCL42, the fifth-second power connection line VCL52, the sixth-second power connection line VCL62, and the second gate connection line GCL2 can extend further into the non-display area NDA than the fourth-third power connection line VCL43, the fifth-third power connection line VCL53, the sixth-third power connection line VCL63, and the third gate connection line GCL3. In an embodiment, the fourth-second power connection line VCL42, the fifth-second power connection line VCL52, the sixth-second power connection line VCL62, and the second gate connection line GCL2 electrically connected to the second pixel PX2 can extend one pixel column further than the fourth-third power connection line VCL43, the fifth-third power connection line VCL53, the sixth-third power connection line VCL63, and the third gate connection line GCL3 electrically connected to the third pixel PX3.

[0184] The connection pattern CP can electrically connect the first power connection line VCL1, the second power connection line VCL2, and the power connection pattern VCP. The connection pattern CP can be connected to the ends of the first power connection line VCL1 and the second power connection line VCL2 respectively through contact holes.

[0185] A connection pattern CP can be defined as multiple patterns or a single pattern. For example, a connection pattern CP may include a first connection pattern CP1 connected to a power connection pattern VCP, and a second connection pattern CP2 connected to a first power connection line VCL1, a second power connection line VCL2, and the first connection pattern CP1. The first connection pattern CP1 and the second connection pattern CP2 may be located in different layers.

[0186] In an embodiment, the connection pattern CP may extend in a direction away from the pixel PX adjacent to the connection pattern CP in the second direction DR2. The connection pattern CP may have a shape extending in a direction away from the first pixel PX1 (e.g., the first pixel PX1 located at the outermost edge of the corner portion DAc). For example, the connection pattern CP may at least partially overlap with each of the first power connection line VCL1, the second power connection line VCL2, the third power connection line VCL3, the second data connection line DCL2, and the third data connection line DCL3 in a planar view.

[0187] The display device DD3 according to an embodiment may include a first power connection line VCL1, a second power connection line VCL2, and a third power connection line VCL3 that transmit power voltage to the pixel PX, and a connection pattern CP that electrically connects the first power connection line VCL1 and the second power connection line VCL2. Since the connection pattern CP extends in a direction away from the pixel PX located at the outermost edge of the corner portion DAc, and the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3 are spaced apart from the pixel PX located at the outermost edge of the corner portion DAc, the introduction of pulse potentials caused by electrostatic discharge generated in the first power connection line VCL1, the second power connection line VCL2, and the third power connection line VCL3 into the pixel PX can be reduced. Accordingly, pixel driving circuit failures can be reduced, and the display quality of the display device DD3 can be improved.

[0188] The display devices DD1, DD2, and DD3 according to the embodiments can be applied to various electronic devices. The electronic devices according to the embodiments may include the display devices described above, and may further include modules or devices with additional functions in addition to the display devices.

[0189] Figure 11 This is a block diagram illustrating an electronic device according to an embodiment.

[0190] refer to Figure 11 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0191] Processor 12 may include at least one of a central processing unit (“CPU”), an application processor (“AP”), a graphics processing unit (“GPU”), a communication processor (“CP”), an image signal processor (“ISP”), and a controller. Processor 12 can transmit control signals (e.g., Figure 1 The control signal CTRL) and input image data (e.g., Figure 1 The input image data (IDAT) is provided to the controller of the display module 11 (e.g., Figure 1 The controller CON).

[0192] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, control signals and / or input image data can be transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0193] The power module 14 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 10.

[0194] At least one of the components of the electronic device 10 described above may be included in the display device according to the embodiment. Furthermore, some of the individual modules functionally included in a single module may be included in the display device, and other components may be provided independently of the display device. For example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided in the electronic device 10 as other devices besides the display device.

[0195] Figure 12 This is a schematic diagram illustrating an electronic device according to various embodiments.

[0196] refer to Figure 12 Various electronic devices that apply the display device according to the embodiments may include not only image display electronic devices (such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions 10_1d, and desktop monitors 10_1e), but also wearable electronic devices (such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c) or in-vehicle electronic devices 10_3 (such as a car dashboard, a central information display (“CID”) located on the car’s center console and / or instrument panel, and a rearview mirror display), etc.

[0197] Although the present display device has been described with reference to embodiments shown in the accompanying drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and other equivalent embodiments are thus possible. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein.

[0198] Furthermore, the features of the various embodiments of this disclosure can be combined in part or in whole. As will be clearly understood by those skilled in the art, various technical interactions and operations are possible. Moreover, the various embodiments can be implemented individually or in combination.

Claims

1. A display device, comprising: A display panel includes a display area and a non-display area adjacent to the display area, the display area including a corner portion; Multiple pixels are disposed in the display area, the multiple pixels are arranged in a grid defined by rows in a first direction and columns in a second direction intersecting the first direction, a first group of pixels is disposed in the corner portion and is arranged in a stepped manner to define the shape of the corner portion; A power connection line is disposed in the non-display area, the power connection line extends from the non-display area to the corner portion in the second direction, and is spaced apart from each other in the first direction, the power connection line transmits power voltage to the plurality of pixels; as well as A connection pattern is used to electrically connect the power connection lines, and the connection pattern extends in a direction away from the pixels adjacent to the connection pattern in the second direction among the plurality of pixels.

2. The display device according to claim 1, wherein, The power connection line includes: The first power connection line transmits the first power voltage; A second power connection line transmits the first power voltage; and The third power connection line transmits the first initialization voltage, and The connection pattern is connected to the first power connection line and the second power connection line, and the connection pattern at least partially overlaps with each of the first power connection line, the second power connection line and the third power connection line.

3. The display device according to claim 1, further comprising: The power connection pattern is adjacent to the power connection line in the second direction. The connection pattern electrically connects the power connection line to the power connection pattern.

4. The display device according to claim 3, wherein, The connection pattern includes a first connection pattern and a second connection pattern disposed in different layers.

5. The display device according to claim 4, wherein, The first connection pattern is connected to the power connection pattern, and The second connection pattern is connected to the power connection line and the first connection pattern.

6. The display device according to claim 4, wherein, Each of the plurality of pixels includes: Active patterns; The first gate electrode is disposed on the active pattern. The capacitor electrode is disposed on the first gate electrode; A second gate electrode is disposed on the capacitor electrode; and The source electrode is disposed on the second gate electrode. Wherein, the first connection pattern and the first gate electrode are disposed in the same layer, and The second connection pattern and the source electrode are disposed in the same layer.

7. The display device according to claim 1, wherein, Each of the plurality of pixels includes: Active patterns; The first gate electrode is disposed on the active pattern; The capacitor electrode is disposed on the first gate electrode; A second gate electrode is disposed on the capacitor electrode; and The source electrode is disposed on the second gate electrode, and The connection pattern and the second gate electrode are disposed in the same layer.

8. The display device according to claim 1, wherein, The connecting pattern has a U-shaped bend in the direction opposite to the second direction.

9. The display device according to claim 1, wherein, In the corner portion, the first group of pixels includes: The first pixel is set in the first row; The second pixel is set in the second row; and The third pixel is set in the third row, and The power connection line extends to the third row and is spaced apart from the second row.

10. The display device according to claim 9, further comprising: A gate connection line extends from the display area to the non-display area in the first direction, and the gate connection line transmits gate signals to the plurality of pixels. The gate connection line includes: The first gate connection line is electrically connected to the first pixel; The second gate connection line is electrically connected to the second pixel; and The third gate connection line is electrically connected to the third pixel, and Specifically, compared to the third gate connection line that extends to the non-display area, the second gate connection line further extends to the non-display area.

11. The display device according to claim 10, wherein, The ends of the first gate connection line and the ends of the second gate connection line are disposed in the second direction.

12. A display device, comprising: A display panel includes a display area and a non-display area adjacent to the display area, the display area including a corner portion; A plurality of pixels are disposed in the display area, the plurality of pixels being arranged in a grid defined by rows in a first direction and columns in a second direction intersecting the first direction. A first group of pixels among the plurality of pixels is disposed in the corner portion and is arranged in a stepped manner to define the shape of the corner portion, wherein, in the corner portion, the first group of pixels includes: The first pixel is set in the first row; The second pixel, set in the second row; and The third pixel is set in the third row; and Multiple power connection lines are arranged in the non-display area in the first direction, and the power connection lines extend from the non-display area to the third row of the corner portion in the second direction, and the power connection lines transmit power voltage to the multiple pixels.

13. The display device according to claim 12, wherein, The power connection lines are spaced apart from the second row.

14. The display device according to claim 12, further comprising: A gate connection line extends from the display area to the non-display area in the first direction, and the gate connection line transmits gate signals to the plurality of pixels.

15. The display device according to claim 14, wherein, The gate connection line includes: The first gate connection line is electrically connected to the first pixel; The second gate connection line is electrically connected to the second pixel; and The third gate connection line is electrically connected to the third pixel, and The second gate connection line extends further into the non-display area than the third gate connection line.

16. The display device according to claim 15, wherein, The ends of the first gate connection line and the ends of the second gate connection line are disposed in the second direction.

17. The display device according to claim 12, further comprising: Connect the power connection lines using the connection pattern.

18. The display device according to claim 17, wherein, The connection pattern extends in a direction away from the pixels adjacent to the connection pattern in the second direction among the plurality of pixels.

19. The display device according to claim 17, wherein, The power connection line includes: The first power connection line transmits the first power voltage; A second power connection line transmits the first power voltage; and The third power connection line transmits the first initialization voltage, and The connection pattern is connected to the first power connection line and the second power connection line, and the connection pattern at least partially overlaps with each of the first power connection line, the second power connection line and the third power connection line.

20. An electronic device comprising: The display device according to any one of claims 1 to 19; as well as The processor provides control signals and input image data to the display device.

Images