Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device includes: a fan-out line portion including a flat portion and a diagonal line portion; a first driving voltage supply line overlapping the diagonal line portion and extending in a first direction; a second driving voltage supply line extending in a second direction and connected to the first driving voltage supply line; a common voltage supply line spaced apart from the second driving voltage supply line; a cover conductive layer covering at least a portion of an area between the second driving voltage supply line and the common voltage supply line in an area overlapping the diagonal line portion and electrically connected to the common voltage supply line; and a light blocking layer disposed on the cover conductive layer and overlapping a portion of the cover conductive layer, wherein the cover conductive layer includes a contact portion connected to the common voltage supply line in an area overlapping the light blocking layer.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0055744 filed with the Korean Intellectual Property Office on April 28, 2025 and Korean Patent Application No. 10-2025-0083859 filed with the Korean Intellectual Property Office on June 24, 2025, the inventive concept of which is incorporated herein by reference in its entirety. Technical Field

[0002] This application relates to apparatuses, and more specifically, to display apparatuses and electronic devices including display apparatuses. Background Technology

[0003] The display device can visually display data. The display device may include a substrate divided into a display area and a peripheral area outside the display area. The display area may include scan lines and data lines formed to be insulated from each other, and a plurality of pixels arranged to be connected to the scan lines and data lines. Furthermore, the display area may include transistors corresponding to each pixel and pixel electrodes electrically connected to the transistors. Additionally, the display area may include counter electrodes commonly provided to the pixels. The peripheral area may include various lines configured to transmit electrical signals to the display area.

[0004] Recently, display devices have been used for various purposes. Accordingly, methods for reducing or effectively utilizing the peripheral area of ​​display devices have been actively researched. Summary of the Invention

[0005] Some example embodiments relate to display devices and electronic devices that include display devices.

[0006] Some example embodiments include display devices with excellent display quality. However, these problems are merely examples, and the scope of this disclosure is not limited thereto.

[0007] Some exemplary embodiments will be set forth in part in the description which follows and will be apparent in part from the description, or may be learned by practicing some exemplary embodiments of the inventive concept.

[0008] According to some example embodiments, the display device includes: a substrate, including a display area comprising a plurality of pixels and a peripheral area outside the display area and including a pad area; a fan-out line portion extending from the pad area to the display area in a plan view and including a straight portion and a sloping portion; a first driving voltage supply line overlapping the sloping portion of the fan-out line portion and extending in a first direction in a plan view; a second driving voltage supply line extending on the first driving voltage supply line and in a second direction intersecting the first direction in a plan view and electrically connected to the first driving voltage supply line; and a common power supply line. A voltage supply line, on the first driving voltage supply line and spaced apart from the second driving voltage supply line in the plan view; a conductive cover layer, in the area overlapping with the diagonal portion of the fan-out line portion, on the second driving voltage supply line and the common voltage supply line, covering the area between the second driving voltage supply line and the common voltage supply line in the plan view and electrically connected to the common voltage supply line; and a light blocking layer, in the peripheral area, on the conductive cover layer and overlapping a portion of the conductive cover layer, wherein, in the area overlapping with the light blocking layer, the conductive cover layer includes a contact portion electrically connected to the common voltage supply line.

[0009] In some example embodiments, the common voltage supply line may include a plurality of first vias passing through the common voltage supply line, and the covering conductive layer may include a plurality of second vias passing through the covering conductive layer and overlapping the plurality of first vias respectively.

[0010] In some example embodiments, the display device may further include a via insulating layer between a common voltage supply line and a cover conductive layer, wherein the via insulating layer may include an opening in a plan view surrounding each of a plurality of second vias, and a contact portion of the cover conductive layer may be in the opening of the via insulating layer.

[0011] In some example embodiments, the opening of the through-hole insulating layer may overlap with the light-blocking layer.

[0012] In some example embodiments, the display device may further include a via insulating layer between a common voltage supply line and a cover conductive layer, wherein the via insulating layer may include a group of openings comprising a plurality of openings between adjacent second vias in a plan view, and the contact portion of the cover conductive layer may be in the group of openings of the via insulating layer.

[0013] In some example embodiments, the openings of the through-hole insulating layer may overlap with the light-blocking layer.

[0014] In some example embodiments, the conductive layer may extend in a first direction.

[0015] In some example embodiments, the conductive overlay may overlap with the diagonal portion of the fan-out line.

[0016] In some example embodiments, the conductive covering layer may include a main portion that overlaps with the light blocking layer and a branch portion that extends from the main portion in a second direction and covers at least a portion of the aforementioned region between the second drive voltage supply line and the common voltage supply line.

[0017] In some example embodiments, the display device may further include a first initialization voltage supply line on the first driving voltage supply line and in the plan view between the common voltage supply line and the second driving voltage supply line, wherein the branch portion covering the conductive layer may include a first sub-branch portion covering the area between the common voltage supply line and the first initialization voltage supply line.

[0018] In some example embodiments, the display device may further include a second initialization voltage supply line on the first driving voltage supply line and between the first initialization voltage supply line and the second driving voltage supply line in a plan view, wherein the branch portion covering the conductive layer may further include a second sub-branch portion spaced apart from the first sub-branch portion in a first direction and covering the area between the first initialization voltage supply line and the second initialization voltage supply line.

[0019] In some example embodiments, the conductive overlay may be spaced apart from the display area.

[0020] In some example embodiments, the display device may further include a drive voltage bus extending in a first direction between the first drive voltage supply line and the display area in a plan view.

[0021] In some example embodiments, the conductive overlay may not overlap with the drive voltage bus.

[0022] In some example embodiments, the width of the area in the second direction where the contact portion covering the conductive layer and the light-blocking layer overlap each other can be from 30 μm to 100 μm.

[0023] In some example embodiments, each of the plurality of pixels may include a light-emitting diode, which may include a pixel electrode on the pixel circuit layer, an emitting layer on the pixel electrode, and a counter electrode on the emitting layer, and the covering conductive layer and the pixel electrode may be on the same layer.

[0024] In some example embodiments, the counter electrode can extend from the display area to the peripheral area to overlap with at least a portion of the conductive layer covering it.

[0025] In some example embodiments, the counter electrode may overlap with a portion of the conductive layer and may not overlap with the light-blocking layer.

[0026] According to some example embodiments, an electronic device includes: a display device configured to display an image; a memory configured to store an application program; and a processor configured to execute the application program and transmit image data signals and / or input control signals to the display device, wherein the display device includes: a substrate including a display area and a peripheral area outside the display area and including a pad area; a fan-out line portion extending from the pad area to the display area in a plan view and including a straight portion and a diagonal portion; a first driving voltage supply line overlapping the diagonal portion of the fan-out line portion and extending in a first direction in a plan view; and a second driving voltage supply line extending on the first driving voltage supply line in a plan view. The figure shows a first driving voltage supply line extending in a second direction intersecting the first direction and electrically connected to it; a common voltage supply line on the first driving voltage supply line and spaced apart from the second driving voltage supply line in the plan view; a covering conductive layer in the area overlapping the diagonal portion of the fan-out line portion on the second driving voltage supply line and the common voltage supply line, covering the area between the second driving voltage supply line and the common voltage supply line in the plan view and electrically connected to the common voltage supply line; and a light blocking layer in the peripheral area, on the covering conductive layer and overlapping a portion of the covering conductive layer, wherein, in the area overlapping with the light blocking layer, the covering conductive layer includes a contact portion electrically connected to the common voltage supply line.

[0027] In some example embodiments, the common voltage supply line may include a plurality of first vias passing through the common voltage supply line, and the covering conductive layer may include a plurality of second vias passing through the covering conductive layer and overlapping the plurality of first vias respectively. Attached Figure Description

[0028] The above and other features and advantages of some exemplary embodiments of the inventive concept will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 This is a perspective view schematically illustrating a display device according to some example embodiments;

[0030] Figure 2 This is an illustrative representation based on some example embodiments. Figure 1 A cross-sectional view of the display device along line I-I';

[0031] Figure 3 This is a schematic plan view of a display panel according to some example embodiments;

[0032] Figure 4 This is a schematic diagram illustrating the equivalent circuit diagram of pixels of a display panel according to some example embodiments;

[0033] Figure 5This is a schematic cross-sectional view illustrating a portion of the display area of ​​a display panel according to some example embodiments;

[0034] Figure 6 It is a schematic enlarged plan view of a portion of a display panel according to some example embodiments and is Figure 3 An enlarged plan view of region "A";

[0035] Figure 7 It is a schematic enlarged plan view of a portion of a display panel according to some example embodiments and is Figure 6 An enlarged plan view of region "B";

[0036] Figures 8 to 10 They are shown separately. Figure 7 The diagram shows a plan view of each layer of the display panel.

[0037] Figure 11 This is an illustrative representation based on some example embodiments. Figure 7 A cross-sectional view of the display panel along line II-II';

[0038] Figure 12 It is a schematic enlarged plan view of a portion of a display panel according to some example embodiments and is Figure 7 An enlarged plan view of region "C";

[0039] Figure 13 This is an illustrative representation based on some example embodiments. Figure 12 A cross-sectional view of the display panel along line III-III';

[0040] Figure 14 It is a schematic enlarged plan view of a portion of a display panel according to some example embodiments and is Figure 7 An enlarged plan view of region "C";

[0041] Figure 15 This is an illustrative representation based on some example embodiments. Figure 14 A cross-sectional view of the display panel along line IV-IV';

[0042] Figure 16 It is a schematic enlarged plan view of a portion of a display panel according to some example embodiments and is Figure 6 An enlarged plan view of region "B";

[0043] Figure 17 It is shown schematically. Figure 7 A plan view of a portion of the display panel shown in the image;

[0044] Figure 18This is an illustrative representation based on some example embodiments. Figure 16 A cross-sectional view of the display panel along line V-V';

[0045] Figure 19 It is a block diagram of an electronic device according to some example embodiments; and

[0046] Figure 20 An electronic device according to some example embodiments is illustrated schematically. Detailed Implementation

[0047] Reference will now be made in detail to some exemplary embodiments illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. At this point, some exemplary embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, only some exemplary embodiments are described below with reference to the accompanying drawings to explain some of the exemplary embodiments currently described. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0048] This disclosure may include some exemplary embodiments and modifications, and some exemplary embodiments of this disclosure are illustrated in the accompanying drawings and will be described in detail herein. Refer to the following and accompanying drawings. Figure 1 The effects and features of the inventive concept, as well as methods for implementing them, will become apparent from the exemplary embodiments described in detail below. However, the inventive concept is not limited to the exemplary embodiments described below and can be implemented in various forms.

[0049] In the following description, some exemplary embodiments will be described in detail with reference to the accompanying drawings, and in the following description, similar reference numerals will indicate the same elements and their redundant descriptions will be omitted for brevity.

[0050] It will be understood that when an element such as a layer, region, or plate is referred to as being "on" another element, the element may be "directly on" that other element or may be "indirectly on" that other element, wherein one or more intermediary elements are between that element and that other element. Furthermore, for ease of description, the dimensions of the components in the drawings may be exaggerated. In other words, the inventive concept is not limited thereto because the dimensions and shapes of the elements in the drawings are arbitrarily shown for ease of description.

[0051] Furthermore, in this paper, the x, y, and z directions are not limited to directions corresponding to the three axes of a Cartesian coordinate system, and can be interpreted in a broader sense. For example, the x, y, and z directions can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0052] It will be understood that although terms such as “first” and “second” may be used in this document to describe various elements, these elements should not be limited by these terms, and these terms are only used to distinguish one element from another.

[0053] It will be understood that terms such as “comprising,” “including,” and “having” as used herein indicate the presence of the stated feature or element, but do not exclude the presence or addition of one or more other features or elements.

[0054] As used herein, "A and / or B" means A, B, or A and B. Furthermore, "at least one of A and B" means A, B, or A and B.

[0055] It will be understood that when a layer, region, or component is referred to as being "connected to" another layer, region, or component, that layer, region, or component may be "directly connected to" that other layer, region, or component, or may be "indirectly connected to" that other layer, region, or component, wherein one or more intermediary layers, regions, or components are between that layer, region, or component and the other layer, region, or component. For example, it will be understood that when a layer, region, or component is referred to as being "electrically connected to" another layer, region, or component, that layer, region, or component may be "directly electrically connected to" that other layer, region, or component, or may be "indirectly electrically connected to" that other layer, region, or component, wherein one or more intermediary layers, regions, or components are between that layer, region, or component and the other layer, region, or component.

[0056] When a component is described as being "connected to" or "electrically connected to" another component, the component may be directly connected to that other component, or one or more other intermediary components may be present. For example, a component described as being "connected to" another component may be "electrically connected to" that other component. Conversely, when a component is described as being "directly connected to" another component, no intermediary component is present.

[0057] When the terms “approximately” and “substantially” are used in conjunction with numerical values ​​in this application, they are intended to indicate that the relevant numerical value includes a tolerance of ±10% around the stated value, unless otherwise expressly defined. Furthermore, it will be understood that whether a numerical value is modified with “approximately” or “substantially”, it should be interpreted as including a tolerance of ±10% around the stated value.

[0058] Figure 1This is a perspective view schematically illustrating a display device according to some example embodiments.

[0059] refer to Figure 1 The display device 1 can display images. The display device 1 may include a display area DA and / or a peripheral area PA.

[0060] Although the flat panel display device is shown as Figure 1 The display device 1 is a display device, but the display device 1 can be implemented in various forms such as flexible, foldable and / or rollable display devices.

[0061] Figure 1 A display device 1 is shown, comprising a display area DA having a quadrilateral shape; however, in some example embodiments, the display area DA may have a circular shape, an elliptical shape, or other polygonal shapes such as a triangle or a pentagon. The corners of the edges of the display area DA may be rounded.

[0062] In some example embodiments, such as Figure 1 As shown, the display device 1 may include a display area DA that is longer in a first direction (e.g., the x-direction) than in a second direction (e.g., the y-direction). In some example embodiments, the display device 1 may include a display area DA that is shorter in the first direction (e.g., the x-direction) than in the second direction (e.g., the y-direction).

[0063] Multiple pixels (PX) can be arranged in a display area (DA). The multiple pixels (PX) can emit light, and the display device 1 can display an image in the display area (DA). In some example embodiments, any one of the multiple pixels (PX) can emit red, green, or blue light. In some example embodiments, any one of the multiple pixels (PX) can emit red, green, blue, or white light.

[0064] The peripheral area PA can be an area arranged around the display area DA, and the peripheral area PA can surround at least a portion of the display area DA. In some example embodiments, the peripheral area PA can be a non-display area in which no pixels PX are arranged. Circuitry, various lines configured to transmit electrical signals to be applied to the display area DA, and / or printed circuit boards (e.g., flexible printed circuit boards) and / or pads to which the driver IC chip is attached can be located in the peripheral area PA.

[0065] For example, display device 1 may include liquid crystal display device, electrophoretic display device, organic light-emitting display device, inorganic EL display device (inorganic light-emitting display device), field emission display device, surface conduction electron emission display device, quantum dot display device, plasma display device and / or cathode ray tube display device.

[0066] Figure 2This is an illustrative representation based on some example embodiments. Figure 1 A cross-sectional view of the display device 1 along line I-I'.

[0067] refer to Figure 2 The display device 1 may include a display panel 10, a light-blocking layer BM and / or a cover window CW.

[0068] Display panel 10 may include a display area DA and a peripheral area PA outside the display area DA. Display panel 10 can provide an image by means of an array of multiple pixels arranged in the display area DA. Display panel 10 may be arranged below an overlay window CW.

[0069] The display panel 10 may include a substrate 100, a pixel layer PXL, and an encapsulation layer 300 that encapsulates the pixel layer PXL, which are sequentially stacked in a third direction (e.g., the z direction).

[0070] The substrate 100 may include a glass material and / or may include a polymer resin. For example, the substrate 100 may include a glass material containing SiO2 as a main component and / or may include various materials with flexible or bendable properties (e.g., resins such as reinforced plastics).

[0071] The pixel layer PXL can be disposed on the substrate 100. The pixel layer PXL may include a display device layer DPL containing display devices disposed in each pixel or one or more pixels, and a pixel circuit layer PCL containing pixel circuitry and / or an insulating layer disposed in each pixel. For example, as... Figure 5 As shown, the pixel circuit layer PCL may include a first thin-film transistor TFT1, a second thin-film transistor TFT2, a first capacitor Cst, and / or an insulating layer. For example, the display element layer DPL may include... Figure 5 The display device 1 uses an organic light-emitting diode (LED) as the display device. In the following description, the display device 1 will be described as including an organic light-emitting diode as the display device; however, the inventive concept is not limited thereto. In some exemplary embodiments, the display device may be an organic light-emitting diode comprising inorganic materials and / or a quantum dot light-emitting diode comprising quantum dots. The display device layer (DPL) may be disposed on the pixel circuit layer (PCL), and multiple insulating layers may be disposed between the pixel circuit and the display device. Some lines and insulating layers of the pixel circuit layer (PCL) may extend to the peripheral region (PA).

[0072] The encapsulation layer 300 can encapsulate the pixel layer PXL on top of the pixel layer PXL. The encapsulation layer 300 can be a thin-film encapsulation layer. The thin-film encapsulation layer can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. When the display panel 10 includes a substrate 100 containing a polymer resin and an encapsulation layer 300 containing a thin-film encapsulation layer containing both inorganic and organic encapsulation layers, the flexibility of the display device 1 can be improved.

[0073] The display panel 10 may further include an optical functional layer 400 above the encapsulation layer 300. The optical functional layer 400 may include an anti-reflective layer. The anti-reflective layer may be configured to reduce the reflectivity of light (external light) incident from the outside toward the display device 1. The anti-reflective layer may include a phase retarder and / or a polarizer. The phase retarder may be film-type or liquid crystal coating-type, and may include λ / 2 phase retarders and / or λ / 4 phase retarders. The polarizer may also be film-type or liquid crystal coating-type. Film-type polarizers may include a stretched synthetic resin film, and liquid crystal coating-type polarizers may include liquid crystals arranged in a specific array. The phase retarder and / or polarizer may further include a protective film. The protective film of the phase retarder and / or polarizer may be defined as the base layer of the anti-reflective layer.

[0074] In some example embodiments, the antireflective layer may include a black matrix and / or color filters. The color filters may be arranged to take into account the color of light emitted from each or one or more pixels of the display panel 10. Each or one of the color filters may include red, green, and / or blue pigments or dyes. In addition to the aforementioned pigments or dyes, each or one of the color filters may further include quantum dots. Some color filters may not include the aforementioned pigments or dyes and may include scattering particles such as titanium dioxide.

[0075] A cover window (CW) may be disposed on the display panel 10. The cover window CW allows light emitted from the display panel 10 to be transmitted to the outside. The cover window CW may comprise materials with excellent light transmittance, heat resistance, chemical resistance, and / or mechanical strength. In some example embodiments, the cover window CW may comprise glass and / or polymer resin. In some example embodiments, for example, the cover window CW may comprise polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and / or cellulose acetate propionate. In some example embodiments, the cover window CW may comprise ultrathin tempered glass (UTG) strengthened by methods such as chemical strengthening or thermal strengthening.

[0076] A light-blocking layer BM can be disposed on the display panel 10. For example, the light-blocking layer BM can be disposed between the display panel 10 and the cover window CW. For example, the light-blocking layer BM can be disposed on the rear surface of the cover window CW. The light-blocking layer BM can be disposed in the peripheral area PA. The light-blocking layer BM can be made black. For example, the light-blocking layer BM can include organic light-blocking materials and / or inorganic light-blocking materials containing black pigments or dyes.

[0077] Figure 3 This is a schematic plan view of a display panel according to some example embodiments.

[0078] refer to Figure 3 The substrate 100 of the display panel 10 may include a display area DA and a peripheral area PA. The peripheral area PA may be located outside the display area DA and may surround the display area DA.

[0079] The display area DA of the display panel 10 may include a plurality of pixels PX arranged in a specific pattern in a first direction (e.g., the x-direction) and a second direction (e.g., the y-direction). Each pixel PX, or one or more pixel PXs, may include a light-emitting diode, such as an organic light-emitting diode, and / or pixel circuitry electrically connected to the light-emitting diode. For example, each pixel PX, or one or more pixel PXs, may emit red light, green light, blue light, and / or white light.

[0080] The pixel circuitry driving the pixel PX can be connected to signal lines and / or voltage lines configured to control the on / off state and brightness of the light-emitting diode. For example, Figure 3 Data lines DL and SL are shown as signal lines, and drive voltage line PL is shown as a voltage line. Pixel PX may be electrically connected to data lines DL and SL. Scan line SL may extend in a first direction (e.g., the x-direction). Data line DL may extend in a second direction (e.g., the y-direction). Pixel PX may be connected to drive voltage line PL. In a plan view, scan line SL, data line DL, and / or drive voltage line PL may overlap with display area DA.

[0081] The peripheral area PA may include pad areas PADA. Pad areas PADA may be arranged outside the display area DA. In some example embodiments, pad areas PADA may be provided as multiple pad areas PADA. For example, the peripheral area PA may include multiple pad areas PADA. In some example embodiments, multiple pad areas PADA may be arranged parallel to each other in a first direction (e.g., the x-direction). Although Figure 3 The diagram shows two pad areas (PADA), but the invention is not limited thereto. For example, the peripheral area (PA) may include one pad area (PADA), or it may include three or more pad areas (PADA). Although Figure 3The diagram shows the pad area PADA arranged outside the display area DA in the -y direction, but the inventive concept is not limited thereto. In some example embodiments, the pad area PADA may be arranged outside the display area DA in the y direction, the -x direction, and / or the x direction.

[0082] Multiple pads can be arranged in the pad area PADA. The pads of the pad area PADA can be exposed without being covered by an insulating layer to electrically connect to a flexible printed circuit board and / or a controller such as a driver IC chip. For example, the controller can convert multiple image signals received from the outside into multiple image data signals, and can transmit the converted signals to the display area DA through the data pads in the pad area PADA. For example, the controller can transmit different voltages to the drive voltage supply line 20 and the common voltage supply line 30 respectively through the pads of the pad area PADA.

[0083] The peripheral area PA of the display panel 10 may include external circuitry for driving pixels PX. For example, the display panel 10 may include a driving voltage supply line 20, a common voltage supply line 30, and / or a fan-out portion FWP disposed in the peripheral area PA.

[0084] The drive voltage supply line 20 can be arranged between the pad area PADA and the display area DA. The drive voltage supply line 20 can be arranged in the peripheral area PA, below the display area DA. For example, the drive voltage supply line 20 can be arranged outside the display area DA in the -y direction. The drive voltage supply line 20 can be electrically connected to the drive voltage line PL arranged in the display area DA. The drive voltage supply line 20 can be electrically connected to the first power pad in the pads of the pad area PADA. The drive voltage supply line 20 can be configured to deliver the drive voltage ELVDD (see...). Figure 4 This is provided to each pixel PX or one or more pixel PXs. For example, the drive voltage ELVDD (see...) Figure 4 The drive voltage line PL, which is electrically connected to the drive voltage supply line 20, can be supplied to each pixel PX or one or more pixels PX.

[0085] The common voltage supply line 30 may include a main common voltage supply line 30a arranged to partially surround the display area DA within the peripheral area PA. A portion of the main common voltage supply line 30a may be arranged between the pad area PADA and the display area DA. In some example embodiments, the main common voltage supply line 30a may extend along a side of the display area DA other than the side adjacent to the drive voltage supply line 20.

[0086] The common voltage supply line 30 may include a secondary common voltage supply line 30b arranged in the peripheral area PA corresponding to one side of the display area DA. For example, the secondary common voltage supply line 30b may be arranged in the peripheral area PA, below the display area DA. The secondary common voltage supply line 30b may be arranged between the pad area PADA and the display area DA. For example, the secondary common voltage supply line 30b may be arranged between the drive voltage supply line 20 and the pad area PADA.

[0087] Common voltage supply line 30 can be electrically connected to the second power pad in the pad area PADA. Common voltage supply line 30 can be configured to supply the common voltage ELVSS (see...). Figure 4 The common voltage supply line 30 is provided to each pixel PX or one or more pixel PXs. The common voltage supply line 30 can be electrically connected to the counter electrode 230 of the light-emitting diode included in each pixel PX or one or more pixel PXs (see...). Figure 5 ) to convert the common voltage ELVSS (see Figure 4 () Provided to each pixel PX or one or more pixels PX.

[0088] The fan-out section (FWP) can be positioned between the display area (DA) and the pad area (PADA). The fan-out section (FWP) can extend from the pad area (PADA) to the display area (DA). For example, the fan-out section (FWP) can include multiple fan-out lines, and these multiple fan-out lines can extend from the pad area (PADA) to the display area (DA).

[0089] In some example embodiments, the fan-out section (FWP) can be provided as multiple fan-out section FWPs. For example, multiple fan-out section FWPs can be arranged to correspond to multiple pad areas (PADA) respectively.

[0090] In some example embodiments, the fan-out section (FWP) can be electrically connected to the data line (DL). The fan-out section (FWP) can also be electrically connected to the data pads within the pads of the pad area (PADA). The fan-out section (FWP) can be configured to transmit data signals (e.g., image data signals) received from the controller via the pad area (PADA) to the display area (DA).

[0091] The fan-out section FWP may include a straight section FW1 extending in a second direction (e.g., the y-direction) and a diagonal section FW2 extending from the straight section FW1 in a diagonal direction. For example, the diagonal section FW2 of the fan-out section FWP may extend in a diagonal direction between a first direction (e.g., the x-direction) and a second direction (e.g., the y-direction). In some example embodiments, the fan-out section FWP may include a plurality of straight sections FW1 and a plurality of diagonal sections FW2, and the straight sections FW1 and diagonal sections FW2 may be arranged alternately in the second direction (e.g., the y-direction).

[0092] In some example embodiments, the fan-out portion FWP may overlap with at least a portion of the drive voltage supply line 20. In some example embodiments, the diagonal portion FW2 of the fan-out portion FWP may overlap with at least a portion of the drive voltage supply line 20.

[0093] Figure 4 This is a schematic diagram illustrating the equivalent circuit diagram of the pixels of a display panel according to some example embodiments.

[0094] refer to Figure 4 The pixel circuit PC can be connected to gate lines such as scan line GWL, first initialization control line GIL, second initialization control line GBL, compensation scan line GCL, and / or transmit control line EML to receive scan signal GW, first initialization control signal GI, second initialization control signal GB, compensation scan signal GC, and / or transmit control signal EM. For example, Figure 4 The scan line GWL, the first initialization control line GIL, the second initialization control line GBL, the compensation scan line GCL, and / or the emission control line EML can be gate lines connected to the pixel circuit PC located in the i-th row (i is a natural number greater than zero).

[0095] The pixel circuit PC can receive the data signal Dm via the data line DL. For example, Figure 4 The data line DL can be a signal line connected to the pixel circuit PC located in the j-th column (j is a natural number greater than zero).

[0096] According to some example embodiments, the pixel circuit PC of the display device can be electrically connected to a light-emitting diode (LED) that emits light of a specific color, and the LED can include a first electrode (or pixel electrode or anode), a second electrode (or counter electrode or cathode), and an intermediate layer therebetween.

[0097] The pixel circuit PC may include multiple transistors T1, T2, T3, T4, T5, T6, T7 and / or T8, and capacitors Cst and / or Ca. The multiple transistors T1, T2, T3, T4, T5, T6, T7 and / or T8 may include a drive transistor T1, a data write transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, an emitter control transistor T6, a second initialization transistor T7, and / or a bias transistor T8. The capacitor Cst and / or Ca may include a first capacitor Cst and a second capacitor Ca.

[0098] In some example embodiments, some of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be p-channel MOSFETs (PMOS), and the others may be n-channel MOSFETs (NMOS). For example, among the transistors T1, T2, T3, T4, T5, T6, T7, and T8, the drive transistor T1, the data write transistor T2, the operation control transistor T5, the emit control transistor T6, the second initialization transistor T7, and / or the bias transistor T8 may be PMOS, and the compensation transistor T3 and / or the first initialization transistor T4 may be NMOS. In some example embodiments, among the transistors T1, T2, T3, T4, T5, T6, T7, and T8, the compensation transistor T3 and the first initialization transistor T4 may be PMOS, and the others may be NMOS. Alternatively, all or one or more of the transistors T1, T2, T3, T4, T5, T6, T7, and T8 may be NMOS or may be PMOS. The following description will primarily focus on the case where the compensation transistor T3 and the first initialization transistor T4 are NMOS, which includes oxide semiconductors, and the other transistors are PMOS.

[0099] In some example embodiments, at least one of the plurality of transistors T1, T2, T3, T4, T5, T6, T7 and T8 may be a transistor including a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and at least one of the plurality of transistors T1, T2, T3, T4, T5, T6, T7 and T8 may be a transistor including an oxide semiconductor layer.

[0100] The driving transistor T1, which directly affects the brightness of the display device, can be configured to include a semiconductor layer comprising polycrystalline silicon with high reliability, and accordingly, a high-resolution display device can be realized. Because oxide semiconductors can have high carrier mobility and low leakage current, their voltage drop can be small even when the driving time is long. For example, low-frequency driving is possible because the color change of the image due to voltage drop can be small even in low-frequency driving. Because oxide semiconductors have low leakage current, at least one of the first initialization transistor T4 and the compensation transistor T3 connected to the gate electrode of the driving transistor T1 can include oxide semiconductors to reduce power consumption while reducing or preventing leakage current that may flow to the gate electrode of the driving transistor T1. For example, the driving transistor T1, the data writing transistor T2, the operation control transistor T5, the emitter control transistor T6, the second initialization transistor T7, and / or the bias transistor T8 can be transistors comprising a low-temperature polycrystalline silicon semiconductor layer, and the compensation transistor T3 and / or the first initialization transistor T4 can be transistors comprising an oxide semiconductor layer.

[0101] A driving transistor T1 can be connected between a light-emitting diode (LED) and a driving voltage line PL (or a vertical driving voltage line) configured to provide a driving voltage ELVDD. The gate electrode of driving transistor T1 can be connected to one end of a first capacitor Cst, which is a storage capacitor. The gate electrode of driving transistor T1 can be connected to a first node N1. The source electrode of driving transistor T1 can be connected to the driving voltage line PL via an operation control transistor T5. The drain electrode of driving transistor T1 can be electrically connected to the first electrode (or pixel electrode or anode) of the LED via an emitter control transistor T6. Based on the switching operation of the data write transistor T2, driving transistor T1 can receive the data signal Dm transmitted via the data line DL and can supply driving current to the LED.

[0102] The gate electrode of the data writing transistor T2 can be connected to the scan line GWL. The first electrode of the data writing transistor T2 can be connected to the data line DL, and the second electrode of the data writing transistor T2 can be connected to the source electrode of the driving transistor T1. Based on the scan signal GW received through the scan line GWL, the data writing transistor T2 can be turned on to transmit the data signal Dm received through the data line DL to the source electrode of the driving transistor T1. Simultaneously, the data signal Dm can be transmitted to the gate electrode of the driving transistor T1 by the turned-on compensation transistor T3.

[0103] The gate electrode of the compensation transistor T3 can be connected to the compensation scan line GCL. The first electrode of the compensation transistor T3 can be connected to the drain electrode of the driving transistor T1, and the second electrode of the compensation transistor T3 can be connected to the first node N1. According to the compensation scan signal GC received through the compensation scan line GCL, the compensation transistor T3 can be turned on to connect the gate electrode and drain electrode of the driving transistor T1 to each other, thereby connecting the driving transistor T1 diode and compensating the threshold voltage (Vth) of the driving transistor T1.

[0104] The gate electrode of the first initialization transistor T4 can be connected to the first initialization control line GIL. The first electrode of the first initialization transistor T4 can be connected to the first initialization voltage line VIL, and the second electrode of the first initialization transistor T4 can be connected to the first node N1. According to the first initialization control signal GI applied from the first initialization control line GIL, the first initialization transistor T4 can be turned on to transmit the first initialization voltage Vint to the gate electrode of the driving transistor T1, thereby initializing the potential of the gate electrode of the driving transistor T1 (e.g., the potential of the first node N1) to a specific voltage. The first initialization voltage Vint can have a voltage level higher than the voltage level of the common voltage ELVSS, or it can have a voltage level equal to the voltage level of the common voltage ELVSS.

[0105] The gate electrode of the control transistor T5 can be connected to the emitter control line EML. The first electrode of the control transistor T5 can be connected to the drive voltage line PL, and the second electrode of the control transistor T5 can be connected to the source electrode of the drive transistor T1.

[0106] The gate electrode of the emitter control transistor T6 can be connected to the emitter control line EML. The first electrode of the emitter control transistor T6 can be connected to the drain electrode of the driver transistor T1, and the second electrode of the emitter control transistor T6 can be electrically connected to the first electrode (or pixel electrode or anode) of the light-emitting diode (LED). The operation control transistor T5 and the emitter control transistor T6 can be simultaneously turned on according to the emitter control signal EM applied from the emitter control line EML. The drive voltage ELVDD applied by the turned-on operation control transistor T5 can be compensated by the driver transistor T1 and then transmitted to the LED.

[0107] The gate electrode of the second initialization transistor T7 can be connected to the second initialization control line GBL. The first electrode of the second initialization transistor T7 can be connected to the first electrode (or pixel electrode or anode) of the light-emitting diode (LED), and the second electrode of the second initialization transistor T7 can be connected to the second initialization voltage line VAL. The second initialization transistor T7 can be turned on to initialize the first electrode (or pixel electrode or anode) of the LED by applying the second initialization control signal GB from the second initialization control line GBL. The second initialization control signal GB can be the same as or different from the first initialization control signal GI.

[0108] As a comparative example of the inventive concept, a black image may not be properly displayed even when the LED emits light, even when the minimum current for displaying a black image flows as the driving current to the driving transistor T1. However, according to the inventive concept, the second initialization transistor T7 can be configured to distribute a portion of the minimum current of the driving transistor T1 as a bypass current to a current path other than the current path toward the LED. Here, the minimum current of the driving transistor T1 can refer to the current under the condition that the gate-source voltage (Vgs) of the driving transistor T1 is lower than the threshold voltage (Vth) of the driving transistor T1 and therefore the driving transistor T1 is turned off. Therefore, the minimum driving current under the condition that the driving transistor T1 is turned off (e.g., a current below 10 picoamps (pA)) can be transmitted to the LED, and thus a black brightness image can be presented. When the minimum driving current for displaying a black image flows, the effect of the bypass current transmission may be significant, while when a large driving current flows for displaying an image such as a general image or a white image, the effect of the bypass current may be almost zero. Therefore, when the drive current for displaying a black image flows, an accurate black brightness image can be achieved by using the second initialization transistor T7 according to the drive current, thereby improving contrast. Thus, a display device with improved display quality can be provided.

[0109] The gate electrode of the bias transistor T8 can be connected to the second initialization control line GBL. The first electrode of the bias transistor T8 can be connected to the bias voltage line VOL through which the bias voltage Vobs is provided, and the second electrode of the bias transistor T8 can be connected to the source electrode of the drive transistor T1.

[0110] One end of the first capacitor Cst can be connected to the gate electrode of the driving transistor T1, and the other end of the first capacitor Cst can be connected to the driving voltage line PL. The first capacitor Cst can be connected between the driving voltage line PL and the first node N1. The charge corresponding to the voltage difference between the driving voltage ELVDD and the voltage of the first node N1 can be stored in the first capacitor Cst.

[0111] The second capacitor Ca can be an auxiliary capacitor and can be electrically connected to the emission control transistor T6, the second initialization transistor T7, and the first electrode (or pixel electrode or anode) of the light-emitting diode (LED). The second capacitor Ca can store and maintain a voltage corresponding to the voltage difference between the first electrode (or pixel electrode or anode) of the LED and the common voltage line VSL while the second initialization transistor T7 is turned on, thereby reducing or preventing the problem of increased black brightness when the emission control transistor T6 is turned off.

[0112] The first electrode (or pixel electrode or anode) of a light-emitting diode (LED) can receive drive current from a driving transistor T1 to emit light, thereby displaying an image. The driving voltage ELVDD can be a specific high-level voltage, and the common voltage ELVSS can be a voltage lower than the driving voltage ELVDD.

[0113] The common voltage line VSL can be electrically connected to the common voltage supply line 30 (see...). Figure 3 To provide the common voltage ELVSS to the pixel PX (see...) Figure 3 ).

[0114] The operation of the pixel circuit PC and the light-emitting diode LED will be described below.

[0115] During the initialization period, a high-level first initialization control signal GI is supplied to the first initialization transistor T4 via the first initialization control line GIL, and a low-level second initialization control signal GB is supplied to the second initialization transistor T7 via the second initialization control line GBL. As a result, each of the first initialization transistor T4 and the second initialization transistor T7 can be turned on. A first initialization voltage Vint applied from the first initialization voltage line VIL is transmitted to the gate electrode of the driving transistor T1 via the first initialization transistor T4, and a second initialization voltage Vaint applied from the second initialization voltage line VAL is transmitted to the first electrode (or pixel electrode or anode) of the light-emitting diode (LED) via the second initialization transistor T7. Accordingly, the voltage of the first electrode (or pixel electrode or anode) of the LED and the voltage of the gate electrode of the driving transistor T1 can be initialized.

[0116] Subsequently, during the data writing period, a low-level scan signal GW can be supplied through the scan line GWL, and a high-level compensation scan signal GC can be supplied through the compensation scan line GCL. Data writing transistor T2 and compensation transistor T3 can be turned on. Data writing transistor T2 can be configured to transmit the data signal Dm from the data line DL to the source electrode of driving transistor T1, and driving transistor T1 can be diode-connected through compensation transistor T3. Then, a compensation voltage, obtained by reducing the threshold voltage (Vth) of driving transistor T1 from the voltage corresponding to the data signal Dm, can be applied to the gate electrode of driving transistor T1.

[0117] The driving voltage ELVDD and the compensation voltage can be applied to the two ends of the first capacitor Cst, and the charge corresponding to the voltage difference between the two ends of the first capacitor Cst can be stored in the first capacitor Cst.

[0118] Subsequently, during the transmission period, the transmission control signal EM supplied from the transmission control line EML can change from a high level to a low level, and the operation control transistor T5 and the transmission control transistor T6 can be turned on. Then, the drive current can be generated based on the voltage difference between the drive voltage ELVDD and the voltage at the gate electrode of the drive transistor T1, and the drive current can be supplied to the light-emitting diode LED through the transmission control transistor T6 to emit light.

[0119] The characteristics of light-emitting diodes (LEDs) that emit different types of light and / or the characteristics of the individual driving transistors (T1) in the multiple pixel circuits (PC) can differ from each other. For example, in the case of high-frequency driving, the color coordinates of the display device may change (e.g., become reddish). However, according to the present invention, the voltage of the source electrode of the driving transistor T1 can be controlled by the bias voltage Vobs through the bias transistor T8. By controlling the driving current in this way, the brightness deviation (current deviation) and color coordinate variation of each pixel can be improved. Therefore, a display device with improved display quality can be provided.

[0120] Figure 5 This is a schematic cross-sectional view illustrating a portion of the display area of ​​a display panel according to some example embodiments.

[0121] refer to Figure 5 The display panel 10 may include a pixel circuit PC disposed in the display area DA and light-emitting diodes (LEDs) electrically connected to the pixel circuit PC. A pixel circuit layer PCL including the pixel circuit PC may be disposed on the substrate 100, and the light-emitting diodes (LEDs) may be disposed on the pixel circuit layer PCL.

[0122] The substrate 100 may include glass, metal, and / or polymer resin. In some example embodiments, the substrate 100 may be flexible or bendable. When the substrate 100 is flexible or bendable, for example, the substrate 100 may include polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and / or cellulose acetate propionate.

[0123] The substrate 100 may have a single-layer or multi-layer structure of the aforementioned materials, and in the case of a multi-layer structure, the substrate 100 may further include an inorganic layer. For example, the substrate 100 may include a first organic substrate layer, a first inorganic barrier layer, a second organic substrate layer, and a second inorganic barrier layer. Each or more of the first and second organic substrate layers may include a polymer resin. Each or more of the first and second inorganic barrier layers may be a barrier layer for reducing or preventing the penetration of external foreign matter, and may include a single or multiple layers comprising inorganic materials such as silicon nitride and / or silicon oxide.

[0124] The bottom metal layer (BML) can be disposed on the substrate 100. The bottom metal layer (BML) can include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In some example embodiments, the bottom metal layer (BML) can be a single molybdenum layer, can have a bilayer structure in which molybdenum and titanium layers are stacked, or can have a trilayer structure in which titanium, aluminum, and titanium layers are stacked.

[0125] The bottom metal layer (BML) can have a constant voltage level. For example, the bottom metal layer (BML) can be electrically connected to the drive voltage line (PL) and can have the same voltage level as the drive voltage line (PL) (e.g., Figure 4 The driving voltage ELVDD in the first thin film transistor TFT1 is used to reduce or prevent the accumulation of negative charges under the first semiconductor layer Act1 of the first thin film transistor TFT1, thereby reducing or preventing or minimizing the problem of image retention due to negative charges. When viewed in a direction perpendicular to the upper surface of the substrate 100, the bottom metal layer BML can completely overlap with the channel region of the first semiconductor layer Act1 of the first thin film transistor TFT1.

[0126] The buffer layer 101 may be disposed on the bottom metal layer BML. The buffer layer 101 may be an inorganic insulating layer comprising an inorganic insulating material such as silicon nitride, silicon oxide and / or silicon oxynitride, and may have a single-layer or multi-layer structure comprising the above materials.

[0127] The first thin-film transistor TFT1 may be disposed on the buffer layer 101. The first thin-film transistor TFT1 may include a first semiconductor layer Act1, a first gate electrode GE1 on the first semiconductor layer Act1, and a first source electrode SE1 and a first drain electrode DE1, each electrically connected to the first semiconductor layer Act1.

[0128] The first semiconductor layer Act1 may include a channel region and doped regions disposed on both sides of the channel region. The channel region of the first semiconductor layer Act1 may overlap with the first gate electrode GE1.

[0129] The first semiconductor layer Act1 may include a silicon semiconductor material. For example, the first semiconductor layer Act1 may include amorphous silicon and / or polycrystalline silicon. For example, the first semiconductor layer Act1 may include polycrystalline silicon that crystallizes at low temperatures.

[0130] The first gate insulating layer 102 may be disposed on the first semiconductor layer Act1. The first gate insulating layer 102 may include an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride and / or silicon oxynitride, and may have a single-layer or multi-layer structure comprising the above materials.

[0131] The first gate electrode GE1 can be disposed on the first gate insulating layer 102. The first gate electrode GE1 and the lower electrode CE1 can be provided integrally as a whole. For example, the first gate electrode GE1 can be used as the lower electrode CE1 of the first capacitor Cst.

[0132] The first gate electrode GE1 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers containing the above materials.

[0133] The second gate insulating layer 103 may be disposed on the first gate electrode GE1. The second gate insulating layer 103 may include an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride and / or silicon oxynitride, and may have a single-layer or multi-layer structure comprising the above-mentioned materials.

[0134] The upper electrode CE2 of the first capacitor Cst can be disposed on the second gate insulating layer 103. The upper electrode CE2 can overlap with the first gate electrode GE1 and / or the lower electrode CE1. The upper electrode CE2 of the first capacitor Cst can include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and can include a single layer or multiple layers comprising the above materials. In some example embodiments, the upper electrode CE2 can include the same material as the lower electrode CE1 and / or the bottom metal layer BML.

[0135] The first interlayer insulating layer 104 may be disposed on the upper electrode CE2. The first interlayer insulating layer 104 may include an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride and / or silicon oxynitride, and may have a single-layer or multi-layer structure comprising the above materials.

[0136] The second thin-film transistor TFT2 can be disposed on the first interlayer insulating layer 104. The second thin-film transistor TFT2 may include a second semiconductor layer Act2, a second gate electrode GE2 on the second semiconductor layer Act2, and a second source electrode SE2 and a second drain electrode DE2, each electrically connected to the second semiconductor layer Act2.

[0137] The second semiconductor layer Act2 and the first semiconductor layer Act1 can be disposed on different layers. For example, the first semiconductor layer Act1 can be disposed on the buffer layer 101, and the second semiconductor layer Act2 can be disposed on the first interlayer insulating layer 104. For example, the vertical distance from the substrate 100 to the second semiconductor layer Act2 can be greater than the vertical distance from the substrate 100 to the first semiconductor layer Act1.

[0138] The second semiconductor layer Act2 may include a channel region and doped regions disposed on both sides of the channel region. The channel region of the second semiconductor layer Act2 may overlap with the second gate electrode GE2.

[0139] The second semiconductor layer Act2 may comprise an oxide semiconductor material. For example, the second semiconductor layer Act2 may comprise an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the second semiconductor layer Act2 may comprise InSnZnO (ITZO) or InGaZnO (IGZO). Because oxide semiconductors have a wide bandgap (approximately 3.1 eV), high carrier mobility, and low leakage current, the voltage drop can be small even with long drive times, and therefore, even under low-frequency drive conditions, the brightness change due to the voltage drop can be small.

[0140] The second gate electrode GE2 may be disposed below and / or above the second semiconductor layer Act2. Figure 5 Examples are shown in which the second gate electrode GE2 includes a lower gate electrode G2a disposed below the second semiconductor layer Act2 and an upper gate electrode G2b disposed on the second semiconductor layer Act2. In some example embodiments, either the lower gate electrode G2a or the upper gate electrode G2b may be omitted.

[0141] The lower gate electrode G2a may comprise the same material as the upper electrode CE2 and may be located in the same layer as the upper electrode CE2 (e.g., on the second gate insulating layer 103). The upper gate electrode G2b may be disposed on the second semiconductor layer Act2. The third gate insulating layer 105 may be disposed between the upper gate electrode G2b and the second semiconductor layer Act2. The upper gate electrode G2b may comprise aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may comprise a single layer or multiple layers comprising the aforementioned materials.

[0142] although Figure 5 The diagram shows the third gate insulating layer 105 disposed only between the upper gate electrode G2b and the second semiconductor layer Act2, but the inventive concept is not limited thereto. In some exemplary embodiments, the third gate insulating layer 105 may be formed to completely cover the substrate 100, like other insulating layers (e.g., the first gate insulating layer 102). The third gate insulating layer 105 may comprise an inorganic insulating layer containing an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure comprising the aforementioned materials.

[0143] The first thin-film transistor TFT1 can be Figure 4 Examples of some transistors in the transistor, and the second thin-film transistor TFT2 can be Figure 4 Examples of other transistors. For example, the first thin-film transistor TFT1 could be... Figure 4 The second thin-film transistor TFT2 can be one of the following: driving transistor T1, data writing transistor T2, operation control transistor T5, emission control transistor T6, second initialization transistor T7, and bias transistor T8. Figure 4 One of the compensation transistor T3 and the first initialization transistor T4.

[0144] The second interlayer insulating layer 106 may be disposed on the upper gate electrode G2b. The second interlayer insulating layer 106 may include an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride and / or silicon oxynitride, and may have a single-layer or multi-layer structure comprising the above materials.

[0145] The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and / or the second drain electrode DE2 may be disposed on the second interlayer insulating layer 106. Each or more of the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers comprising the aforementioned materials. In some example embodiments, each or more of the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may have a three-layer structure of aluminum layer / titanium layer / aluminum layer.

[0146] The first via insulating layer 110 may be disposed on the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and / or the second drain electrode DE2. The first via insulating layer 110 may cover the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and / or the second drain electrode DE2, and may be disposed on the second interlayer insulating layer 106. The first via insulating layer 110 may be referred to as a first planarization layer providing a flat upper surface.

[0147] The first through-hole insulating layer 110 may include an organic insulating material. For example, the first through-hole insulating layer 110 may include photoresist, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and / or any mixture thereof.

[0148] The driving voltage line PL, the common voltage line VSL, and / or the data line DL can be arranged on the first through-hole insulating layer 110 in the display area DA. The driving voltage line PL, the common voltage line VSL, and / or the data line DL can include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and can include a single layer or multiple layers containing the above materials. In some example embodiments, the driving voltage line PL, the common voltage line VSL, and / or the data line DL can have a three-layer structure of aluminum layer / titanium layer / aluminum layer.

[0149] The second via insulating layer 120 may be disposed on the drive voltage line PL, the common voltage line VSL, and / or the data line DL. The second via insulating layer 120 may cover the drive voltage line PL, the common voltage line VSL, and / or the data line DL, and may be disposed on the first via insulating layer 110. The second via insulating layer 120 may be referred to as a second planarization layer providing a flat upper surface.

[0150] The second via insulating layer 120 may include an organic insulating material. For example, the second via insulating layer 120 may include photoresist, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, and / or any mixture thereof.

[0151] The light-emitting diode (LED) can be disposed on the second via insulating layer 120. The LED may include a pixel electrode 210, an intermediate layer 220 and a counter electrode 230 on the second via insulating layer 120.

[0152] Pixel electrode 210 may include a (semi-)transparent electrode or a reflective electrode. For example, pixel electrode 210 may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and / or any compounds thereof, and a transparent or semi-transparent electrode layer situated above the reflective layer. The transparent or semi-transparent electrode layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. x It can be at least one of ZnO or ZnO2, indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). For example, the pixel electrode 210 can have a three-layer structure of ITO / Ag / ITO.

[0153] The edge of the pixel electrode 210 can be covered by the dam layer 130, and the central portion of the pixel electrode 210 can overlap with the intermediate layer 220 through the pixel opening 130OP of the dam layer 130. For example, the dam layer 130 can cover the edge of the pixel electrode 210 and can define a pixel opening 130OP that exposes a portion of the pixel electrode 210. The pixel opening 130OP of the dam layer 130 can define the emission region EA of the light-emitting diode (LED).

[0154] Although the pixel electrode 210 can be formed for each light-emitting diode (LED), the counter electrode 230 can be formed to correspond to multiple LEDs. For example, multiple LEDs can share the counter electrode 230, and the stacked structure of the pixel electrode 210, the intermediate layer 220, and the counter electrode 230 can correspond to the LEDs.

[0155] An intermediate layer 220 may be disposed on the pixel electrode 210. The intermediate layer 220 may include an emission layer 222, a first functional layer 221 disposed beneath the emission layer 222, and / or a second functional layer 223 disposed on the emission layer 222. The emission layer 222 may have a patterned shape corresponding to the pixel electrode 210. The emission layer 222 may include a high-molecular-weight or low-molecular-weight organic material for emitting light of a specific color. The first functional layer 221 may be a hole transport layer. In some example embodiments, the first functional layer 221 may include a hole injection layer and / or a hole transport layer. The second functional layer 223 may include an electron transport layer and / or an electron injection layer. The first functional layer 221 and the second functional layer 223 may be integrally formed to correspond to a plurality of light-emitting diodes (LEDs). In some example embodiments, the first functional layer 221 and / or the second functional layer 223 may be omitted.

[0156] The counter electrode 230 can be disposed on the intermediate layer 220. The counter electrode 230 can be a transparent electrode, a translucent electrode, or a reflective electrode. For example, the counter electrode 230 can include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), lithium aluminum (Al-Li), calcium (Ca), magnesium indium (Mg-In), magnesium silver (Mg-Ag), ytterbium (Yb), silver ytterbium (Ag-Yb), indium tin oxide (ITO), indium zinc oxide (IZO), and / or any combination thereof. The counter electrode 230 can be integrally formed to correspond to multiple light-emitting diodes (LEDs).

[0157] The encapsulation layer 300 can be disposed on a light-emitting diode (LED). The encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. As some example embodiments, Figure 5 The encapsulation layer 300 is shown to include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330.

[0158] The first inorganic encapsulation layer 310 and / or the second inorganic encapsulation layer 330 may include materials such as silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y Aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO) xThe inorganic insulating material can be ZnO or ZnO2. The first inorganic encapsulation layer 310 and / or the second inorganic encapsulation layer 330 can have a single-layer or multi-layer structure including the aforementioned inorganic insulating material.

[0159] The organic encapsulation layer 320 can alleviate the internal stress of the first inorganic encapsulation layer 310 and / or the second inorganic encapsulation layer 330. The organic encapsulation layer 320 may include polymeric materials. Polymeric materials may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resins (e.g., polymethyl methacrylate or polyacrylic acid), and / or any combination thereof.

[0160] The organic encapsulation layer 320 can be formed by applying a material that is fluid and contains monomers, and then reacting the monomers to combine them into a polymer using heat and / or light such as ultraviolet light. In some example embodiments, the organic encapsulation layer 320 can be formed by applying a polymeric material.

[0161] Figure 6 It is a schematic enlarged plan view of a portion of a display panel according to some example embodiments and is Figure 3 An enlarged plan view of region "A".

[0162] For ease of illustration, Figure 6 The diagram schematically illustrates the straight portion FW1 and the angled portion FW2 of the fan-out line section FWP, respectively, corresponding to their respective arrangement areas. For example, as... Figure 6 As shown, the oblique portion FW2 of the fan-out line section FWP can be arranged between the straight portions FW1 of the fan-out line section FWP.

[0163] refer to Figure 6 The display panel 10 may include a drive voltage bus 25, a common voltage bus 35, a first initialization voltage bus 45, a second-first initialization voltage bus 55a and / or a second-second initialization voltage bus 55b arranged in the peripheral area PA.

[0164] Each or more of the drive voltage bus 25, common voltage bus 35, first initialization voltage bus 45, second-first initialization voltage bus 55a, and second-second initialization voltage bus 55b may be arranged between the display area DA and the first drive voltage supply line 21 described below. Each or more of the drive voltage bus 25, common voltage bus 35, first initialization voltage bus 45, second-first initialization voltage bus 55a, and second-second initialization voltage bus 55b may extend in a first direction (e.g., the x-direction).

[0165] Each or more of the drive voltage bus 25, common voltage bus 35, first initialization voltage bus 45, second-first initialization voltage bus 55a, and second-second initialization voltage bus 55b can be electrically connected to each or one or more pixels PX arranged in the display area DA. For example, drive voltage bus 25, common voltage bus 35, and first initialization voltage bus 45 can respectively connect the drive voltage ELVDD (see...) Figure 4 ), common voltage ELVSS (see Figure 4 ) and the first initialization voltage Vint (see Figure 4 ) is transmitted to each pixel PX or one or more pixels PX. For example, the 2-1 initialization voltage bus 55a can be configured to transmit the second initialization voltage Vaint (see Figure 4 This is transmitted to pixel PX that emits light of a first color (e.g., green) and pixel PX that emits light of a second color (e.g., blue). For example, the 2-2 initialization voltage bus 55b can transmit the second initialization voltage Vaint (see...) Figure 4 ) provides to the pixel PX that emits a third color (e.g., red) light.

[0166] Figure 6 The diagram shows a drive voltage bus 25 arranged between the display area DA and a first initialization voltage bus 45, the first initialization voltage bus 45 arranged between the drive voltage bus 25 and a second-second initialization voltage bus 55b, the second-second initialization voltage bus 55b arranged between the first initialization voltage bus 45 and a second-first initialization voltage bus 55a, and a common voltage bus 35 arranged between the second-first initialization voltage bus 55a and the first drive voltage supply line 21; however, the inventive concept is not limited thereto. The arrangement order of the drive voltage bus 25, common voltage bus 35, first initialization voltage bus 45, second-first initialization voltage bus 55a and / or second-second initialization voltage bus 55b can be modified differently according to some exemplary embodiments.

[0167] The drive voltage supply line 20 may include a first drive voltage supply line 21 and a second drive voltage supply line 22 that are electrically connected to each other.

[0168] At least a portion of the first drive voltage supply line 21 may extend in a first direction (e.g., the x-direction). For example, the first drive voltage supply line 21 may be referred to as a horizontal drive voltage supply line. At least a portion of the first drive voltage supply line 21 may overlap with the sloping portion FW2 of the fan-out line portion FWP. For example, the portion of the first drive voltage supply line 21 extending in the first direction (e.g., the x-direction) may overlap with the sloping portion FW2 of the fan-out line portion FWP.

[0169] The second driving voltage supply line 22 can be arranged on the first driving voltage supply line 21. At least a portion of the second driving voltage supply line 22 can overlap with the first driving voltage supply line 21, and the second driving voltage supply line 22 can be connected (or electrically connected) to the first driving voltage supply line 21 through a contact hole. Because the second driving voltage supply line 22 is arranged on the first driving voltage supply line 21, the first driving voltage supply line 21 and the second driving voltage supply line 22 can be referred to as the lower driving voltage supply line and the upper driving voltage supply line, respectively.

[0170] The second drive voltage supply line 22 may extend in a second direction (e.g., the y-direction). For example, the second drive voltage supply line 22 may be referred to as the vertical drive voltage supply line. The second drive voltage supply line 22 may be connected (or electrically connected) to the drive voltage bus 25 via a contact hole. The second drive voltage supply line 22 may be electrically connected to the referenced above. Figure 3 The pad area PADA is described. In some example embodiments, the second drive voltage supply line 22 may include multiple patterns arranged in a second direction (e.g., the y-direction). For example, the multiple patterns of the second drive voltage supply line 22 may be electrically connected to each other through conductive layers arranged on different layers of the second drive voltage supply line 22.

[0171] The common voltage supply line 30 may include a main common voltage supply line 30a and / or a secondary common voltage supply line 30b. In some example embodiments, the main common voltage supply line 30a may be arranged to surround at least a portion of the display area DA and may be connected to the counter electrode 230 extending from both sides of the display area DA to the peripheral area PA (see [link to relevant documentation]). Figure 5 In some example embodiments, the secondary common voltage supply line 30b may be electrically connected to the common voltage bus 35.

[0172] Each or one or more of the main common voltage supply line 30a and the secondary common voltage supply line 30b may include the first common voltage supply line 31 and / or the second common voltage supply line 32.

[0173] The second common voltage supply line 32 can be arranged on the first common voltage supply line 31. At least a portion of the second common voltage supply line 32 can overlap with the first common voltage supply line 31, and the second common voltage supply line 32 can be connected (or electrically connected) to the first common voltage supply line 31 through a contact hole. Because the second common voltage supply line 32 is arranged on the first common voltage supply line 31, the first common voltage supply line 31 and the second common voltage supply line 32 can be referred to as the lower common voltage supply line and the upper common voltage supply line, respectively.

[0174] The second common voltage supply line 32 may extend in a first direction (e.g., the x-direction). In some example embodiments, the second common voltage supply line 32 may be connected (or electrically connected) to the common voltage bus 35 via a contact hole. For example, the second common voltage supply line 32 of the secondary common voltage supply line 30b may be connected (or electrically connected) to the common voltage bus 35 via a contact hole. The second common voltage supply line 32 may be electrically connected to the referenced above. Figure 3 The pad area PADA is described. In some example embodiments, the second common voltage supply line 32 may include multiple patterns arranged in a second direction (e.g., the y-direction). For example, the multiple patterns of the second common voltage supply line 32 may be electrically connected to each other through conductive layers arranged on different layers of the second common voltage supply line 32.

[0175] The display panel 10 may further include a first initialization voltage supply line 40, a second-1 initialization voltage supply line 50a, and / or a second-2 initialization voltage supply line 50b arranged in the peripheral area PA. The first initialization voltage supply line 40 may be configured to supply a first initialization voltage Vint (see...). Figure 4 The second initialization voltage supply line 50a and / or the second initialization voltage supply line 50b can be configured to supply the second initialization voltage Vaint (see [reference]). Figure 4 This is provided to each pixel PX or one or more pixels PX. For example, the 2-1 initialization voltage supply line 50a can be configured to supply the second initialization voltage Vaint (see...). Figure 4 The system provides initialization voltage supply line 50b to a pixel PX that emits light of a first color (e.g., green) and a pixel PX that emits light of a second color (e.g., blue), and the second-second initialization voltage supply line 50b can be configured to supply the second initialization voltage Vaint (see [reference]). Figure 4 ) provides to the pixel PX that emits a third color (e.g., red) light.

[0176] The first initialization voltage supply line 40 may include a first lower initialization voltage supply line 41 and / or a first upper initialization voltage supply line 42. The first upper initialization voltage supply line 42 may be arranged on the first lower initialization voltage supply line 41. At least a portion of the first upper initialization voltage supply line 42 may overlap with the first lower initialization voltage supply line 41, and the first upper initialization voltage supply line 42 may be connected (or electrically connected) to the first lower initialization voltage supply line 41 via a contact hole.

[0177] The first initialization voltage supply line 42 may extend in a second direction (e.g., the y-direction). In some example embodiments, the first initialization voltage supply line 42 may be connected (or electrically connected) to the first initialization voltage bus 45 via a contact hole. The first initialization voltage supply line 42 may be electrically connected to the referenced above. Figure 3 The pad area PADA is described. In some example embodiments, the first upper initialization voltage supply line 42 may include multiple patterns arranged in a second direction (e.g., the y-direction). For example, the multiple patterns of the first upper initialization voltage supply line 42 may be electrically connected to each other through conductive layers arranged on different layers from the first upper initialization voltage supply line 42.

[0178] The 2-1 initialization voltage supply line 50a may include the 2-1 lower initialization voltage supply line 51a and / or the 2-1 upper initialization voltage supply line 52a. The 2-1 upper initialization voltage supply line 52a may be arranged on the 2-1 lower initialization voltage supply line 51a. At least a portion of the 2-1 upper initialization voltage supply line 52a may overlap with the 2-1 lower initialization voltage supply line 51a, and the 2-1 upper initialization voltage supply line 52a may be connected (or electrically connected) to the 2-1 lower initialization voltage supply line 51a through a contact hole.

[0179] The initialization voltage supply line 52a on the 2-1 axis may extend in a second direction (e.g., the y-direction). In some example embodiments, the initialization voltage supply line 52a on the 2-1 axis may be connected (or electrically connected) to the initialization voltage bus 55a on the 2-1 axis via a contact hole. The initialization voltage supply line 52a on the 2-1 axis may be electrically connected to the referenced above. Figure 3 The pad area PADA is described. In some example embodiments, the initialization voltage supply line 52a on the 2-1 may include multiple patterns arranged in a second direction (e.g., the y-direction). For example, the multiple patterns of the initialization voltage supply line 52a on the 2-1 may be electrically connected to each other through conductive layers arranged in a different layer than the initialization voltage supply line 52a on the 2-1.

[0180] The 2-2 initialization voltage supply line 50b may include the 2-2 lower initialization voltage supply line 51b and / or the 2-2 upper initialization voltage supply line 52b. The 2-2 upper initialization voltage supply line 52b may be arranged on the 2-2 lower initialization voltage supply line 51b. At least a portion of the 2-2 upper initialization voltage supply line 52b may overlap with the 2-2 lower initialization voltage supply line 51b, and the 2-2 upper initialization voltage supply line 52b may be connected (or electrically connected) to the 2-2 lower initialization voltage supply line 51b through a contact hole.

[0181] The initialization voltage supply line 52b on the 2-2 axis may extend in a second direction (e.g., the y-direction). In some example embodiments, the initialization voltage supply line 52b on the 2-2 axis may be connected (or electrically connected) to the initialization voltage bus 55b on the 2-2 axis via a contact hole. The initialization voltage supply line 52b on the 2-2 axis may be electrically connected to the referenced above. Figure 3 The pad area PADA is described. In some example embodiments, the initialization voltage supply line 52b on the 2-2 may include multiple patterns arranged in a second direction (e.g., the y-direction). For example, the multiple patterns of the initialization voltage supply line 52b on the 2-2 may be electrically connected to each other through conductive layers arranged on different layers of the initialization voltage supply line 52b on the 2-2.

[0182] In some example embodiments, the first lower initialization voltage supply line 41 and / or the second-first lower initialization voltage supply line 51a may be arranged between the first drive voltage supply line 21 and the first common voltage supply line 31 of the secondary common voltage supply line 30b. For example, as Figure 6 As shown, the first lower initialization voltage supply line 41 can be arranged between the first common voltage supply line 31 and the second-first lower initialization voltage supply line 51a, and the second-first lower initialization voltage supply line 51a can be arranged between the first lower initialization voltage supply line 41 and the first drive voltage supply line 21.

[0183] In some example embodiments, the first lower initialization voltage supply line 41, the second-first lower initialization voltage supply line 51a, and the second-second lower initialization voltage supply line 51b can be arranged between the first driving voltage supply line 21 and the first common voltage supply line 31 of the main common voltage supply line 30a. For example, the first lower initialization voltage supply line 41 can be arranged between the first driving voltage supply line 21 and the second-first lower initialization voltage supply line 51a, the second-first lower initialization voltage supply line 51a can be arranged between the first lower initialization voltage supply line 41 and the second-second lower initialization voltage supply line 51b, and the second-second lower initialization voltage supply line 51b can be arranged between the second-first lower initialization voltage supply line 51a and the first common voltage supply line 31.

[0184] In some example embodiments, the first common voltage supply line 31 of the secondary common voltage supply line 30b may be arranged between the first drive voltage supply lines 21.

[0185] However, the arrangement of each or one or more voltage supply lines is not limited to... Figure 6The arrangement shown can be modified in different ways. In some example embodiments, the second-1 lower initialization voltage supply line 51a and / or the second-2 lower initialization voltage supply line 51b can be arranged between the first drive voltage supply line 21 and the first common voltage supply line 31 of the secondary common voltage supply line 30b.

[0186] In some example embodiments, the first initialization voltage supply line 42 and / or the second-first initialization voltage supply line 52a may be arranged between the second drive voltage supply line 22 and the second common voltage supply line 32 of the secondary common voltage supply line 30b. For example, as Figure 6 As shown, the first initialization voltage supply line 42 can be arranged between the second common voltage supply line 32 and the second-first initialization voltage supply line 52a, and the second-first initialization voltage supply line 52a can be arranged between the first initialization voltage supply line 42 and the second drive voltage supply line 22.

[0187] In some example embodiments, the first upper initialization voltage supply line 42, the second-1st upper initialization voltage supply line 52a, and / or the second-2nd upper initialization voltage supply line 52b may be arranged between the second drive voltage supply line 22 and the second common voltage supply line 32 of the main common voltage supply line 30a. For example, the first upper initialization voltage supply line 42 may be arranged between the second drive voltage supply line 22 and the second-1st upper initialization voltage supply line 52a, the second-1st upper initialization voltage supply line 52a may be arranged between the first upper initialization voltage supply line 42 and the second-2nd upper initialization voltage supply line 52b, and the second-2nd upper initialization voltage supply line 52b may be arranged between the second-1st upper initialization voltage supply line 52a and the second common voltage supply line 32.

[0188] In some example embodiments, the second common voltage supply line 32 of the secondary common voltage supply line 30b may be arranged between the second drive voltage supply lines 22.

[0189] However, the arrangement of each or one or more voltage supply lines is not limited to... Figure 6 The arrangement shown can be modified in different ways. In some example embodiments, the initialization voltage supply line 52a on the 2-1 and / or the initialization voltage supply line 52b on the 2-2 can be arranged between the second drive voltage supply line 22 and the second common voltage supply line 32 of the sub-common voltage supply line 30b.

[0190] In some example embodiments, the drive voltage bus 25, common voltage bus 35, first initialization voltage bus 45, second-first initialization voltage bus 55a, second-second initialization voltage bus 55b, first drive voltage supply line 21, first common voltage supply line 31, first lower initialization voltage supply line 41, second-first lower initialization voltage supply line 51a and / or second-second lower initialization voltage supply line 51b can be arranged on the same layer (e.g., arranged in the second interlayer insulation layer 106 (see...)). Figure 5 )superior).

[0191] In some example embodiments, the second drive voltage supply line 22, the second common voltage supply line 32, the first upper initialization voltage supply line 42, the second-1 upper initialization voltage supply line 52a and / or the second-2 upper initialization voltage supply line 52b can be arranged on the same layer (e.g., arranged on the first via insulation layer 110 (see...)). Figure 5 )superior).

[0192] Figure 7 It is a schematic enlarged plan view of a portion of a display panel according to some example embodiments and is Figure 6 An enlarged plan view of region "B".

[0193] Figures 8 to 10 They are shown separately. Figure 7 The diagram shows a plan view of each layer of the display panel. In other words, Figure 7 References are shown Figures 8 to 10 The described layers are stacked sequentially.

[0194] Figure 11 This is an illustrative representation based on some example embodiments. Figure 7 A cross-sectional view of the display panel along line II-II'.

[0195] refer to Figure 7 and Figure 11 The fan-out section (FWP) may include a first fan-out layer (FL1) and / or a second fan-out layer (FL2). For example, each or one or more of the straight section (FW1) and the diagonal section (FW2) of the fan-out section (FWP) may include a first fan-out layer (FL1) and / or a second fan-out layer (FL2). In a plan view, the first fan-out layer (FL1) and the second fan-out layer (FL2) may be arranged alternately. For example, in a plan view, the second fan-out layer (FL2) may be arranged between adjacent first fan-out layers (FL1). For example, in a plan view, the first fan-out layer (FL1) may be arranged between adjacent second fan-out layers (FL2).

[0196] In some example embodiments, the second fan-out layer FL2 may be disposed above the first fan-out layer FL1. The first fan-out layer FL1 and the second fan-out layer FL2 may not overlap each other. In some example embodiments, the first fan-out layer FL1 may be disposed above the first fan-out layer FL1. Figure 5 The first gate electrode GE1 is disposed on the same layer (e.g., on the first gate insulating layer 102). In some example embodiments, the second fan-out layer FL2 may be disposed with... Figure 5 The upper electrode CE2 of the first capacitor Cst is arranged in the same layer (e.g., arranged on the second gate insulating layer 103).

[0197] Each or more of the first fan-out layer FL1 and the second fan-out layer FL2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers comprising the above-mentioned materials. The first fan-out layer FL1 and the second fan-out layer FL2 may include the same conductive material, or may include different conductive materials.

[0198] The first interlayer insulation layer 104 can be arranged on the fan-out section FWP, and the second interlayer insulation layer 106 can be arranged on the first interlayer insulation layer 104.

[0199] refer to Figure 7 , Figure 8 and Figure 11 The drive voltage bus 25, common voltage bus 35, first initialization voltage bus 45, second-first initialization voltage bus 55a, second-second initialization voltage bus 55b, first drive voltage supply line 21, first common voltage supply line 31, first lower initialization voltage supply line 41 and / or second-first lower initialization voltage supply line 51a can be arranged on the fan-out section FWP. The drive voltage bus 25, common voltage bus 35, first initialization voltage bus 45, second-first initialization voltage bus 55a, second-second initialization voltage bus 55b, first drive voltage supply line 21, first common voltage supply line 31, first lower initialization voltage supply line 41 and / or second-first lower initialization voltage supply line 51a can be arranged on the second interlayer insulation layer 106.

[0200] Each or more of the following: drive voltage bus 25, common voltage bus 35, first initialization voltage bus 45, second-first initialization voltage bus 55a, and second-second initialization voltage bus 55b, may be arranged in the display area DA (see [link]). Figure 6 () and between the first portion 21a of the first drive voltage supply line 21 described below.

[0201] In some example embodiments, at least some of the drive voltage bus 25, common voltage bus 35, first initialization voltage bus 45, second-first initialization voltage bus 55a, and second-second initialization voltage bus 55b may overlap with the straight portion FW1 of the fanout portion FWP. For example, as Figure 8 As shown, the driving voltage bus 25, the first initialization voltage bus 45, the second-first initialization voltage bus 55a, and / or the second-second initialization voltage bus 55b may overlap with the flat portion FW1, and a portion of the common voltage bus 35 may overlap with the diagonal portion FW2. However, the inventive concept is not limited to the illustrations, and for example, each or one or more of the driving voltage bus 25, the common voltage bus 35, the first initialization voltage bus 45, the second-first initialization voltage bus 55a, and the second-second initialization voltage bus 55b may overlap with the flat portion FW1.

[0202] In some example embodiments, at least some of the drive voltage bus 25, common voltage bus 35, first initialization voltage bus 45, second-first initialization voltage bus 55a, and second-second initialization voltage bus 55b may not overlap with the overlay conductive layer CCL described below. For example, as Figure 7 As shown, the driving voltage bus 25, the first initialization voltage bus 45, and / or the second-second initialization voltage bus 55b may not overlap with the covering conductive layer CCL. However, the inventive concept is not limited to the illustration, and for example, each or one or more of the driving voltage bus 25, the common voltage bus 35, the first initialization voltage bus 45, the second-first initialization voltage bus 55a, and the second-second initialization voltage bus 55b may not overlap with the covering conductive layer CCL.

[0203] The first drive voltage supply line 21 may include a first portion 21a extending in a first direction (e.g., the x-direction) and / or from the first portion 21a toward the pad area PADA (see Figure 3 The second portion 21b extends in the direction of (e.g., the -y direction). The first portion 21a of the first drive voltage supply line 21 may be arranged on the slanted portion FW2 of the fan-out line portion FWP and may overlap with the slanted portion FW2 of the fan-out line portion FWP.

[0204] The first common voltage supply line 31 and the first portion 21a of the first driving voltage supply line 21 may be spaced apart from each other in a second direction (e.g., the y-direction). For example, the first common voltage supply line 31 may be spaced apart from the first portion 21a of the first driving voltage supply line 21 in the -y direction. The second portion 21b of the first common voltage supply line 31 and the first driving voltage supply line 21 may be spaced apart from each other in a first direction (e.g., the x-direction). For example, the first common voltage supply line 31 may be spaced apart from the second portion 21b of the first driving voltage supply line 21 in the -x direction.

[0205] In some example embodiments, the first lower initialization voltage supply line 41 and / or the second-first lower initialization voltage supply line 51a may be arranged between the second portion 21b of the first drive voltage supply line 21 and the first common voltage supply line 31. For example, as Figure 8 As shown, the first lower initialization voltage supply line 41 can be arranged between the first common voltage supply line 31 and the second-first lower initialization voltage supply line 51a, and the second-first lower initialization voltage supply line 51a can be arranged between the first lower initialization voltage supply line 41 and the second part 21b of the first drive voltage supply line 21.

[0206] Each or one or more of the following: drive voltage bus 25, common voltage bus 35, first initialization voltage bus 45, second-first initialization voltage bus 55a, second-second initialization voltage bus 55b, first drive voltage supply line 21, first common voltage supply line 31, first lower initialization voltage supply line 41 and second-first lower initialization voltage supply line 51a may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may include a single layer or multiple layers containing the above materials.

[0207] The first through-hole insulating layer 110 can be arranged on the drive voltage bus 25, the common voltage bus 35, the first initialization voltage bus 45, the second-first initialization voltage bus 55a, the second-second initialization voltage bus 55b, the first drive voltage supply line 21, the first common voltage supply line 31, the first lower initialization voltage supply line 41 and / or the second-first lower initialization voltage supply line 51a.

[0208] refer to Figure 7 , Figure 8 , Figure 9 and Figure 11The second driving voltage supply line 22, the second common voltage supply line 32, the first upper initialization voltage supply line 42, and / or the second-first upper initialization voltage supply line 52a can be arranged on the first driving voltage supply line 21. Each or at least a portion of the second driving voltage supply line 22, the second common voltage supply line 32, the first upper initialization voltage supply line 42, and the second-first upper initialization voltage supply line 52a can overlap with the first portion 21a of the first driving voltage supply line 21. The second driving voltage supply line 22, the second common voltage supply line 32, the first upper initialization voltage supply line 42, and / or the second-first upper initialization voltage supply line 52a can be arranged on the first through-hole insulating layer 110.

[0209] The second driving voltage supply line 22, the second common voltage supply line 32, the first upper initialization voltage supply line 42 and / or the second-first upper initialization voltage supply line 52a may be spaced apart from each other in a first direction (e.g., the x direction).

[0210] In some example embodiments, a portion of the first drive voltage supply line 21 may be exposed in a first region Ra between the second common voltage supply line 32 and the first upper initialization voltage supply line 42. In some example embodiments, a portion of the first drive voltage supply line 21 may be exposed in a second region Rb between the first upper initialization voltage supply line 42 and the second-first upper initialization voltage supply line 52a. In some example embodiments, a portion of the first drive voltage supply line 21 may be exposed in a third region Rc between the second-first upper initialization voltage supply line 52a and the second drive voltage supply line 22. For example, a first portion 21a of the first drive voltage supply line 21 may be exposed in the first region Ra, the second region Rb, and the third region Rc. In this paragraph, being exposed may mean that it does not overlap with the second drive voltage supply line 22 and conductive lines disposed on the same layer as the second drive voltage supply line 22 (e.g., the second common voltage supply line 32, the first upper initialization voltage supply line 42, and / or the second-first upper initialization voltage supply line 52a).

[0211] In the area where the first portion 21a of the first driving voltage supply line 21 overlaps with the diagonal portion FW2 of the fan-out line portion FWP, the first portion 21a of the first driving voltage supply line 21 may include portions that overlap with the second driving voltage supply line 22 and conductive lines arranged in the same layer as the second driving voltage supply line 22 (e.g., the second common voltage supply line 32, the first upper initialization voltage supply line 42, and / or the second-first upper initialization voltage supply line 52a), as well as portions that are exposed by not overlapping with the second driving voltage supply line 22 and conductive lines arranged in the same layer as the second driving voltage supply line 22 (e.g., the second common voltage supply line 32, the first upper initialization voltage supply line 42, and / or the second-first upper initialization voltage supply line 52a).

[0212] Each or one or more of the second driving voltage supply line 22, the second common voltage supply line 32, the first upper initialization voltage supply line 42, and the second-1st upper initialization voltage supply line 52a may include multiple first vias H1. For example, the first via H1 of the second driving voltage supply line 22 may pass through the second driving voltage supply line 22, the first via H1 of the second common voltage supply line 32 may pass through the second common voltage supply line 32, the first via H1 of the first upper initialization voltage supply line 42 may pass through the first upper initialization voltage supply line 42, and / or the first via H1 of the second-1st upper initialization voltage supply line 52a may pass through the second-1st upper initialization voltage supply line 52a.

[0213] The second drive voltage supply line 22, the second common voltage supply line 32, the first upper initialization voltage supply line 42 and / or the second-first upper initialization voltage supply line 52a, the first through hole H1 can be used as a degassing path for discharging gas from the organic insulating layer (e.g., the first through hole insulating layer 110 and / or the second through hole insulating layer 120).

[0214] Each or one or more of the second driving voltage supply line 22, the second common voltage supply line 32, the first upper initialization voltage supply line 42, and the second-first upper initialization voltage supply line 52a may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may include a single layer or multiple layers containing the above materials.

[0215] Display panel 10 (see Figure 3 ) may include arrangements in the peripheral area PA (see Figure 6The driving voltage transmission line 61, the second-second initialization voltage transmission line 62, the second-first initialization voltage transmission line 63, the common voltage transmission line 64 and / or the first initialization voltage transmission line 65 in the ).

[0216] The drive voltage transmission line 61, the second-second initialization voltage transmission line 62, the second-first initialization voltage transmission line 63, the common voltage transmission line 64 and / or the first initialization voltage transmission line 65 may be arranged on the same layer (e.g., on the first through-hole insulation layer 110) and may include the same material as the second drive voltage supply line 22.

[0217] Each or one or more of the drive voltage transmission line 61, the second-second initialization voltage transmission line 62, the second-first initialization voltage transmission line 63, the common voltage transmission line 64, and the first initialization voltage transmission line 65 may extend in a second direction (e.g., the y direction).

[0218] The drive voltage transmission line 61 can electrically connect the first drive voltage supply line 21 and the drive voltage bus 25 to each other. For example, the drive voltage transmission line 61 can be connected to the first drive voltage supply line 21 at one end through a contact hole, and can be connected to the drive voltage bus 25 at the other end through a contact hole.

[0219] The 2-2 initialization voltage transmission line 62 can be electrically connected to the 2-2 initialization voltage bus 55b and can be extended to the display area DA (see...). Figure 6 ) is electrically connected to the pixel circuit PC (see Figure 5 The 2-2 initialization voltage transmission line 62 can be connected to the 2-2 initialization voltage bus 55b via a contact hole.

[0220] The 2-1 initialization voltage transmission line 63 can be electrically connected to the 2-1 initialization voltage bus 55a and can be extended to the display area DA (see...). Figure 6 ) is electrically connected to the pixel circuit PC (see Figure 5 The 2-1 initialization voltage transmission line 63 can be connected to the 2-1 initialization voltage bus 55a via a contact hole.

[0221] Common voltage transmission line 64 can be electrically connected to common voltage bus 35 and can extend to display area DA (see...). Figure 6 ) is electrically connected to the pixel circuit PC (see Figure 5 Common voltage transmission line 64 can be connected to common voltage bus 35 via contact holes.

[0222] The first initialization voltage transmission line 65 can be electrically connected to the first initialization voltage bus 45 and can extend to the display area DA (see...). Figure 6) is electrically connected to the pixel circuit PC (see Figure 5 The first initialization voltage transmission line 65 can be connected to the first initialization voltage bus 45 through a contact hole.

[0223] The second through-hole insulating layer 120 may be disposed on the second driving voltage supply line 22, the second common voltage supply line 32, the first upper initialization voltage supply line 42, the second-first upper initialization voltage supply line 52a, the driving voltage transmission line 61, the second-second initialization voltage transmission line 62, the second-first initialization voltage transmission line 63, the common voltage transmission line 64 and / or the first initialization voltage transmission line 65.

[0224] refer to Figures 7 to 11 The conductive layer CCL can be arranged on the second driving voltage supply line 22, the second common voltage supply line 32, the first upper initialization voltage supply line 42 and / or the second-first upper initialization voltage supply line 52a.

[0225] In some example embodiments, the conductive layer CCL can be used with a light-emitting diode (LED) (see...) Figure 5 ) pixel electrode 210 (see Figure 5 The conductive layer CCL is disposed on the same layer (e.g., on the second via insulating layer 120). However, the inventive concept is not limited thereto, and the conductive layer CCL can be disposed on the light-emitting diode (LED) (see [link to LED documentation]). Figure 5 The topmost conductive layer in the conductive layer below is arranged in the same layer.

[0226] The conductive layer CCL may include the pixel electrode 210 (see...) Figure 5 The conductive material is the same as that used in the conductive layer. For example, the conductive layer CCL may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and / or any compound thereof, and a transparent or translucent electrode layer above the reflective layer. The transparent or translucent electrode layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. x It can be at least one of ZnO or ZnO2, indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). For example, the conductive coating CCL can have a three-layer structure of ITO / Ag / ITO.

[0227] The conductive layer CCL can be located in the peripheral region PA (see...) Figure 6 In, and can be used with display area DA (see) Figure 6 ) are spaced apart. For example, the conductive overlay CCL can be separated from the display area DA (see Figure 6 The conductive layer CCL is spaced approximately 70µm or more from the display area DA (see...). Figure 6 The space between the layers can serve as a degassing path for the exhaust of gases from the organic insulating layers (e.g., the first through-hole insulating layer 110 and / or the second through-hole insulating layer 120), thereby reducing the pressure on the display panel 10 (see [link]). Figure 3 The risk of shrinkage. For example, when the conductive layer CCL covers the display area DA (see... Figure 6 When the distance between the display panels is approximately 70µm or more, the display panel 10 can be reduced more effectively (see [reference]). Figure 3 The risk of contraction.

[0228] The conductive cover layer CCL may overlap with the sloping portion FW2 of the fan-out line portion FWP. In some example embodiments, the conductive cover layer CCL may overlap with the sloping portion FW2, but may only partially overlap with each or one or more of the straight portions FW1 arranged above and below the sloping portion FW2, or may not overlap with each or one or more of the straight portions FW1 arranged above and below the sloping portion FW2. In some example embodiments, the conductive cover layer CCL may only partially overlap with each or one or more of the second common voltage supply line 32, the first upper initialization voltage supply line 42, the second-first upper initialization voltage supply line 52a, and the second drive voltage supply line 22. In some example embodiments, the area of ​​the conductive cover layer CCL may be formed to be not excessively large, thereby reducing the display panel 10 (see [link to documentation]) due to degassing. Figure 3 This reduces the risk of shrinkage. For example, in some example embodiments, the cover conductive layer (CCL) can be smaller than that of a conventional cover conductive layer.

[0229] In some example embodiments, the overlay conductive layer CCL may extend in a first direction (e.g., the x-direction) in the region overlapping with the diagonal portion FW2 of the fan-out line portion FWP. For example, in the region overlapping with the diagonal portion FW2 of the fan-out line portion FWP, the overlay conductive layer CCL may cover each or one or more of the second common voltage supply line 32, the first upper initialization voltage supply line 42, the second-first upper initialization voltage supply line 52a, and the second drive voltage supply line 22, or may overlap with each or one or more of the second common voltage supply line 32, the first upper initialization voltage supply line 42, the second-first upper initialization voltage supply line 52a, and the second drive voltage supply line 22.

[0230] In the area overlapping with the diagonal portion FW2 of the fan-out line portion FWP, the cover conductive layer CCL may cover at least a portion of the area between the second common voltage supply line 32 and the second drive voltage supply line 22, or may overlap with that portion. The cover conductive layer CCL may cover one or more of the following: a first region Ra between the second common voltage supply line 32 and the first upper initialization voltage supply line 42; a second region Rb between the first upper initialization voltage supply line 42 and the second-1 upper initialization voltage supply line 52a; and a third region Rc between the second-1 upper initialization voltage supply line 52a and the second drive voltage supply line 22; or may overlap with one or more of the following: the first region Ra, the second region Rb, and the third region Rc. The cover conductive layer CCL may cover... Figure 6 The area between the adjacent second common voltage supply line 32 and the second drive voltage supply line 22 shown, or may overlap with this area. The conductive cover layer CCL may cover, as shown in the figure. Figure 6 The regions shown are the adjacent second drive voltage supply lines 22 and the first upper initialization voltage supply line 42, the adjacent first upper initialization voltage supply line 42 and the second-1 upper initialization voltage supply line 52a, the adjacent second-1 upper initialization voltage supply line 52a and the second-2 upper initialization voltage supply line 52b, and / or the adjacent second-2 upper initialization voltage supply line 52b and the second common voltage supply line 32, or may overlap with these regions.

[0231] The conductive cover layer CCL may include a plurality of second vias H2 passing through the conductive cover layer CCL. The second vias H2 of the conductive cover layer CCL may overlap with the first vias H1. For example, the second vias H2 of the conductive cover layer CCL may overlap with the first vias H1 of the second drive voltage supply line 22, the first vias H1 of the second common voltage supply line 32, the first vias H1 of the first upper initialization voltage supply line 42, and / or the first vias H1 of the second-1 upper initialization voltage supply line 52a.

[0232] The second via H2 covering the conductive layer CCL can serve as a degassing path for discharging gas from the organic insulating layer (e.g., the first via insulating layer 110 and / or the second via insulating layer 120). In some example embodiments, because the first via H1 overlaps with the second via H2, the length of the degassing path can be made shorter, thereby effectively discharging gas from the organic insulating layer (e.g., the first via insulating layer 110 and / or the second via insulating layer 120).

[0233] Because the first driving voltage supply line 21 is arranged below the first via insulating layer 110 and the second via insulating layer 120 corresponding to the planarization layer, the first driving voltage supply line 21 can have a curved upper surface due to the fan-out line portion FWP in the area overlapping with the diagonal portion FW2 of the fan-out line portion FWP. The area of ​​the first driving voltage supply line 21 that does not overlap with the conductive layer above the first via insulating layer 110 or the second via insulating layer 120 can have an external light reflectivity different from the external light reflectivity of the area of ​​the first driving voltage supply line 21 that overlaps with the conductive layer above the first via insulating layer 110 or the second via insulating layer 120.

[0234] In the area overlapping with the diagonal portion FW2 of the fan-out line portion FWP, in a comparative example where the conductive layer covering it is not arranged on the first drive voltage supply line 21 and therefore the first drive voltage supply line 21 does not overlap with the conductive layer above the first via insulating layer 110, the external light reflectivity between the area overlapping with the conductive layer above the first via insulating layer 110 and the area not overlapping with the conductive layer above the first via insulating layer 110 may be different from each other, and therefore the phenomenon of spots or reflective bands being visible may occur. For example, in the area where the first portion 21a of the first driving voltage supply line 21 overlaps with the diagonal portion FW2 of the fan-out line portion FWP, the area where the second driving voltage supply line 22, the second common voltage supply line 32, the first upper initialization voltage supply line 42 and the second-1 upper initialization voltage supply line 52a are arranged (or the area where the second driving voltage supply line 22, the second common voltage supply line 32, the first upper initialization voltage supply line 42 and the second-1 upper initialization voltage supply line 52a overlap) and the area where the second driving voltage supply line 22, the second common voltage supply line 32, the first upper initialization voltage supply line 42 and the second-1 upper initialization voltage supply line 52a are not arranged (or the area where the second driving voltage supply line 22, the second common voltage supply line 32, the first upper initialization voltage supply line 42 and the second-1 upper initialization voltage supply line 52a do not overlap) may have different external light reflectivities, and therefore, spots or reflective bands may appear.

[0235] In some example embodiments, in the area where the first portion 21a of the first driving voltage supply line 21 overlaps with the diagonal portion FW2 of the fan-out line portion FWP, the cover conductive layer CCL may extend in a first direction (e.g., the x-direction), and therefore the first portion 21a of the first driving voltage supply line 21 may not include the area overlapping with the cover conductive layer CCL above the first via insulating layer 110 and not overlapping with the conductive layer above the first via insulating layer 110. Therefore, because external light is uniformly reflected by the cover conductive layer CCL, the visibility of spots or reflective bands can be effectively reduced, thereby improving the display panel 10 (see [link]). Figure 3 The display quality of ).

[0236] refer to Figure 7 and Figure 10 A portion of the conductive layer CCL can overlap with the light-blocking layer BM. The light-blocking layer BM can be arranged in the peripheral region PA (see...). Figure 6 The light-blocking layer BM can cover a portion of the conductive layer CCL and can face the pad area PADA (see [link]). Figure 3 )extend.

[0237] The light-blocking layer BM can be combined with the display area DA (see...) Figure 6 ) can be arranged separately from the outer area PA (see Figure 6 It may partially overlap with the outer region PA (see...) Figure 6 The other parts overlap. In some example embodiments, the conductive overlay layer CCL is arranged in the peripheral region PA (see...). Figure 6 In areas that do not overlap with the light-blocking layer BM (e.g., the area where the first portion 21a of the first drive voltage supply line 21 and the diagonal portion FW2 of the fan-out line portion FWP overlap each other), the appearance of spots or reflective bands due to external light reflection can be reduced or prevented.

[0238] In the region R1 where the conductive cover layer CCL and the light-blocking layer BM overlap, the conductive cover layer CCL can be connected (or electrically connected) to the second common voltage supply line 32. Because the conductive cover layer CCL includes a contact portion in the region R1 overlapping with the light-blocking layer BM that connects to the second common voltage supply line 32, the appearance of spots or reflective bands due to the contact portion of the conductive cover layer CCL can be reduced or prevented. Reference will be made below. Figures 12 to 15 This will be described in detail.

[0239] To prevent or reduce the impact of gases emitted from the organic insulating layers (e.g., the first through-hole insulating layer 110 and / or the second through-hole insulating layer 120) on the display panel 10 (see [link]). Figure 3To mitigate the risk of shrinkage, according to some example embodiments, the conductive cover layer CCL may overlap with the light-blocking layer BM only in some areas where the contact portions described above are arranged, and may not overlap with the light-blocking layer BM in other areas.

[0240] The width W1 of the region R1 where the conductive layer CCL and the light-blocking layer BM overlap is approximately 30 μm to approximately 100 μm in the second direction (e.g., the y-direction). When the area of ​​the conductive layer CCL increases and therefore the width W1 of the region R1 where the conductive layer CCL and the light-blocking layer BM overlap exceeds 100 μm, the display panel 10 (see [reference]) will experience a problem due to the exhaust of gas from the organic insulating layer (e.g., the first through-hole insulating layer 110 and / or the second through-hole insulating layer 120). Figure 3 The risk of shrinkage may increase significantly. When the width W1 of the region R1 in which the conductive layer CCL and the light-blocking layer BM overlap is less than 30 μm, areas with different external light reflectivities may appear because the contact portion of the conductive layer CCL and the second common voltage supply line 32 does not overlap with the light-blocking layer BM, and therefore the display panel 10 (see Figure 3 The display quality of the display panel 10 may be reduced. According to some example embodiments, because the width W1 of the region R1 in which the conductive layer CCL and the light-blocking layer BM overlap is approximately 30 μm to approximately 100 μm in a second direction (e.g., the y-direction), the display quality can be significantly reduced (see [reference]). Figure 3 The risk of shrinkage can be reduced and the display panel 10 (see) can be improved. Figure 3 The display quality of ).

[0241] Counter electrode 230 can be obtained from display area DA (see Figure 6 ) extends to the outer area PA (see Figure 6 The counter electrode 230 may be disposed on the conductive cover layer CCL. The counter electrode 230 may be electrically connected to the conductive cover layer CCL and may receive a common voltage ELVSS (see [reference]) through the conductive cover layer CCL. Figure 4 ).

[0242] In some example embodiments, the counter electrode 230 may overlap with a portion of the conductive overlay layer CCL and may not overlap with the light-blocking layer BM. For example, in a plan view, the counter electrode 230 may be spaced apart from the light-blocking layer BM.

[0243] In some example embodiments, because the conductive overlay CCL connects (or electrically connects) the second common voltage supply line 32 and the counter electrode 230 to each other to transmit the common voltage ELVSS (see [link to documentation]). Figure 4 The signal is transmitted to the counter electrode 230, so that it is connected to the display panel 10 therein (see...). Figure 3 Compared to the comparative example excluding the conductive overlay, the arrangement in the peripheral region PA (see...) Figure 6 The area of ​​the counter electrode 230 in the outer region PA (see...) can be reduced. Figure 6 When the area of ​​the counter electrode 230 in the ) is reduced, it can improve the ability to control, for example, the organic encapsulation layer 320 (see Figure 5 The design freedom of the dam section for the return flow of a single unit.

[0244] However, the arrangement of the counter electrode 230 is not limited to that shown in the figure, and the counter electrode 230 may completely overlap with the covering conductive layer CCL.

[0245] Figure 12 It is a schematic enlarged plan view of a portion of a display panel according to some example embodiments and is Figure 7 An enlarged plan view of region "C".

[0246] Figure 13 This is an illustrative representation based on some example embodiments. Figure 12 A cross-sectional view of the display panel along line III-III'.

[0247] refer to Figure 12 and Figure 13 In the region R1 overlapping with the light-blocking layer BM, the overlay conductive layer CCL may include a contact portion CTP connected (or electrically connected) to the second common voltage supply line 32. Because the overlay conductive layer CCL is connected (or electrically connected) to the second common voltage supply line 32, the overlay conductive layer CCL can be used as a device configured to transmit the common voltage ELVSS (see [link to documentation]). Figure 4 () common voltage transmission line, and can be referenced as follows Figures 7 to 11 The description of the improved display panel 10 (see Figure 3 The display quality of ).

[0248] In some example embodiments, the second via insulating layer 120 disposed between the second common voltage supply line 32 and the overlay conductive layer CCL may include an opening 120OP surrounding each or one or more of the plurality of second vias H2 in a plan view. The second via insulating layer 120 may include an opening 120OP surrounding each or one or more of the plurality of first vias H1 in a plan view.

[0249] The opening 120OP of the second via insulating layer 120 can overlap with the light blocking layer BM. Because the opening 120OP of the second via insulating layer 120 overlaps with the light blocking layer BM (e.g., because the contact portion CTP covering the conductive layer CCL overlaps with the light blocking layer BM), the formation of areas with different external light reflectivities due to the opening 120OP of the second via insulating layer 120 can be reduced or prevented. Accordingly, the display panel 10 (see...) Figure 3 The display quality can be improved.

[0250] The contact portion CTP of the conductive layer CCL can be disposed in the opening 120OP of the second via insulating layer 120 and can be connected (or electrically connected) to the second common voltage supply line 32. For example, in a plan view, the contact portion CTP of the conductive layer CCL can surround each or one or more of the plurality of second vias H2 (or first vias H1).

[0251] Figure 14 It is a schematic enlarged plan view of a portion of a display panel according to some example embodiments and is Figure 7 An enlarged plan view of region "C".

[0252] Figure 15 This is an illustrative representation based on some example embodiments. Figure 14 A cross-sectional view of the display panel along line IV-IV'.

[0253] refer to Figure 14 and Figure 15 In the region R1 that overlaps with the light-blocking layer BM, the conductive layer CCL may include a contact portion CTP' connected (or electrically connected) to the second common voltage supply line 32.

[0254] In some example embodiments, the second via insulating layer 120 may include an opening group OPG comprising a plurality of openings 120OP' arranged in a plan view among adjacent second vias H2. The opening group OPG may be provided as a plurality of opening groups OPG. The second via insulating layer 120 may include an opening group OPG comprising a plurality of openings 120OP' arranged in a plan view among adjacent first vias H1.

[0255] The opening group OPG of the second via insulating layer 120 can overlap with the light blocking layer BM. For example, multiple openings 120OP' of the second via insulating layer 120 can overlap with the light blocking layer BM. Because the opening group OPG of the second via insulating layer 120 overlaps with the light blocking layer BM (e.g., because the contact portion CTP' covering the conductive layer CCL overlaps with the light blocking layer BM), the formation of areas with different external light reflectivities due to the opening group OPG of the second via insulating layer 120 can be reduced or prevented. Accordingly, the display panel 10 (see...) Figure 3 The display quality can be improved.

[0256] The contact portion CTP' of the conductive layer CCL can be arranged in the opening group OPG of the second via insulating layer 120. For example, the contact portion CTP' of the conductive layer CCL can be arranged in each opening 120OP' or one or more openings 120OP' of the second via insulating layer 120, and can be connected (or electrically connected) to the second common voltage supply line 32. For example, in a plan view, the contact portion CTP' of the conductive layer CCL can be arranged between adjacent second vias H2 among a plurality of second vias H2.

[0257] Figure 16 It is a schematic enlarged plan view of a portion of a display panel according to some example embodiments and is Figure 6 An enlarged plan view of region "B".

[0258] Figure 17 It is shown schematically. Figure 16 A floor plan of a portion of the display panel shown in the image. Figure 16 References are shown Figure 8 , Figure 9 and Figure 17 The described layers are stacked sequentially.

[0259] Figure 18 This is an illustrative representation based on some example embodiments. Figure 16 A cross-sectional view of the display panel along line V-V'.

[0260] Reference Figures 16 to 18 In the example embodiments described, references to the above will be omitted. Figures 6 to 11 The descriptions of the provided example embodiments are repetitive, and the main focus will be on the differences between them.

[0261] refer to Figures 16 to 18In some example embodiments, the conductive layer CCL may include a main portion STP that overlaps with the light blocking layer BM in the region that overlaps with the diagonal portion FW2 of the fan-out line portion FWP, and a branch portion BRP that extends from the main portion STP in a second direction (e.g., the y direction) and covers at least a portion of the region between the second drive voltage supply line 22 and the second common voltage supply line 32.

[0262] In the area overlapping with the light-blocking layer BM, the main portion STP of the conductive layer CCL can be connected (or electrically connected) to the second common voltage supply line 32. Because the main portion STP of the conductive layer CCL includes a contact portion connecting to the second common voltage supply line 32 in the region R1 overlapping with the light-blocking layer BM, the formation of areas with different external light reflectivities due to the contact portions of the conductive layer CCL can be reduced or prevented. Accordingly, the display panel 10 (see...) Figure 3 The display quality can be improved.

[0263] The contact portion, including the main STP portion of the CCL overlay, can be referenced above. Figure 12 and Figure 13 The provided description of the CTP contact portion and the above reference Figure 14 and Figure 15 The contact portion CTP is described in the same way as the provided contact portion. For example, in a plan view, the contact portion of the main portion STP may surround each or one or more of the plurality of second through holes H2 (or first through holes H1). For example, in a plan view, the contact portion of the main portion STP may be arranged between adjacent second through holes H2.

[0264] A branch portion (BRP) may include one or more of its sub-branch portions extending from the trunk portion (STP) in a second direction (e.g., the y-direction). These sub-branch portions may be spaced apart from each other in a first direction (e.g., the x-direction). For example, a branch portion (BRP) may include one or more first sub-branch portions (BRP1), second sub-branch portions (BRP2), and / or third sub-branch portions (BRP3) extending from the trunk portion (STP) in a second direction (e.g., the y-direction). The first sub-branch portions (BRP1), second sub-branch portions (BRP2), and third sub-branch portions (BRP3) may be spaced apart from each other in the first direction (e.g., the x-direction).

[0265] The first sub-branch portion BRP1 covering the conductive layer CCL can cover the first region Ra between the second common voltage supply line 32 and the first upper initialization voltage supply line 42, or it can overlap with the first region Ra. The second sub-branch portion BRP2 covering the conductive layer CCL can cover the second region Rb between the first upper initialization voltage supply line 42 and the second-first upper initialization voltage supply line 52a, or it can overlap with the second region Rb. The third sub-branch portion BRP3 covering the conductive layer CCL can cover the third region Rc between the second-first upper initialization voltage supply line 52a and the second driving voltage supply line 22, or it can overlap with the third region Rc.

[0266] As an example, Figures 16 to 18 The diagram illustrates a first sub-branch portion BRP1, a second sub-branch portion BRP2, and a third sub-branch portion BRP3; however, the inventive concept is not limited thereto. For example, the conductive overlay CCL may further include a covering such as Figure 6 The region between the adjacent second common voltage supply line 32 and the second drive voltage supply line 22, or the sub-branch portion overlapping that region, as shown. The conductive cover layer CCL may further include a cover such as Figure 6 The sub-branch portion of the area between the adjacent second drive voltage supply line 22 and the first upper initialization voltage supply line 42 shown in the figure, covering as Figure 6 The sub-branch portion of the region between the first upper initialization voltage supply line 42 and the second-first upper initialization voltage supply line 52a, which are adjacent to each other, is covered as shown. Figure 6 The sub-branch portions and / or coverages of the area between the adjacent initialization voltage supply lines 52a and 52b on the 2-1th upper part of the diagram are as shown. Figure 6 The sub-branch portion of the area between the adjacent 2-2 upper initial voltage supply line 52b and the second common voltage supply line 32 is shown.

[0267] Because the main section STP of the conductive layer CCL is connected (or electrically connected) to the second common voltage supply line 32, the main section STP of the conductive layer CCL can be used to be configured to transmit the common voltage ELVSS (see [link to documentation]). Figure 4 ( ) common voltage transmission line.

[0268] In some example embodiments, in the area where the first portion 21a of the first driving voltage supply line 21 and the diagonal portion FW2 of the fan-out line portion FWP overlap each other, the cover conductive layer CCL may include sub-branch portions disposed on the second via insulating layer 120 to cover the area of ​​the first driving voltage supply line 21 that does not overlap with the conductive layer above the first via insulating layer 110. Accordingly, the first portion 21a of the first driving voltage supply line 21 may not include the area that does not overlap with the conductive layer above the first via insulating layer 110. Therefore, because external light is uniformly reflected by the cover conductive layer CCL, the visibility of spots or reflective bands can be effectively reduced, thereby improving the display panel 10 (see...). Figure 3 The display quality of ).

[0269] In some example embodiments, because the main trunk (STP) and branch trunk (BRP) are connected to each other, the entire conductive overlay (CCL) can be used to be configured to transmit the common voltage ELVSS (see [link to documentation]). Figure 4 The common voltage transmission line of the display panel 10 (see) can also improve the display panel 10 (see) Figure 3 The display quality of ).

[0270] Counter electrode 230 can be obtained from display area DA (see Figure 6 ) extends to the outer area PA (see Figure 6 The electrode 230 overlaps with the branch portion BRP of the conductive layer CCL. The counter electrode 230 can be electrically connected to the branch portion BRP of the conductive layer CCL and can receive the common voltage ELVSS through the conductive layer CCL (see [link to documentation]). Figure 4 ).

[0271] The display device according to some example embodiments can be applied to various electronic devices. The electronic device according to some example embodiments may include the above-described display device (e.g., ...). Figure 1 The display device 1), and in addition to the display device, the electronic device according to some example embodiments may further include modules or devices with other additional functions.

[0272] Figure 19 This is a block diagram of an electronic device according to some example embodiments.

[0273] refer to Figure 19 According to some example embodiments, the electronic device 1000 may include a display module 1001, a processor 1002, a memory 1003 and / or a power module 1004.

[0274] The processor 1002 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0275] The memory 1003 can store data information necessary for or sufficient for the operation of the processor 1002 or the display module 1001. When the processor 1002 executes the application program stored in the memory 1003, image data signals and / or input control signals can be transmitted to the display module 1001, and the display module 1001 can process the received signals and output image information through the display screen.

[0276] The power module 1004 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power necessary for or sufficient for the operation of the electronic device 1000.

[0277] At least one of the components of the electronic device 1000 described above may be included in the display device according to some of the example embodiments described above. Furthermore, in terms of function, some of the modules described above may be included in the display device, and other modules may be provided separately from the display device. For example, the display device may include a display module 1001, and the processor 1002, memory 1003, and power module 1004 may be provided in the form of other devices in the electronic device 1000 that are not display devices.

[0278] In some example embodiments, the display module 1001 included in the display device can operate based on image data signals and can receive input control signals from the processor 1002.

[0279] Figure 20 An electronic device according to some example embodiments is illustrated schematically.

[0280] refer to Figure 20 The various electronic devices, including display devices according to some example embodiments, may include not only electronic devices for displaying images such as smartphones 1000a, tablet computers 1000b, laptop computers 1000c, televisions (TVs) 1000d and / or desktop monitors 1000e, but also wearable electronic devices including display modules such as smart glasses 1000f, head-mounted displays 1000g and / or smartwatches 1000h, and / or vehicle electronic devices 1000i including display modules such as in-vehicle mirror displays, central information displays (CIDs) arranged in the center fascia and / or dashboard of a vehicle, and / or instrument panels of a vehicle.

[0281] According to some example embodiments, the display device may include a conductive overlay disposed in an area overlapping the diagonal portion of the fan-out line in a plan view, thereby reducing the visibility of spots or reflective bands that may occur in the area where the diagonal portion of the fan-out line and the horizontal drive voltage supply line overlap, thereby improving the display quality of the display device. However, the scope of the inventive concept is not limited to these effects.

[0282] One or more of the elements disclosed above may include one or more processing circuits such as hardware containing logic circuits, hardware / software combinations such as processors running software, or combinations thereof, or may be implemented in one or more processing circuits such as hardware containing logic circuits, hardware / software combinations such as processors running software, or combinations thereof. For example, more specifically, the processing circuits may include, but are not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0283] It should be understood that some of the exemplary embodiments described herein are to be considered in a descriptive sense only and are not intended to be limiting. The description of features or aspects within each exemplary embodiment should generally be considered applicable to other similar features or aspects in other exemplary embodiments. Although some exemplary embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the claims.

Claims

1. A display device, comprising: The substrate includes a display area containing multiple pixels and a peripheral area outside the display area and including a pad area; The fan-out line portion extends from the pad area to the display area in the plan view and includes a straight portion and a diagonal portion; A first driving voltage supply line extends in a first direction on the oblique portion of the fan-out line portion, overlaps with the oblique portion of the fan-out line portion, and extends in the plan view. The second driving voltage supply line extends on the first driving voltage supply line and in the plan view in a second direction intersecting the first direction and is electrically connected to the first driving voltage supply line. A common voltage supply line is located on the first drive voltage supply line and is spaced apart from the second drive voltage supply line in the plan view; A conductive layer is provided, covering at least a portion of the area between the second drive voltage supply line and the common voltage supply line in the area overlapping with the diagonal portion of the fan-out line portion, and electrically connected to the common voltage supply line in the plan view; as well as A light-blocking layer is located in the peripheral region, on the conductive overlay layer, and overlapping a portion of the conductive overlay layer. In the region overlapping with the light-blocking layer, the conductive overlay includes a contact portion electrically connected to the common voltage supply line.

2. The display device according to claim 1, wherein, The common voltage supply line includes a plurality of first through holes passing through the common voltage supply line, and The conductive cover layer includes a plurality of second vias that pass through the conductive cover layer and overlap with the plurality of first vias, respectively.

3. The display device according to claim 2, further comprising: A through-hole insulating layer is located between the common voltage supply line and the cover conductive layer. The through-hole insulating layer includes an opening surrounding each of the plurality of second through holes in the plan view, and The contact portion of the conductive layer is located in the opening of the through-hole insulating layer.

4. The display device according to claim 3, wherein, The opening of the through-hole insulating layer overlaps with the light-blocking layer.

5. The display device according to claim 2, further comprising: A through-hole insulating layer is located between the common voltage supply line and the cover conductive layer. The through-hole insulating layer includes an opening group comprising a plurality of openings between adjacent second through holes in the plurality of second through holes in the plan view, and The contact portion of the conductive layer is located in the group of openings in the through-hole insulating layer.

6. The display device according to claim 5, wherein, The opening group of the through-hole insulating layer overlaps with the light-blocking layer.

7. The display device according to claim 1, wherein, The conductive covering layer extends in the first direction.

8. The display device according to claim 7, wherein, The conductive covering layer overlaps with the diagonal portion of the fan-out line.

9. The display device according to claim 1, wherein, The conductive overlay includes a main portion that overlaps with the light-blocking layer and a branch portion that extends from the main portion in the second direction and covers at least a portion of the region between the second drive voltage supply line and the common voltage supply line.

10. The display device according to claim 9, further comprising: A first initialization voltage supply line is located on the first drive voltage supply line and between the common voltage supply line and the second drive voltage supply line in the plan view. The branch portion of the conductive layer includes a first sub-branch portion that covers the area between the common voltage supply line and the first initial voltage supply line.

11. The display device according to claim 10, further comprising: A second initialization voltage supply line is located on the first drive voltage supply line and between the first initialization voltage supply line and the second drive voltage supply line in the plan view. The branch portion covering the conductive layer further includes a second sub-branch portion that is spaced apart from the first sub-branch portion in the first direction and covers the area between the first initialization voltage supply line and the second initialization voltage supply line.

12. The display device according to claim 1, wherein, The conductive overlay is separated from the display area.

13. The display device according to claim 1, further comprising: A drive voltage bus extends in the first direction between the first drive voltage supply line and the display area in the plan view.

14. The display device according to claim 13, wherein, The conductive overlay does not overlap with the drive voltage bus.

15. The display device according to claim 1, wherein, The width of the area in the second direction where the contact portion of the conductive layer and the light-blocking layer overlap is 30 μm to 100 μm.

16. The display device according to claim 1, wherein, Each of the plurality of pixels includes a light-emitting diode. The light-emitting diode includes a pixel electrode on the pixel circuit layer, an emitting layer on the pixel electrode, and a counter electrode on the emitting layer. The conductive overlay and the pixel electrode are on the same layer.

17. The display device according to claim 16, wherein, The counter electrode extends from the display area to the peripheral area to overlap with at least a portion of the conductive overlay layer.

18. The display device according to claim 17, wherein, The counter electrode overlaps with a portion of the conductive layer but not with the light-blocking layer.

19. An electronic device comprising: The display device according to any one of claims 1 to 18 is configured to display an image; The memory is configured to store applications. as well as The processor is configured to execute the application and transmit image data signals and / or input control signals to the display device.

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