Display panel and display device

Abstract

The present disclosure provides a display panel and a display device, and relates to the technical field of display, comprising a substrate, a first power supply wiring layer located on one side of the substrate, and a data wiring layer located on the side of the first power supply wiring layer away from the substrate, wherein the first power supply wiring layer comprises a plurality of first power supply wiring portions arranged along a first direction and extending along a second direction, and the first direction and the second direction intersect; on the first power supply wiring layer, adjacent first power supply wiring portions are spaced apart by a break and are not connected to each other; the data wiring layer comprises a plurality of data lines arranged along the first direction and extending along the second direction; and along the thickness direction of the display panel, the orthographic projection of at least part of the data lines on the substrate overlaps the orthographic projection of the break on the substrate. In this way, the crosstalk problem between signals can be reduced, and the display effect can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] As display technology continues to evolve towards higher resolution, higher refresh rates, and narrower bezels, display panels capable of precise image quality control have become the mainstream choice for smartphones, wearable devices, and high-end display terminals. To achieve this precise image quality control, each pixel of the display panel is driven by a complex thin-film transistor circuit. With users' increasing demands for image uniformity and color accuracy, the signal stability of the pixel circuits has become a core indicator for measuring display quality.

[0003] However, when displaying specific image content, existing display panels may exhibit abnormal bright or dark lines or color deviations due to crosstalk issues between signals. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a display panel and display device, which aim to reduce crosstalk between signals and improve display performance.

[0005] In a first aspect, this disclosure provides a display panel, including a substrate, a first power trace layer located on one side of the substrate, and a data trace layer located on the side of the first power trace layer facing away from the substrate. The first power trace layer includes a plurality of first power trace portions arranged along a first direction and extending along a second direction, the first direction and the second direction intersecting each other. In the first power trace layer, adjacent first power trace portions are spaced apart by a break and are not connected to each other. The data trace layer includes a plurality of data lines arranged along the first direction and extending along the second direction. In the thickness direction of the display panel, at least a portion of the data lines have their orthographic projections on the substrate overlapping with the orthographic projections of the breaks on the substrate.

[0006] Secondly, based on the same inventive concept, this disclosure also provides a display device, including the display panel provided in the first aspect of this disclosure.

[0007] The technical solution provided in this disclosure has the following advantages compared with the prior art: This disclosure physically cuts off the path for lateral charge flow by creating a break in the first power trace layer, confining the disturbance signal to the current column or a local area. Furthermore, along the thickness direction of the display panel, the projection of at least a portion of the data lines overlaps with the break, meaning that in the region where the voltage jump of the data line is most severe, the metal area directly beneath it is reduced or disconnected. This effectively reduces the parasitic capacitance between the data lines and the first power trace layer, thereby effectively weakening the noise energy coupled into the first power trace layer.

[0008] Furthermore, this disclosure, through the break design of the first power trace layer, ensures that the first power traces between each column are not connected to each other. The pixel power environment corresponding to each column of the first power trace is relatively independent and uniform. The potential fluctuation caused by the jump of a data signal in a certain row is confined within a specific vertical trace and will not affect other pixels in the same row. This reduces the mutual interference between pixel circuits corresponding to different first power traces caused by dynamic screen switching, thereby effectively reducing or avoiding the problem of potential differences at key nodes of pixel circuits. When the display panel displays high-contrast images (such as black background white images), there will be no bright or dark lines caused by the lateral flow of charge, which is beneficial to improving the grayscale accuracy of the overall image. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0010] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 The diagram shown is a schematic diagram of a pixel circuit in a display panel provided in an embodiment of this disclosure; Figure 2 The diagram shown is a planar schematic of a metal layer electrically connected to the first power supply trace. Figure 3 The diagram shown illustrates the relative positions of pixel circuits, data lines, and light-emitting elements in a display panel provided in this embodiment of the present disclosure. Figure 4 The diagram shows the effect of the signal transitions of the first and second data lines on the signals of the first power trace and the metal layer. Figure 5 The figure shown is a plan view of a display panel provided in an embodiment of this disclosure; Figure 6 The diagram shown is a schematic diagram of a film layer of a display panel provided in an embodiment of this disclosure; Figure 7 The figure shown is a planar schematic diagram of a first power supply trace layer in a display panel provided in an embodiment of this disclosure; Figure 8 The diagram shows a relative positional relationship between the data line and the first power supply trace. Figure 9The figure shown is a planar schematic diagram of a second power supply trace layer in a display panel provided in an embodiment of this disclosure; Figure 10 The diagram shows a connection schematic of the first power supply trace and the second power supply trace. Figure 11 The figure shown is a planar schematic diagram of a first repeating unit provided in an embodiment of this disclosure; Figure 12 The diagram shown illustrates the relative positional relationship between multiple pixel circuits and the first power supply trace in a display panel provided in an embodiment of this disclosure. Figure 13 The diagram shown illustrates another relative positional relationship between multiple pixel circuits and the first power supply trace in a display panel provided in this embodiment of the present disclosure. Figure 14 The diagram shown illustrates a relative positional relationship between the first power supply trace and the bonding area provided in an embodiment of this disclosure. Figure 15 The diagram shown illustrates the relative positional relationship between the first power supply trace and the control signal line provided in an embodiment of this disclosure. Figure 16 The diagram shown illustrates the relative positional relationship between the first power supply trace and the light-emitting element in a display panel provided in this embodiment. Figure 17 The diagram shown illustrates the relative positions of the first power supply trace, the light-emitting element, and the data line in a display panel provided in an embodiment of this disclosure. Figure 18 The figure shown is another planar schematic diagram of the first power supply trace layer in the display panel provided in the embodiment of this disclosure; Figure 19 The diagram shown illustrates the relative positional relationship between the first power trace layer and the data line in a display panel provided in this embodiment. Figure 20 The diagram shown is a planar structural schematic of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0012] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0013] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0014] Figure 1The diagram shows a schematic of a pixel circuit in a display panel according to an embodiment of this disclosure. The pixel circuit 41 is electrically connected to the light-emitting element D and is used to drive the light-emitting element D to emit light. This embodiment uses a pixel circuit 41 comprising seven transistors (T0~T6) and a storage capacitor C0 as an example for illustration. However, this disclosure is not limited to this. In some other embodiments of this disclosure, the pixel circuit 41 may also include other numbers of transistors and storage capacitors, and this disclosure does not limit the type of transistors. Transistor T0 is a driving transistor, and the storage capacitor C0 plays a crucial role in maintaining the gate potential of the driving transistor and ensuring the stability of the light emission of the light-emitting element D. According to the circuit design, one electrode of the storage capacitor C0 is usually directly connected to the first power supply line PVDD to receive the first power supply voltage signal. While this structure helps stabilize the potential, it also establishes a physical signal coupling path. That is, the storage capacitor C0 is connected between the first power supply line PVDD and the gate of the driving transistor T0 in the circuit. The function of the storage capacitor C0 is to utilize the DC stability of the first power supply line PVDD to maintain the potential of the gate of the driving transistor T0. However, from the perspective of AC signals, this is equivalent to forming a signal coupling path between the first power supply trace PVDD and the gate of the driving transistor T0. When the first power supply trace PVDD generates potential fluctuations, it will be directly conducted to the gate of the driving transistor T0 through the storage capacitor C0, thereby interfering with the gate potential of the driving transistor T0.

[0015] Specifically, in display panels, the voltage stability of the first power supply trace (PVDD) is crucial to ensure stable light emission from a large number of light-emitting elements. In actual array substrate manufacturing processes, to effectively reduce the cross-region impedance of the PVDD and minimize voltage drop, designers typically utilize multiple metal layers within the display area for electrical interconnection, collectively carrying the first power supply voltage signal. Some specific metal layers employ a fully planar interconnection or a dense grid design in their spatial layout; for example, please refer to... Figure 2 , Figure 2 The diagram shows a planar schematic of a metal layer PVDD0 electrically connected to the first power trace PVDD. When the first power trace PVDD is electrically connected to the metal layer PVDD0, an extremely low impedance voltage feedback network can be constructed, making the potential of the first power voltage signal in the entire panel tend to be uniform.

[0016] However, when one end of the storage capacitor C0 in the pixel circuit is connected to a critical node of the driving transistor and the other end is connected to the first power supply trace PVDD, it is also connected to the aforementioned fully planar or densely gridded metal layer PVDD0. During the display scanning phase, when the data line DATA writes signals, the data voltage will undergo drastic instantaneous jumps according to the grayscale requirements. Specifically, when the data line DATA and the first power supply trace PVDD are set on the same layer or the distance between their film layers is small, there will be a coupling capacitance between them. During data writing, the dynamic voltage change on the data line DATA may be transmitted to the first power supply trace PVDD through the aforementioned coupling capacitance. Since the first power supply trace PVDD is connected to a critical node inside the pixel circuit, such as the gate of the driving transistor T0, through the storage capacitor C0, the aforementioned dynamic voltage change will be further coupled to the gate of the driving transistor T0 through the storage capacitor C0, causing the gate potential of the driving transistor T0 to jump drastically and synchronously.

[0017] Furthermore, since the metal layer where the first power trace PVDD is located is electrically connected to the metal layer PVDD0 with a fully planar connection or a densely gridded design, and the resistivity of the metal layer PVDD0 is similar in the horizontal and vertical directions, the coupling disturbance generated by the local pixel will be rapidly propagated to the neighboring pixel along the unobstructed horizontal metal path. Figure 3 The diagram shown is a relative positional relationship diagram of pixel circuits, data lines and light-emitting elements in a display panel provided in an embodiment of this disclosure. Optionally, the light-emitting element D includes a green light-emitting element G, a red light-emitting element R and a blue light-emitting element B. The red light-emitting element R and the blue light-emitting element B located in the same column are connected to the same first data line DATA(RB), and the green light-emitting element G located in the same column is connected to the same second data line DATA(G). Figure 4 The diagram illustrates the impact of signal transitions on the first data line DATA(RB) and the second data line DATA(G) on the signals of the first power trace PVDD and the metal layer PVDD0. Figure 4 The dashed lines in the diagram represent the ideal signals in the first power supply trace PVDD and the metal layer PVDD0. The solid lines corresponding to the dashed lines represent the actual signal conditions. It is evident that signal transitions in both the first data line DATA(RB) and the second data line DATA(G) affect the signals in the first power supply trace PVDD and the metal layer PVDD0, causing the first power supply signal to become non-constant. Furthermore, during the signal potential's attempt to stabilize, fluctuations can interfere with the potentials of critical nodes in other pixel circuits within the same row, such as the gate potential of the driving transistor T0. Due to slight differences in the degree of disturbance and recovery time at critical nodes in each pixel circuit, the potentials of the driving transistors ultimately written into different pixel circuits deviate, potentially resulting in abnormal bright or dark lines or color deviations on the display panel, affecting the display effect.

[0018] To solve the above-mentioned technical problems, this disclosure provides a display panel 100. Figure 5 The image shown is a plan view of a display panel provided in an embodiment of this disclosure. Figure 6 The diagram shown is a schematic diagram of a film layer of a display panel provided in an embodiment of this disclosure. Figure 7 The figure shown is a plan view of the first power supply layer 10 in a display panel provided in an embodiment of this disclosure. Figure 8 The diagram shown illustrates the relative positional relationship between the data line DATA and the first power supply trace 11. Please refer to it. Figures 5 to 8 The display panel 100 provided in this embodiment includes a substrate 00, a first power trace layer 10 located on one side of the substrate 00, and a data trace layer DA located on the side of the first power trace layer 10 away from the substrate 00. The first power trace layer 10 includes a plurality of first power trace portions 11 arranged along a first direction D1 and extending along a second direction D2, and the first direction D1 and the second direction D2 intersect. In the first power trace layer 10, adjacent first power trace portions 11 are spaced apart by a break K0 and are not connected to each other. The data trace layer DA includes a plurality of data lines DATA arranged along the first direction D1 and extending along the second direction D2. In the thickness direction of the display panel, at least a portion of the data lines DATA have their orthographic projections on the substrate 00 overlapping with the orthographic projections of the break K0 on the substrate 00.

[0019] Optionally, the display panel provided in this embodiment can be a display panel using organic light-emitting diode (OLED) display technology, i.e., an OLED (Organic Light-Emitting Diode) display panel, for example, please refer to... Figure 6 The basic structure of the light-emitting element D in an OLED display panel includes an anode 301, a light-emitting material layer 302, and a cathode 303. When a suitable voltage is supplied, holes generated in the anode 301 and electrons generated in the cathode 303 combine in the light-emitting material layer 302 to produce light. Compared to LCD displays, OLED display panels have high visibility and high brightness, and are also more energy-efficient, lighter, and thinner.

[0020] by Figure 6Taking a display panel as an example, the display panel includes a substrate 00, a driving layer 40, and a display layer 20. The display layer 20 includes a pixel definition layer 19, which defines multiple pixel openings. A light-emitting material layer 302 is located at least within the pixel openings along a direction perpendicular to the substrate 00. An anode 301 and a cathode 303 are located on opposite sides of the light-emitting material layer 302, with the anode 301 located on the side of the cathode 303 facing the substrate 00. Optionally, an encapsulation layer 50 is provided on the side of the cathode 303 away from the anode 301. Optionally, the encapsulation layer 50 includes a first inorganic layer 51, an organic layer 52, and a second inorganic layer 53 stacked together. A pixel circuit 41 is provided in the driving layer 40 to provide a driving voltage to the light-emitting element D, driving the light-emitting element D to emit light. The pixel circuit 41 includes multiple transistors T. The specific structure of the pixel circuit 41 can be found in [reference needed]. Figure 1 However, not based on Figure 1 For the limited purposes, optionally, in the driving layer 40, the gate of transistor T is disposed in the first metal layer M1, and the source and drain of transistor T are disposed in the second metal layer M2. The display panel also includes an active layer 01 disposed on the side of the first metal layer M1 facing the substrate 00 and an auxiliary metal layer M0 disposed on the side of the active layer 01 facing the substrate 00. It should be noted that the display panel may include transistors with a dual-gate structure. In this case, one gate of the transistor may be located in the first metal layer M1, and the other gate may be located in the auxiliary metal layer M0. Along the direction perpendicular to the plane where the substrate 00 is located, both the first metal layer M1 and the auxiliary metal layer M0 overlap with the active layer 01. The auxiliary metal layer M0 also has a light-shielding function to prevent light from affecting the active layer 01. Optionally, a capacitor metal layer MC is further included between the first metal layer M1 and the second metal layer M2. The capacitor metal layer MC can form a capacitor structure with the first metal layer M1 or with the second metal layer M2. The accompanying drawings only illustrate the example of the capacitor metal layer MC forming a capacitor structure with the first metal layer M1. Optionally, a third metal layer M3 is also included on the side of the second metal layer M2 away from the substrate 00. Another metal layer can be provided on the side of the third metal layer M3 away from the substrate 00 as needed. This disclosure does not make specific limitations in this regard. Signal lines can be laid in each metal layer.

[0021] Optionally, the first power trace layer 10 mentioned in the embodiments of this disclosure may be disposed on the same layer as any of the aforementioned metal layers. Figure 6 This embodiment is illustrated using the example of the first power supply layer 10 and the auxiliary metal layer M0 being on the same layer. Optionally, the data layer DA mentioned in this embodiment may be disposed on the same layer as the aforementioned second metal layer M2 or third metal layer M3. Figure 6 The example shown is based on the configuration of the data trace layer DA and the second metal layer M2 being on the same layer.

[0022] Please refer to Figure 7and Figure 8 In this disclosure, the first power trace layer 10 adopts a structure of multiple unconnected first power trace portions 11 arranged along a first direction D1. Adjacent first power trace portions 11 are isolated by a break K0 along the first direction D1, preventing them from connecting. The data line DATA overlaps with the break K0 of the first power trace layer 10 in the thickness direction. This means that the first power trace layer 10 below the data line DATA, which is most prone to coupling interference, is physically severed laterally. It should be noted that the first power trace layer 10 mentioned in this embodiment refers to any metal layer in the display panel that transmits the first power voltage signal. When there are multiple metal layers transmitting the first power voltage signal, each layer must satisfy the characteristics of the break included in the first power trace layer 10 mentioned in this embodiment. The break K0 mentioned in this embodiment refers to the area corresponding to the interval between two adjacent first power trace portions 11.

[0023] In related technologies, after a data signal is coupled to the metal layer corresponding to the first power trace via a coupling capacitor, the charge will rapidly spread to the entire row of pixels along the low-impedance lateral metal path because the metal in the part of the metal layer electrically connected to the first power trace is laterally connected. However, in this embodiment, by setting a break K0 on the first power trace layer 10, the path for lateral charge flow is physically cut off, limiting the disturbance signal to the current column or a local area. Furthermore, considering that if the data line DATA overlaps with the metal of the first power trace layer 10, a coupling capacitor may also be generated between them, and the larger the overlap area, the larger the coupling capacitor may be, and the greater the impact of the data line DATA's transition on the first power trace layer 10 will be. Therefore, in this application, please refer to... Figure 8 Along the thickness direction of the display panel, at least part of the projection of the data line DATA overlaps with the break point K0, which means that the metal area of ​​the first power trace layer 10 directly below the data line DATA will be reduced. This can effectively reduce the coupling capacitance between the data line DATA and the first power trace layer 10, thereby helping to reduce the noise energy coupled into the first power trace layer 10 when the data signal changes.

[0024] Therefore, this disclosure, through the design of the break point K0 in the first power trace layer 10, ensures that the first power traces 11 between each column are not connected to each other. The pixel power environment corresponding to each column of the first power trace 11 is relatively independent and uniform. The potential fluctuation caused by the jump of a certain row of data signals is confined within a specific vertical trace and will not affect other pixels in the same row. This reduces the mutual interference between the pixel circuits 41 corresponding to different first power traces 11 due to dynamic screen switching, thereby effectively reducing or avoiding the problem of potential differences in key nodes of the pixel circuits 41. When the display panel displays high-contrast images (such as black background white images), there will be no bright or dark lines caused by the lateral flow of charge, which is beneficial to improving the grayscale accuracy of the overall image.

[0025] Please continue to refer to this. Figure 7 and Figure 8 In one optional embodiment of this disclosure, a plurality of first power supply traces 11 are configured to receive the same first power supply signal. Optionally, the first power supply signal is a positive power supply signal supplied to the pixel circuit.

[0026] In this embodiment, although the multiple first power supply traces 11 are disconnected from each other, they are all ultimately connected to the same power input terminal and receive the same first power signal. This means that under static or steady-state conditions, the power potential at all points on the screen remains equal, ensuring the basic uniformity of display brightness. Although the multiple first power supply traces 11 receive the same first power signal, there is a break K0 between adjacent first power supply traces 11, and they are isolated from each other at the AC signal or transient pulse level. When a data signal in a certain column changes, and the resulting disturbance current attempts to spread laterally, the further conduction of the disturbance current will be directly interrupted by the break K0. Moreover, in this disclosure, although adjacent first power supply traces 11 also receive the same signal, there is no low-impedance path between them in the first power supply trace layer 10, and the noise current cannot directly cross the break K0, thus being forcibly locked within the specific column that generates interference, effectively protecting other pixels in the same row.

[0027] Figure 9 The figure shown is a plan view of a second power supply trace layer in a display panel provided in an embodiment of this disclosure. Figure 10 The diagram shows a connection schematic of the first power trace 11 and the second power trace 12. This embodiment uses the example where the second power trace layer 70 and the data trace layer DA are both located on the second metal layer M2, and the first power trace 11 is located on the auxiliary metal layer M0. However, this is not a limitation. Please refer to... Figure 6 and Figure 9In one optional embodiment of this disclosure, the display panel further includes a second power trace layer 70, which is located on the side of the first power trace layer 10 away from the substrate 00. The second power trace layer 70 includes a plurality of second power trace portions 12, and the first power trace portion 11 and the second power trace portion 12 are electrically connected through a connection hole LK.

[0028] In this embodiment, the first power trace portion 11 in the first power trace layer 10 maintains a horizontally discontinuous strip structure, for example, please refer to Figure 7 and Figure 8 The second power trace layer 70 is further away from the substrate 00 than the first power trace layer 10. The sheet resistance of the second power trace layer 70 can be less than that of the first power trace layer 10. For example, the thickness of the second power trace layer 70 is greater than that of the first power trace layer 10. The second power trace layer 70 can serve as the main transmission channel for the first power signal, while the first power trace layer 10 can serve as an auxiliary channel.

[0029] When the first power trace 11 and the second power trace 12 are electrically connected through vias, the first power trace 11, which has a higher resistance, is connected in parallel across the entire screen with the second power trace layer 70, which has a higher conductivity. When a data voltage jump occurs and is coupled to the first power trace 11 or the second power trace 12 (for example, a coupling capacitor formed by the data line being adjacent to the first power trace 11 is coupled to the first power trace 11, or a coupling capacitor formed by the data line being overlapping with the overlapping second power trace 12 is coupled to the second power trace 12), since the first power trace 11 is laterally disconnected from each other and the second power trace 12 is also laterally disconnected from each other, the disturbance charge generated by the data voltage jump will be safely confined to a local area. Moreover, since the first power trace 11 and the second power trace 12 are connected in parallel through the connection hole LK, the common impedance formed by the two is low, so the aforementioned disturbance charge can be quickly released through the parallel network structure formed by the first power trace 11 and the second power trace 12. This greatly accelerates the recovery speed of DC signals and effectively solves the problem of slow recovery caused by the high resistance of the first power trace layer 10 (for example, the thickness of the first power trace portion 11 in the first power trace layer 10 is small), thereby helping to reduce or eliminate lateral line crosstalk.

[0030] In this disclosure, although the first power trace layer 10 is horizontally cut off (divided into independent first power trace sections 11), and the second power trace layer 70 is also horizontally cut off (divided into independent second power trace sections 12), multiple second power trace sections 12 can be electrically connected to each other via a power bus and receive power uniformly in the non-display area of ​​the display panel. Furthermore, when the impedance of the second power trace layer 70 is low, it can construct a stable power supply architecture across the entire screen. Within the display area, the first power signal can be transmitted vertically with low impedance along each low-impedance second power trace section 12. Moreover, since the first power trace section 11 and the second power trace section 12 are connected via a connection hole LK, the first power signal can also be evenly distributed to each first power trace section 11. This ensures that the first power supply voltage of each pixel on the entire screen remains consistent under static image conditions, effectively reducing voltage drop (IR Drop) in large-size or high-brightness displays and guaranteeing the basic uniformity of the display panel's brightness.

[0031] Please continue to refer to this. Figure 9 and Figure 10 In one optional embodiment of this disclosure, the connection hole LK is located at two opposite ends of the second power supply trace portion 12 along the second direction D2.

[0032] In this disclosure, the second power trace 12 extends along the second direction D2. In this elongated structure, by punching holes at both ends to connect to the first power trace 11, the first power trace layer 10 and the second power trace layer 70 can electrically converge at the periphery of the display area without needing to punch holes in the corresponding area of ​​the display area. Since there is no need to provide connection holes in each pixel area inside the display area, it is beneficial to simplify the semiconductor manufacturing process within the display area.

[0033] When data signals undergo drastic dynamic changes, the resulting disturbance charges can cause dynamic disturbances in the local potential of the current column's power supply structure. If the aforementioned connection hole is provided within the display area, the locally generated disturbance charges will be transmitted and spread between the first power supply layer 10 and the second power supply layer 70 in the display area, easily exacerbating potential fluctuations on the low-impedance second power supply layer 70. However, in this embodiment, by moving the connection hole LK to both ends of the first power supply section 11, the connection hole LK can be located in the non-display area. Within the display area, the two metal layers, the first power supply layer 10 and the second power supply layer 70, are physically decoupled (isolated). The locally generated coupling noise is locked within the independent vertical strip corresponding to the power supply section of the current column and cannot diffuse to the laterally adjacent pixel circuits. Furthermore, since the connection hole LK is located in the non-display area, the disturbance charge corresponding to the power supply trace of the current column can be conducted to the non-display area along the vertical path, and further conducted to the power bus position in the non-display area. The power bus can dilute the disturbance charge, so that the dynamic disturbance cannot directly affect the adjacent pixels laterally inside the display area, thereby reducing the lateral line crosstalk to a lower level.

[0034] Furthermore, if holes are drilled only at the top or bottom, the potential recovery speed at the far end (such as the center area of ​​the panel) will be significantly slowed due to the large sheet resistance and thin film thickness of the first power trace layer 10. This solution involves drilling holes at both the top and bottom ends of the second power trace section 12, forming a closed-loop network of bidirectional power supply / bidirectional current leakage for each vertical first power trace section 11. When the DC signal is disturbed, the disturbed charge can be rapidly released simultaneously in both the top and bottom directions, and the power supply charge can also be injected simultaneously from both the top and bottom sides. This significantly improves the signal recovery speed, effectively solving the problem of slow signal recovery caused by the high resistance of the second power trace layer 70 itself, and ensuring the uniformity of the full-screen brightness under steady-state conditions (reducing IR drop).

[0035] Furthermore, considering that in high-pixel-density display panels or those with under-display cameras, any metal via within the display area occupies valuable pixel space and causes light scattering and obstruction, thereby reducing the panel's aperture ratio and transmittance, this embodiment moves all vias between the first power trace 11 and the second power trace 12 to both ends of the vertical axis (e.g., in the non-display area surrounding the display area). This eliminates a large number of densely packed holes within the display area, maximizing the release of light-transmitting area within the pixels and significantly improving the product's transmittance.

[0036] Please continue to refer to this. Figure 7 In one optional embodiment of this disclosure, the minimum width of the fracture K0 along the first direction D1 is W, where W ≥ 3 μm.

[0037] In the thin-film transistor array manufacturing process, the first power supply layer 10 is typically formed by exposure and development of metals (such as Al, Cu, Mo, etc.) through photolithography and etching processes. By setting the minimum width of the break point K0, within the effective display area of ​​the entire display panel, regardless of any process fluctuations (such as excessively fast or insufficient etching), the distance between the narrowest points of all breaks K0 used to cut the lateral connections must be at least 3 μm or more.

[0038] In actual semiconductor mass production, due to process defects such as uneven metal layer etching, photoresist residue, or metal stripping, if the break point K0 is designed to be too narrow (e.g., less than 3μm), metal residue is very likely to occur, resulting in a tiny, invisible metal bridge between the two first power supply traces 11 that should have been disconnected. Setting W ≥ 3μm provides sufficient safety tolerance for the process. Even under the most unfavorable etching deviations, it ensures that the lateral metal is completely severed, which helps eliminate the possibility of solution failure due to local micro-short circuits and helps ensure the absolute effectiveness of lateral isolation.

[0039] Furthermore, when the width of the break K0 is too small (e.g., less than 3μm), even if two adjacent first power supply traces 11 are disconnected, when a data voltage jump causes voltage fluctuations in the first power supply signal, a large parasitic capacitance will still form on the metal surfaces at both ends of the break K0. The smaller the width of the break K0, the larger the parasitic capacitance will be. High-frequency data signal dynamic disturbance noise can still easily penetrate the break K0 and affect adjacent pixels, causing lateral crosstalk. Therefore, when W≥3μm, by increasing the physical distance between the metal at both ends, the parasitic capacitance and edge coupling effect between the two layers of first power supply traces 11 are attenuated to a negligible level. This truly builds a high-impedance isolation structure at the electrical dynamic (AC) level, forcibly locking the dynamic noise current and preventing it from crossing laterally, thereby minimizing lateral crosstalk.

[0040] Optionally, the width W of the break K0 is less than 10μm, which helps to ensure the effective area of ​​the first power supply trace 11 and avoids the problem of large voltage drop due to the small effective area of ​​the first power supply trace 11.

[0041] Figure 11 The diagram shown is a plan view of the first repeating unit 111 provided in an embodiment of this disclosure. Please refer to it. Figure 11In one optional embodiment of this disclosure, the first power trace portion 11 includes a plurality of repeating units 110 arranged and connected along the second direction D2. Each repeating unit 110 includes a first part B1 and a second part B2 located on one side of the first part B1 and connected to it along the second direction D2. The first part B1 extends along the first direction D1, and the second part B2 is also connected to the first part B1 in an adjacent repeating unit 110. The break point K0 includes a first break point K1. In two adjacent first power trace portions 11 along the first direction D1, the first break point K1 is located between adjacent first parts B1 along the first direction D1, and the width of the first break point K1 is W1. The display panel includes a plurality of pixel circuits 41 arranged in an array. The width of a single pixel circuit 41 along the first direction D1 is W0, where 3μm ≤ W1 ≤ W0. The second part B2 can be an irregularly shaped structure to increase the effective area of ​​the first power trace portion 11. Optionally, the span of one repeating unit 110 along the first direction D1 can correspond to two pixel circuits 41. To clearly illustrate the structure of the repeating unit 110, Figure 11 The diagram only shows the two pixel circuits 41 corresponding to one repeating unit 110. In fact, each repeating unit 110 has a corresponding pixel circuit 41 in its area.

[0042] In this embodiment, each first power supply trace 11 is formed by connecting multiple repeating units 110 end to end along the second direction D2 (longitudinal). Between two adjacent first power supply traces 11 in the transverse direction, a first break K1 is precisely opened at the opposite position of the two transverse first traces B1. The transverse traces that might have been connected are completely cut off here. The width W1 of the first break K1 must not only meet the minimum process requirement for short circuit prevention (≥3μm), but also be less than or equal to the width W0 of a single pixel circuit 41 along the first direction D1.

[0043] In traditional designs, to reduce impedance, horizontal traces are typically routed across the entire screen. In this solution, while the first B1 still extends horizontally to cover and shield specific nodes within the pixel, a first break K1 is left between adjacent first B1 sections. When a local data signal abruptly couples to the first B1, any noise charge attempting to conduct laterally is directly cut off at the first break K1. This precise truncation at the end of the first B1 completely eliminates the horizontal crosstalk path, minimizing horizontal line crosstalk to the greatest extent possible.

[0044] If the width W1 of the first break K1 exceeds the width W0 of a single pixel circuit 41 along the first direction D1, it means that a large area of ​​the metal layer is missing in the lateral direction. This will cause the overall impedance of the first power supply trace 11 to spike sharply, severely affecting the recovery speed of the DC potential and causing new bright and dark line problems. Setting W1≤W0 ensures that the first part B1 still retains a sufficiently large metal area inside the pixel unit. This ensures the conductivity of the first power supply signal during longitudinal transmission, maintains a high signal transmission speed, and reduces voltage drop. Therefore, in this embodiment, the first break K1 not only serves as electrical isolation but also appropriately releases some light-transmitting space, further improving the overall transmittance of the product without compromising the low-impedance power supply.

[0045] Please continue to refer to this. Figure 11 and combined Figure 8 In one optional embodiment of this disclosure, the break K0 further includes a second break K2. Among two adjacent first power supply traces 11 along the first direction D1, the second break K2 is located between adjacent second portions B2 along the second direction D2. Along the thickness direction of the display panel, the data line DATA overlaps with the second break K2. The width W2 of the second break K2 along the first direction D1 is greater than or equal to the width W1 of the first break K1 along the first direction D1. In this embodiment, the second portion B2 has an irregular structure, and the second break K2 also has an irregular structure, as an example for explanation. When the second break K2 is an irregularly structured break K0, its width W2 along the first direction D1 can be considered as the minimum width of the interval between two adjacent second portions B2 along the first direction D1.

[0046] In this embodiment, the first power supply trace 11 is cascaded from multiple repeating units 110, each containing a first section B1 (extending laterally) and a second section B2. A first break K1 is located between adjacent first sections B1 in the lateral direction (first direction D1), responsible for providing physical blocking in the lateral direction. A second break K2 is located between opposing second sections B2 in the lateral direction. That is, two adjacent second sections B2 are not continuous in their lateral projection; there is a specific gap between them, namely the second break K2. The data line DATA, whose signal transitions are most drastic, overlaps with the second break K2 in its thickness direction. This means that the metal film layer directly beneath the data line DATA is hollowed out or broken here. The width W2 of the second break K2 along the first direction D1 is defined to be greater than or equal to the width W1 of the first break K1. This indicates that in the critical area through which the data line DATA flows, the metal yields more, and the second break K2 is wider.

[0047] Considering that during the display scanning phase, the data voltage undergoes drastic instantaneous jumps based on grayscale requirements, and due to the coupling effect of the storage capacitor, these localized data voltage fluctuations can directly couple to the metal film layer where the first power trace is located. The larger the overlap area between the data line DATA and the underlying power metal layer (first power trace 11), the larger the parasitic capacitance between them, and the stronger the dynamic noise energy coupled into the power layer during voltage jumps. By precisely arranging the data line DATA directly above the second break K2, the area of ​​the power layer metal directly below the data line DATA in the core region where voltage jumps are most severe is significantly reduced. This design physically and topologically greatly reduces the dynamic parasitic capacitance between the data line DATA and the first power trace layer 10. Due to the reduced capacitance, noise energy that could couple into the first power trace layer 10 during data signal jumps is significantly intercepted.

[0048] The data line DATA transmits high-frequency dynamic pulse signals (AC signals). As mentioned earlier, if the break point K0 is too narrow, the AC signal can easily generate cross-current AC coupling through the space plate capacitance. This embodiment limits the lateral width of the second break point K2 to be larger, making the distance between the second part B2 of the adjacent first power trace 11 greater. This dilutes the edge parasitic capacitance between the power traces on both sides of the data line DATA to near zero. With this double protection, not only is the total amount of coupled noise reduced, but the remaining noise is also weakened in its high-frequency AC crossing capability due to the extremely wide second break point K2, and the disturbance signal is confined within the longitudinal path of the current column.

[0049] Within a pixel, the data line DATA already occupies a certain vertical space. This solution creates a wider second break K2 below the data line DATA, effectively reducing the ineffective power metal coverage in the projected area of ​​the data line DATA without reducing the effective vertical conductive area. By overlapping the data line DATA with the wider second break K2 in the thickness direction, this disclosure cleverly creates a metal buffer in the area with the most severe dynamic voltage fluctuations (directly below the data line DATA). By increasing the width of the second break K2, the capacitive coupling path for noise injection from the data line DATA to the power layer is directly reduced. This solution not only achieves a significant reduction in lateral line crosstalk but also improves the panel's transmittance using spatial multiplexing technology.

[0050] Alternatively, please continue to refer to Figure 8 and Figure 11Along the thickness direction of the display panel, at least one data line DATA overlaps with both the first break K1 and the second break K2. In the first power trace layer 10, since there is a first break K1 between the first horizontal part B1 and a second break K2 between the second vertical part B2, these two breaks are aligned or staggered in the horizontal direction, forming a non-metallic gap band extending along the second direction D2 (vertical) on the panel. The data line DATA passes longitudinally along this non-metallic gap band formed by the first break K1 and the second break K2. From the thickness direction of the display panel (top view perspective), the data line DATA is suspended above the first break K1 and the second break K2, and very little metal remains in the first power trace layer 10 below it. When the data line DATA overlaps with both the first break K1 and the second break K2, it means that the metal of the first power trace layer 10 directly below the data line DATA (the most dangerous coupling area) along the flow path of the entire column of pixels is significantly and continuously recessed and hollowed out. This physically eliminates most of the overlap between the data line and the power trace on that layer, achieving an extreme reduction in parasitic capacitance. Because the parasitic capacitance is reduced to its theoretical extreme, the noise energy that can couple into the power network during data voltage transitions is significantly reduced, effectively improving the stability of the first power supply voltage signal.

[0051] Please continue to refer to this. Figure 6 and Figure 11 In one optional embodiment of this disclosure, the display panel further includes an active layer 01. Along the thickness direction of the display panel, the active layer 01 is located between the first power trace layer 10 and the data trace layer DA. The active layer 01 includes a plurality of channels GD. Along the thickness direction of the display panel, a second part B2 overlaps with the channels. The second part B2 is multiplexed as a shielding part of the channel GD.

[0052] by Figure 11 For example, the second part B2 includes multiple block structures, and the area corresponding to each block structure can be regarded as the area where the channel on the active layer is located. The channel of the active layer is extremely sensitive to light. If stray light generated by ambient light refraction and substrate polarization directly shines on the channel, photogenerated carriers will be generated inside the semiconductor. This will cause a serious drift in the critical threshold voltage of the transistor, generating uncontrollable static leakage current, making it impossible to maintain the potential of the storage capacitor, directly leading to unstable pixel light emission, screen flickering, or uneven brightness. In this embodiment, the second part B2 in the first power supply layer 10 is a metal structure with excellent light shielding properties. It is reused as a shielding part placed directly below the channel, like a natural protective part, blocking stray light from below (on the substrate 00 side). This ensures that the channel is always in a backlit dark room environment, eliminating photogenerated leakage current and greatly improving the electrical stability of the transistor.

[0053] Considering the potential for complex electrostatic residues or dynamic electric field interference from nearby traces on one side of the substrate, without shielding, these stray electric fields would affect the transistor from below the channel, producing the so-called back-gate effect and degrading the transistor bias state. The second part, B2, carries the first power signal, which is an extremely stable DC constant potential signal. Placing a metal block with a stable DC constant potential below the channel creates an electrostatic shield. This absorbs and dissipates dynamic electric field interference from the substrate's 00 direction, maintaining the channel's potential environment in an absolutely pure steady state. This ensures that the driving transistor can accurately and without distortion control the luminous current, improving the grayscale accuracy of the image.

[0054] In traditional technologies, a separate shielding metal layer needs to be fabricated and connected to a potential wire to stabilize the channel. This not only increases the number of exposure and etching processes (increasing production costs and defect rates) but also increases metal line density, severely compressing the light-transmitting space inside the pixel (reducing aperture ratio). This disclosure directly integrates the second part B2 of the first power supply trace 11 with the shielding metal layer. Without adding any additional semiconductor processes, it effectively solves the two major pain points of power delivery and channel shielding. It simplifies the ineffective metal overlap inside the pixel, thereby freeing up more light-transmitting channels and further increasing the aperture ratio and screen transmittance of the display panel.

[0055] Figure 12 The diagram shown illustrates the relative positions of multiple pixel circuits 41 and the first power supply trace 11 in a display panel provided in this embodiment. Please refer to the diagram. Figure 12 In one optional embodiment of this disclosure, the display panel includes a plurality of pixel circuits 41 arranged in an array. Along the thickness direction of the display panel, a first power supply trace 11 corresponds to N columns of the pixel circuits. That is, N columns of pixel circuits 41 are included between two adjacent first breaks K1 along the first direction D1, where N ≥ 2. It should be noted that... Figure 12 The example is illustrated using N=2 as an example only, but it is not limited to this.

[0056] Thus, the first power supply traces 11 beneath each consecutive N columns of pixel circuits 41 are interconnected in the lateral direction (first direction D1) and jointly carry the first power supply voltage signal. These N columns of pixel circuits together constitute a basic power supply loop unit. A first break K1 appears only in the lateral direction every N columns of pixel circuits 41. This means that different loop units (each group of N columns of pixel circuits) are completely physically disconnected and electrically isolated in the first power supply trace layer 10.

[0057] Although N columns of pixels are allowed to be connected horizontally in this embodiment, the maximum distance of noise propagation in the lateral direction is forcibly limited to the width of the N-column pixel circuit 41 due to the presence of the periodic break K0. When the disturbance current attempts to spread to the entire screen, it will be directly locked by the break K0 at most N columns of pixels. As long as the value of N is controlled within a reasonable range (e.g., the spatial distance is extremely small, satisfying the limit of human eye spatial resolution), the slight brightness difference caused by this weak local potential fluctuation in the lateral direction will be completely within the visual inertia range of human eye, thereby completely eliminating lateral line crosstalk in perception. When the display panel displays high-contrast images such as black backgrounds and white blocks, abnormal bright and dark lines will no longer appear on the left and right sides.

[0058] Considering that while N=1 provides the highest isolation, it also leads to excessively sparse M0 metal mesh, causing its longitudinal / lateral resistance to spike, and local charges to recover very slowly after being disturbed because they cannot mutually support each other, resulting in more severe potential write deviations. Therefore, N≥2 is set to maintain a certain density of low-impedance lateral metal paths at the microscopic level, constructing a small-scale low-impedance voltage compensation network. When a column of pixels is disturbed by data voltage jumps, adjacent columns of pixels can use this laterally connected metal layer to share and quickly replenish the charge, greatly accelerating the potential recovery speed of DC signals and effectively compensating for the slow recovery caused by the high resistance of the first power trace layer.

[0059] Please continue to refer to this. Figure 12 In one optional embodiment of this disclosure, the number of columns of pixel circuits corresponding to different first power supply traces 11 is the same along the thickness direction of the display panel. This embodiment is described using the example of each first power supply trace 11 corresponding to two columns of pixel circuits, but it is not limited thereto.

[0060] In traditional technologies, when the power trace layer employs a full-screen mesh or long-line strong connection design, coupling noise can spread unimpeded laterally to the entire row (full screen) when data voltage experiences drastic jumps. The solution provided in this embodiment introduces a break K0 between adjacent first power trace sections 11, and each first power trace section 11 corresponds to the same number of pixel circuits, physically dividing the horizontally continuous metal layer into discrete, periodically repeating loop units. The maximum lateral diffusion distance of locally generated coupling potential fluctuations is rigidly locked within the physical width corresponding to the first power trace section 11. As long as the span of the first power trace section 11 is controlled within a very small range, this slight local brightness deviation is completely below the spatial resolution limit of the human eye, thus completely eliminating lateral line crosstalk perceptually.

[0061] However, if each column of pixels were completely horizontally disconnected, the metal network would become extremely sparse. Disturbances in localized charge would make it difficult to quickly replenish from external sources, slowing down potential recovery and potentially worsening image quality during dynamic scene transitions. This embodiment introduces a break K0 in the first power trace layer 10, ensuring that the first power trace 11 corresponds to at least two columns of pixel circuits. This means that a small-scale horizontal low-impedance path is still maintained within the area corresponding to a single first power trace 11. When a data line DATA corresponding to the first power trace 11 changes, neighboring pixels can share the charge through the connected horizontal path, rapidly diverting and replenishing it.

[0062] Furthermore, if different power supply traces 11 correspond to different numbers of pixel circuits, slight asymmetric differences may occur in the parasitic impedance, charge release path, and steady-state voltage drop faced by pixels in different columns. The human eye is extremely sensitive to such periodic changes, which can easily lead to striped display unevenness. This embodiment uses different power supply traces 11 corresponding to the same number of pixel circuits to ensure that the impedance network topology of all pixels in the horizontal direction is basically symmetrical and uniform. The potential decay constant of each pixel after being affected by data voltage jumps is basically the same, thereby ensuring high uniformity of display brightness and improving the grayscale accuracy of the overall image.

[0063] In mainstream OLED pixel arrangements, for example Figure 3 In the pixel arrangement structure shown, the light-emitting elements are arranged in 2 or 4 columns of pixel circuits as a periodically repeating basic color display group. Figure 3 In this embodiment, one pixel column includes alternating red light-emitting elements R and blue light-emitting elements B, while the other pixel column includes only green light-emitting elements G. These two pixel columns are arranged alternately along the first direction D1. When a first power supply trace 11 corresponds to two pixel circuit columns, it can achieve effective physical spatial overlap with the pixel arrangement and anode pattern of the upper layer. This means that the power supply electric field and parasitic capacitance environment under sub-pixels of the same color are the same or similar, effectively avoiding the problem of local color shift or decreased color accuracy caused by asymmetry in the power supply layer structure.

[0064] Figure 13 The diagram shown illustrates another relative positional relationship between the plurality of pixel circuits 41 and the first power supply trace 11 in the display panel provided in this embodiment. Please refer to the diagram. Figure 13 In one optional embodiment of this disclosure, the number of pixel circuit columns corresponding to at least two first power supply traces 11 is different along the thickness direction of the display panel. This embodiment is described using the example of at least one first power supply trace 11 corresponding to 2 columns of pixel circuits and at least one first power supply trace corresponding to 4 columns of pixel circuits, but it is not limited thereto.

[0065] Considering that if the number of columns of pixel circuits corresponding to different first power supply traces 11 is exactly the same, the number of columns of pixel circuits contained between any two adjacent breaks is also exactly the same. Under high PPI dense grid conditions, if the metal break K0 overlaps with the upper optical structure such as the polarizer at a specific frequency, moiré fringes are easily formed optically. This embodiment adopts a design with at least two first power supply traces 11 corresponding to different numbers of pixel circuit columns, so that the number of columns of pixel circuits contained between adjacent breaks K0 is not exactly the same. This breaks the absolute single high-frequency pattern of the transverse physical gaps of the first power supply trace layer 10 in space, achieving a spatial demodulation effect, which helps to weaken or avoid the formation of moiré fringes.

[0066] Furthermore, within a single scan cycle, data signals may not be written to all pixel circuits 41 of that row simultaneously. This means that the timing, amplitude, and frequency of data voltage transitions may differ between different pixel columns. When the number of pixel circuits 41 between two adjacent first breaks K1 is not exactly equal, a tighter break K0 (e.g., disconnecting every two pixel circuits 41) can be set below the columns of pixel circuits 41 where data voltage transitions are most intense and coupling energy is most concentrated, to provide strong physical blocking. Conversely, a wider connected region (e.g., disconnecting every four pixel circuits 41) can be set below the columns of pixels with stable timing and weak transitions to enhance local power supply capabilities. This non-equidistant design deeply spatially couples the charge discharge channel with the drive write timing, achieving targeted anti-crosstalk optimization.

[0067] Figure 14 The diagram shown illustrates the relative positional relationship between the first power supply trace 11 and the bonding area BP according to an embodiment of this disclosure. Please refer to the diagram. Figure 14 In one optional embodiment of this disclosure, the display panel includes a bonding area BP, and a first power trace 11 is configured to obtain a first power signal from the bonding area BP; the repeating unit 110 in the first power trace 11 includes a first repeating unit 111 and a second repeating unit 112 arranged along the second direction D2, the first repeating unit 111 being located between the second repeating unit 112 and the bonding area BP; in the plurality of first power traces 11, the distance between adjacent first breaks K1 along the first direction D1 in the region where the plurality of first repeating units 111 arranged along the first direction D1 are located is H1; the distance between adjacent first breaks K1 along the first direction D1 in the region where the plurality of second repeating units 112 arranged along the first direction D1 are located is H2, H2 < H1.

[0068] The power supply path disclosed herein is as follows: a first power signal is output from the bonding area BP, and can be connected to the first power trace 11 via the power bus DZ, and then transmitted to the far end of the panel along the second direction D2. The first repeating unit 111 is located between the second repeating unit 112 and the bonding area BP; that is, the first repeating unit 111 is closer to the bonding area BP, and the distance H1 between adjacent first breaks K1 along the first direction D1 in the area where the first repeating unit 111 is located is larger. Compared to the first repeating unit 111, the second repeating unit 112 is located further away from the bonding area BP, and the distance H2 between adjacent first breaks K1 along the first direction D1 in the area where the second repeating unit 112 is located is smaller.

[0069] The area near the first repeating unit 111 of the bonding area BP is often the initial point where the data line is output from the driver chip and the signal is written vertically. At this time, the transient amplitude of the data voltage is the largest, the high-frequency components are the most concentrated, and the noise energy coupled into the first power trace layer 10 is also at its peak. The first break point K1 in this area adopts a larger disconnection distance, making the distance between adjacent first power traces 11 larger. This isolation band design can apply the most extreme physical blockage in the area where the noise energy is strongest and crosstalk is most likely to occur. As soon as the noise current is generated, it is locked in a very small local column by the closely spaced first break points K1, and cannot spread laterally, thus effectively solving the lateral line crosstalk phenomenon near the bonding area BP.

[0070] As the first power signal is transmitted to the distant second repeating unit 112 area, the power signal may experience a significant cumulative voltage drop due to the inherent line resistance of the long-distance trace. If the distance between the breaks K0 at the distant end remains large, the metal network of the first power trace layer 10 may become too sparse, resulting in an extremely slow DC potential recovery speed at the distant end. This not only fails to maintain the stability of the large-screen illumination but also induces secondary crosstalk due to the slow recovery. By designing a smaller distance between the first breaks K1 on the side far from the bonding area BP, only a smaller area of ​​metal needs to be removed, effectively reserving a larger metal area for the second repeating unit 112. This increases the effective lateral parallel area of ​​the distant first power trace section 11, greatly reducing the DC impedance of the distant network. When local pixels at the distant end fluctuate due to data voltage jumps, the larger area of ​​the metal structure can share the load and provide rapid charge compensation. This greatly accelerates the oscillation recovery speed of the distant DC signal, reduces the distant voltage drop, and ensures the brightness uniformity of the full-screen steady-state display.

[0071] As data signals are transmitted longitudinally towards the far end, the low-pass filtering effect of the parasitic RC impedance of the traces causes the edges of their high-frequency transitions to gradually become smoother (natural signal attenuation). This means that the capacitive coupling noise energy induced at the far end is inherently weaker. The distance design between the first break points K1 in this solution perfectly matches the natural spatial attenuation trend of noise energy. A larger spacing distance (H1) is provided at the near end where strong isolation is required, and a smaller spacing distance (H2) is provided at the far end where low impedance is required. Thus, at the entire display panel level, a closed loop of full-screen dynamic crosstalk prevention performance and full-screen static power supply uniformity is achieved with the most streamlined geometric deformation.

[0072] Please continue to refer to this. Figure 14 In one optional embodiment of this disclosure, the display panel includes a bonding area BP, and a first power trace 11 is configured to obtain a first power signal from the bonding area BP; the first power trace 11 includes a first repeating unit 111 and a second repeating unit 112 arranged along a second direction D2, the first repeating unit 111 being located between the second repeating unit 112 and the bonding area BP; the area of ​​the orthographic projection of a single first repeating unit 111 onto the substrate 00 is S1, and the area of ​​the orthographic projection of a single second repeating unit 112 onto the substrate 00 is S2, wherein S2 > S1.

[0073] When the data line first enters the area of ​​the first repeating unit 111 from the bonding area BP output, its voltage signal transition is the steepest and its high-frequency noise energy is the strongest. If the metal area of ​​the first power trace layer 10 below is too large at this time, it will generate a very large plate parasitic capacitance, causing high-frequency noise to continuously couple into the power network, which may cause lateral line crosstalk.

[0074] In this embodiment, the area of ​​the single first repeating unit 111 near the end is set to be small, for example, by narrowing the line width, increasing the cutout, or reducing the area of ​​the horizontal first part B1. At this time, the overlap area between the data line DATA and the first power trace 11 can be further reduced. In the region with the strongest noise kinetic energy, the parasitic capacitance is precisely minimized. Due to the significant reduction in the overlap area, the noise energy coupled into the first power trace layer 10 when the data signal changes is greatly intercepted, effectively eliminating the horizontal line crosstalk phenomenon near the bonding area BP end.

[0075] As the power supply distance increases, the first power signal faces a significant DC voltage drop (IR Drop) at the far end (the area of ​​the second repeating unit 112) due to accumulated line resistance. If the area of ​​the second repeating unit 112 at the far end remains small, the high line resistance will cause the DC potential at the far end to recover very slowly after being subjected to dynamic disturbances due to a lack of backup charge replenishment, leading to secondary crosstalk and uneven brightness across the entire screen. Therefore, the area of ​​the individual repeating unit 110 at the far end is set to be larger (e.g., by widening the line width of the second vertical section or increasing the shielding area of ​​the first horizontal section). Increased area means a significant increase in the effective conductive cross-sectional area, linearly reducing the resistance of the longitudinal power supply path at the far end and strongly suppressing the voltage drop at the far end. When the far end is subjected to dynamic disturbances, the larger area of ​​the metal layer can provide a huge local charge buffer pool, allowing the DC signal to achieve ultra-fast oscillation recovery along the low-impedance, large-area network, ensuring the absolute basic uniformity of the screen's light emission under both static and dynamic conditions.

[0076] As data signals are transmitted to the distant end, the edges of high-frequency transitions gradually become smoother due to the RC low-pass filtering effect of the trace itself (noise energy naturally attenuates). Therefore, in regions with weaker noise at the distant end, increasing the area of ​​the second repeating unit 112 does not introduce fatal coupling crosstalk; instead, it utilizes this natural law to focus on impedance optimization. Using a smaller area in the first repeating unit 111 in the near-bonding region BP, where crosstalk prevention is most critical, effectively achieves crosstalk prevention.

[0077] Figure 15 The diagram shown illustrates the relative positional relationship between the first power supply trace 11 and the control signal line L provided in an embodiment of this disclosure. Please refer to the diagram. Figure 15 In one optional embodiment of this disclosure, the display panel further includes a control wiring layer (e.g., Figure 6 The first metal layer M1, capacitor metal layer MC, etc. are located on the side of the first power supply layer 10 away from the substrate 00. The control wiring layer includes multiple control signal lines L extending along the first direction D1 and arranged along the second direction D2. Along the thickness direction of the display panel, the control signal lines L overlap with the second break K2.

[0078] In the pixel circuit 41 of the display panel, the control signal line L may include, for example, Figure 1 The scan lines S1 and S2, the emission control line Emit, etc., are shown. These signal lines carry high-frequency pulse signals or step voltages during the display scanning phase.

[0079] In traditional gridded or full-planar power layer designs, lateral control lines and lateral power lines often overlap significantly, or the control lines are surrounded by power layer metal, leading to severe dynamic coupling problems. The control signal line L experiences dramatic, high-frequency potential jumps during operation. If a large area of ​​power metal is directly beneath the control line, the presence of plate parasitic capacitance causes these high-frequency pulses to couple into the first power trace layer 10, causing ripples in the first power signal and exacerbating lateral line crosstalk. Conversely, local fluctuations on the first power trace layer 10 can also interfere with the waveform of the control signal (blunting pulse edges or causing overshoot), affecting the accuracy of transistor switching.

[0080] In this embodiment, by overlapping the control signal line L with the second break K2 in the thickness direction, the effective overlap area between the control signal line L and the first power trace 11 is reduced in the vertical space, thereby significantly reducing the interlayer parasitic capacitance between the two layers. On the one hand, this design greatly reduces the capacitive load of the control signal line L during transmission, reduces the RC delay of the control signal, and ensures high-fidelity transmission of the switching pulse. On the other hand, due to the precise reduction of the overlap area, the noise energy coupled into the first power trace layer 10 during dynamic transitions of the control signal line L is effectively weakened. In addition, thanks to the physical blocking effect of the second break K2, local potential disturbances or coupled noise on the control signal line L cannot be transversely propagated across the first power trace layer 10, thereby forcibly confining dynamic interference to a local area of ​​a specific column, effectively preventing the disturbance signal from affecting other pixels in the same row, effectively eliminating transverse line crosstalk, and greatly improving the high-contrast picture quality of the display panel.

[0081] Figure 16 The diagram shown illustrates the relative positional relationship between the first power supply trace 11 and the light-emitting element in a display panel provided in this embodiment. Please refer to the diagram. Figure 16 In one optional embodiment of this disclosure, the display panel includes a plurality of pixel circuits 41 arranged in an array and a plurality of light-emitting elements connected to the pixel circuits 41. The pixel circuits 41 include a first pixel circuit 411 and a second pixel circuit 412. The light-emitting elements D include a first light-emitting element D01 and a second light-emitting element D02. The first light-emitting element D01 is electrically connected to the first pixel circuit 411, and the second light-emitting element D02 is electrically connected to the second pixel circuit 412. The pixel opening area of ​​a single first light-emitting element D01 is smaller than the pixel opening area of ​​a single second light-emitting element D02. Along the thickness direction of the display panel, the overlap area between the first light-emitting element D01 and the break K0 is larger than the overlap area between the second light-emitting element D02 and the break K0.

[0082] In a display panel, light-emitting elements of different colors exhibit significant asymmetry in their sensitivity to potential fluctuations due to differences in the luminous efficiency of their light-emitting materials, human eye sensitivity, and anode geometry. In this embodiment, the first light-emitting element D01, connected to the first pixel circuit 411, has a smaller opening area and higher sensitivity; while the second light-emitting element D02, connected to the second pixel circuit 412, has a larger opening area and lower sensitivity.

[0083] The human visual system is far more sensitive to brightness changes in specific wavelengths, such as the green band (approximately 555nm), than to red and blue. This means that when the first power signal fluctuates due to data signal jumps during the dynamic scanning phase, even if the key nodes of the pixel circuits corresponding to different color light-emitting elements show the same magnitude of potential deviation, the physical brightness oscillations generated by the green light-emitting element will be amplified several times in the human eye, becoming a factor that induces macroscopic lateral line crosstalk.

[0084] It should be noted that the location of the light-emitting element can be considered as the location of the corresponding anode. In this embodiment, in the thickness direction of the display panel, the overlap area between the first light-emitting element D01 and the break K0 is greater than the overlap area between the second light-emitting element D02 and the break K0, so that the first light-emitting element D01 avoids the physical first power supply trace 11 as much as possible. This greatly reduces the parasitic capacitance between the anode of the first light-emitting element D01 and the first power supply trace 11. When the anode of the first light-emitting element D01 does not overlap with the first power supply trace 11 or the overlap area is small, and the overlap area with the break K0 is large, the parasitic capacitance between the anode of the first light-emitting element D01 and the first power supply trace 11 will be very small. Due to the loss of the capacitive coupling path, even if a weak dynamic ripple remains inside the first power supply trace layer 10 during dynamic operation, this noise cannot be capacitively conducted to the upper first light-emitting element D01. This targeted noise reduction mechanism builds the strongest firewall in the color channel, which is most sensitive to human vision, effectively preventing the visual manifestation of bright and dark line crosstalk.

[0085] In one optional embodiment of this disclosure, the first light-emitting element D01 is a green light-emitting element G, and the second light-emitting element D02 is a red light-emitting element R or a blue light-emitting element B.

[0086] Because of its high lumen efficiency, the green light-emitting element G typically has a smaller pixel aperture area and anode area than the red light-emitting element R and the blue light-emitting element B in order to balance the white balance of the entire screen. The smaller the anode area, the weaker its ability to hold steady-state charge (self-capacitance). Once even a small amount of external noise is coupled in, the percentage fluctuation of the anode potential of the green light-emitting element G will be significantly higher than that of the larger anode of the red light-emitting element R or the blue light-emitting element B.

[0087] This disclosure arranges the green light-emitting element G to overlap with the break point K0 as much as possible, avoiding the first power supply trace 11. This also ensures that the anode of the green light-emitting element G overlaps with the break point K0 as much as possible, thus reducing the overlap area between the anode and the first power supply trace 11. This helps to reduce the interlayer parasitic capacitance load corresponding to the green light-emitting element G. This significantly shortens the electrical charging and discharging delay of the anode node of the first light-emitting element D01 when facing dynamic grayscale switching. Even under weak disturbances, the self-recovery speed of its DC potential can be increased exponentially, making the dynamic response between different color light-emitting elements highly consistent and eliminating local dynamic color deviations caused by different color channel recovery speeds.

[0088] In high-PPI panels, every inch of space within a pixel is precious. The break point K0 is an intentionally created metal-free vacuum zone to cut off lateral crosstalk, and the green light-emitting element G happens to be small in size. This solution spatially nests and reuses the first light-emitting element D01, which has a smaller pixel aperture area, with the metal-free break point K0 area. Without changing the original longitudinal conductive cross-sectional area of ​​the first power supply trace layer 10, the green light-emitting element is placed in the space of the break point K0. This eliminates the parasitic coupling of the green light-emitting element and eliminates the need for further area concessions in the main power supply trace (thus avoiding far-end IRDrop deterioration), achieving a balance between macroscopic and microscopic considerations: no increase in impedance, a sharp reduction in crosstalk, and preservation of aperture ratio.

[0089] Figure 17 The diagram shown illustrates the relative positions of the first power supply trace 11, the light-emitting element, and the data line DATA in a display panel provided in this embodiment. Please refer to the diagram. Figure 17 In one optional embodiment of this disclosure, the display panel includes a plurality of pixel circuits 41 arranged in an array and a plurality of light-emitting elements D connected to the pixel circuits 41. The pixel circuits 41 include a first pixel circuit 411 and a second pixel circuit 412. The light-emitting elements D include a first light-emitting element D01 and a second light-emitting element D02. The first light-emitting element D01 is electrically connected to the first pixel circuit 411, and the second light-emitting element D02 is electrically connected to the second pixel circuit 412. The pixel aperture area of ​​a single first light-emitting element D01 is smaller than the pixel aperture area of ​​a single second light-emitting element D02. The data line DATA includes a first data line DA1 and a second data line DA2. The first data line DA1 is electrically connected to the first pixel circuit 411, and the second data line DA2 is electrically connected to the second pixel circuit 412. Along the thickness direction of the display panel, the overlap area between the first data line DA1 and the first power supply trace 11 is less than or equal to the overlap area between the second data line DA2 and the first power supply trace 11. In other words, the overlap area between the first data line DA1 and the break point K0 is greater than the overlap area between the second data line DA2 and the break point K0.

[0090] Optionally, the first light-emitting element D01 is a green light-emitting element G, and the second light-emitting element D02 is a red light-emitting element R or a blue light-emitting element B. The human eye is extremely sensitive to slight fluctuations in brightness in the green band (far more so than in red and blue). The same potential ripple on the first power supply trace 11 will amplify the visual crosstalk caused by the first light-emitting element D01 several times. The opening area and anode area of ​​the first light-emitting element D01 are usually small, and its ability to accommodate steady-state charge is weak. When the same amount of charge is coupled in from the outside, the percentage fluctuation of the anode potential of the first light-emitting element D01 will be significantly higher than that of the anode of the larger-area second light-emitting element D02, making it more susceptible to interference.

[0091] To address this, this embodiment reduces the overlap area between the first data line DA1 and the first power supply trace 11, thereby reducing the parasitic capacitance between them. Therefore, even if the data signal on the first data line DA1 experiences a drastic grayscale jump, the amount of dynamic charge that can be injected into the power network will be minimal due to the extremely small parasitic capacitance, effectively reducing or eliminating factors that induce lateral line crosstalk.

[0092] The parasitic capacitance of the data line (DATA) to the power / ground layer constitutes its main load capacitance. The larger the capacitance, the more severe the RC delay of the data signal during long-distance transmission, resulting in blunted voltage pulse edges and affecting the accurate writing of grayscale. This embodiment reduces the area of ​​the first power trace 11 below the first data line (DA1), thus protecting the first power trace layer and indirectly reducing the capacitive load of the first data line (DA1) itself. This results in a steeper, higher-fidelity write waveform for the green grayscale signal, which is most sensitive to the human eye, enabling it to be charged to the target potential with extremely high precision within a very short scan time, further improving the dynamic stability of the full-screen white balance.

[0093] If all the metal in the first power trace layer 10 below all data lines (DATA) is indiscriminately removed, it will result in a large area of ​​the first power trace layer 10 being missing across the entire screen, causing a significant spike in its vertical resistance, leading to severe DC voltage drop and uneven brightness across the entire screen. This solution employs an asymmetrical design, precisely allowing metal clearance only below the high-risk first light-emitting element D01, while retaining normal metal area below the less sensitive red / blue light-emitting elements to maintain vertical power supply capability. This on-demand, precise spatial geometric reuse achieves a qualitative leap in full-screen dynamic crosstalk prevention performance with minimal space constraints, without sacrificing the low DC impedance of the main power network (and without worsening IR drop).

[0094] Figure 18 The figure shown is another planar schematic diagram of the first power supply trace layer 10 in the display panel provided in this embodiment of the present disclosure. Figure 19 The diagram shown illustrates the relative positional relationship between the first power supply layer 10 and the data line DATA in a display panel provided in this embodiment. Please refer to the diagram. Figure 18 and Figure 19 In one optional embodiment of this disclosure, the first power supply trace 11 is a strip structure extending along the second direction D2. Along the thickness direction of the display panel, the orthogonal projection of the data line DATA onto the substrate 00 is located within the orthogonal projection range of the break point K0 onto the substrate 00.

[0095] Since the first power trace 11 is straight, a straight, longitudinally extending non-metallic gap (i.e., the break K0 region) of equal width is naturally formed between two adjacent first power traces 11 in the first direction D1. In the thickness direction (top view), the top layer data line DATA also extends straight longitudinally, and its overall orthographic projection on the substrate 00 is completely confined and enclosed within the orthographic projection range of the bottom layer break K0. This means that when the data line DATA crosses the entire effective display area, there is no solid metal of the first power trace layer 10 directly below it. In this way, the data line DATA achieves absolute vertical retreat from the solid metal of the power layer throughout its entire path. The vertical overlap area of ​​the two metal layers is directly reduced to zero, reducing the interlayer parasitic capacitance between the data line DATA and the power trace layer to the theoretical physical limit. When the data signal undergoes any violent instantaneous jump, it will not leak coupling charge to the power layer network below, thereby cutting off the triggering medium for lateral crosstalk.

[0096] When data signals cause weak local disturbances on the power layer due to indirect capacitive coupling with control lines and other layers, noise can propagate across the gap if the break point K0 is not pure enough. Since the first power trace 11 is a straight strip, the break point K0 presents an extremely regular, seamless, and highly continuous isolation band. The power traces on both sides of the data line DATA are cut off horizontally, and because the data line DATA is effectively wrapped by the break point K0, its potential role as a horizontal AC jumper is completely blocked. The remaining weak disturbance charge, after colliding with this straight vacuum barrier horizontally, is forcibly clamped within the vertical path of the current column, and is forced to release only towards the low-impedance main power layer at the top and bottom of the panel, thus minimizing horizontal crosstalk.

[0097] Furthermore, the regular, straight strip structure is the most ideal geometry in semiconductor manufacturing, least affected by process variations. Whether it's photoresist spraying or etching gas flow, it exhibits extremely high uniformity along straight strips. This completely eliminates the risk of localized short circuits or micro-open circuits, leaving a huge safety tolerance for mass production in factories, and greatly improving the mass production yield and capacity of display panels.

[0098] Based on the same inventive concept, this disclosure also provides a display device. Figure 20 The diagram shown is a planar structural schematic of a display device 200 provided in an embodiment of this disclosure. Please refer to it. Figure 20 The display device 200 includes the display panel 100 provided in any of the foregoing embodiments of the present disclosure.

[0099] The display device 200 provided in this embodiment can be any electronic device with display function, such as a touch screen, mobile phone, tablet computer, laptop computer, e-reader, or television. It can also be a large-size splicing display device, such as a command center screen. The display device 200 provided in this embodiment has the beneficial effects of the display panel 100 provided in this embodiment. For details, please refer to the specific descriptions of the display module in the above embodiments. These descriptions will not be repeated here.

[0100] Understandably, attached Figure 20 The rectangular structure is used as an example to illustrate one shape of the display device 200. In some other embodiments of this disclosure, the display device 200 may also be circular, elliptical, fan-shaped or any other feasible shape, and this disclosure does not specifically limit it.

[0101] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0102] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: Substrate; A first power trace layer located on one side of the substrate, the first power trace layer includes a plurality of first power trace portions arranged along a first direction and extending along a second direction, the first direction and the second direction intersecting; in the first power trace layer, adjacent first power trace portions are spaced apart by a break and are not connected to each other. A data trace layer located on the side of the first power trace layer away from the substrate, the data trace layer including multiple data lines arranged along the first direction and extending along the second direction; Wherein, along the thickness direction of the display panel, at least a portion of the data lines' orthogonal projections on the substrate overlap with the orthogonal projections of the break on the substrate.

2. The display panel according to claim 1, characterized in that, Multiple first power traces are configured to receive the same first power signal.

3. The display panel according to claim 1, characterized in that, The display panel further includes a second power trace layer, which is located on the side of the first power trace layer away from the substrate. The second power trace layer includes a plurality of second power trace portions, and the first power trace portions and the second power trace portions are electrically connected through connecting holes.

4. The display panel according to claim 3, characterized in that, The connection holes are located at two opposite ends of the second power supply trace along the second direction.

5. The display panel according to claim 1, characterized in that, Along the first direction, the minimum width of the fracture is W, where W ≥ 3 μm.

6. The display panel according to claim 1, characterized in that, The first power supply trace includes a plurality of repeating units arranged and connected along the second direction. Each repeating unit includes a first part and a second part located on one side of the first part and connected to the first part along the second direction. The first part extends along the first direction, and the second part is also connected to the first part in an adjacent repeating unit. The break includes a first break, in which the first break is located between two adjacent first power trace portions along the first direction, and the width of the first break is W1. The display panel includes multiple pixel circuits arranged in an array, and the width of a single pixel circuit along the first direction is W0, wherein 3μm≤W1≤W0.

7. The display panel according to claim 6, characterized in that, The break also includes a second break, in which the second break is located between two adjacent first power supply traces along the first direction; along the thickness direction of the display panel, the data line overlaps with the second break; the width of the second break along the first direction is greater than or equal to the width of the first break along the first direction.

8. The display panel according to claim 6, characterized in that, The display panel further includes an active layer. Along the thickness direction of the display panel, the active layer is located between the first power trace layer and the data trace layer. The active layer includes multiple channels. Along the thickness direction of the display panel, the second part overlaps with the channels; the second part is multiplexed as a shielding part of the channels.

9. The display panel according to claim 6, characterized in that, The display panel includes a plurality of pixel circuits arranged in an array. Along the thickness direction of the display panel, one first power supply trace corresponds to N columns of the pixel circuits, where N≥2.

10. The display panel according to claim 9, characterized in that, Along the thickness direction of the display panel, the number of columns of the pixel circuits corresponding to different first power supply traces is the same.

11. The display panel according to claim 9, characterized in that, Along the thickness direction of the display panel, at least two of the first power supply traces correspond to different numbers of columns of the pixel circuits.

12. The display panel according to claim 6, characterized in that, The display panel includes a bonding area, and the first power trace is configured to obtain a first power signal from the bonding area; the repeating unit in the first power trace includes a first repeating unit and a second repeating unit arranged along the second direction, and the first repeating unit is located between the second repeating unit and the bonding area. In the plurality of first power supply traces, the distance between adjacent first breaks in the region where the plurality of first repeating units arranged along the first direction are located is H1; the distance between adjacent first breaks in the region where the plurality of second repeating units arranged along the first direction are located is H2, where H2 < H1.

13. The display panel according to claim 6, characterized in that, The display panel includes a bonding area, and the first power trace is configured to obtain a first power signal from the bonding area; the repeating unit in the first power trace includes a first repeating unit and a second repeating unit arranged along the second direction, and the first repeating unit is located between the second repeating unit and the bonding area. The area of ​​the orthographic projection of a single first repeating unit onto the substrate is S1, and the area of ​​the orthographic projection of a single second repeating unit onto the substrate is S2, wherein S2 > S1.

14. The display panel according to claim 7, characterized in that, The display panel further includes a control wiring layer, which is located on the side of the first power wiring layer away from the substrate. The control wiring layer includes a plurality of control signal lines extending along the first direction and arranged along the second direction. Along the thickness direction of the display panel, the control signal lines overlap with the second break.

15. The display panel according to claim 1, characterized in that, The display panel includes a plurality of pixel circuits arranged in an array and a plurality of light-emitting elements connected to the pixel circuits. The pixel circuits include a first pixel circuit and a second pixel circuit, and the light-emitting elements include a first light-emitting element and a second light-emitting element. The first light-emitting element is electrically connected to the first pixel circuit, and the second light-emitting element is electrically connected to the second pixel circuit. The pixel aperture area of ​​a single first light-emitting element is smaller than the pixel aperture area of ​​a single second light-emitting element. Wherein, along the thickness direction of the display panel, the overlap area between the first light-emitting element and the fracture is greater than the overlap area between the second light-emitting element and the fracture.

16. The display panel according to claim 15, characterized in that, The first light-emitting element is a green light-emitting element, and the second light-emitting element is a red light-emitting element or a blue light-emitting element.

17. The display panel according to claim 1, characterized in that, The display panel includes a plurality of pixel circuits arranged in an array and a plurality of light-emitting elements connected to the pixel circuits. The pixel circuits include a first pixel circuit and a second pixel circuit, and the light-emitting elements include a first light-emitting element and a second light-emitting element. The first light-emitting element is electrically connected to the first pixel circuit, and the second light-emitting element is electrically connected to the second pixel circuit. The pixel aperture area of ​​a single first light-emitting element is smaller than the pixel aperture area of ​​a single second light-emitting element. The data line includes a first data line and a second data line, wherein the first data line is electrically connected to the first pixel circuit and the second data line is electrically connected to the second pixel circuit; Wherein, along the thickness direction of the display panel, the overlap area between the first data line and the first power trace is less than or equal to the overlap area between the second data line and the first power trace.

18. The display panel according to claim 1, characterized in that, The first power trace is a strip-shaped structure extending along the second direction. Along the thickness direction of the display panel, the data line is located within the orthogonal projection of the substrate, and the break point is within the orthogonal projection range of the substrate.

19. A display device, characterized in that, Includes the display panel described in any one of claims 1 to 18.

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