A display panel and display device

Abstract

Embodiments of the present application disclose a display panel and a display device. The display panel comprises a signal line and a light emitting element. The signal line comprises a first power signal line extending along a first direction and arranged along a second direction. The first direction and the second direction intersect. The light emitting element comprises an anode. The first power signal line comprises a break. In a direction perpendicular to a light-out surface of the display panel, a region where the break is located does not overlap the anode. The technical scheme of the embodiments of the present application can improve light transmittance of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the continuous development of display technology, display panels have been widely used in people's production and daily life. However, there are still some technical problems in existing display panels that need to be solved. For example, in existing display panels, the light transmittance of the array layer where the pixel circuit is located is basically fixed, and the pixel aperture ratio is developing towards a larger aperture ratio (the pixel anode area is increasing), which makes it difficult to further improve the light transmittance of the display panel and cannot meet the requirements of under-display optical devices (such as fingerprint recognition modules) for higher light transmittance. Summary of the Invention

[0003] This invention provides a display panel and a display device to improve the light transmittance of the display panel.

[0004] According to one aspect of the present invention, a display panel is provided, comprising: Signal lines; the signal lines include first power signal lines extending along a first direction and arranged along a second direction; the first direction and the second direction intersect; Light-emitting element; the light-emitting element includes an anode; The first power signal line includes a break along a direction perpendicular to the light-emitting surface of the display panel, and the area where the break is located does not overlap with the anode.

[0005] According to another aspect of the present invention, a display device is provided, comprising a display panel provided in any embodiment of the present invention.

[0006] The technical solution of this invention provides a break in the first power signal line that extends along the first direction and is arranged along the second direction. In the direction perpendicular to the light-emitting surface of the display panel, the area where the break is located does not overlap with the anode. This reduces the metal density in the non-pixel opening area (the area without anode shielding), increases the light-transmitting area of ​​the display panel, and thus increases the light transmittance of the display panel.

[0007] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 2 This is a circuit element diagram of a pixel circuit provided in an embodiment of the present invention; Figure 3 This invention provides, within a driving cycle, the capability to... Figure 2 A timing diagram of the implementation of the signal of the pixel circuit shown; Figure 4 yes Figure 1 A schematic diagram of a cross-section along section line A-A'; Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention; Figure 6 yes Figure 5 A schematic diagram of a portion of the structure of the provided display panel; Figure 7 yes Figure 5 A schematic diagram of another part of the structure in the provided display panel; Figure 8 yes Figure 5 A schematic diagram of another part of the structure in the provided display panel; Figure 9 yes Figure 5 A schematic diagram of another part of the structure in the provided display panel; Figure 10 yes Figure 5 A schematic diagram of another part of the structure in the provided display panel; Figure 11 yes Figure 5 A schematic diagram of another part of the structure in the provided display panel; Figure 12 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention; Figure 13 yes Figure 12 A schematic diagram of a portion of the structure of the provided display panel; Figure 14 yes Figure 12 A schematic diagram of another part of the structure in the provided display panel; Figure 15 This is a schematic diagram of a portion of the structure of the display panel provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0010] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0011] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0012] First, it should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. The terms "comprising" and similar terms mean that the element or object preceding the word encompasses the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes. Furthermore, the shapes and sizes of the components in the accompanying drawings do not reflect actual proportions and are only intended to illustrate the content of this invention.

[0013] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a circuit element diagram of a pixel circuit provided in an embodiment of the present invention. Figure 3 This invention provides, within a driving cycle, the capability to... Figure 2 The timing diagram shows an implementation of the signal of the pixel circuit. Figure 4 yes Figure 1 A schematic diagram of a cross-section along section line A-A'. Figure 5This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 6 yes Figure 5 A schematic diagram of a portion of the structure of the provided display panel. Figure 7 yes Figure 5 A schematic diagram of another part of the structure in the provided display panel. Figure 8 yes Figure 5 A schematic diagram of another part of the structure in the provided display panel. Figure 9 yes Figure 5 A schematic diagram of another part of the structure in the provided display panel. Figure 10 yes Figure 5 A schematic diagram of another part of the structure in the provided display panel. Figure 11 yes Figure 5 A schematic diagram of another part of the structure in the provided display panel is shown for reference. Figures 1-11 As shown, an embodiment of the present invention provides a display panel 10, which includes signal lines 101 and light-emitting elements 200; the signal lines 101 include a first power signal line PVDD1 extending along a first direction X and arranged along a second direction Y; the first direction X and the second direction Y intersect; the light-emitting element 200 includes an anode 200a; the first power signal line PVDD1 includes a break D, which is perpendicular to the light-emitting surface of the display panel, and the area where the break D is located does not overlap with the anode 200a.

[0014] refer to Figure 1 As shown, the display panel 10 also includes a pixel circuit 100, which is electrically connected to the light-emitting element 200 of the display panel 10 to drive the light-emitting element 200 and ensure that the light-emitting element 200 emits light for display. (Reference) Figure 2 As shown, the signal line 101 in the display panel 10 is configured to provide voltage and / or current signals to the pixel circuit 100 to control the working state of the pixel circuit 100, thereby driving the light-emitting element 200 and ensuring the display effect.

[0015] refer to Figure 2 As shown, the pixel circuit 100 includes a driving transistor T3, and the signal line 101 includes a power signal line PVDD. The driving transistor T3 is coupled between the power signal line PVDD and the light-emitting element 200. The power signal provided by the power signal line PVDD can be transmitted to the light-emitting element 200 through the driving transistor T3, thereby driving the light-emitting element 200 to emit light.

[0016] refer to Figure 5 , Figure 10 and Figure 11As shown, a power signal line PVDD typically includes a first power signal line PVDD1 extending along a first direction X and arranged along a second direction Y, and a second power signal line PVDD2 extending along the second direction Y and arranged along the first direction X. The first power signal line PVDD1 and the second power signal line PVDD2 are arranged in different layers and electrically connected. In this way, a double-layer mesh structure of power signal lines PVDD can be formed, which can effectively reduce the voltage drop in the power signal lines PVDD, ensure the transmission effect of the power signal (PVDD), and ensure the uniformity of the power signal (PVDD) received by different pixel circuits.

[0017] refer to Figure 5 and Figure 11 As shown, in this embodiment of the invention, by setting a break D on the first power signal line PVDD1 extending along the first direction X and arranged along the second direction Y, and ensuring that the area where the break D is located does not overlap with the anode 200a in the direction perpendicular to the light-emitting surface of the display panel (i.e., the thickness direction of the display panel), the metal density of the non-pixel opening area (the area not blocked by the anode 200a) can be reduced, the light-transmitting area of ​​the display panel can be increased, and the light transmittance of the display panel can be increased.

[0018] Understandably, although the first power signal line PVDD1 has a partial break, the power signal line PVDD as a whole still maintains a double-layer mesh design. Therefore, this solution can still ensure that the power signal (PVDD) is provided to each pixel circuit.

[0019] In summary, the display panel provided by the embodiments of the present invention reduces the metal density of non-pixel opening areas (areas without anode shielding) by setting a break in the first power signal line extending along the first direction and arranged along the second direction, and ensuring that the area where the break is located does not overlap with the anode in the direction perpendicular to the light-emitting surface of the display panel, thereby increasing the light transmittance of the display panel.

[0020] It should be noted that the pixel circuit 100 can be configured in various ways; refer to... Figure 2 As shown, the pixel circuit 100 is illustrated using "7T1C" as an example, where "T" represents a transistor and "C" represents a storage capacitor. Based on the arrangement of the pixel circuit 100 and signal lines 101, those skilled in the art can make adaptive adjustments according to their needs.

[0021] For example, refer to Figure 2As shown, in addition to the driving transistor T3, the pixel circuit 100 may also include a first light-emitting control transistor T1, a data writing transistor T2, a threshold compensation transistor T4, an initialization transistor T5, a second light-emitting control transistor T6, a reset transistor T7, and a storage capacitor Cst. In addition to the power signal line PVDD, the signal line 101 may also include a data signal line DATA, a first scan signal line S1, a second scan signal line S2, a third scan signal line SP, a light-emitting control signal line EMIT, and an initialization signal line VREF.

[0022] For the working process of pixel circuit 100, refer to Figure 2 For example: The first scan signal line S1 controls the on and off of the initialization transistor T5, and resets the gate potential of the driving transistor T3 when the initialization transistor T5 is on, that is, transmits the initialization signal of the initialization signal line VREF to the initialization transistor T5, and resets the connection node (first node N1) of the driving transistor T3, the initialization transistor T5, the threshold compensation transistor T4, and the storage capacitor Cst. The second scan signal line S2 controls the on and off of the threshold compensation transistor T4, and compensates the threshold voltage of the driving transistor T3 when the threshold compensation transistor T4 is on. The third scan signal line SP controls the on and off of the data writing transistor T2, and writes the data signal on the data signal line DATA to the gate of the driving transistor T3 when the data writing transistor T2 is on. At the same time, the third scan signal line SP also controls the on and off of the reset transistor T7, and resets the anode of the light-emitting element 200 connected to the pixel circuit 100 when the reset transistor T7 is on, that is, transmits the reset signal of the reset signal line VREF to the anode of the light-emitting element 200. The light-emitting control signal line EMIT controls the on and off of the first light-emitting control transistor T1 and the second light-emitting control transistor T6. When the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are on, the power signal transmitted by the power signal line PVDD is transmitted to the light-emitting element 200, thereby driving the light-emitting element 200 to emit light.

[0023] refer to Figure 3 As shown, the enable level of the scan signal / light emission control signal can turn on the transistor, and the de-enable level can turn off the transistor (or cut off). Figure 2 Taking the example where the first light-emitting control transistor T1, data writing transistor T2, driving transistor T3, threshold compensation transistor T4, initialization transistor T5, second light-emitting control transistor T6, and reset transistor T7 are all P-type transistors, accordingly, Figure 3The enable level of the signals transmitted by the first scan signal line S1, the second scan signal line S2, the third scan signal line SP, and the light emission control signal line EMIT is low, and the disable level is high. In other embodiments, the transistors in the pixel circuit can be diverse, for example, including both N-type and P-type transistors. This embodiment of the invention does not limit this and can be adaptively adjusted according to actual production needs.

[0024] Further, refer to Figure 3 As shown, in one driving cycle F of the pixel circuit 100, the gate signal transmitted by the light emission control signal line EMIT includes multiple disabled level stages and multiple enabled level stages, which are arranged alternately. When the light emission control signal line EMIT is at the disabled level, the first light emission control transistor T1 and the second light emission control transistor T6 are turned off. When the light emission control signal line EMIT is at the enabled level, the first light emission control transistor T1 and the second light emission control transistor T6 are turned on.

[0025] Further, refer to Figure 3 As shown, in one driving cycle F of the pixel circuit 100, at least a data writing stage F1 and a light emission stage F2 are included. The data writing stage F1 includes a disabled level stage of the light emission control signal EMIT, and the light emission stage F2 includes an enabled level stage of the light emission control signal EMIT. Specifically, if one driving cycle F of the pixel circuit 100 is a high-frequency cycle, then the driving cycle F includes a data writing stage F1 and a light emission stage F2. If one driving cycle F of the pixel circuit 100 is a low-frequency cycle, then the driving cycle F includes a data writing stage F1, a light emission stage F2, and a light emission holding stage F3. In the light emission holding stage F3, the light emission control signal EMIT includes multiple disabled level stages and at least one enabled level stage. Figure 3 (The example below illustrates this using an enable level phase.) Figure 3 The illustration will only take the low-frequency mode as an example.

[0026] refer to Figure 3 As shown, the data writing stage F1 includes an initialization stage F11 and a data signal writing stage F12. In the initialization stage F11, the first scan signal line S1 is enabled, and the initialization transistor T5 is turned on to initialize (reset) the first node N1. In the data signal writing stage F12, the second scan signal line S2 and the third scan signal line SP are enabled, and the data writing transistor T2 and the threshold compensation transistor T4 are turned on to complete data writing and threshold compensation. Simultaneously, the reset transistor T7 is turned on to perform an anode reset on the light-emitting element 200.

[0027] Further, refer to Figures 4-11 As shown, Figure 5 A schematic diagram of the overall structure of the display panel is shown (and...). Figure 2 (corresponding to the pixel circuit shown), from Figure 5 As can be seen, the display panel 10 is composed of multiple overlapping film layers. To clearly understand the specific placement of these film layers, please refer to... Figure 4 , Figure 7 , Figure 8 , Figure 10 and Figure 11 The different film layers in the display panel 10 are illustrated from bottom to top, including the active layer POLY, the first metal layer M1, the capacitor metal layer MC, the second metal layer M2, and the film layer RE (not shown separately) containing the anode 200a. In addition, the display panel 10 also includes a substrate 300 and a buffer layer 310. All the aforementioned film layers are disposed on the side of the buffer layer 310 away from the substrate 300. Furthermore, an insulating film layer 400 exists between each metal film layer (the number and type of the insulating film layer 400 are not limited). Based on the specific film layer configuration of the display panel 10, adaptive adjustments can be made according to actual production needs, such as adding or removing some film layers. This embodiment of the invention does not impose specific limitations on this.

[0028] Figure 9 The stack-up diagram of the active layer POLY and the first metal layer M1 is shown in the reference diagram. Figure 8 and Figure 9 As shown, optionally, the first scan signal line S1, the second scan signal line S2, the third scan signal line SP, and the light emission control signal line EMIT are all located on the first metal layer M1 and spaced apart. Furthermore, the first metal layer M1 also has a second capacitor plate C2 (lower plate, multiplexed as the gate of the driving transistor T3) of the storage capacitor Cst. (Reference) Figure 10 As shown, the capacitor metal layer Mc is provided with an initialization signal line VREF and a first capacitor plate C1 (upper plate) for the storage capacitor Cst. (Reference) Figure 11 As shown, the second metal layer M2 is provided with a first power signal line PVDD1 and a data line DATA. Figure 6 The overall film layer structure of the pixel circuit is shown. Based on the component arrangement of the pixel circuit, the film layer of the display panel and the structure in each film layer can be adaptively adjusted according to actual production needs. This embodiment of the invention does not impose specific limitations on this.

[0029] Next, continue to refer to Figures 5-11 The method of setting the break point will be further explained in detail.

[0030] Further, refer to Figure 5 As shown, along the direction perpendicular to the light-emitting surface of the display panel, the area where the break D is located does not overlap with the storage capacitor Cst.

[0031] Specifically, the less metal overlaps with the break point D in the thickness direction of the display panel, the greater the improvement in light transmittance. The area where the storage capacitor Cst is located is a densely populated area of ​​the pixel circuit 100 with a high metal density. By ensuring that the area where the break point D is located does not overlap with the storage capacitor Cst in the thickness direction of the display panel, it is beneficial to ensure that the area where the break point D is located is in a region with sparse metal density, reducing or even avoiding the overlap of other metals with the area where the break point D is located, thereby effectively improving light transmittance.

[0032] refer to Figure 5 and Figure 11 As shown, optionally, the display panel 10 includes pixel circuit groups 11 arranged in an array along the first direction X and the second direction Y; each pixel circuit group 11 includes three pixel circuits 100 arranged along the second direction Y; the first power signal line PVDD1 includes a first power line segment PVDDa, and the first power line segment PVDDa is configured in a one-to-one correspondence with the pixel circuit 100; along the first direction X, in at least one pair of adjacent pixel circuit groups 11, there is a break D between at least one pair of adjacent first power line segments PVDDa.

[0033] For details, please refer to Figure 5 and Figure 11 As shown, the pixel circuits 100 are arranged in an array along the first direction X and the second direction Y. Along the second direction Y, three pixel circuits 100 arranged side by side form a group, constituting a pixel circuit group 11. Therefore, the pixel circuit group 11 is also arranged in an array along the first direction X and the second direction Y.

[0034] Furthermore, one pixel circuit group 11 corresponds to one light-emitting unit, and one light-emitting unit includes three light-emitting elements 200 with different light-emitting colors. The pixel circuit 100 and the light-emitting element 200 are electrically connected in a one-to-one correspondence. The three pixel circuits 100 in one pixel circuit group 11 are respectively used to drive the three light-emitting elements 200 in one light-emitting unit to emit light.

[0035] refer to Figure 5 and Figure 11 As shown, the first power signal line PVDD1, which originally extends along the first direction X, passes through the area where multiple pixel circuits 100 are arranged along the first direction X. That is, each pixel circuit 100 corresponds to a segment of the first power signal line PVDD1 (i.e., the first power line segment PVDDa) and is electrically connected to the first power line segment PVDDa. In this embodiment, by setting the break point D between two adjacent first power line segments PVDDa, it can be ensured that the setting of the break point D does not affect the electrical connection between the first power signal line PVDD1 and each pixel circuit 100.

[0036] Furthermore, regarding the number of breaks D, for any two adjacent pixel circuit groups 11 along the first direction X, the two adjacent first power supply segments PVDDa corresponding to the two adjacent pixel circuits 100 along the first direction X constitute a group. Since a pixel circuit group 11 includes three pixel circuits 100, there are three groups of combinations formed by two adjacent first power supply segments PVDDa along the first direction X in two adjacent pixel circuit groups 11 along the first direction X. Optionally, at least one group of two adjacent first power supply segments PVDDa has a break D between them. That is, along the first direction X, two adjacent pixel circuit groups 11 include three groups of combinations formed by two adjacent first power supply segments PVDDa along the first direction X. This can be a group of two adjacent first power supply segments PVDDa with a break D between them, two groups of two adjacent first power supply segments PVDDa with a break D between them, or all three groups of two adjacent first power supply segments PVDDa with a break D between them.

[0037] For details, please refer to Figure 5 and Figure 11 As shown, optionally, the pixel circuit group 11 includes a first pixel circuit 110, a second pixel circuit 120, and a third pixel circuit 130 arranged side by side along the second direction Y; the light-emitting element 200 includes a first light-emitting element 210, a second light-emitting element 220, and a third light-emitting element 230, the first light-emitting element 210 including a first anode 210a, the second light-emitting element 220 including a second anode 220a, and the third light-emitting element 230 including a third anode 230a, the first pixel circuit 110 being electrically connected to the first anode 210a, the second pixel circuit 120 being electrically connected to the second anode 220a, and the third pixel circuit 130 being electrically connected to the third anode 230a. Along the first direction X, in two adjacent pixel circuit groups 11, the two adjacent first power supply segments PVDDa corresponding to the two adjacent first pixel circuits 110 form one group, the two adjacent first power supply segments PVDDa corresponding to the two adjacent second pixel circuits 120 form one group, and the two adjacent first power supply segments PVDDa corresponding to the two adjacent third pixel circuits 130 form one group. Among these three groups of adjacent first power supply segments PVDDa, at least one group of two adjacent first power supply segments PVDDa has a break D between them.

[0038] For example, refer to Figure 5 and Figure 11As shown in this example, along the first direction X, in two adjacent pixel circuit groups 11, there is a break D between two adjacent first power supply segments PVDDa corresponding to two adjacent first pixel circuits 110, there is a break D between two adjacent first power supply segments PVDDa corresponding to two adjacent second pixel circuits 120, and there is also a break D between two adjacent first power supply segments PVDDa corresponding to two adjacent third pixel circuits 130. At this time, there are three breaks D in two adjacent pixel circuit groups 11 along the first direction X, which can effectively improve the light transmittance.

[0039] It should be noted that for the break D between two adjacent first power line segments PVDDa corresponding to two adjacent pixel circuits 100 along the first direction X, the region where the break D is located can overlap with the region where at least one of the pixel circuits 100 is located. Figure 5 The illustration only takes the overlap of the break point D with the upper pixel circuit 100 of the two adjacent pixel circuits 100 as an example. In other embodiments, the break point D may also overlap with the lower pixel circuit 100. The present invention does not limit this, as long as it does not affect the electrical connection between the two first power line segments PVDDa and their respective corresponding pixel circuits 100.

[0040] Figure 12 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 13 yes Figure 12 A schematic diagram of a portion of the structure of the provided display panel. Figure 14 yes Figure 12 A schematic diagram of another part of the structure in the provided display panel is shown for reference. Figures 12-14 As shown, in another embodiment, optionally, the area of ​​the first anode 210a and the area of ​​the second anode 220a are both smaller than the area of ​​the third anode 230a; along the first direction X, in two adjacent pixel circuit groups 11, there is a break D between two adjacent first power supply segments PVDDa corresponding to two adjacent first pixel circuits 110, there is a break D between two adjacent first power supply segments PVDDa corresponding to two adjacent second pixel circuits 120, and the adjacent first power supply segments PVDDa corresponding to two adjacent third pixel circuits 130 are connected.

[0041] Specifically, in this embodiment, along the first direction X, in two adjacent pixel circuit groups 11, there is a break D between two adjacent first power line segments PVDDa. Specifically, there is a break D between the two adjacent first power line segments PVDDa corresponding to the pixel circuits (first pixel circuit 110 and second pixel circuit 120) connected by the two anodes with smaller areas (first anode 210a and second anode 220a). There is no break D between the adjacent first power line segments PVDDa corresponding to the pixel circuit (third pixel circuit 130) connected by the anode with the largest area 200a (third anode 230a), but instead, there is a whole first power signal line PVDD1.

[0042] refer to Figure 12 and Figure 13 As shown, for the third anode 230a with the largest area, when the third anode 230a covers most of the first power signal line PVDD1 corresponding to the third pixel circuit 130, the effect of setting a break on the first power signal line PVDD1 to improve light transmittance is negligible. Therefore, it is possible to select two adjacent first power line segments PVDDa corresponding to two adjacent third pixel circuits 130 to remain connected (without setting a break). At this time, the multiple third pixel circuits 130 arranged along the first direction X correspond to a whole first power signal line PVDD1.

[0043] refer to Figure 6 and Figure 11 As shown, a portion of the power line segment in the first power signal line PVDD1 corresponds to multiple connection vias ( Figure 11 The circled position on the first power signal line PVDD1 (which is the location of the connecting via) is used for hole connection with components in the pixel circuit 100 (such as the storage capacitor Cst and the first light-emitting control transistor T1). In the prior art, when the first power signal line PVDD1 is set as a whole, a part of the power line segment does not overlap with the connecting via (this part of the power line segment connects between two adjacent power line segments that overlap with the connecting via). In this application, a break D can be set at this part of the power line segment that does not overlap with the connecting via to ensure that the hole connection between the first power signal line PVDD1 and the pixel circuit 100 is not affected.

[0044] refer to Figure 12 As shown (for comparison) Figure 5In some designs, irregularly shaped anodes can be designed to increase the area of ​​the anode (such as the third anode 230a). This allows the anode 200a to shield components of the pixel circuit 100 (such as the initialization transistor T5 and the threshold compensation transistor T4), preventing light from affecting transistor performance and ensuring circuit stability. It also increases the pixel aperture ratio. Based on this design, since the third anode 230a shields most of the first power signal line PVDD1, especially the portion of PVDD1 that does not overlap with the connecting via, the space for setting the break is limited, thus limiting the effect of improving light transmittance. Therefore, it is possible to choose to maintain the connection between two adjacent first power line segments PVDDa corresponding to two adjacent third pixel circuits 130.

[0045] Optionally, refer to Figure 12 As shown, the third light-emitting element 230 is a blue light-emitting element, and one of the first light-emitting element 210 and the second light-emitting element 220 is a red light-emitting element, while the other is a green light-emitting element. In this way, the size design of the anode area can be matched to the unbalanced luminous efficiency of the three colors of light-emitting elements (red, green, and blue), thus extending the service life of the display panel.

[0046] refer to Figure 2 and Figure 6 As shown, optionally, the signal line 101 further includes a first type of signal line 101a extending along the second direction Y and arranged along the first direction X; the region where the break point D is located overlaps with at most one first type of signal line 101a; along the first direction X, the width of the first type of signal line 101a is less than the length of the break point D. For example, the width of the first type of signal line 101a is less than 3 μm.

[0047] Specifically, in addition to signal lines extending along the first direction X and arranged along the second direction Y (such as the first power signal line PVDD1 and the data signal line DATA), the display panel 10 is also provided with a number of signal lines extending along the second direction Y and arranged along the first direction X (collectively referred to as the first type of signal lines 101a).

[0048] refer to Figure 6 As shown, the first type of signal line 101a includes an initialization signal line VREF, scan signal lines (such as the first scan signal line S1, the second scan signal line S2, and the third scan signal line SP), and a light emission control signal line EMIT.

[0049] Since the extension directions of the first power signal line PVDD1 and the first type signal line 101a intersect, the fewer the first type signal lines 101a overlap with the area where the break point D is located, the better the light transmittance will be. In this embodiment, the area where the break point D is located overlaps with at most one first type signal line 101a. That is, the area where the break point D is located does not overlap with the first type signal line 101a, or the area where the break point D is located overlaps with only one first type signal line 101a. Furthermore, when the area where the break point D is located overlaps with one first type signal line 101a, the width of the first type signal line 101a in the first direction X is less than the length of the break point D. This setting can avoid the first type signal line 101a from excessively blocking the break point D, thus affecting the improvement of light transmittance.

[0050] refer to Figure 6 As shown, optionally, the length of the region containing the fracture D along the first direction X is greater than 3 μm. This setting helps to balance process capability and light transmission effect.

[0051] refer to Figure 6 and Figure 7 The display panel 10 includes an active layer POLY; optionally, corresponding to a pixel circuit 100, the active layer POLY includes a first active pattern P1 and a second active pattern P2; the first active pattern P1 includes an active portion corresponding to an initialization transistor T5, a threshold compensation transistor T4, a driving transistor T3, a reset transistor T7, a first light-emitting control transistor T1, and a second light-emitting control transistor T6 (the active portion corresponding to each transistor is shown in the dashed box); the second active pattern P2 includes an active portion corresponding to a data writing transistor T2; along the second direction X, there is a first gap space Q between the first active pattern P1 and the second active pattern P2, and the area where the break point D is located overlaps with the first gap space Q.

[0052] Specifically, the lines in the area where the first active pattern P1 is located are relatively dense, while the lines in the first gap space Q are less dense. Originally, the first power signal line PVDD1, which was a whole line, passed through the first gap space Q between the first active pattern P1 and the second active pattern P2. This application improves the light transmittance by setting the break point D at the position where the first power signal line PVDD1 overlaps with the first gap space Q, that is, by setting the area where the break point D is located to overlap with the first gap space Q.

[0053] refer to Figure 5 , Figure 6 and Figure 9As shown, signal line 101 includes a first scan signal line S1, a second scan signal line S2, a third scan signal line SP, and a light emission control signal line EMIT, which are arranged on the same layer and spaced apart along the first direction X. The first scan signal line S1 is electrically connected to the gate of the initialization transistor T5, the second scan signal line S2 is electrically connected to the gate of the threshold compensation transistor T4, the third scan signal line SP is electrically connected to the gate of the data writing transistor T2 and the gate of the reset transistor T7, and the light emission control signal line EMIT is electrically connected to the gates of the first light emission control transistor T1 and the second light emission control transistor T6. Optionally, along the direction perpendicular to the light-emitting surface of the display panel, the first scan signal line S1, the second scan signal line S2, and the light emission control signal line EMIT all overlap with the first active pattern P1 and do not overlap with the second active pattern P2. The third scan signal line SP overlaps with the first active pattern P1, the second active pattern P2, and the area where the break point D is located. Along the first direction X, the length of the area where the break point D is located is greater than the width of the third scan signal line SP.

[0054] Specifically, the position where the first scan signal line S1 overlaps with the first active pattern P1 is the position of the gate of the initialization transistor T5. The overlap enables the first scan signal line S1 to control the conduction or deactivation of the initialization transistor T5. Similarly, the position where the second scan signal line S2 overlaps with the first active pattern P1 is the position of the gate of the threshold compensation transistor T4. The position where the third scan signal line SP overlaps with the first active pattern P1 is the position of the gate of the reset transistor T7. The position where the third scan signal line SP overlaps with the second active pattern P2 is the position of the gate of the data writing transistor T2. The two overlapping positions of the light emission control signal line EMIT with the first active pattern P1 are the positions of the gates of the first light emission control transistor T1 and the second light emission control transistor T2.

[0055] refer to Figure 6 As shown, in this embodiment, for the initialization signal line VREF, the first scan signal line S1, the second scan signal line S2, the third scan signal line SP, and the light emission control signal line EMIT, which extend along the second direction Y and are arranged along the first direction X, the area where the break point D is located only overlaps with the third scan signal line SP, and the length of the area where the break point D is located in the first direction X is greater than the width of the third scan signal line SP in the first direction X. This can minimize the impact of other traces on the light transmittance improvement effect. (Reference) Figure 5 As shown, since the fracture point D is located in the area outside the anode 200a, and only the third scan signal line SP overlaps with the fracture point D, the area of ​​the area where the fracture point D is located minus the area of ​​the part of the third scan line SP that overlaps with the fracture point D is the actual increase in the light-transmitting area.

[0056] refer to Figure 5As shown, optionally, the anode 200a includes a first type anode 200a1 and a second type anode 200a2, the first type anode 200a1 and the second type anode 200a2 are alternately arranged in the first direction X and staggered in the second direction Y; along the direction perpendicular to the light-emitting surface of the display panel, the first type anode 200a1 overlaps with one pixel circuit row, and the second type anode 200a2 overlaps with two adjacent pixel circuit rows; the pixel circuit row includes a plurality of pixel circuits 100 arranged along the second direction X.

[0057] For details, please refer to Figure 5 As shown, one pixel circuit group 11 corresponds to one light-emitting unit (first light-emitting element 210, second light-emitting element 220, and third light-emitting element 230). Multiple light-emitting units in the display panel include first and second light-emitting units arranged alternately side-by-side along the second direction Y. The center line connecting the three anodes 200a of the three light-emitting elements 200 in the first light-emitting unit forms a first acute-angled triangle A1. The center line connecting the three anodes 200a of the three light-emitting elements 200 in the second light-emitting unit forms a second acute-angled triangle A2. The shapes of the first acute-angled triangle A1 and the second acute-angled triangle A2 are inverted in the first direction X, forming an overall layout where the first type of anodes 200a1 and the second type of anodes 200a2 are alternately arranged in the first direction X and staggered in the second direction Y. Specifically, the first type of anode 200a1 overlaps only with one row of pixel circuits 100, and the second type of anode 200a2 overlaps with two adjacent rows of pixel circuits 100.

[0058] For example, refer to Figure 5 As shown, in the first light-emitting unit corresponding to the first acute triangle A1, the first anode 210a of the first light-emitting element 210 and the third anode 230a of the third light-emitting element 230 are first-type anodes 200a1, which only overlap with the pixel circuit row where the pixel circuit group 11 corresponding to the light-emitting unit is located (the overlapping area is relatively large). The second anode 220a of the second light-emitting element 220 is a second-type anode 200a2, which not only overlaps with the pixel circuit row where the pixel circuit group 11 corresponding to the light-emitting unit is located (the overlapping area is relatively small), but also overlaps with the next row of pixel circuits 100 (only the position overlaps, there is no electrical connection). The arrangement of the second light-emitting unit is reversed compared to that of the first light-emitting unit. Therefore, in the second light-emitting unit corresponding to the second acute triangle A2, the first anode 210a of the first light-emitting element 210 and the third anode 230a of the third light-emitting element 230 are second-type anodes 200a2 (arranged side by side with the second anode 220a of the second light-emitting element 220a in the first light-emitting unit), and the second anode 220a of the second light-emitting element 220 is a first-type anode 200a1 (arranged side by side with the first anode 210a of the first light-emitting element 210 and the third anode 230a of the third light-emitting element 230 in the first light-emitting unit).

[0059] The arrangement of the anodes determines the pixel arrangement. The aforementioned anode arrangement places the pixels diagonally on the display panel. Because the diagonal direction is longer, more space can be used to create pixel apertures while still meeting the minimum pixel pitch requirement, thus increasing the pixel aperture ratio and simultaneously increasing the anode area. However, a larger anode area results in lower light transmittance of the display panel. This embodiment of the invention addresses this by setting a break D on the first power signal line PVDD1 and ensuring that the area of ​​break D does not overlap with the anode 200a. This reduces the impact of increased anode area on the light transmittance of the display panel to a certain extent, ensuring that the light transmittance of the display panel meets the requirements.

[0060] Furthermore, based on the above anode arrangement and the relative positional relationship between the anode and the pixel circuit, refer to Figure 5 and Figure 6 As shown, the pixel circuit 100 includes a first light-emitting control transistor T1, which is electrically connected to a first power signal line PVDD1. Optionally, along the first direction X, the area where the break point D is located is between the adjacent first light-emitting control transistor T1 and the second type anode 200a2.

[0061] Specifically, the first light-emitting control transistor T1 is electrically connected to the first power signal line PVDD1 through a connecting via. In the area between the side of the first light-emitting control transistor T1 away from the storage capacitor Cst and the second type anode 200a2, the metal trace density is low. By setting the area where the break point D is located between the adjacent first light-emitting control transistor T1 and the second type anode 200a2, it is beneficial to reduce the influence of other metal traces on light transmittance, thereby effectively improving light transmittance.

[0062] refer to Figure 5 , Figure 6 and Figure 10 The pixel circuit 100 includes a storage capacitor Cst, which includes a first capacitor plate C1 electrically connected to the first power signal line PVDD. Optionally, the display panel also includes a first connection structure 102. Along the second direction Y, the first connection structure 102 is connected between two adjacent first capacitor plates C1.

[0063] Since the first capacitor plate C1 (upper plate) of the storage capacitor Cst is connected to the first power signal line PVDD1 by drilling, and the two adjacent first capacitor plates C1 are connected by setting the first connection structure 102, the first capacitor plate C1 and the first connection structure 102 can be used to form the second power signal line PVDD2 extending along the second direction Y, so as to realize the double-layer grid design of the power signal line PVDD.

[0064] refer to Figure 10The first capacitor plate C1 is located in the capacitor metal layer Mc, and the initialization signal line VREF is also in the same layer. Optionally, along the first direction X, at least part of the width of the first connection structure 102 is greater than the width of the initialization signal line VREF.

[0065] Specifically, since the first power signal line PVDD1 has a break D, the transmission impedance of the power signal (PVDD) is increased. By increasing the width of at least part of the first connection structure 102 so that the width of at least part of the first connection structure 102 is greater than the width of the initialization signal line VREF, the effect of the increased impedance caused by the disconnection of the first power signal line PVDD1 can be offset / improved, and the normal transmission of the power signal (PVDD) can be guaranteed.

[0066] For example, Figure 10 The illustration is based on the example where the width of all first connection structures 102 is greater than the width of the initial signal line VREF. In other embodiments, only a portion of the first connection structures 102 may have their width increased. For example, Figure 15 This is a schematic diagram of a portion of the structure of a display panel provided in an embodiment of the present invention, for reference. Figure 5 and Figure 15 As shown, the first connection structure 102 includes a first sub-connection structure 1021 and a second sub-connection structure 1022. Along the direction perpendicular to the light-emitting surface of the display panel, the anode 200a covers the first sub-connection structure 1021, and the second sub-connection structure 1022 does not overlap with the anode 200a. Optionally, in the first direction X, the width of the first sub-connection structure 1021 is greater than the width of the second sub-connection structure 1022.

[0067] Specifically, among the multiple first connection structures 102, the first sub-connection structure 1021 is covered by the anode 200a, and the second sub-connection structure 1022 does not overlap with the anode 200a. By setting the width of the first sub-connection structure 1021 to be greater than the width of the second sub-connection structure 1022, for example, the width of the second sub-connection structure 1022 remains unchanged, and only the width of the first sub-connection structure 1021 covered by the anode 200a is increased (the widened first sub-connection structure 1021 is still covered by the anode 200a), the actual light-shielding area of ​​the first connection structure 102 remains unchanged, avoiding the reduction of impedance due to the increase in the width of the first connection structure 102, which would affect the light transmittance.

[0068] Optionally, the width of the second sub-connection structure 1022 is equal to the width of the initialization signal line VREF, and the width of the first sub-connection structure 1021 is greater than the width of the initialization signal line VREF.

[0069] In addition, refer to Figure 10As shown, optionally, the display panel may further include a third power signal line PVDD3. The third power signal line PVDD3 extends along the second direction Y and is arranged along the first direction X, and is electrically connected to the first power signal line PVDD1. In a direction perpendicular to the light-emitting surface of the display panel, the third power signal line PVDD3 overlaps with the active portions of the dual-gate initialization transistor T5 and the threshold compensation transistor T4. This avoids the impact of light on the performance of the initialization transistor T5 and the threshold compensation transistor T4, and also reduces the impedance of the power signal PVDD, further mitigating the impact of the increased impedance caused by the disconnection of the first power signal line PVDD1.

[0070] Based on the same inventive concept, embodiments of the present invention also provide a display device. For example, Figure 16 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 16 As shown, the display device 20 includes the display panel 10 provided in any of the above embodiments, and therefore has the same beneficial effects as the above display panel. The similarities can be found in the descriptions of the above embodiments, and will not be repeated here. The display device 20 can be an OLED display device. Additionally, the display device 200 provided in the embodiments of the present invention can be... Figure 16 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet, digital camera, smart bracelet, smart glasses, in-vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on this.

[0071] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: Signal lines; the signal lines include first power signal lines extending in a first direction and arranged in a second direction; The first direction and the second direction intersect; Light-emitting elements; The light-emitting element includes an anode; The first power signal line includes a break along a direction perpendicular to the light-emitting surface of the display panel, and the area where the break is located does not overlap with the anode.

2. The display panel according to claim 1, characterized in that, The display panel further includes a pixel circuit; the pixel circuit includes a storage capacitor; Along the direction perpendicular to the light-emitting surface of the display panel, the area where the break is located does not overlap with the storage capacitor.

3. The display panel according to claim 1, characterized in that, The display panel further includes a pixel circuit group arranged in an array along the first direction and the second direction; one pixel circuit group includes three pixel circuits arranged along the second direction; The first power signal line includes a first power line segment, and the first power line segment is configured to correspond one-to-one with the pixel circuit; along the first direction, in at least one group of two adjacent pixel circuit groups, there is a break between two adjacent first power line segments.

4. The display panel according to claim 3, characterized in that, Along the first direction, in two adjacent pixel circuit groups, there is a break between two adjacent first power supply segments.

5. The display panel according to claim 4, characterized in that, The pixel circuit group includes a first pixel circuit, a second pixel circuit, and a third pixel circuit arranged side by side along the second direction; The light-emitting element includes a first light-emitting element, a second light-emitting element, and a third light-emitting element. The first light-emitting element includes a first anode, the second light-emitting element includes a second anode, and the third light-emitting element includes a third anode. The first pixel circuit is electrically connected to the first anode, the second pixel circuit is electrically connected to the second anode, and the third pixel circuit is electrically connected to the third anode. The area of ​​the first anode and the area of ​​the second anode are both smaller than the area of ​​the third anode; along the first direction, in two adjacent pixel circuit groups, there is a break between two adjacent first power supply lines corresponding to two adjacent first pixel circuits, there is a break between two adjacent first power supply lines corresponding to two adjacent second pixel circuits, and two adjacent first power supply lines corresponding to two adjacent third pixel circuits are connected.

6. The display panel according to claim 1, characterized in that, The display panel further includes pixel circuits arranged in an array along the first direction and the second direction. The pixel circuits include a first light-emitting control transistor, which is electrically connected to the first power signal line. The anode includes a first type of anode and a second type of anode, which are alternately arranged in the first direction and staggered in the second direction; along the direction perpendicular to the light-emitting surface of the display panel, the first type of anode overlaps with one pixel circuit row, and the second type of anode overlaps with two adjacent pixel circuit rows; the pixel circuit row includes a plurality of pixel circuits arranged along the second direction; Along the first direction, the region where the break is located is situated between the adjacent first light-emitting control transistor and the second type of anode.

7. The display panel according to claim 1, characterized in that, The signal lines also include a first type of signal lines extending along the second direction and arranged along the first direction; the first type of signal lines include initialization signal lines, scan signal lines, and light emission control signal lines. The area where the fracture is located overlaps with at most one of the first type of signal lines; along the first direction, the width of the first type of signal line is less than 3 μm.

8. The display panel according to claim 1, characterized in that, Along the first direction, the length of the region where the fracture is located is greater than 3 μm.

9. The display panel according to claim 1, characterized in that, The display panel also includes: Pixel circuit; the pixel circuit includes a storage capacitor, the storage capacitor including a first capacitor plate electrically connected to the first power signal line; A first connection structure; along the second direction, the first connection structure is connected between two adjacent first capacitor plates; The first connection structure includes a first sub-connection structure and a second sub-connection structure. Along a direction perpendicular to the light-emitting surface of the display panel, the anode covers the first sub-connection structure, and the second sub-connection structure does not overlap with the anode. In the first direction, the width of the first sub-connection structure is greater than the width of the second sub-connection structure.

10. The display panel according to claim 1, characterized in that, The display panel further includes a pixel circuit, which includes an initialization transistor, a threshold compensation transistor, a driving transistor, a reset transistor, a first light-emitting control transistor, a second light-emitting control transistor, and a data writing transistor. The display panel further includes an active layer; corresponding to one pixel circuit, the active layer includes a first active pattern and a second active pattern; the first active pattern includes the active portions corresponding to the initialization transistor, the threshold compensation transistor, the driving transistor, the reset transistor, the first light-emitting control transistor, and the second light-emitting control transistor; the second active pattern includes the active portion corresponding to the data writing transistor; Along the second direction, there is a first gap space between the first active pattern and the second active pattern, and the area where the break is located overlaps with the first gap space.

11. The display panel according to claim 10, characterized in that, The signal lines also include a first scan signal line, a second scan signal line, a third scan signal line, and a light emission control signal line, which are arranged at intervals along the same layer in the first direction; The first scan signal line is electrically connected to the gate of the initialization transistor, the second scan signal line is electrically connected to the gate of the threshold compensation transistor, the third scan signal line is electrically connected to the gate of the data writing transistor and the gate of the reset transistor, and the light emission control signal line is electrically connected to the gates of the first light emission control transistor and the second light emission control transistor. Along the direction perpendicular to the light-emitting surface of the display panel, the first scanning signal line, the second scanning signal line, and the light-emitting control signal line all overlap with the first active pattern, but do not overlap with the second active pattern. The third scanning signal line overlaps with the first active pattern, the second active pattern, and the area where the break is located. Along the first direction, the length of the region where the break is located is greater than the width of the third scan signal line.

12. A display device, characterized in that, Includes the display panel as described in any one of claims 1-11.

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