Display device and method of manufacturing the same

Abstract

The present disclosure relates to a display device and a manufacturing method thereof. The display device includes a thin film transistor and a light emitting device disposed in each of a plurality of subpixels, an encapsulation layer disposed above the light emitting device, a touch sensor disposed on the encapsulation layer, a connection line extending from a non-display area to the touch sensor, and a touch planarization layer disposed on the touch sensor and the connection line, wherein an end portion of the touch planarization layer in the non-display area is disposed directly on a bank layer in the non-display area.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0055983, filed in Korea on April 29, 2025, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device and a method for manufacturing the same. Background Technology

[0003] A touch panel is a type of input device installed in various display devices such as liquid crystal display (LCD) devices, organic light-emitting display (OLED) devices, and electrophoretic display (EPD) devices, and enables users to input information by directly touching the screen with their fingers or a pen while viewing the display device. Summary of the Invention

[0004] The display device according to this disclosure includes a thin-film transistor and a light-emitting device disposed in each of a plurality of sub-pixels, an encapsulation layer disposed above the light-emitting device, a touch sensor disposed on the encapsulation layer, at least one link line extending from a non-display area to the touch sensor, and a touch planarization layer disposed on the touch sensor and the at least one link line, wherein the end of the touch planarization layer in the non-display area is directly disposed on the embankment layer in the non-display area.

[0005] The at least one connection line includes a first connection line extending into the non-display area to be electrically connected to the touch sensor and a second connection line electrically connected to the first connection line in the non-display area to apply a touch signal to the first connection line.

[0006] The second connecting line is disposed in the first non-display area, and the first connecting line and the second connecting line are connected to each other in the first non-display area or the second non-display area.

[0007] The thin-film transistor includes a semiconductor layer, a gate insulating layer on the semiconductor layer, a gate electrode on the gate insulating layer, an interlayer insulating layer, and a source electrode and a drain electrode on the interlayer insulating layer. A first planarization layer is disposed on the thin-film transistor, a connection pattern electrically connected to the drain electrode is disposed on the first planarization layer, and a second planarization layer is disposed on the connection pattern.

[0008] Contact holes are formed in the second planarization layer, such that the first connecting line and the second connecting line are electrically connected to each other within the contact holes. In some embodiments, the first connecting line may be made of the same material as the touch electrodes of the touch sensor, and the second connecting line may be made of the same material as the connecting pattern.

[0009] Contact holes can be formed in the first and second planarization layers, allowing the first and second connecting lines to be electrically connected to each other within the contact holes. In some embodiments, the first connecting line is made of the same material as the touch electrodes of the touch sensor, and the second connecting line is made of the same material as the source and drain electrodes.

[0010] The embankment layer in the first non-display area includes a protruding portion that protrudes toward the curved area. The thickness of the protruding portion is less than the thickness of the remaining portion of the embankment layer, and the end of the touch planarization layer is directly disposed on the protruding portion of the embankment layer.

[0011] A method of manufacturing a display device includes providing a substrate comprising a display area and a non-display area, wherein the display area has a plurality of sub-pixels, and wherein the non-display area comprises (i) a second non-display area disposed outside and adjacent to the display area, (ii) a first non-display area outside the second non-display area, and (iii) a curved area between the first non-display area and the second non-display area, forming a first touch line in the non-display area, forming a dam layer between the sub-pixels of the display area and in the non-display area, providing thin-film transistors and light-emitting devices in the sub-pixels, forming an encapsulation layer over the light-emitting devices except in the first non-display area, forming a touch buffer layer on the encapsulation layer, etching the touch buffer layer of the first non-display area to expose a portion of the dam layer to the outside, forming a touch sensor and a second touch line on the touch buffer layer, and forming a touch planarization layer on the touch sensor and the second touch line, wherein an end of the touch planarization layer contacts an upper surface of the exposed portion of the dam layer. Attached Figure Description

[0012] Figure 1 This is a schematic block diagram of an example of a display device according to the present disclosure.

[0013] Figure 2 yes Figure 1 A schematic block diagram of an example of a subpixel of a display device.

[0014] Figure 3 This is a circuit diagram that conceptually illustrates an example of a sub-pixel of a display device according to the present disclosure.

[0015] Figure 4 This is a plan view of an example of a display device according to the first embodiment of the present disclosure.

[0016] Figure 5 yes Figure 4 A magnified plan view of a sample area A.

[0017] Figure 6 It is along Figure 5 A cross-sectional view of an example taken from line I-I'.

[0018] Figure 7A and Figure 7B They are Figure 6 An enlarged cross-sectional view of an example of region B. Figure 7A This is an enlarged cross-sectional view of an example of a display device with a general structure. Figure 7B This is an enlarged cross-sectional view of an example of a display device according to the present disclosure.

[0019] Figures 8A to 8F This is a view illustrating an example of a method for manufacturing a display device according to this disclosure.

[0020] Figure 9 This is a view showing an example of the structure of a display device according to a second embodiment of the present disclosure.

[0021] Figure 10 This is a view showing an example of the structure of a display device according to a third embodiment of the present disclosure. Detailed Implementation

[0022] This disclosure relates to a display device and a method of manufacturing the same, and more specifically, to a display device capable of preventing defects caused by the disconnection of the touch line.

[0023] Touch panels can be implemented using an external method to attach to the outside of the display panel, or using an embedded method to be installed inside the display panel. Specifically, embedded display panels can be used to realize thin and portable terminal devices such as smartphones, tablets, and laptops.

[0024] However, in embedded display panels, touch lines are often formed inside the display panel, which may lead to problems where touch cannot be recognized when there are defects in the touch lines of the touch panel when touch signals are applied.

[0025] Embodiments of this disclosure may provide a display device and a method for manufacturing the same, which can prevent touch line separation that may occur due to layer separation in the connection area of ​​the touch line.

[0026] Another embodiment of this disclosure may provide a display device that can prevent foreign substances (e.g., moisture) from seeping in from the outside due to cracks generated in the connection area of ​​the touch line.

[0027] Another embodiment of this disclosure may also provide an environmentally friendly display device that minimizes the emission of harmful substances.

[0028] The advantages and features of this disclosure, as well as the methods for implementing them, will become clear from the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. The embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art to which it pertains. This disclosure is defined only by the scope of the appended claims.

[0029] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings for describing embodiments of the present disclosure are illustrative, and therefore the present disclosure is not limited to what is shown. Throughout the present disclosure, the same reference numerals refer to the same components. Furthermore, in the following description of the present disclosure, detailed descriptions of known related technologies will be omitted where it is determined that such detailed descriptions unnecessarily obscure the spirit of the present disclosure. When terms such as "comprising," "having," or "including" are used in the present disclosure, other parts may be added unless the term "only" is used herein. When a component is indicated as singular, the plural is included unless otherwise stated.

[0030] When analyzing components, even if there is no explicit description, it should be interpreted as including the error range.

[0031] When describing positional relationships, for example, when the positional relationship between two parts is described as "above", "over", "below", "near", etc., one or more other parts may be located between the two parts unless "immediately" or "directly" is used.

[0032] When describing temporal relationships, for example, when using words such as "after," "following," "next," or "before" to describe the sequence of events, non-continuous situations can also be included unless "immediately" or "directly" is used.

[0033] Although the terms first, second, etc., are used to describe various components, these components are not substantially limited by these terms. These terms are only used to distinguish one component from another. Therefore, within the technical spirit of this disclosure, the first component described below can be substantially the second component.

[0034] In describing the components of this disclosure, terms such as first, second, A, B, (a), (b), etc., may be used. These terms are used only to distinguish one component from another, and the nature, order, or number of components is not limited by these terms. When describing a component as "connected" or "coupled" to another component, the component may be directly connected to the other component, but may be indirectly connected to the other component without specific description. It should be understood that other components may be "inserted" between any two connected or potentially connected components.

[0035] As used herein, the term "apparatus" can include display apparatuses, such as liquid crystal modules (LCMs) including display panels and driving units for driving the display panels, and organic light-emitting display modules (OLED modules). Furthermore, the term "apparatus" can also include notebook computers, televisions, computer monitors, vehicle electrical systems including devices for vehicles or other types of vehicles, and sets of electronic apparatus or assemblies that are finished products (complete or final products) including LCMs and OLED modules, such as mobile electronic devices or electronic boards for smartphones.

[0036] Therefore, the apparatus in this disclosure may include the display device itself, such as an LCM or OLED module, as well as application products including an LCM or OLED module, or complete sets of apparatus as end users.

[0037] In the following, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0038] Figure 1 This is a schematic block diagram of an organic light-emitting display device according to the present disclosure. Figure 2 It is a schematic block diagram of its sub-pixels.

[0039] like Figure 1 As shown, the organic light-emitting display device 100 includes an image processing unit 102, a timing control unit 104, a gate driving unit 106, a data driving unit 107, a power supply unit 108, and a display panel 109.

[0040] The image processing unit 102 outputs image data provided from the outside and drive signals for driving various devices. For example, the drive signals from the image processing unit 102 may include data enable signals, vertical synchronization signals, horizontal synchronization signals, and clock signals.

[0041] Image data and drive signals are provided from image processing unit 102 to timing control unit 104. Timing control unit 104 writes and outputs gate timing control signal GDC for controlling the drive timing of gate drive unit 106 and data timing control signal DDC for controlling the drive timing of data drive unit 107 based on the drive signals from image processing unit 102.

[0042] The gate driving unit 106 outputs a scan signal to the display panel 109 in response to a gate timing control signal GDC provided from the timing control unit 104. The gate driving unit 106 outputs the scan signal through multiple gate lines GL1 to GLm. In this case, the gate driving unit 106 may be formed in the form of an integrated circuit (IC), but is not limited thereto.

[0043] The data driving unit 107 outputs a data voltage to the display panel 109 in response to a data timing control signal DDC input from the timing control unit 104. The data driving unit 107 samples and latches the digital data signal DATA provided from the timing control unit 104 to convert it into an analog data voltage based on the gamma voltage. The data driving unit 107 outputs the data voltage through multiple data lines DL1 to DLn. In this case, the data driving unit 107 can be mounted on the upper surface of the display panel 109 in the form of an integrated circuit (IC), but is not limited thereto.

[0044] The power supply unit 108 outputs a high-potential voltage VDD and a low-potential voltage VSS to provide them to the display panel 109. The high-potential voltage VDD is provided to the display panel 109 through a first power line EVDD, and the low-potential voltage VSS is provided to the display panel 109 through a second power line EVSS. In some embodiments, the voltage from the power supply unit 108 is applied to the data driving unit 107 or the gate driving unit 106 to drive them.

[0045] The display panel 109 displays images based on the data voltage from the data driving unit 107, the scan signal from the gate driving unit 106, and the power from the power supply unit 108.

[0046] The display panel (PAN) includes multiple subpixels (SPs) for displaying images. Subpixels (SPs) may include red, green, and blue subpixels. Additionally, subpixels (SPs) may include white, red, green, and blue subpixels. White, red, green, and blue subpixels may be formed in the same area or in different areas.

[0047] like Figure 2 As shown, a sub-pixel SP can be connected to gate line GL1, data line DL1, first power line EVDD, and second power line EVSS. The number of transistors and capacitors disposed in the sub-pixel SP and the driving method are determined according to the configuration of the pixel circuit of the sub-pixel SP.

[0048] Figure 3 This is a circuit diagram showing the sub-pixel SP of the organic light-emitting display device 100 according to the present disclosure.

[0049] like Figure 3 As shown, the organic light-emitting display device 100 according to this disclosure includes intersecting gate lines GL, data lines DL, and power lines PL to define sub-pixels SP. Switching thin-film transistors Ts, driving thin-film transistors DT, storage capacitors Cst, and organic light-emitting devices D are disposed in the sub-pixels SP.

[0050] The switching thin-film transistor Ts is connected to the gate line GL and the data line DL. The driving thin-film transistor Td and the storage capacitor Cst are connected between the switching thin-film transistor Ts and the power line PL. The organic light-emitting device D is connected to the driving thin-film transistor Td.

[0051] In an organic light-emitting display device with this structure, when the switching thin-film transistor Ts is turned on according to the gate signal applied to the gate line GL, the data signal applied to the data line DL is applied to the gate electrode of the driving thin-film transistor Td and one electrode of the storage capacitor Cst through the switching thin-film transistor Ts.

[0052] The driving thin-film transistor Td is turned on according to the data signal applied to the gate electrode. As a result, a current proportional to the data signal is supplied from the power line PL through the driving thin-film transistor Td to the organic light-emitting device D, and then the organic light-emitting device D emits light with a brightness proportional to the current flowing through the driving thin-film transistor Td. Although not shown in the figure, a light-emitting control thin-film transistor can be disposed between the driving thin-film transistor Td and the organic light-emitting device D.

[0053] In some implementations, the storage capacitor Cst is charged with a voltage proportional to the data signal to maintain a constant voltage at the gate electrode of the driving thin-film transistor Td within a frame.

[0054] The figure shows only two thin-film transistors Td and Ts and one capacitor Cst, but this disclosure is not limited thereto. Three or more thin-film transistors and two or more capacitors may be provided in this disclosure.

[0055] In the following, a display device according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0056] Figure 4 This is a plan view of an example of a display device 100 according to the present disclosure.

[0057] like Figure 4 As shown, according to an embodiment of the display device 100 of this disclosure, there is a display area AA for displaying an image and a non-display area NA outside the display area AA.

[0058] For example, the display device 100 may be a flexible display device. In this case, the substrate of the display device 100 is a flexible substrate and a base member made of an insulating material for supporting the various components of the display device 100. For example, the substrate may be made of a flexible plastic material such as polyimide (PI).

[0059] In some embodiments, the display device 100 may have non-rectangular corner regions, and the display area AA may have a shape corresponding to the non-rectangular corner regions. For example, the corner between the display area AA and the non-display area NA may be rounded. However, the display device 100 of this disclosure is not limited to this shape, but can be formed into various shapes depending on the design of the installed electronic devices.

[0060] Pixel P, comprising multiple sub-pixels SP1, SP2, and SP3, is disposed in display area AA. In this case, each of sub-pixels SP1, SP2, and SP3 may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. Furthermore, pixel P may also include a white (W) sub-pixel.

[0061] Multiple gate lines and data lines are arranged in the display area AA to define multiple sub-pixels SP in the intersection area of ​​the gate lines and data lines. In each sub-pixel SP1, SP2 and SP3, a thin-film transistor as a switching device and a display device for displaying an image are arranged.

[0062] Display devices can include a variety of display devices. For example, a display device can be an organic light-emitting display device, a liquid crystal display device, a quantum dot display device, a micro LED display device, or a mini LED display device.

[0063] The non-display area NA is the area where no image is displayed. Various signal lines and circuits used to drive the display elements of the display area AA are located in the non-display area NA. For example, the gate drive unit 106, the data drive unit (not shown), the connection line LNK, and multiple pads PADs can be located in the non-display area NA. The non-display area NA can be a border area, and the configuration described in this specification is not limited to this.

[0064] In some embodiments, the non-display area NA includes a first non-display area NA1, a curved area BA, and a second non-display area NA2. The second non-display area NA2 is a region directly disposed outside and extending from the display area AA. The curved area BA is a region extending from the second non-display area NA2 and can be positioned in conjunction with... Figure 1 The curve bends along the horizontal curve in the direction indicated by the arrow. The first non-displayed area NA1 extends from the curved area BA.

[0065] Multiple connection lines (LNKs) and multiple pads (PADs) can be arranged in the first non-display area NA1. Each of the multiple pads connects a connection line (LNK) to a flexible film or printed circuit board. Each connection line (LNK) connects a pad (PAD) to the display area AA.

[0066] The pads include multiple first pads PAD1, multiple second pads PAD2, and multiple third pads PAD3. The multiple first pads PAD1 are disposed on both sides of a first non-display area NA1, and the multiple second pads PAD2 and third pads PAD3 are disposed at the center of the first non-display area NA1. For example, the multiple second pads PAD2 can be disposed between the multiple first pads PAD1, and the multiple third pads PAD3 can be disposed between the multiple second pads PAD2.

[0067] The connecting line LNK includes multiple first connecting lines LNK1, multiple second connecting lines LNK2, and multiple third connecting lines LNK3.

[0068] Multiple first pads PAD1 are electrically connected to multiple first connection lines LNK1. The first connection lines LNK1 can be connection lines connected to the gate drive unit 106.

[0069] Multiple second pads PAD2 are electrically connected to multiple second connection lines LNK2. The second connection lines LNK2 can be connection lines that connect to data lines, power lines, etc., located in the display area AA.

[0070] Multiple third pads (PAD3) are electrically connected to multiple third connection lines (LNK3). The third connection lines (LNK3) can be touch connection lines connected to the touch line.

[0071] A gate driving unit 106 is disposed in the second non-display area NA2. The gate driving unit 106 provides multiple scan signals to multiple gate lines GL according to multiple gate control signals provided from the timing control unit. Although Figure 4 Two gate driving units 106 are shown disposed on both sides of the display area AA, but the number and arrangement of the gate driving units 106 are not limited thereto.

[0072] In some implementations, the second non-display area NA2 is the area surrounding the display area AA, and a portion of the second non-display area NA2 may be disposed between the curved area BA and the display area AA. Multiple connection lines LNK, such as gate connection lines, power connection lines, data connection lines, and touch connection lines, may be disposed in the second non-display area NA2 to transmit signals from multiple pads PAD to the display area AA.

[0073] Figure 5 yes Figure 4 A magnified plan view of a region A example, showing details of the connecting line LNK.

[0074] like Figure 5As shown, the display panel PNL of the display device 100 includes a display area AA and a non-display area NA. The non-display area NA includes a first non-display area NA1, a second non-display area NA2, and a curved area BA.

[0075] The third connection line LNK3 is located in the first non-display area NA1, the second non-display area NA2, and the curved area BA. The third connection line LNK3 applies touch drive signals to the display panel PNL and receives touch signals from the touch panel.

[0076] Each of the multiple third connecting lines LNK3 includes a 3-1 connecting line LNK3-1 and a 3-2 connecting line LNK3-2. The 3-1 connecting line LNK3-1 may be located in the second non-display area NA2 and extend to the curved area BA and the second non-display area NA2, but is not limited thereto.

[0077] Although the 3-1 connecting line LNK3-1 and the 3-2 connecting line LNK3-2 have different widths to illustrate the positional relationship between the two connecting lines in the figure, the actual widths of the 3-1 connecting line LNK3-1 and the 3-2 connecting line LNK3-2 are the same.

[0078] Multiple contact holes (CNTs) are formed in the first non-display area NA1. As described later, 3-1 connecting lines LNK3-1 and 3-2 connecting lines LNK3-2 are formed on different layers with an insulating layer inserted between them, and the 3-1 connecting lines LNK3-1 and 3-2 connecting lines LNK3-2 are electrically connected through the contact holes (CNTs). Multiple third connecting lines LNK3 are arranged along the width direction of the curved area BA. In this case, the multiple third connecting lines LNK3 are spaced apart from each other by a predetermined distance d. In the figures, contact holes (CNTs) are formed in the first non-display area NA1, but this disclosure is not limited thereto. Contact holes (CNTs) may be formed in the curved area BA or the second non-display area NA2.

[0079] Each insulating layer can be disposed on the upper and lower portions of the third connecting lines LNK3 at the ends of the plurality of third connecting lines LNK3. In some embodiments, the insulating layers overlap each other. The insulating layers may include inorganic insulating layers and organic insulating layers. In some cases, problems may arise when inorganic and organic insulating layers overlap each other because the bonding strength between the inorganic and organic insulating layers may be reduced due to the boundary characteristics between them. As a result, the layers (e.g., inorganic and organic insulating layers) may separate from each other.

[0080] When layers separate from each other, foreign substances such as moisture can penetrate between the layers. This problem is further exacerbated by the creation of one or more cracks during delamination, which can further facilitate the penetration of foreign substances. For example, in… Figure 5 In the example, the separation of the layers can cause the ends of the 3-1 connecting lines LNK3-1, which are located above and below the layers, to delaminate, and the delamination of the third connecting line LNK3 can cause touch defects in the touch panel.

[0081] The embodiments of this disclosure can help reduce the occurrence of layer separation at the end of the 3-1 connecting line LNK3-1 (i.e., at the connection area between the 3-1 connecting line LNK3-1 and the 3-2 connecting line LNK3-2), thereby mitigating the defects caused by layer separation.

[0082] Hereinafter, an exemplary embodiment of the display device 100 that can reduce layer separation will be described in detail with reference to the accompanying drawings.

[0083] Figure 6 It is along Figure 5 The figure shows a cross-sectional view taken along line I-I', which specifically illustrates an example of the structure of the display device 100 according to an embodiment of the present disclosure. In the figure, for ease of description, only a portion of the display area AA and a portion of the non-display area NA are shown.

[0084] like Figure 6 As shown, the substrate 140 includes a display area AA and a non-display area NA, which includes a first non-display area NA1, a curved area BA, and a second non-display area NA2.

[0085] In some embodiments, the substrate 140 may be made of a plastic material, for example, the substrate may be made of at least one of polyimide, polymethyl methacrylate, polyethylene terephthalate, polyethersulfone and polycarbonate, but is not limited thereto.

[0086] When the substrate 140 is made of polyimide, the substrate 140 may be made of multiple polyimide layers, and inorganic layers may be further disposed between the polyimide layers, but not limited thereto.

[0087] A buffer layer 142 is formed on the substrate 140. The buffer layer 142 may be formed over the entire area of ​​the substrate 140 to enhance the adhesion between the substrate 140 and the layers thereon. In addition, the buffer layer 142 can block various types of defects, such as alkaline components flowing out of the substrate 140. Furthermore, the buffer layer 142 can delay the diffusion of moisture or oxygen that has permeated into the substrate 140.

[0088] The buffer layer 142 can be a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). When the buffer layer 142 is made of multiple layers, SiOx and SiNx can be formed alternately. Depending on the type and material of the substrate 140, the structure and type of the thin-film transistor, etc., the buffer layer 142 can be omitted.

[0089] Thin-film transistors are formed on the buffer layer in each sub-pixel SP1 and SP2. For ease of description, only the driving thin-film transistors among the various thin-film transistors that can be disposed in the display area AA are shown, but other thin-film transistors, such as switching thin-film transistors, may also be included. In the figure, a thin-film transistor with a top gate structure is shown, but the thin-film transistor is not limited to this structure and may be formed into other structures such as a thin-film transistor with a bottom gate structure.

[0090] The thin-film transistor includes a semiconductor pattern 112 disposed on a buffer layer 142, a gate insulating layer 144 covering the semiconductor pattern 112, a gate electrode 114 on the gate insulating layer 144, an interlayer insulating layer 146 covering the gate electrode 114, and a source electrode 115 and a drain electrode 116 on the interlayer insulating layer 146.

[0091] The semiconductor pattern 112 can be made of a polycrystalline semiconductor. For example, the polycrystalline semiconductor can be made of low-temperature polycrystalline silicon (LTPS) with high mobility, but is not limited to this.

[0092] The semiconductor pattern 112 can be made of oxide semiconductor. For example, the semiconductor pattern 112 can be made of one of IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), IGTO (indium gallium tin oxide), and IGO (indium gallium oxide), but is not limited thereto. The semiconductor pattern 112 includes a channel region 112a in the central region and source regions 112b and drain regions 112c, which are doped layers on both sides of the channel region 112a.

[0093] The gate insulating layer 144 may be composed of a single layer or multiple layers of inorganic materials such as SiOx or SiNx, but is not limited thereto.

[0094] The gate electrode 114 is made of metal. For example, the gate electrode 114 may be formed of a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof, but is not limited thereto.

[0095] The interlayer insulating layer 146 may be made of an organic material such as photosensitive acrylate, or it may be formed of a single layer or multiple layers of an inorganic material such as SiOx or SiNx, but is not limited thereto. Furthermore, the interlayer insulating layer 146 may be formed of multiple layers of organic and inorganic materials, but is not limited thereto.

[0096] The source electrode 115 and drain electrode 116 are formed of a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but are not limited thereto. The source electrode 115 and drain electrode 116 can contact the source region 112b and drain region 112c of the semiconductor pattern 112 through contact holes formed in the gate insulating layer 144 and the interlayer insulating layer 146, respectively.

[0097] Although not shown in the figure, a bottom shielding metal layer may be disposed on the substrate 140 below the semiconductor pattern 112. The bottom shielding metal layer minimizes back channeling caused by charges trapped in the substrate 140, thereby preventing image retention or degradation of transistor performance. The bottom shielding metal layer may be composed of a single layer or multiple layers of titanium (Ti), molybdenum (Mo), or alloys thereof, but is not limited thereto.

[0098] A first planarization layer 148 is formed on a substrate on which thin-film transistors are disposed. The first planarization layer 148 may be formed of an organic material such as photosensitive acrylate, but is not limited thereto. The first planarization layer 148 may include multiple layers, including inorganic layers and organic layers.

[0099] A connection pattern 154 is disposed on the first planarization layer 148 and electrically connected to the drain electrode 116 of the thin-film transistor T through a contact hole formed in the first planarization layer 148. The connection pattern 154 may be made of metal.

[0100] A second planarization layer 150 is formed on a first planarization layer 148 on which the connection pattern 154 is formed. The second planarization layer 150 may be formed of an organic material, such as a photosensitive acrylate, but is not limited thereto. The second planarization layer 150 may include multiple layers, including inorganic layers and organic layers. The second planarization layer 150 may be made of the same material as the first planarization layer 148, but may also be made of different materials.

[0101] In this disclosure, by forming the planarization layer as a two-layer structure including a first planarization layer 148 and a second planarization layer 150, various electrodes and signal lines can be formed between the first planarization layer 148 and the second planarization layer 150. Therefore, since the electrodes can be arranged vertically, the area caused by the electrodes and signal lines in the sub-pixels can be reduced, and thus the area of ​​the sub-pixels used in the high-resolution display device 100 can be reduced.

[0102] The light-emitting device D is disposed on the second planarization layer 150 in the display area AA. The light-emitting device D includes a first electrode 132, a light-emitting layer 134 (e.g., an organic layer) and a second electrode 136.

[0103] The first electrode 132 is disposed on the second planarization layer 150 and electrically connected to the drain electrode 116 of the thin-film transistor through a contact hole formed in the second planarization layer 150. The first electrode 132 may be formed of at least one of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or alloys thereof.

[0104] Furthermore, the first electrode 132 may be formed of a transparent metal oxide material such as indium tin oxide (ITO) or indium zinc oxide (IZO). When the first electrode 132 is formed of a transparent metal oxide, the first electrode 132 may also include a reflective electrode made of an opaque conductive material that reflects light.

[0105] The thin-film transistor T connected to the first electrode 132 can be a light-emitting control transistor.

[0106] A dam layer (BNK) is formed at the boundary between subpixels on the second planarization layer 150. The dam layer (BNK) can be a barrier wall to define the subpixels. The dam layer (BNK) separates each subpixel to prevent light of a specific color output from adjacent pixels from being mixed and output.

[0107] The embankment layer BNK is made of at least one of the following materials: inorganic insulating material (e.g., SiNx or SiOx), organic insulating material (e.g., benzocyclobutene, acrylic resin, epoxy resin, phenolic resin, polyamide resin), or photosensitizer containing black pigment, but is not limited thereto.

[0108] Furthermore, the dam layer BNK may include light-absorbing materials or light-blocking materials. For example, the dam layer BNK may be formed of at least one material that absorbs light of a specific wavelength. The dam layer BNK may have a structure in which at least two of a red color filter, a green color filter, and a blue color filter are deposited.

[0109] The light-emitting layer 134 can be formed in the R, G, and B pixels, and can include an R emitting layer that emits red light, a G emitting layer that emits green light, and a B emitting layer that emits blue light. For example, the light-emitting layer 134 can include an organic light-emitting layer, an inorganic light-emitting layer, a nanoscale material layer, a quantum dot, a micro LED light-emitting layer, or a mini LED light-emitting layer, but is not limited thereto.

[0110] The light-emitting layer 134 may also include an electron injection layer for injecting electrons into the light-emitting layer, a hole injection layer for injecting holes into the light-emitting layer, an electron transport layer for transporting injected electrons to the light-emitting layer, a hole transport layer for transporting injected holes to the light-emitting layer, an electron blocking layer, and a hole blocking layer, but is not limited thereto.

[0111] The second electrode 136 is disposed on the light-emitting layer 134 and may be formed of a translucent conductive material that transmits light. For example, the second electrode 136 may be made of one or more alloys, such as LiF / Al, CsF / Al, Mg:Ag, Ca / Ag, Ca:Ag, LiF / Mg:Ag, LiF / Ca / Ag, or LiF / Ca:Ag. Furthermore, the second electrode 136 may be made of a transparent metal oxide material (e.g., ITO or IZO), but is not limited thereto.

[0112] Furthermore, the light-emitting device D can be formed as a series structure. The series structure may include multiple organic light-emitting layers and a charge-generating layer disposed between the organic light-emitting layers. The charge-generating layer is configured to regulate the charge balance among the multiple organic light-emitting layers and can be formed from multiple layers including a first charge-generating layer and a second charge-generating layer. The charge-generating layer may include an N-type charge-generating layer and a P-type charge-generating layer. In this case, the charge-generating layer may be formed from an organic layer doped with an alkali metal (e.g., Li, Na, K, or Cs) or an alkaline earth metal (e.g., Mg, Sr, Ba, or Ra), but is not limited thereto.

[0113] An encapsulation layer 160 is formed on the light-emitting device D to seal the light-emitting device D. When the light-emitting device D is exposed to impurities such as moisture or oxygen, pixel shrinkage, such as a reduction in the light-emitting area or defects in the light-emitting area like dark spots, may occur. Furthermore, oxygen or moisture penetrating the light-emitting device D can oxidize the metal electrodes. The encapsulation layer 160 blocks impurities such as oxygen and moisture from the outside to prevent defects in the light-emitting device D and its various electrodes.

[0114] The encapsulation layer 160 may be formed of a first encapsulation layer 162, a second encapsulation layer 164, and a third encapsulation layer 166, but is not limited thereto. In some embodiments, the encapsulation layer 160 may be formed of two, four, or more layers.

[0115] The first encapsulation layer 162 and the third encapsulation layer 166 may each be made of a single layer or multiple layers of inorganic materials such as SiOx, SiON, SiNx, etc., and may also include organic materials between inorganic materials such as SiOx, SiON, SiNx, etc., but are not limited thereto. The second encapsulation layer 164 may be made of epoxy resin.

[0116] A touch buffer layer 182 is formed on the encapsulation layer 160, and a touch sensor TS is disposed thereon. The touch sensor TS includes a bridging electrode 192 disposed on the touch buffer layer 182, a touch interlayer insulating layer 184 disposed on the bridging electrode 192, and touch electrodes 194a and 194b disposed on the touch interlayer insulating layer 184.

[0117] The touch buffer layer 182 and the inter-touch insulating layer 184 can be made of inorganic materials. For example, the touch buffer layer 182 and the inter-touch insulating layer 184 can be made of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto. The touch buffer layer 182 and the inter-touch insulating layer 184 extend from the display area AA to the second non-display area NA2.

[0118] The bridging electrode 192 and the touch electrodes 194a and 194b can be formed as a single layer or multiple layers of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Furthermore, the bridging electrode 192 and the touch electrodes 194a and 194b can be made of a transparent metal oxide such as ITO or IZO.

[0119] The bridging electrode 192 and the touch electrode 194a are electrically connected to each other through contact holes formed in the interlayer insulating layer 184. Although not shown in the figure, the touch electrodes 194a and 194b may be formed in a grid shape.

[0120] A touch planarization layer 186 is formed on the touch sensor TS to protect the touch sensor TS. The touch planarization layer 186 may be made of organic materials, or may be formed of multiple layers of organic and inorganic layers.

[0121] Although the touch sensor TS is depicted on the encapsulation layer 160 in the accompanying drawings, this disclosure is not limited to this structure. The touch sensor TS may be disposed below the encapsulation layer 160.

[0122] Although not shown in the figures, connection line 3-1 LNK3-1 is disposed on the interlayer insulating layer 184 of the display area AA to electrically connect to the touch electrodes 194a and 194b in the display area AA. In this case, connection line 3-1 LNK3-1 extends from the display area AA to the first non-display area NA1. Connection line 3-2 LNK3-2 is disposed on the first planarization layer 148 of the first non-display area NA1. In some embodiments, connection line 3-2 LNK3-2 extends from the first non-display area NA1 through the curved area BA to the second non-display area NA2 to input external touch signals, but this disclosure is not limited thereto.

[0123] 3-1 connecting wire LNK3-1 and 3-2 connecting wire LNK3-2 are electrically connected to each other through contact hole CNT.

[0124] By removing the second planarization layer 150 to form the contact hole CNT, the 3-2 connection line LNK3-2 disposed on the first planarization layer 148 is exposed to the outside through the contact hole CNT.

[0125] Connection line 3-1 (LNK3-1) extends from the display area AA into the contact hole CNT and directly contacts connection line 3-2 (LNK3-2), thus electrically connecting connection line 3-1 (LNK3-1) and connection line 3-2 (LNK3-2) to each other. As a result, externally applied touch signals are provided to the touch sensor TS via connection line 3-2 (LNK3-2) and connection line 3-1 (LNK3-1).

[0126] The 3-1 connecting wire LNK3-1 may be made of the same metal as the touch electrodes 194a and 194b, but is not limited to this.

[0127] 3-2 Connecting line LNK3-2 can be formed of the same metal as connecting pattern 154.

[0128] A touch planarization layer 186 is formed on the touch sensor TS to protect the touch sensor TS. The touch planarization layer 186 may be made of an organic material, or may be formed of multiple organic and inorganic layers. The touch planarization layer 186 is formed in the display area AA, and may extend to a portion of the second non-display area NA2, the curved area BA, and the first non-display area NA1.

[0129] A touch passivation layer 188 is disposed on the touch planarization layer 186. In this case, the touch passivation layer 188 may be formed of an organic material, or the organic / inorganic layer may be formed of multiple layers, but is not limited thereto. Although not shown in the figure, a dam DAM is disposed in the second non-display area NA2. Since the organic material forming the second encapsulation layer 164 is fluid, the organic material may flow out to the outside of the substrate 140 due to its fluidity when the second encapsulation layer 164 is formed. Since the dam DAM is formed around the display area NA, the organic material flowing out from the substrate 140 can be blocked by the dam DAM when the second encapsulation layer 164 is formed. Therefore, the organic material will not flow out of the substrate 140.

[0130] Furthermore, although not shown in the figures, a microcoating can be disposed in the non-display areas, particularly in the curved areas. The microcoating is made of a flexible organic material to block moisture from the outside. Additionally, the microcoating reduces tensile and contractile stresses that can be received by the lines by positioning various lines in the curved areas near the neutral plane during the bending process. The touch planarization layer 186 extends from the display area AA to the curved area BA, and the end of the touch planarization layer 186 is directly disposed on the upper surface of the embankment layer BNK in the first non-display area NA1. As described above, in this disclosure, since the end of the touch planarization layer 186 is directly disposed on and in contact with the upper surface of the embankment layer BNK, this helps to prevent delamination of the touch planarization layer 186, which will be described in detail below.

[0131] Figure 7A and Figure 7B yes Figure 6 A magnified cross-sectional view of region B. Specifically, Figure 7A This is an enlarged cross-sectional view showing an example of the contact area between connection lines LNK3-1 (3-1) and LNK3-2 (3-2) of a display device with an alternative structure. In contrast, Figure 7B This is an enlarged cross-sectional view showing the contact area of ​​the 3-1 connecting line LNK3-1 and the 3-2 connecting line LNK3-2 of the display device according to an embodiment of the present disclosure.

[0132] like Figure 7A As shown, in a display device with an alternative structure, a touch buffer layer 182 and a touch interlayer insulating layer 184 are disposed on a dam layer BNK outside the contact hole CNT and extend outward. Therefore, the end of the touch planarization layer 186 is disposed on the interlayer insulating layer 184, such that the end CP1 of the touch planarization layer 186 directly contacts the interlayer insulating layer 184.

[0133] When the touch planarization layer 186 is made of an organic material and the interlayer insulating layer 184 is made of an inorganic material, the boundary characteristics between the touch planarization layer 186 and the interlayer insulating layer 184 may deteriorate, resulting in reduced adhesion between them. Consequently, problems may occur in display devices with this structure, as the ends of the touch planarization layer 186 may easily delaminate from the interlayer insulating layer 184, cracks may form in the touch planarization layer 186, and / or the 3-1 connecting line LKN3-1 may be damaged.

[0134] On the other hand, such as Figure 7B As shown, in the display device 100 according to an embodiment of the present disclosure, the end of the touch planarization layer 186 (made of organic material) is directly disposed on the embankment layer BNK (also made of organic material) in the contact area of ​​the touch line, thereby enhancing the adhesion between the touch planarization layer 186 and the embankment layer BNK and preventing the touch planarization layer 186 from delaminating. Specifically, as Figure 7B As shown in the example, since the 3-2 connection line LKN3-2 is disposed on the first planarization layer 148 and the contact hole CNT is formed in the second planarization layer 150 above the 3-2 connection line LKN3-2, the 3-2 connection line LKN3-2 is exposed to the outside through the contact hole CNT. In this case, the touch buffer layer 182 and the touch interlayer insulating layer 184 are formed on the second planarization layer 150 and the embankment layer BNK, and the touch buffer layer 182 and the touch interlayer insulating layer 184 extend within the contact hole CNT. However, the touch buffer layer 182 and the touch interlayer insulating layer 184 are etched in the central region of the contact hole CNT to expose the 3-2 connection line LKN3-2 to the outside.

[0135] Since the embankment layer BNK is formed on the second planarization layer 150 and the end of the embankment layer BNK is spaced apart from the contact hole CNT by a predetermined distance, the second planarization layer 150 and the embankment layer BNK can be formed in a stepped shape.

[0136] Since the 3-1 connecting line LKN3-1 is located inside the contact hole CNT and electrically connected to the 3-2 connecting line LKN3-2, external touch signals are provided to the touch sensor TS through the 3-2 connecting line LKN3-2 and the 3-1 connecting line LKN3-1.

[0137] A touch planarization layer 186 is disposed above the contact hole CNT. The touch planarization layer 186 extends from the display area AA to the second non-display area NA2, and the end CP2 is disposed directly on the embankment layer BNK.

[0138] The embankment layer BNK and the touch planarization layer 186 can be formed of organic materials. Therefore, since the touch planarization layer 186 is directly disposed on and in contact with the embankment layer BNK, the organic materials of the touch planarization layer 186 and the organic materials of the embankment layer BNK are in contact with each other at the ends of the touch planarization layer 186. Therefore, since the organic materials bond to each other at the interface between the embankment layer BNK and the touch planarization layer 186, this helps to prevent delamination at the ends of the touch planarization layer 186.

[0139] As described above, in the display device 100 according to the present disclosure, since the end of the touch planarization layer 186 made of organic material is directly disposed on the embankment layer BNK made of organic material in the contact area of ​​the touch line, the adhesion between the touch planarization layer 186 and the embankment layer BNK is improved to prevent delamination of the touch planarization layer 186, and thus it can help prevent defects such as cracks or damage to the touch line caused by delamination of the touch planarization layer 186.

[0140] In the following, a method for manufacturing a display device 100 according to the present disclosure will be described in detail with reference to the accompanying drawings.

[0141] Figures 8A to 8F This is a view illustrating an example of a method for manufacturing a display device 100 according to this disclosure.

[0142] like Figure 8A As shown, a buffer layer 142 is formed over the entire substrate 140. The substrate 140 can be made of a rigid material such as glass, or of a plastic material. The plastic material may include polyimide, polymethyl methacrylate, polyethylene terephthalate, polyethersulfone, and polycarbonate. The buffer layer 142 may be formed of a single layer or multiple layers of SiNx or SiOx.

[0143] Subsequently, a polycrystalline semiconductor material such as polycrystalline silicon or an oxide semiconductor material such as IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), IGTO (indium gallium tin oxide), and IGO (indium gallium oxide) is deposited and etched to form a semiconductor layer 112 on the buffer layer 142. Furthermore, impurities are doped onto both sides of the semiconductor layer 112 to form a channel region 112a, a source region 112b, and a drain region 112c.

[0144] Subsequently, a gate insulating layer 144 is formed by depositing an inorganic material such as SiOx or SiNx. Then, a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) is deposited by sputtering and etched by wet etching to form a gate electrode 114. Afterward, an organic material such as a photosensitive acrylate material or an inorganic material such as SiNx or SiOx is deposited on the gate electrode 114 to form an interlayer insulating layer 146. Then, the interlayer insulating layer 146 above the source region 112b and drain region 112c of the semiconductor layer 112 is dry etched to form contact holes therein.

[0145] Subsequently, a metal such as Cr, Mo, Ta, Cu, Ti, Al, or an Al alloy is deposited and etched by sputtering to form a source electrode 115 and a drain electrode 116. The source electrode 115 and the drain electrode 116 are in ohmic contact with the source region 112b and the drain region 112c of the semiconductor layer 112 through contact holes in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively.

[0146] Subsequently, an organic material such as photosensitive acrylate is deposited on the source electrode 115 and the drain electrode 116 to form a planarization layer 148 on the interlayer insulating layer 146, and then the first planarization layer 148 on the drain electrode 116 is dry etched to form a contact hole.

[0147] Subsequently, a single layer or multiple layers of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), their alloys, or metal oxides such as indium tin oxide (ITO) or indium zinc oxide (IZO) are deposited, and then etched to form a connection pattern 154. In this case, the connection pattern 154 is electrically connected to the drain electrode 116 of the thin-film transistor T through contact holes formed in the first planarization layer 148.

[0148] Subsequently, an organic material such as photosensitive acrylate is deposited to form a second planarization layer 150, and then contact holes are formed by dry etching over the second planarization layer 150 connecting the pattern 154.

[0149] Subsequently, metals such as silver (AG), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), and chromium (Cr) are stacked by sputtering and etched by wet etching to form a first electrode 132 on the second planarization layer 150. In this case, the first electrode 132 is electrically connected to the drain electrode 116 of the thin-film transistor through a contact hole.

[0150] Subsequently, at least one of the following materials is deposited on the second planarization layer 150: inorganic insulating material (such as SiNx or SiOx), organic material (such as BCB (benzocyclobutene), acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin), and photoresist including black pigment, and is dry etched to form the embankment layer BNK.

[0151] Subsequently, a light-emitting layer 134 is formed by depositing a light-emitting material on the first electrode 132, and then a metal oxide such as ITO or IZO is deposited to form a second electrode 136.

[0152] like Figure 8B As shown, an encapsulation layer 160, comprising a first encapsulation layer 162, a second encapsulation layer 164, and a third encapsulation layer 166, is formed above the light-emitting device D. In this case, the first encapsulation layer 162 and the third encapsulation layer 166 can be formed by depositing inorganic materials using a chemical vapor deposition (CVD) process.

[0153] When the first encapsulation layer 162 and the third encapsulation layer 166 are formed, although not shown in the figure, inorganic materials are deposited while the first non-display area NA and the curved area BA are blocked by blocking members such as masks, so that the first encapsulation layer 162 and the third encapsulation layer 166 can be formed on the entire substrate 140 except for the first non-display area NA and the curved area BA.

[0154] The second encapsulation layer 164 can be formed by directly coating the organic material onto the first encapsulation layer 162 using a spin coating method or a dispensing method.

[0155] Subsequently, an inorganic material such as SiOx or SiNx is deposited and etched on the third encapsulation layer 166 to form a touch buffer layer 182 thereon. In some embodiments, the touch buffer layer 182 extends from the display area AA to the curved area BA, such that the touch buffer layer 182 extends into a portion of the area inside the contact hole CNT, and the second touch connection line LNK3-2 is exposed to the outside by patterning the touch buffer layer 182 in the central region inside the contact hole CNT.

[0156] After that, as Figure 8C As shown, metal is deposited on the entire substrate 140 and then etched to form a bridging electrode 192 on the touch buffer layer 182 of the display area AA.

[0157] Subsequently, inorganic materials (such as SiOx or SiNx) are deposited on the touch buffer layer 182 on which bridging electrodes 192 are formed, and metal is deposited on it and then etched to form touch electrodes 194a and 194b in the display area AA, and touch connection line LNK3-1 is formed in the curved area BA.

[0158] In some embodiments, each of the touch electrodes 194a and 194b is electrically connected to the bridging electrode 192 through a contact hole formed in the touch buffer layer 182, and touch connection line 3-1 LNK3-1 extends into the contact hole CNT of the first non-display area NA1 and is electrically connected to touch connection line 3-2 LNK3-2.

[0159] After that, as Figure 8D As shown, the touch buffer layer 182 and the touch interlayer insulating layer 184 above the embankment layer BNK outside the contact hole CNT of the first non-display area NA1 are etched to expose the embankment layer BNK to the outside. In this case, the touch buffer layer 182 and the touch interlayer insulating layer 184 can be etched using the same etching process as the etching process of the first encapsulation layer 162 and the third encapsulation layer 166.

[0160] The first encapsulation layer 162 and the third encapsulation layer 166 are patterned in a masking process instead of an etching process, such that the first encapsulation layer 162 and the third encapsulation layer 166 are not formed in the curved region, but are formed in a portion of the first non-display region NA1 and the second non-display region NA2, for example, in the side portion of the display device 100. Therefore, the first encapsulation layer 162 and the third encapsulation layer 166 are exposed to the outside from the side portion of the display device 100, and the exposed first encapsulation layer 162 and the third encapsulation layer 166 become pathways for moisture to penetrate from the outside. To avoid moisture penetration, the first encapsulation layer 162 and the third encapsulation layer 166 in the end portion of the display device 100 can be removed. Therefore, although... Figure 8D As not shown in the diagram, in the display device of this disclosure, a first encapsulation layer 162 and a third encapsulation layer 166 are etched into the first non-display area NA1 and the second non-display area NA2 (e.g., in the end of the display device 100) such that the first encapsulation layer 162 and the third encapsulation layer 166 are spaced apart from the side end of the display device 100 by a predetermined distance to prevent moisture from penetrating along the side end portion of the display device (i.e., along the outer edge portion).

[0161] In some embodiments, the first encapsulation layer 162 and the third encapsulation layer 166 are etched before the formation of the touch buffer layer 182. However, in other embodiments, the first encapsulation layer 162 and the third encapsulation layer 166 may be etched after the formation of the touch buffer layer 182 and the touch electrodes 194a and 194b, such that the touch buffer layer 182 and the interlayer insulating layer 184 may be etched simultaneously with the first encapsulation layer 162 and the third encapsulation layer 166, thereby forming a contact hole CNT on the embankment layer BNK in the curved region BA, from which the touch buffer layer 182 and the interlayer insulating layer 184 are removed.

[0162] After that, as Figure 8E As shown, an organic material is coated and etched to form a touch planarization layer 186 in the display area AA and the curved area BA. In some embodiments, the touch planarization layer 186 is spaced at a predetermined distance from the side of the display device 100, and specifically, the end of the touch planarization layer 186 is in direct contact with the exposed upper surface of the embankment layer BNK.

[0163] Since both the touch planarization layer 186 and the embankment layer BNK are made of organic materials, they are bonded at the boundary between them. This improves the bonding strength between the touch planarization layer 186 and the embankment layer BNK and helps prevent delamination at the ends of the touch planarization layer 186.

[0164] Subsequently, as Figure 8F As shown, an organic material is coated and then etched to form a touch passivation layer 188 in the display area AA.

[0165] In some embodiments, after depositing the touch buffer layer 182 and the touch interlayer insulating layer 184, the side portions of the first encapsulation layer 162 and the third encapsulation layer 166 may be etched. Generally, a portion of the touch buffer layer 182 and the touch interlayer insulating layer 184 in the curved region BA is removed, exposing the embankment layer BNK made of organic material to the outside. Therefore, since the ends of the touch planarization layer 186 made of organic material are in direct contact with the upper surface of the embankment layer BNK made of organic material, delamination of the touch planarization layer 186 due to reduced adhesion at the boundaries of the ends of the touch planarization layer 186 can be prevented.

[0166] Furthermore, in some embodiments, the first encapsulation layer 162 and the third encapsulation layer 166 can be etched after the touch electrodes 194a and 194b and the 3-1 touch connection line LNK3-1 are formed. Therefore, the formation of a residual metal layer on the exposed upper surface of the embankment layer BNK can be prevented. This helps prevent reduced adhesion between the touch planarization layer 186 and the embankment layer BNK caused by the residual metal layer, thereby more effectively preventing delamination of the touch planarization layer 186.

[0167] Figure 9 This is a view showing an example of the structure of a display device 100 according to a second embodiment of the present disclosure.

[0168] Figure 6The display device shown differs from the display device of this embodiment in that the 3-2 connecting line LKN3-2 is disposed on the interlayer insulating layer 146. In this case, the 3-2 connecting line LKN3-2 can be made of the same material as the source electrode 115 and drain electrode 116 of the thin-film transistor T. Furthermore, a contact hole CNT is formed by removing the first planarization layer 148 and the second planarization layer 150, and the 3-1 connecting line LKN3-1 and the 3-2 connecting line LKN3-2 are electrically connected to each other in the contact hole CNT.

[0169] Figure 10 This is a view illustrating an example of a display device 200 according to a third embodiment of the present disclosure. In this case, descriptions of the display device 200 according to the present disclosure are omitted or briefly described. Figure 6 The display device 100 of the first embodiment has the same configuration, and only other configurations are described in detail.

[0170] like Figure 10 As shown, the thin-film transistor T and the light-emitting device D are respectively disposed in the display area AA, and the embankment layer BNK is disposed in the display area AA and the non-display area NA.

[0171] The protruding portion BNK-1 is configured to protrude from the embankment layer BNK disposed in the first non-display area NA1. For example, the protruding portion BNK-1 protrudes from the lower surface of the embankment layer BNK and its thickness is less than the thickness of the remaining portion of the embankment layer BNK.

[0172] Remove the touch buffer layer 282 and the interlayer insulation layer 284 above the protruding part BNK-1, so that a portion of the protruding part BNK-1 is exposed to the outside.

[0173] A touch planarization layer 286 is disposed on and protects the touch sensor TS. The touch planarization layer 286 is formed in the display area AA and extends to a portion of the second non-display area NA2, the curved area BA, and the first non-display area NA1. The end of the touch planarization layer 286 is directly disposed on the upper surface of the protruding portion BNK-1 of the first display area NA1. As described above, in this embodiment, since the end of the touch planarization layer 286, made of organic material, is directly disposed on and in contact with the protruding portion BNK-1 of the embankment layer BNK, made of organic material, the boundary characteristics between the touch planarization layer 286 and the protruding portion BNK-1 of the embankment layer BNK can be improved, thereby preventing delamination of the touch planarization layer 286.

[0174] The above description and accompanying drawings are merely illustrative of various embodiments of this disclosure, and those skilled in the art to which this disclosure pertains can combine and configure them without departing from the essential characteristics of this disclosure. Various modifications or variations, such as separation, substitution, and alteration, are possible. Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical spirit of this disclosure, but are for illustrative purposes, and the scope of the technical spirit of this disclosure is not limited by these embodiments.

Claims

1. A display device, comprising: A substrate includes a display area and a non-display area, wherein the display area has a plurality of sub-pixels, and wherein the non-display area includes: a second non-display area disposed outside the display area and adjacent to the display area, a first non-display area outside the second non-display area, and a curved area between the first non-display area and the second non-display area; A dike layer is disposed in the display area and the non-display area; Thin-film transistors and light-emitting devices are disposed in each of the plurality of sub-pixels; An encapsulation layer is disposed above the light-emitting device; A touch sensor is disposed on the encapsulation layer; At least one connecting line extends from the non-display area to the touch sensor; and A touch planarization layer is disposed on the touch sensor and the at least one connecting line and overlaps with the touch sensor and the at least one connecting line. Wherein, the end of the touch flattening layer in the non-display area is directly disposed on the embankment layer in the non-display area and in contact with the embankment layer in the non-display area.

2. The display device according to claim 1, wherein, The at least one connecting line includes: A first connecting line extends into the non-display area to be electrically connected to the touch sensor; and A second connection line is electrically connected to the first connection line in the non-display area to apply a touch signal to the first connection line.

3. The display device according to claim 2, wherein, The second connecting line is located in the first non-display area.

4. The display device according to claim 3, wherein, The first connecting line and the second connecting line are connected to each other in the first non-display area or the second non-display area.

5. The display device according to claim 2, in, The thin-film transistor includes a semiconductor layer, a gate insulating layer on the semiconductor layer, a gate electrode on the gate insulating layer, an interlayer insulating layer, and a source electrode and a drain electrode on the interlayer insulating layer. The display device further includes: a first planarization layer located above the thin-film transistor; a connection pattern electrically connected to the drain electrode on the first planarization layer; and a second planarization layer located on the connection pattern.

6. The display device according to claim 5, wherein, The second planarization layer has contact holes, wherein the first connecting line and the second connecting line are electrically connected to each other within the contact holes.

7. The display device according to claim 6, in, The first connecting wire is made of the same material as the touch electrodes of the touch sensor, and The second connecting line is made of the same material as the connecting pattern.

8. The display device according to claim 5, wherein, Contact holes are formed in the first planarization layer and the second planarization layer, and the first connecting line and the second connecting line are electrically connected to each other in the contact holes.

9. The display device according to claim 8, in, The first connecting wire is made of the same material as the touch electrodes of the touch sensor, and The second connecting line is made of the same material as the source electrode and the drain electrode.

10. The display device according to claim 1, wherein, The touch planarization layer and the embankment layer are made of organic materials.

11. The display device according to claim 1, further comprising: A touch passivation layer disposed on top of the touch flattening layer in the display area.

12. The display device according to claim 1, in, The embankment layer in the first non-display area includes a protruding portion projecting toward the curved area, and the thickness of the protruding portion of the embankment layer is less than the thickness of the remaining portion of the embankment layer. The end of the touch planarization layer is directly disposed on the protruding portion of the embankment layer in the first non-display area and is in contact with the protruding portion of the embankment layer in the first non-display area.

13. A method for manufacturing a display device, comprising: A substrate is provided, the substrate including a display area and a non-display area, wherein the display area has a plurality of sub-pixels, and wherein the non-display area includes: (i) a second non-display area disposed outside the display area and adjacent to the display area, (ii) a first non-display area outside the second non-display area, and (iii) a curved area between the first non-display area and the second non-display area; A first touch line is formed in the non-display area; A dam layer is formed in the display area and the non-display area, wherein the dam layer is formed between the sub-pixels in the display area; Each of the sub-pixels is provided with a thin-film transistor and a light-emitting device; An encapsulation layer is formed over the light-emitting device in the display area, wherein the encapsulation layer does not extend into the first non-display area; A touch buffer layer is formed on the encapsulation layer, wherein the touch buffer layer extends into the first non-display area; The touch buffer layer of the first non-display area is etched to expose a portion of the embankment layer to the outside; A touch sensor and a second touch line are formed on the touch buffer layer; and A touch planarization layer is formed on the touch sensor and the second touch line. The end of the touch planarization layer contacts the upper surface of the exposed portion of the embankment layer.

14. The method according to claim 13, wherein, Forming the encapsulation layer includes: An inorganic material is deposited on the light-emitting device to form a first encapsulation layer; Depositing organic material on a portion of the first encapsulation layer to form a second encapsulation layer; and Depositing the inorganic material on a portion of the first encapsulation layer and the second encapsulation layer to form a third encapsulation layer; and The first encapsulation layer and the third encapsulation layer of the non-display area are etched.

15. The method of claim 13, further comprising forming a touch passivation layer on the touch planarization layer in the display area.

16. The method according to claim 15, wherein, Forming the touch passivation layer includes etching the touch passivation layer, and Specifically, the touch buffer layer outside the touch planarization layer is etched simultaneously with the touch passivation layer.

17. The method according to claim 13, in, The embankment layer includes a protruding portion projecting toward the display area, and the thickness of the protruding portion is less than the thickness of the remaining portion of the embankment layer. The process of etching the touch buffer layer of the first non-display area includes etching the touch buffer layer above the protruding portion of the embankment layer to expose the protruding portion of the embankment layer to the outside.

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