A quantum chip packaging method and system, quantum chip unit

Abstract

The application discloses a quantum chip packaging method and system and a quantum chip unit. The method comprises the following steps: placing the quantum chip into a buffer oxide etching solution for soaking to remove the oxide layer on the surface of the quantum chip; performing ultrapure water rinsing on the quantum chip after the oxide layer is removed to remove residual substances on the surface of the quantum chip, wherein the ultrapure water rinsing comprises at least one of deionized water rinsing, megasonic cleaning in ultrapure water and ozone water cleaning; within a first time period after the ultrapure water rinsing, transferring the quantum chip to a wire bonder in a low-oxygen environment with an oxygen content not exceeding a set threshold, and performing wire bonding on the quantum chip and a packaging box; within a second time period after the wire bonding, transferring the packaging box and the quantum chip in the packaging box to a glove box in a low-oxygen environment, and performing seam welding on the bottom shell and the cover plate of the packaging box in the glove box to complete the packaging of the quantum chip. The packaging method can improve the low-temperature performance of the quantum chip and improve the reliability of the quantum chip.

Description

Technical Field

[0001] This invention relates to the field of quantum chip processing technology, and in particular to a quantum chip packaging method and system, and a quantum chip unit. Background Technology

[0002] Superconducting quantum chips are key components of quantum computers. They typically require encapsulation before use. For example, Chinese invention patent CN118900621A discloses a method for encapsulating superconducting quantum chips using a flip-chip bonding process with a packaging substrate. Other similar encapsulation methods also exist in the prior art.

[0003] Existing superconducting quantum chip packaging methods all employ conventional methods. The inventors of this application have discovered that superconducting quantum chips packaged using conventional methods exhibit core defects in low-temperature performance and reliability. Specifically:

[0004] The low-temperature performance defects are mainly reflected in the increased interfacial resistance caused by the oxide layer and the low-temperature frosting and delamination caused by moisture penetration.

[0005] The reliability defects are mainly reflected in the attenuation of wire bonding strength, insufficient electromagnetic shielding effectiveness, weak thermal management capability, and long-term airtightness failure.

[0006] These shortcomings mean that the packaged superconducting quantum chip cannot adequately meet the application requirements of superconducting quantum computing. Summary of the Invention

[0007] In view of the above problems, the present invention is proposed to provide a quantum chip packaging method and system, and a quantum chip unit that overcomes or at least partially solves the above problems.

[0008] This invention provides a quantum chip packaging method, comprising:

[0009] The quantum chip is immersed in a buffer oxide etching solution to remove the oxide layer on the surface of the quantum chip;

[0010] The quantum chip after removing the oxide layer is rinsed with ultrapure water to remove residual substances on the surface of the quantum chip. The ultrapure water rinsing includes at least one of the following: deionized water rinsing, megasonic cleaning in ultrapure water, and ozone water cleaning.

[0011] Within the first hour after rinsing with ultrapure water, the quantum chip is transferred to a wire bonding machine in a low-oxygen environment where the oxygen content does not exceed a set threshold, and the quantum chip is wire bonded to the packaging box.

[0012] Within two hours after wire bonding, the package and the quantum chip inside are transferred to a glove box in a low-oxygen environment. The bottom shell and cover of the package are then seam-welded in the glove box to complete the packaging of the quantum chip.

[0013] In some optional embodiments, immersing the quantum chip in a buffered oxide etching solution includes:

[0014] The quantum chip is immersed in a buffer oxide etching solution for a third time, during which the etching solution is stirred by inert gas bubbling. The third time is 30-60 seconds, and the immersion temperature is 20-25℃. The buffer oxide etching solution is a mixed solution of NH4F and HF, wherein the ratio of NH4F:HF is 4:1-7:1.

[0015] In some optional embodiments, the step of rinsing the quantum chip with ultrapure water after removing the oxide layer to remove residual substances from the surface of the quantum chip includes:

[0016] Perform at least one of the following ultrapure water rinsing steps to remove residual material from the surface of the quantum chip:

[0017] The quantum chip after removing the oxide layer was immersed in deionized water for a fourth time, wherein the conductivity of the deionized water was greater than 18.2 MΩ·cm, and the fourth time was 1-3 minutes.

[0018] After removing the oxide layer, the quantum chip is placed in ultrapure water for a fifth time using megasonic cleaning, wherein the frequency of the megasonic wave is greater than 1MHz and the fifth time is 3-5 minutes.

[0019] The quantum chip, after the oxide layer has been removed, is immersed in ozone water for a sixth time, wherein the concentration of the ozone water is greater than 5 ppm and the sixth time is 1-3 minutes.

[0020] In some optional embodiments, before transferring the quantum chip to the wire bonding machine within a first time period after ultrapure water rinsing, the method further includes:

[0021] The quantum chip is dried with inert gas.

[0022] In some optional embodiments, a low-oxygen environment refers to an environment with an oxygen content of <1 ppm, an inert gas purity of ≥99.999%, and a humidity of <0.1 ppm.

[0023] In some alternative embodiments, the first duration is ≤1 minute; the second duration is ≤1 minute.

[0024] In some alternative embodiments, the quantum chip and package are provided with a low-oxygen environment by the inert gas purging function provided by the wire bonding machine, and wire bonding is performed using thermo-ultrasonic ball bonding or wedge bonding with gold wire (Au) material with a diameter of 25-50μm or superconducting aluminum wire (Al) material with a diameter of 30-75μm.

[0025] In some optional embodiments, the seam welding sealing of the bottom shell and cover plate of the packaging box in the glove box includes:

[0026] Clean contaminants and remove oxide layers from the surface of the packaging box;

[0027] In a glove box filled with inert gas, the mating edges of the cover plate and the bottom shell of the packaging box are welded.

[0028] This invention provides a quantum chip unit, including: a packaging box and a quantum chip located in the packaging box, wherein the packaging box includes a bottom shell and a cover plate;

[0029] The quantum chip is packaged into a packaging box using the method described above.

[0030] This invention provides a quantum chip packaging system, comprising: a first immersion container, a second immersion container, a wire bonding machine, and a glove box;

[0031] The first immersion container is used to hold a buffer oxide etching solution to immerse the quantum chip and remove the oxide layer on the surface of the quantum chip.

[0032] The second soaking container is used to hold ultrapure water to soak the quantum chip after the oxide layer has been removed to remove residual substances on the surface of the quantum chip; the ultrapure water includes at least one of deionized water and ozone water;

[0033] The wire bonding machine is used to provide a low-oxygen environment with an oxygen content not exceeding a set threshold, and to perform wire bonding on the quantum chip and packaging box transferred within the first time after rinsing with ultrapure water.

[0034] The glove box is used to provide a low-oxygen environment and to seam-weld the package and the quantum chip inside it that have been transferred over the second time interval after wire bonding, thus completing the packaging of the quantum chip.

[0035] The beneficial effects of the above-described technical solutions provided in the embodiments of the present invention include at least the following:

[0036] Removing the surface oxide layer of the quantum chip in a buffered oxide etching solution, through the reaction of fluoride ions with the oxide layer, reduces surface defects and roughness, thereby minimizing the decoherence time loss of the qubits. Following oxide removal, ultrapure water rinsing removes residual substances. This rinsing can utilize deionized water, megasonic cleaning in ultrapure water, or a combination of these methods to effectively remove residual fluorides and particulate contaminants, preventing crystallization or gas release during low-temperature operation, improving the chemical stability of the chip surface, and effectively preventing secondary oxidation. After removing residual materials, the chip is rapidly transferred to a low-oxygen environment wire bonding machine for wire bonding to the package. Wire bonding in a low-oxygen environment effectively reduces surface oxidation and embrittlement, improving solder joint conductivity and fatigue resistance. Following wire bonding, the chip and package are rapidly transferred to a low-oxygen glove box for seam welding of the package bottom and cover. Seam welding in a low-oxygen environment effectively improves the sealing of the packaged quantum chip and package, preventing low-temperature frost formation and moisture penetration that could lead to interface delamination. This method effectively enhances the reliability and low-temperature performance of quantum chip packaging.

[0037] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.

[0038] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0039] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0040] Figure 1 This is a flowchart of the quantum chip packaging method in Embodiment 1 of the present invention;

[0041] Figure 2 This is a schematic diagram of the principle framework of the quantum chip packaging method in Embodiment 1 of the present invention;

[0042] Figure 3 This is a flowchart of the quantum chip packaging method in Embodiment 2 of the present invention;

[0043] Figure 4 This is a schematic diagram of the quantum chip structure in an embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of the quantum chip packaging system in an embodiment of the present invention. Detailed Implementation

[0045] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0046] In order to solve the problems of low-temperature performance defects and reliability defects in existing superconducting quantum chip packaging methods, the inventors of this application have analyzed and studied the causes of these problems.

[0047] I. Regarding the low-temperature performance defects, the oxide layer leads to a sharp increase in interfacial resistance and moisture penetration causes low-temperature frosting, delamination, and other problems.

[0048] 1. Regarding the issue of oxide layer causing a sharp increase in interfacial resistance.

[0049] Conventional packaging methods, such as wire bonding or flip-chip bonding, are performed in the air, causing an oxide layer (e.g., Al2O3) to rapidly form on the aluminum / copper pads. At low temperatures, the contact resistance between the oxide layer and the metal increases significantly (up to 10-100 mΩ), leading to a shortened decoherence time (T1 / T2) for the qubits. For example, the Josephson junction in superconducting quantum chips is extremely sensitive to interface oxidation; the oxide layer introduces parasitic capacitance and energy level splitting anomalies, resulting in increased contact resistance and a shortened decoherence time.

[0050] 2. Regarding the issue of low-temperature frosting and stratification caused by moisture penetration.

[0051] Conventional screw-locking encapsulation is not hermetically airtight and cannot effectively isolate moisture. At low temperatures (e.g., mK levels), residual moisture inside can condense into ice crystals, generating mechanical stress that can lead to delamination at the quantum chip-substrate interface or cracking of the encapsulation's inner wall. Studies have found that moisture penetration can cause changes in the dielectric constant of the molding compound exceeding 20%, affecting the performance of high-frequency circuits.

[0052] II. Regarding reliability defects, including issues such as wire bond strength attenuation, insufficient electromagnetic shielding effectiveness, weak thermal management capabilities, and long-term airtightness failure.

[0053] 1. Regarding the issue of wire bond strength attenuation

[0054] In conventional packaging methods, wire bonding is performed in an air environment, making it susceptible to oxidation and contamination. Under temperature cycling (-65℃ to 150℃), the bond strength of gold wires decays at a rate of 0.0021 g / cycle (18μm wire), while silicon-aluminum wires decay even faster (exponentially). Mechanical vibrations caused by screw tightening accelerate bond point breakage, especially in power devices, where the risk of intermetallic compound (IMC) layer crack propagation increases by 30% under drop impacts on 380μm thick aluminum wires.

[0055] 2. Regarding the problem of insufficient electromagnetic shielding effectiveness

[0056] Conventional packaging methods use non-hermetic enclosures, lacking multi-layered shielding structures (such as Al / Nb superconducting shielding layers). External microwave noise (such as cavity mode resonance) crosstalk can reach -30dB, while optimized hermetic packaging can suppress it to below -50dB. The screw gaps in non-hermetic enclosures can also introduce magnetic flux noise, disrupting the stability of superconducting quantum bit energy levels.

[0057] 3. Regarding the issue of weak thermal management capabilities

[0058] Conventional packaging methods involve soldering in a non-hermetic environment, resulting in poor heat dissipation at flip-chip solder joints. Under high current operation (such as in power devices), local hotspot temperatures can exceed 150°C, accelerating solder creep and the growth of the intermetallic compound (IMC) layer. Studies have found that non-hermetic coarse aluminum wire bonding exhibits a tensile force fluctuation of 11.71% under 270mW ultrasonic power, demonstrating poor data convergence.

[0059] 4. Regarding the issue of long-term airtightness failure

[0060] In conventional packaging methods for quantum chips, screw tightening relies on the compression of sealing rings, but low-temperature thermal cycling (>10) can cause problems. 3 (This) can lead to aging of the sealing ring, with a helium leakage rate >1×10⁻⁶. -7 mbar·L / s, much higher than that of airtight laser welding (<1×10). - 9 (mbar·L / s). Continuous penetration of moisture and oxygen can trigger electrochemical migration, leading to bonding site corrosion failure.

[0061] Because conventional packaging methods have numerous drawbacks in terms of low-temperature performance and reliability, the inventors of this application have discovered that improving the packaging method by packaging quantum chips in a low-oxygen environment can effectively improve the performance of the packaged chip. Based on this, this invention provides a quantum chip packaging method applicable to the packaging of quantum chips, including superconducting quantum chips. This method includes pretreatment before quantum chip packaging and the packaging process in a low-oxygen environment. In this method, both the quantum chip wire bonding and encapsulation processes are performed in a low-oxygen environment. Before wire bonding, the chip is immersed in a buffered oxide etching solution and rinsed with ultrapure water to remove the oxide layer and clean any impurities after oxide removal. After cleaning, the chip is transferred to the low-oxygen environment for wire bonding as quickly as possible within a certain time. After wire bonding, the chip is transferred to a low-oxygen glove box for packaging as quickly as possible within a certain time.

[0062] Example 1

[0063] Embodiment 1 of the present invention provides a quantum chip packaging method, the process of which is as follows: Figure 1 and Figure 2 As shown, it includes the following steps:

[0064] S101: Immerse the quantum chip in a buffer oxide etching solution to remove the oxide layer on the surface of the quantum chip.

[0065] In this step, the prepared quantum chip is immersed in a buffer oxide etching solution for a third time. Through the chemical reaction between the oxide on the surface of the quantum chip and the buffer oxide etching solution, the oxide on the surface of the quantum chip is effectively removed. The third time is 30-60 seconds, and the immersion temperature is 20-25℃. The buffer oxide etching solution is a mixed solution of NH4F and HF, wherein the ratio of NH4F:HF is 4:1-7:1.

[0066] S102: After removing the oxide layer, the quantum chip is rinsed with ultrapure water to remove residual substances from its surface. The ultrapure water rinsing includes at least one of the following: deionized water rinsing, megasonic cleaning in ultrapure water, and ozone water cleaning. Ultrapure water refers to water with a resistivity greater than a certain value (e.g., 18 MΩ·cm).

[0067] This step can employ any one or a combination of deionized water rinsing, megasonic cleaning in ultrapure water, and ozone water cleaning to remove residual substances from the quantum chip surface and improve the surface quality of the quantum chip. In other words, at least one of the following ultrapure water rinsing steps can be performed in this step to remove residual substances from the quantum chip surface:

[0068] 1) After removing the oxide layer, the quantum chip is immersed in deionized water for a fourth time. The conductivity of the deionized water is greater than 18.2 MΩ·cm. The fourth time is 1-3 minutes.

[0069] 2) After removing the oxide layer, the quantum chip is cleaned with megasonic waves for a fifth time. The frequency of the megasonic waves is greater than 1MHz, and the fifth time is 3-5 minutes.

[0070] 3) After removing the oxide layer, immerse the quantum chip in ozone water for a sixth time. The concentration of ozone water is greater than 5 ppm, and the sixth time is 1-3 minutes.

[0071] Optionally, the steps of rinsing with deionized water, ultrasonic cleaning in ultrapure water, and ozone water cleaning can be performed sequentially.

[0072] The quantum chip after removing the oxide layer was immersed in deionized water for a fourth time, wherein the conductivity of the deionized water was greater than 18.2 MΩ·cm, and the fourth time was 1-3 minutes.

[0073] After rinsing with deionized water, the quantum chip is placed in ultrapure water for megasonic cleaning for a fifth time. The frequency of the megasonic waves is greater than 1MHz, and the fifth time is 3-5 minutes. In this step, the ultrapure water can be deionized water, that is, after soaking in deionized water, it can be placed in a new cup of deionized water for megasonic cleaning.

[0074] The quantum chip, after being cleaned by megason, was immersed in ozone water for a sixth time, with the concentration of ozone water being greater than 5 ppm. The sixth time was 1-3 minutes.

[0075] Performing the above three cleaning steps in sequence will yield better cleaning results.

[0076] S103: Within the first time after rinsing with ultrapure water, the quantum chip is transferred to a wire bonding machine in a low-oxygen environment where the oxygen content does not exceed a set threshold, and the quantum chip is wire bonded to the packaging box.

[0077] After removing surface oxides and residual substances from the quantum chip, it is immediately and rapidly transferred to a low-oxygen environment wire bonding machine for bonding, minimizing oxidation of the quantum chip by the high-oxygen-content air environment. The low-oxygen environment is defined as an environment with an oxygen content <1ppm, an inert gas purity ≥99.999%, and a humidity <0.1ppm. The bonding time is ≤1 minute.

[0078] Optionally, before transferring the quantum chip to the wire bonding machine, the process further includes drying the quantum chip with an inert gas.

[0079] Optionally, in this step, a low-oxygen environment is provided for the quantum chip and packaging box by using the inert gas purging function provided by the wire bonding machine, and wire bonding is performed using thermal ultrasonic ball bonding or wedge bonding with gold wire (Au) material with a diameter of 25-50μm or superconducting aluminum wire (Al) material with a diameter of 30-75μm.

[0080] S104: Within the second time interval after wire bonding, the package and the quantum chip inside are transferred to a glove box with a low-oxygen environment. The bottom shell and cover of the package are then welded together in the glove box to complete the packaging of the quantum chip.

[0081] After the quantum chip is bonded to the packaging box, it is immediately and rapidly transferred to a low-oxygen glove box for sealing to minimize oxidation of the quantum chip caused by the high-oxygen environment. When seam welding the bottom shell and cover plate of the packaging box in the glove box, the surface of the packaging box is first cleaned of contaminants and oxide layers are removed; then, in a glove box filled with inert gas, the contact edges between the cover plate and the bottom shell of the packaging box are welded. The second welding process should last ≤1 minute. Different welding operation steps can be designed according to the different shapes of the packaging box.

[0082] The inert gas described in this application is, for example, but not limited to, suitable gases such as nitrogen, helium, and nitrogen-helium mixtures.

[0083] The method described in this embodiment of the invention removes the surface oxide layer of the quantum chip in a buffer oxide etching solution. The surface oxide layer is removed by the reaction of fluoride ions with the chip surface oxide layer, which can reduce chip surface defects, reduce chip surface roughness, and thus reduce the loss of decoherence time of the quantum bits. After removing the surface oxide layer, ultrapure water rinsing is performed to remove residual substances on the surface of the quantum chip. Combining deionized water rinsing, megasonic cleaning in ultrapure water and ozone water cleaning can effectively remove residual fluorides and particulate contaminants on the chip surface, avoid crystallization or gas release when the chip is used in a low-temperature environment, improve the chemical stability of the chip surface, and effectively prevent secondary oxidation. After removing residual materials, the chip is rapidly transferred to a low-oxygen environment wire bonding machine for wire bonding of the quantum chip and the package. Wire bonding in a low-oxygen environment effectively reduces the oxidation and embrittlement of the bonding surface and improves the conductivity and fatigue strength of the solder joints. After wire bonding, the chip and package are rapidly transferred to a low-oxygen environment glove box for seam welding of the package bottom shell and cover plate. Seam welding in a low-oxygen environment effectively improves the sealing of the packaged quantum chip and package, preventing interface delamination caused by low-temperature frost formation and moisture penetration. This method can effectively improve the reliability and low-temperature performance of quantum chip packaging.

[0084] Example 2

[0085] This invention provides a specific implementation flow of the above-described quantum chip packaging method, using a superconducting quantum chip as an example. The flow is as follows: Figure 2 and Figure 3 As shown, it includes the following steps:

[0086] S201: Immerse the quantum chip in a buffer oxide etching solution for a third time to remove the oxide layer on the surface of the quantum chip.

[0087] See Figure 2 The superconducting quantum chip shown (black part in the figure) has a natural metal / silicon oxide layer on its surface, which is blue part in the figure.

[0088] In this step, the quantum chip is immersed in buffered oxide etchant (BOE), where fluoride ions (F-) react with the natural oxide layer (such as Al2O3) on the aluminum / niobium surface to form a soluble complex. The oxidation rate of the aluminum film under natural conditions is approximately 0.01–0.1 nm / day, and the normal reaction formula is: Al2O3 + 6HF → 2AlF3 + 3H2O.

[0089] The reaction when HF is in excess is Al2O3 + 12HF → 2H3AlF3 + 3H2O.

[0090] The effectiveness of BOE solution with an NH4F:HF ratio of 4:1-7:1 and process parameters of 20-25℃ and immersion time of 30-60 seconds for removing 3-5nm oxide layers was experimentally verified.

[0091] The operation process is as follows:

[0092] The quantum chip (wafer) is vertically immersed in the BOE bath, and nitrogen is used for bubbling and stirring to enhance the uniformity of the reaction.

[0093] Experiments were conducted on different NH4F:HF ratios of 4:1, 5:1, 6:1, and 7:1, with temperatures set at 20, 22, and 25°C and soaking times set at 30, 40, 50, and 60 seconds, respectively. Experiments were also conducted on ratios outside the 4:1-7:1 range and time and temperature ranges outside the aforementioned process parameters. The experiments demonstrated that using the ratio range of 4:1-7:1 and the process parameters (temperature 20-25°C, soaking time 30-60 seconds) effectively removed the oxide layer.

[0094] In this embodiment, after removing the oxide layer, a three-stage ultrapure water rinse is performed (see the figure showing immersion in ultrapure water) to inhibit secondary oxidation, see steps S202-203.

[0095] S202: Immerse the quantum chip, after removing the oxide layer, in deionized water for four hours to remove residual substances on the surface of the quantum chip.

[0096] In this step, experiments were conducted for cases with resistivity greater than 18.2, such as using deionized water with different resistivities (18.2, 18.5, 19, 20, etc.), rinsing for 1, 2, and 3 minutes respectively. Experiments were also conducted for cases with resistivity less than 18.2, such as 18 or 17.5, or rinsing for less than 1 minute and more than 3 minutes respectively. The experiments showed that rinsing with deionized water with a conductivity greater than 18.2 MΩ·cm for 1-3 minutes can achieve better rinsing results.

[0097] S203: Perform megasonic cleaning on the quantum chip after removing the oxide layer for the fifth time to remove residual substances on the surface of the quantum chip.

[0098] In this step, experiments were conducted for different situations, including when the sound wave frequency is greater than 1MHz (e.g., frequencies of 1, 1.2, 1.5, 2, etc.) and when the sound wave frequency is less than 1MHz (e.g., frequencies of 0.5, 0.8, etc.) and when the rinsing time is 0.5, 1, 3, 4, 5, 6, etc. The results showed that using megasonic waves with a sound wave frequency greater than 1MHz for 3-5 minutes to assist in cleaning can achieve a very good cleaning effect.

[0099] S204: Immerse the quantum chip, after removing the oxide layer, in ozone water for six hours to remove residual substances on the surface of the quantum chip.

[0100] In this step, experiments were conducted for ozone water concentrations greater than 5 ppm, such as concentrations of 5, 6, 7, and 8; and for concentrations less than 5 ppm, such as frequencies of 3 and 4, and rinsing times of 0.5, 1, 2, 3, and 4. The results showed that rinsing for 1-3 minutes with ozone water concentrations greater than 5 ppm can achieve a good cleaning effect.

[0101] The above steps S202-204 can be selectively performed, either one or several, or all three steps can be performed sequentially. That is, after removing the oxide layer, the quantum chip is rinsed in deionized water, then the quantum chip rinsed in deionized water is placed in ultrapure water for megasonic cleaning, and then the quantum chip cleaned in megasonic water is placed in ozone water for cleaning, thereby improving the cleaning effect.

[0102] S205: Within a first time period after removing residual material, the quantum chip is dried with an inert gas and then transferred to a wire bonding machine in a low-oxygen environment where the oxygen content does not exceed a set threshold. The inert gas drying process is, for example, but not limited to, nitrogen drying.

[0103] See Figure 2 In the process, the superconducting quantum chip with the oxide layer removed is dried with nitrogen after being taken out of the soaking container.

[0104] S206: Wire bond the quantum chip to the packaging box.

[0105] In steps S205-206 above, the chip, after being rinsed with ultrapure water, is rapidly transferred within 1 minute to a wire bonding machine in a low-oxygen environment protected by nitrogen for wire bonding between the superconducting quantum chip and the packaging box. Verification was conducted for different transfer times of 0.5, 0.6, 0.8, 1, 1.2, and 1.5 minutes. The verification results show that transfer times of no more than 1 minute do not affect chip performance. However, the probability of secondary oxidation increases when the transfer time exceeds 1 minute.

[0106] Bonding environment control: A low-oxygen environment is achieved using an inert gas, such as, but not limited to, nitrogen; this application uses nitrogen as an example. The bonding environment can be controlled as follows: nitrogen purity ≥ 99.999%, oxygen content < 1 ppm, and humidity < 0.1 ppm. The wire bonding machine itself provides nitrogen purging. In this application, experiments were conducted to verify different inert gas purities, oxygen contents, and humidity levels. The verification results show that nitrogen purity ≥ 99.999%, oxygen content < 1 ppm, and humidity < 0.1 ppm yields the best results.

[0107] Transfer time: The time from BOE processing to entering the bonding machine is ≤1 minute to avoid surface contamination.

[0108] Bonding process:

[0109] Bonding method: Thermosonic ball bonding or wedge bonding is used, with gold wire (Au) in diameter of 25-50μm or superconducting aluminum wire (Al) in diameter of 30-75μm.

[0110] Bonding parameters:

[0111] Temperature: The stage temperature should be 80-120℃ (if using Al lines, a lower temperature is required, such as below 50℃) to avoid thermal stress damage to the Josephson junction.

[0112] Ultrasonic power: 50-100mW, frequency 60-120kHz, duration 100-300ms / solder joint.

[0113] Pressure: Bonding head pressure 30-50gf (gram force) to ensure uniform deformation of the solder joint and no cracks.

[0114] Solder joint quality inspection: Interface integrity is checked by tensile testing (5-10 gf / line) and electron microscopy (SEM).

[0115] Time control: The total bonding time for a single chip is approximately 10-30 minutes (depending on the number of solder joints), and batch operations are required to reduce the risk of exposure to nitrogen environment.

[0116] See Figure 2 As shown, the chip and the package are wire bonded under nitrogen protection. The figure shows an example of a black wire connecting the chip and the yellow bonding point on the package.

[0117] The inventors of this application have also conducted experiments on various parameters in the above-mentioned wire bonding process and selected a reasonable parameter range through the experiments.

[0118] S207: Within the second time interval after wire bonding, transfer the package and its quantum chip to a low-oxygen glove box. The low-oxygen environment can be achieved by filling the glove box with inert gas.

[0119] S208: The bottom shell and cover of the packaging box are sealed by seam welding in the glove box to complete the packaging of the quantum chip.

[0120] The packaged enclosure and chip (as a whole) were placed in a nitrogen-filled glove box within one minute, where parallel seam soldering was performed for sealing. Verification was conducted for different transfer times of 0.5, 0.6, 0.8, 1, 1.2, and 1.5 minutes. The verification results showed that transfer times of no more than one minute did not affect chip performance. However, the probability of secondary oxidation increased after transfer times exceeded one minute.

[0121] Steps S207-208 above encapsulate the quantum chip. Specifically, this may include the following processing steps:

[0122] 1. Pre-treatment stage: This stage involves material inspection and cleaning.

[0123] Check the size compatibility between the outer casing and the cover plate of the encapsulation box. The shape of the encapsulation box is, for example, but not limited to, a cuboid or cylindrical encapsulation box. Different shaped openings can be made on the encapsulation box, such as circular or rectangular openings, and the opening shape should match the shape of the cover plate. The cover plate of the encapsulation box is, for example, but not limited to, a rectangular or circular cover plate. The length and width of the rectangular cover plate should be 0.05–0.1 mm smaller than the bottom shell, and the diameter of the circular cover plate should be 0.05–0.1 mm smaller than the bottom shell. Other shapes follow a similar pattern, with the cover plate slightly smaller than the opening on the bottom shell. Then, clean the encapsulation box to remove surface oil and oxide layers.

[0124] 2. Environmental preparation.

[0125] I) Purification and Gas Control

[0126] When operating in a cleanroom environment of level 8 or higher, the glove box should be filled with positive pressure inert gas, which can be nitrogen or a nitrogen-helium mixture. The moisture content should be ≤40ppm. The glove box should be purged for more than 8 hours before subsequent sealing operations can be carried out.

[0127] 2) Pre-baking and dehumidification

[0128] If the quantum chip is a device sensitive to high moisture content, it needs to be placed in an oven and evacuated to a specified value, such as ≤1×10⁻⁶. -3 mbar, heated to ≤150℃ and kept warm.

[0129] 3. Welding execution

[0130] Different welding operations can be used for different shapes:

[0131] Taking the welding of a rectangular cover plate as an example: first weld the two parallel welds on the long side, then rotate 90° and weld the two welds on the wide side, with the starting points overlapping to form a closed seal.

[0132] Taking the welding of a circular cover plate as an example: the electrode moves in a circular arc of ≥180° along the edge of the cover plate, and a continuous weld is formed by continuous pulse current.

[0133] The welding process can be dynamically controlled, either through program control for automatic welding or manually. When using automatic welding, a step-by-step capping verification procedure can be employed; after confirming that everything is correct, switch to automatic mode. The welding speed should not be too fast (to prevent incomplete welds).

[0134] See Figure 2 As shown, parallel seam welding is performed on the packaging box and cover plate to achieve sealing.

[0135] The inventors of this application also conducted experiments on various parameters in the above-mentioned sealing process and selected a reasonable range of parameters through the experiments.

[0136] The quantum chip packaging method provided by this invention, applicable to various quantum chips such as superconducting quantum chips, involves pretreatment before packaging and packaging operations in a low-oxygen environment. Specifically, after the quantum chip is fabricated, it is immersed in a buffered oxide etchant (BOE solution) to remove the surface oxide layer and rinsed with ultrapure water. It is then immediately placed in a nitrogen-protected, low-oxygen environment wire bonding device to complete the wire bonding process with the packaging box. Subsequently, it is immediately transferred to a nitrogen-filled glove box where parallel seam welding is performed to weld the packaging box and its cover plate, completing the hermetic packaging. In existing technologies, after chip fabrication, the chip is exposed to air and the packaging process with the packaging box is completed through wire bonding / flip-chip bonding. The packaging box is then non-hermetically sealed using conventional screw locking devices. The packaging method provided in this application significantly improves the low-temperature performance and reliability of quantum chips compared to current packaging methods.

[0137] The low-oxygen environment packaging method used in this invention for chip pretreatment ensures that the chip remains in a low-oxygen environment after fabrication, avoiding oxidation of silicon and metals. This reduces SA and MA losses (TLS losses) and non-TLS losses, and has advantages including, but not limited to, the following:

[0138] In the back-end process of superconducting quantum chips, an optimized process of BOE cleaning, low-oxygen environment protection wire bonding, and laser welding capping is adopted. Through the synergy of multiple technologies, the reliability and low-temperature performance of the device are significantly improved, especially in suppressing surface loss (SA) and material-dependent loss (TLS).

[0139] The advantages of each specific process step are analyzed in detail below:

[0140] I. BOE Cleaning and Ultrapure Water Rinsing: Eliminating Interface Defects

[0141] 1) Effective removal of the oxide layer can effectively suppress TLS noise.

[0142] Buffered oxide etchant (BOE) generates soluble AlF6 by reacting fluoride ions with the natural oxide layer (such as Al2O3) on the surface of the aluminum / niobium superconducting material of the quantum chip. 3- Thoroughly remove oxide residues. The oxide layer is one of the main sources of noise in two-level systems (TLS). Cleaning the oxide layer with BOE can reduce its defect density by three orders of magnitude. After cleaning, the surface roughness Ra is less than 0.5 nm (verified by atomic force microscopy during the experiment), reducing the loss of decoherence time (T1, T2) of the qubit.

[0143] 2) Effective removal of oxide layer and residual material can ensure the low-temperature stability of quantum chip.

[0144] After oxide removal, ultrapure water rinsing removes residual substances from the surface. Using deionized water combined with megasonic (1MHz) and ozone water treatment more effectively removes residual fluorides and particulate contaminants, preventing crystallization or gas release (such as H2) at low temperatures (mK level). Cleaning with deionized water with a resistivity ≥18.2 MΩ·cm effectively reduces residual substances. Due to the good chemical stability of this ultrapure water, secondary oxidation of the chip surface is prevented, ensuring an interface contact resistance <1 mΩ. In contrast, traditional processes often result in oxide layer residues of 10-100 mΩ, making secondary oxidation highly likely.

[0145] Second, low-oxygen environment protection wire bonding can effectively suppress thermal stress and reduce parasitic losses.

[0146] Performing wire bonding (such as Au or Al wire bonding) in a low-oxygen environment can reduce the problem of oxidative embrittlement at the bonding interface and improve the conductivity and fatigue strength of the solder joint. For example, conventional bonding wires are prone to impedance mismatch or breakage due to oxidation during high-density integration, while the bonding yield under nitrogen protection can be improved by more than 20%.

[0147] Third, roll resist soldering in a glove box in a low-oxygen environment can effectively improve the airtightness of the packaged quantum chip and optimize the electromagnetic shielding effect.

[0148] By sealing the quantum chip packaging box using seam welding, hermetic packaging of the quantum chip can be achieved. Furthermore, humidity control during the packaging process ensures that the helium leakage rate of the parallel seam weld is less than 1×10⁻⁶. -9 mbar·L / s, leakage rate of traditional screw-locking sealing method >1×10 -7 The packaging method of this application can improve the airtightness by two orders of magnitude compared with the traditional screw-locking packaging method, which can effectively avoid interface delamination caused by low temperature frost and moisture penetration.

[0149] The chip pretreatment and hermetic packaging method in a low-oxygen environment proposed in this invention improves the reliability and low-temperature performance of superconducting quantum chip packaging.

[0150] Based on the same inventive concept, embodiments of the present invention also provide a quantum chip unit, such as... Figure 4 As shown, it includes: a packaging box 1 and a quantum chip 2 located in the packaging box. The packaging box 1 includes a bottom shell 11 and a cover plate 12. The quantum chip 2 is packaged into the packaging box 1 using the above method, and the two are bonded together by leads 3.

[0151] This invention also provides a quantum chip packaging system, see [link to relevant documentation]. Figure 5 As shown, it includes: a first soaking container 10, a second soaking container 20, a wire bonding machine 30, and a glove box 40;

[0152] The first immersion container 10 is used to hold a buffer oxide etching solution to immerse the quantum chip and remove the oxide layer on the surface of the quantum chip.

[0153] The second soaking container 20 is used to hold ultrapure water to soak the quantum chip after the oxide layer has been removed to remove residual substances on the surface of the quantum chip; the ultrapure water includes at least one of deionized water and ozone water;

[0154] The wire bonding machine 30 is used to provide a low-oxygen environment with an oxygen content not exceeding a set threshold, and to perform wire bonding on the quantum chip and the packaging box transferred within the first time after rinsing with ultrapure water.

[0155] The glove box 40 is used to provide a low-oxygen environment and to seam weld the package and the quantum chip inside it that are transferred over the second time period after wire bonding, thus completing the packaging of the quantum chip.

[0156] Unless otherwise specifically stated, terms such as processing, calculation, operation, determination, display, etc., may refer to the actions and / or processes of one or more processing or computing systems or similar devices that represent the manipulation and conversion of data representing physical (e.g., electronic) quantities within the registers or memory of the processing system into other data similarly representing physical quantities within the memory, registers, or other such information storage, transmission, or display devices of the processing system. Information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0157] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process may be rearranged without departing from the scope of this disclosure. The appended method claims provide elements of various steps in an exemplary order and are not intended to limit the scope to the specific order or hierarchy described.

[0158] In the detailed description above, various features are combined together in a single embodiment to simplify this disclosure. This approach to disclosure should not be construed as reflecting an intention that embodiments of the claimed subject matter require more features than are explicitly stated in each claim. Rather, as reflected in the appended claims, the invention is presented with fewer features than all of the features in a single disclosed embodiment. Therefore, the appended claims are hereby explicitly incorporated into the detailed description, with each claim representing a separate preferred embodiment of the invention.

[0159] Those skilled in the art will also understand that the various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments herein can be implemented as electronic hardware, computer software, or a combination thereof. To clearly illustrate the interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps described above are generally described in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in alternative ways for each specific application; however, such implementation decisions should not be construed as departing from the scope of this disclosure.

[0160] The steps of the methods or algorithms described in conjunction with the embodiments herein can be directly embodied in hardware, software modules executed by a processor, or a combination thereof. The software modules can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium well known in the art. An exemplary storage medium is connected to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a user terminal. Alternatively, the processor and storage medium can exist as discrete components in the user terminal.

[0161] For software implementation, the techniques described in this application can be implemented using modules (e.g., procedures, functions, etc.) that perform the functions described in this application. This software code can be stored in memory units and executed by a processor. The memory units can be implemented within the processor or outside the processor; in the latter case, they are communicatively coupled to the processor via various means, as is well known in the art.

[0162] The foregoing description includes examples of one or more embodiments. It is certainly impossible to describe all possible combinations of components or methods in order to describe the above embodiments, but those skilled in the art will recognize that further combinations and arrangements of the various embodiments are possible. Therefore, the embodiments described herein are intended to cover all such changes, modifications, and variations that fall within the scope of the appended claims. Furthermore, the term "comprising" as used in the specification or claims is interpreted in a manner similar to the term "including," as interpreted when used as a conjunction in the claims. Additionally, the use of any term "or" in the specification of the claims is intended to mean "non-exclusive or."

Claims

1. A quantum chip packaging method, characterized in that, include: The quantum chip is immersed in a buffer oxide etching solution to remove the oxide layer on the surface of the quantum chip; The quantum chip after removing the oxide layer is rinsed with ultrapure water to remove residual substances on the surface of the quantum chip. The ultrapure water rinsing includes at least one of the following: deionized water rinsing, megasonic cleaning in ultrapure water, and ozone water cleaning. Within the first hour after rinsing with ultrapure water, the quantum chip is transferred to a wire bonding machine in a low-oxygen environment where the oxygen content does not exceed a set threshold, and the quantum chip is wire bonded to the packaging box. Within two hours after wire bonding, the package and the quantum chip inside are transferred to a glove box in a low-oxygen environment. The bottom shell and cover of the package are then seam-welded in the glove box to complete the packaging of the quantum chip.

2. The method as described in claim 1, characterized in that, The step of immersing the quantum chip in a buffer oxide etching solution includes: The quantum chip is immersed in a buffer oxide etching solution for a third time, during which the etching solution is stirred by inert gas bubbling. The third time is 30-60 seconds, and the immersion temperature is 20-25℃. The buffer oxide etching solution is a mixed solution of NH4F and HF, wherein the ratio of NH4F:HF is 4:1-7:

1.

3. The method as described in claim 1, characterized in that, The process of rinsing the quantum chip with ultrapure water after removing the oxide layer to remove residual substances from the surface of the quantum chip includes: Perform at least one of the following ultrapure water rinsing steps to remove residual material from the surface of the quantum chip: The quantum chip after removing the oxide layer was immersed in deionized water for a fourth time, wherein the conductivity of the deionized water was greater than 18.2 MΩ·cm, and the fourth time was 1-3 minutes. After removing the oxide layer, the quantum chip is placed in ultrapure water for a fifth time using megasonic cleaning, wherein the frequency of the megasonic wave is greater than 1MHz and the fifth time is 3-5 minutes. The quantum chip, after the oxide layer has been removed, is immersed in ozone water for a sixth time, wherein the concentration of the ozone water is greater than 5 ppm and the sixth time is 1-3 minutes.

4. The method as described in claim 1, characterized in that, Within the first time period after rinsing with ultrapure water, before transferring the quantum chip to the wire bonding machine, the following steps are also included: The quantum chip is dried with inert gas.

5. The method as described in claim 1, characterized in that, A low-oxygen environment refers to an environment with an oxygen content of <1ppm, an inert gas purity of ≥99.999%, and a humidity of <0.1ppm.

6. The method as described in claim 1, characterized in that, The first duration is ≤1 minute; the second duration is ≤1 minute.

7. The method as described in claim 1, characterized in that, The inert gas purging function provided by the wire bonding machine provides a low-oxygen environment for the quantum chip and packaging box. The wire bonding is performed using thermo-ultrasonic ball bonding or wedge bonding, with gold wire (Au) material with a diameter of 25-50μm or superconducting aluminum wire (Al) material with a diameter of 30-75μm.

8. The method as described in claim 1, characterized in that, The process of sealing the bottom shell and cover of the packaging box by seam welding in the glove box includes: Clean contaminants and remove oxide layers from the surface of the packaging box; In a glove box filled with inert gas, the mating edges of the cover plate and the bottom shell of the packaging box are welded.

9. A quantum chip unit, characterized in that, include: A packaging box and a quantum chip located within the packaging box, the packaging box including a bottom shell and a cover plate; The quantum chip is encapsulated in a packaging box using the method described in any one of claims 1-8.

10. A quantum chip packaging system, characterized in that, include: First soaking container, second soaking container, wire bonding machine and glove box; The first immersion container is used to hold a buffer oxide etching solution to immerse the quantum chip and remove the oxide layer on the surface of the quantum chip. The second soaking container is used to hold ultrapure water to soak the quantum chip after the oxide layer has been removed to remove residual substances on the surface of the quantum chip; the ultrapure water includes at least one of deionized water and ozone water; The wire bonding machine is used to provide a low-oxygen environment with an oxygen content not exceeding a set threshold, and to perform wire bonding on the quantum chip and packaging box transferred within the first time after rinsing with ultrapure water. The glove box is used to provide a low-oxygen environment and to seam-weld the package and the quantum chip inside it that have been transferred over the second time interval after wire bonding, thus completing the packaging of the quantum chip.

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