Vertical package flex tape chip carrier

Abstract

The present application belongs to the chip packaging technical field, disclose a kind of vertical packaging flexible band line chip box, including packaging unit, working unit and signal leading-out unit, working unit includes core chip, interface chip and circuit board, three are sequentially stacked from bottom to top in packaging unit.It is located between core chip and circuit board: its side towards core chip is equipped with high-density signal switching part, and is electrically connected with core chip;The side towards circuit board is equipped with low-density signal switching part, and is electrically connected with circuit board, to realize the conversion of signal port from micron level high-density arrangement to millimeter level low-density arrangement.By the vertical stacking structure of core chip, interface chip and circuit board, and the port density conversion function of interface chip, the present application avoids the parasitic effect introduced by plane overhanging bonding wire, improves the transmission quality of high-frequency signal;At the same time, it is conducive to the scale expansion of quantum chip packaging structure.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more particularly to a vertically packaged flexible stripline chip box. Background Technology

[0002] Superconducting quantum computing, with its advantages of high scalability, high compatibility with semiconductor processes, and ease of measurement, control, and coupling, is considered one of the most promising technological routes for achieving scalable universal quantum computing. As the number of qubits increases, its computing and storage capabilities expand exponentially. However, building a highly fault-tolerant, scalable, large-scale universal quantum computer requires millions of qubits as its hardware foundation, and each qubit typically needs to be configured with independent measurement and control circuitry.

[0003] Currently, superconducting quantum chips are commonly packaged using wire bonding. Specifically, the chip is mounted on a circuit board, and electrical connections between the chip and the board are achieved via metal wires (usually gold or aluminum). Connection leads are pre-installed around the chip on the circuit board, through which the chip's signals are routed to an external measurement and control system. However, this packaging method faces the following problems in practical applications: First, as a suspended, slender structure, the metal wire bonding wire introduces significant parasitic inductance and capacitance under high-frequency microwave control signals. These parasitic parameters cause impedance mismatch, leading to signal reflection, energy attenuation, and waveform distortion, thereby degrading signal transmission quality and severely affecting the fidelity of superconducting quantum bit control signals.

[0004] Second, as the number of qubits in superconducting quantum chips continues to increase, the number of connection interfaces that need to be arranged on the circuit board also increases accordingly. It should be noted that the number of qubits integrated inside the chip increases with the square of the side length (L...). 2 The number of qubits increases exponentially, while the physical pins responsible for data throughput only increase linearly with the perimeter (4L). This imbalance between the growth rate of "quadratic" throughput and "linear" channel supply leads to a sharp increase in wiring density per unit edge length. To alleviate this pressure, the pin layout can be distributed by expanding the overall board area, but this is only a temporary solution—as the number of qubits continues to increase, the board area itself will inevitably expand sharply, ultimately limited by factors such as product physical size, cost, and signal transmission delay, and cannot be expanded indefinitely. At the same time, the space available for packaging inside the dilution cooler is extremely limited, and large-area planar packaging solutions cannot meet the integration requirements of large-scale quantum processors within a limited cooling space, which has become one of the key bottlenecks restricting the expansion of superconducting quantum computing systems. Summary of the Invention

[0005] The purpose of this invention is to provide a vertically packaged flexible stripline chip box to solve the problems of signal quality degradation and limited circuit board area expansion in existing wire bonding packaging of superconducting quantum chips. This chip box, through a vertical lead-out structure and interface density conversion mechanism, eliminates the influence of parasitic parameters on high-frequency signals, improving signal transmission quality; on the other hand, it increases the interface density on the circuit board, effectively suppressing the increase in circuit board area with the number of qubits, and helping to reduce the occupation of the limited space inside the dilution refrigerator.

[0006] To achieve this objective, the present invention adopts the following technical solution: Vertically packaged flexible stripline chip box, including: Packaging unit; The working unit includes a core chip, at least one interface chip, and a circuit board. The core chip, the interface chip, and the circuit board are all disposed within the packaging unit, and at least one interface chip is located between the core chip and the circuit board. The surface of the core chip facing the interface chip has a plurality of first signal connection portions, and the surface of the circuit board facing the interface chip has a plurality of second signal connection portions. The interface chip has a first end face and a second end face disposed opposite to each other. The first end face faces the core chip and has a plurality of first signal conversion portions arranged at a first density. The first signal conversion portions are electrically connected to the corresponding first signal connection portions. The second end face faces the circuit board and has a plurality of second signal conversion portions arranged at a second density. The second signal conversion portions are electrically connected to the corresponding second signal connection portions. The first density is greater than the second density. The signal extraction unit includes a plurality of signal lines, the first end of each of the signal lines being electrically connected to each of the second signal connection portions, and the second end of each of the signal lines passing through the packaging unit and extending outside the packaging unit for extracting signals from the core chip.

[0007] As an optional solution for vertically packaged flexible ribbon chip boxes, the first signal connection portion includes a first bonding bump, and the first signal transition portion includes a second bonding bump, wherein the second bonding bump is bonded to the first bonding bump.

[0008] As an optional solution for vertically packaged flexible ribbon chip boxes, the interface chip has a first through-silicon via (TSV) extending through its thickness direction. One end of the TSV is electrically connected to the second bonding bump, and the other end of the TSV is electrically connected to the second signal adapter via a first wire.

[0009] As an alternative to a vertically packaged flexible ribbon chip box, the second signal adapter includes a third bonding bump, which is electrically connected to the first conductor.

[0010] As an alternative to the vertically packaged flexible ribbon chip box, the second signal connection portion includes a fourth bonding bump, which is located on the side of the circuit board facing the interface chip, and the fourth bonding bump is bonded to the third bonding bump.

[0011] As an optional solution for vertically packaged flexible ribbon chip box, the circuit board has a signal terminal on the side opposite to the interface chip. The circuit board has a second through-silicon via (TSV) that extends through its thickness direction. One end of the TSV is electrically connected to the fourth bonding bump, and the other end of the TSV is electrically connected to the signal terminal through a second wire. The core of the signal line is electrically connected to the corresponding signal terminal.

[0012] As an optional solution for vertically packaged flexible stripline chip boxes, the signal line is a flexible stripline.

[0013] As an optional solution for vertically packaged flexible ribbon chip boxes, the packaging unit includes a base, and the base has a first storage slot and a second storage slot arranged sequentially along its thickness direction and interconnected with each other. The core chip is disposed in the first storage slot, the interface chip is disposed in the second storage slot, and the circuit board is disposed on the top surface of the base.

[0014] As an optional solution for vertically packaged flexible ribbon chip boxes, the packaging unit also includes a cover, which has a third storage slot and a wire pass-through port. The cover is sealed to the base, the circuit board is housed in the third storage slot, and the second end of the signal line passes through the wire pass-through port and extends to the outside of the cover.

[0015] As an optional solution for vertically packaged flexible ribbon chip boxes, the packaging unit further includes a cover with a third storage groove. The signal line is embedded in the cover, and the cover is sealed to the base. The circuit board is housed in the third storage groove, and the first end of the signal line extends out of the cover and is electrically connected to the second signal connection part.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: The vertically packaged flexible stripline chip box provided by this invention stacks the core chip, interface chip, and circuit board sequentially from bottom to top within the packaging unit. High-density and low-density signal transition sections are respectively set on the opposite ends of the interface chip, enabling reliable transition from the micron-level high-density interface of the core chip to the millimeter-level low-density interface of the circuit board. This vertically stacked lead-out architecture eliminates the traditional suspended wire bonding scheme, fundamentally eliminating the introduction path of parasitic inductance and capacitance, effectively suppressing the reflection, energy attenuation, and waveform distortion of high-frequency microwave signals, and significantly improving signal transmission quality. Simultaneously, through the organic combination of the density conversion of the interface chip and the three-dimensional vertically stacked lead-out architecture, the dense signal ports of the core chip do not need to be fan-out matched on the plane of the circuit board, but are directly led out along the vertical direction. Compared to the problem of significant expansion of the circuit board area caused by the increase in the number of interfaces in the prior art, this solution uses the interface chip to expand the micron-level high-density interface to the millimeter-level low-density interface, greatly reducing the wiring density requirements of the circuit board; the vertical lead-out method also avoids the winding of signal lines within the circuit board plane, freeing up a large amount of planar space. The synergistic effect of the two effectively suppresses the expansion of the circuit board area with the number of qubits while ensuring the reliable extraction of all signals. This reduces the occupation of the limited test space inside the dilution refrigerator and provides a reliable technical path for the integrated packaging of large-scale superconducting quantum processors. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the content of the embodiments of the present invention and these drawings without creative effort.

[0018] Figure 1 This is an assembly diagram of the vertically packaged flexible ribbon chip box in Embodiment 1 of the present invention; Figure 2 This is an internal schematic diagram of the vertically packaged flexible ribbon chip box in Embodiment 1 of the present invention; Figure 3 This is an enlarged schematic diagram of a partial internal connection of the vertically packaged flexible ribbon chip box in Embodiment 1 of the present invention; Figure 4 This is a cross-sectional view of a partial connection inside the vertically packaged flexible ribbon chip box in Embodiment 1 of the present invention; Figure 5 This is an internal schematic diagram of the vertically packaged flexible ribbon chip box in Embodiment 2 of the present invention.

[0019] Figure label: 1. Packaging unit; 2. Working unit; 3. Signal output unit; 11. Base; 111. First storage slot; 112. Second storage slot; 12. Cover; 121. Third storage slot; 122. Cable entry point; 21. Core chip; 211. First bonding bump; 22. Interface chip; 221. Second bonding bump; 222. First through-silicon via; 223. First wire; 224. Third bonding bump; 23. Circuit board; 231. Fourth bonding bump; 232. Signal terminal; 233. Second through-silicon via; 234. Second wire; 31. Signal line; 311. Wire core. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] In the description of this invention, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection or a detachable connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0022] In the description of this invention, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0023] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0024] To improve signal transmission quality and prevent the circuit board area from significantly expanding with the increase in the number of qubits, thereby reducing the occupation of the limited space inside the dilution cooler, this embodiment provides a vertically packaged flexible stripline chip box, which is described below in conjunction with... Figures 1 to 5 The specific content of this embodiment will be described in detail.

[0025] Example 1 like Figures 1 to 4 As shown, the vertically packaged flexible stripline chip box provided in this embodiment includes a packaging unit 1, a working unit 2, and a signal lead-out unit 3.

[0026] The working unit 2 includes a core chip 21, at least one interface chip 22, and a circuit board 23. The core chip 21, interface chip 22, and circuit board 23 are all disposed within the packaging unit 1, and at least one interface chip 22 is located between the core chip 21 and the circuit board 23. The surface of the core chip 21 facing the interface chip 22 is provided with a plurality of first signal connection portions, and the surface of the circuit board 23 facing the interface chip 22 is provided with a plurality of second signal connection portions. The interface chip 22 has a first end face and a second end face disposed opposite to each other. The first end face faces the core chip 21 and is provided with a plurality of first signal conversion portions spaced at a first density. The first signal conversion portions are electrically connected to the corresponding first signal connection portions. The second end face of the interface chip 22 faces the circuit board 23 and is provided with a plurality of second signal conversion portions spaced at a second density. The second signal conversion portions are electrically connected to the corresponding second signal connection portions. The first density is greater than the second density.

[0027] The signal lead-out unit 3 includes a plurality of signal lines 31, each signal line 31 having a wire core 311 inside. The first end of each signal line 31 (or wire core 311) is electrically connected to each second signal connection part in a corresponding manner. The second end of each signal line 31 (or wire core 311) passes through the packaging unit 1 and extends to the outside of the packaging unit 1 for leading out the signals of the core chip 21.

[0028] It should be noted that in this embodiment, the first signal conversion section of the interface chip 22 is electrically connected to the corresponding second signal conversion section. For example, the core chip 21 in this embodiment can be a superconducting quantum chip.

[0029] Because the core chip 21 is small in size, the density of the first signal connection portion on the core chip 21 is very high (e.g., micrometer level), while the actual signal line 31 used is relatively large in size, and the density of signal lines 31 that can be connected on the circuit board 23 is relatively low (e.g., millimeter level). There is a significant scale difference between the two, making it difficult for the circuit board 23 to directly match the signal port arrangement of the core chip 21. To solve this problem, in this embodiment, the core chip 21, the interface chip 22, and the circuit board 23 are vertically stacked from bottom to top. High-density signal conversion portions and low-density signal conversion portions are respectively provided and electrically connected on the opposite end faces of the interface chip 22, so that the high-density interface of the core chip 21 is gradually diffused to the lower-density interface that can be made on the circuit board and cables. The three are electrically connected sequentially from bottom to top.

[0030] In traditional solutions, suspended, slender metal wire bonding introduces parasitic inductance and capacitance, causing impedance mismatch under high-frequency microwave control signals, leading to signal reflection, energy attenuation, and waveform distortion. This embodiment, through the aforementioned vertical stacking structure and the density conversion function of the interface chip 22, allows the signal from the core chip 21 to be directly transferred to the circuit board 23 via the internal traces of the interface chip 22. This replaces the traditional planar suspended metal wire bonding scheme with a vertical interconnect architecture, eliminating the path for parasitic inductance and capacitance at its source. This effectively avoids the impact of parasitic parameters on signal integrity, significantly improves the transmission quality of high-frequency microwave control signals, and ensures the fidelity of quantum bit gate operations.

[0031] Meanwhile, this embodiment utilizes interface chip 22 to achieve a gradual diffusion of signal ports from micrometer-level high density to millimeter-level low density, eliminating the need for high-density interface fan-out wiring on the circuit board and effectively improving the interface layout efficiency on circuit board 23. The core chip 21, interface chip 22, and circuit board 23 are vertically stacked and packaged, making full use of the vertical space and allowing signals to be directly led out in the vertical direction, avoiding the need for signal lines to loop around in the circuit board plane. The synergistic effect of these two components increases the interface density on circuit board 23, effectively suppressing the expansion of circuit board 23 area with the increase of the number of qubits, further reducing the package size, significantly improving the overall integration, and greatly reducing the occupation of internal testing space in the dilution refrigerator. This provides a reliable structural foundation for the integrated packaging of large-scale superconducting quantum chips and can better adapt to the needs of the continuous expansion of the future quantum processor scale.

[0032] For example, such as Figure 4As shown, the first signal connection portion includes a first bonding bump 211, and the first signal transition portion includes a second bonding bump 221. The second bonding bump 221 is bonded to the first bonding bump 211, thereby realizing the electrical interconnection between the core chip 21 and the interface chip 22. The interface chip 22 has a first through-silicon via 222 extending along its thickness. One end of the first through-silicon via 222 is electrically connected to the second bonding bump 221, and the other end is electrically connected to the second signal transition portion via a first wire 223. Specifically, the second signal transition portion includes a third bonding bump 224, which is connected to the first wire 223, thereby transmitting the signal from the core chip 21 to the upper surface of the interface chip 22 through the vertical traces inside the interface chip 22.

[0033] Furthermore, such as Figure 4 As shown, the second signal connection portion includes a fourth bonding bump 231, which is located on the side of the circuit board 23 facing the interface chip 22. The fourth bonding bump 231 is bonded to the third bonding bump 224 to achieve electrical interconnection between the interface chip 22 and the circuit board 23. For example, a signal terminal 232 is provided on the side of the circuit board 23 facing away from the interface chip 22. A second through-silicon via 233 is provided inside the circuit board 23, extending along the thickness direction of the circuit board 23. One end of the second through-silicon via 233 is electrically connected to the fourth bonding bump 231, and the other end of the second through-silicon via 233 is electrically connected to the signal terminal 232 via a second wire 234. The signal line 31 is electrically connected to the corresponding signal terminal 232, thereby leading the signal of the core chip 21 to an external system.

[0034] Optionally, the first bonding bump 211, the second bonding bump 221, the third bonding bump 224 and the fourth bonding bump 231 in this embodiment can be implemented using structures such as metal pillars or metal balls, such as indium pillars or indium balls, without further restrictions.

[0035] Regarding the signal transmission path, this embodiment employs a combination of bonding bumps, through-silicon vias (TSVs), and planar conductors to construct a complete vertical signal path from the core chip 21 through the interface chip 22 to the circuit board 23. Compared to the suspended, slender metal wires in traditional wire bonding schemes, this vertical path is shorter and more compact, effectively reducing signal transmission distance and lowering transmission losses. Furthermore, the bonding bumps made of indium (such as indium pillars or indium balls) possess excellent ductility and low-temperature bonding characteristics, enabling high-precision alignment and stable electrical connections in the vertical direction. Simultaneously, the TSVs, as vertical interconnect channels, provide high-density, low-latency signal transmission capabilities, further enhancing the overall electrical performance of the package structure.

[0036] In terms of space utilization, this embodiment integrates the core chip 21, interface chip 22 and circuit board 23 tightly by vertical stacking and interconnection via silicon vias, without requiring additional horizontal space. This helps to suppress the expansion of the circuit board 23 area with the increase of the number of qubits and maintain the compactness of the overall packaging structure.

[0037] Furthermore, signal line 31 is a flexible ribbon cable. The flexible ribbon cable can be made of materials with good flexibility and bendability, such as flexible coaxial cable, flexible flat cable, or flexible ribbon cable. The flexible ribbon cable has good bendability and foldability, allowing for flexible routing and arrangement according to the actual spatial layout inside the dilution chiller. In addition, the flexible ribbon cable can adopt a multi-core integrated design, integrating multiple signal channels into a single flexible cable, thereby reducing the number of cables, simplifying the wiring structure, and improving the overall system integration and wiring neatness.

[0038] For example, the packaging unit 1 in this embodiment includes a base 11. The base 11 has a first receiving groove 111 and a second receiving groove 112 arranged sequentially along the thickness direction of the base 11 and communicating with each other. The core chip 21 is disposed in the first receiving groove 111, the interface chip 22 is disposed in the second receiving groove 112, and the circuit board 23 is disposed on the top surface of the base 11. Through the limiting effect of the first receiving groove 111 and the second receiving groove 112, the installation positions of the core chip 21 and the interface chip 22 within the base 11 can be effectively limited, ensuring the alignment accuracy and stacking stability between layers.

[0039] Furthermore, the packaging unit 1 also includes a cover 12, which has a third receiving groove 121 and a wiring port 122. The cover 12 is sealed to the base 11, and the circuit board 23 is housed in the third receiving groove 121. The second end of the signal line 31 (or wire core 311) passes through the wiring port 122 and extends to the outside of the cover 12. The cover 12 is sealed to the base 11, forming a tight fit that effectively protects the internal working unit 2 from damage or abrasion. Simultaneously, the circuit board 23 housed in the third receiving groove 121 shields the wiring port 122, placing the core chip 21 and the interface chip 22 within the enclosed space formed by the circuit board 23 and the base 11. The circuit board 23 serves both as an electrical component for signal conversion and as the upper enclosure of the packaging structure, achieving an integrated design of function and structure.

[0040] Example 2 This embodiment provides a vertically packaged flexible stripline chip box, whose basic structure is the same as that of Embodiment 1. The only difference is the arrangement of the cover 12 and the signal line 31 of the packaging unit 1. This embodiment will not describe the structure that is the same as that of Embodiment 1 again.

[0041] Furthermore, such as Figure 5 As shown, the packaging unit 1 also includes a cover 12, which has a third receiving groove 121. The signal line 31 is embedded in the cover 12, and the cover 12 is sealed to the base 11. The circuit board 23 is housed in the third receiving groove 121, and the first end of the signal line 31 extends out of the cover 12 and is electrically connected to the second signal connection part. Specifically, the cover 12 has multiple protrusions, and each signal line 31 is embedded in a corresponding protrusion, with the second end of the signal line 31 extending outward from the protrusion.

[0042] By integrating the signal line 31 of the signal lead-out unit 3 with the cover 12 of the packaging unit 1 into a single structure, the first end of the signal line 31 can be electrically connected to the second signal connection part of the circuit board 23 simultaneously while the cover 12 is installed, thereby completing the mechanical packaging and electrical connection in one go and simplifying the assembly process.

[0043] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A vertically packaged flexible stripline chip box, characterized in that, include: Packaging unit (1); The working unit (2) includes a core chip (21), at least one interface chip (22), and a circuit board (23). The core chip (21), the interface chip (22), and the circuit board (23) are all disposed within the packaging unit (1), and at least one interface chip (22) is located between the core chip (21) and the circuit board (23). The surface of the core chip (21) facing the interface chip (22) is provided with a plurality of first signal connection portions, and the surface of the circuit board (23) facing the interface chip (22) is provided with a plurality of second signal connection portions. The interface chip (22) has a first end face and a second end face disposed opposite to each other. The first end face faces the core chip (21) and is provided with a plurality of first signal conversion portions at a first density. The first signal conversion portions are electrically connected to the corresponding first signal connection portions. The second end face faces the circuit board (23) and is provided with a plurality of second signal conversion portions at a second density. The second signal conversion portions are electrically connected to the corresponding second signal connection portions. The first density is greater than the second density. The signal extraction unit (3) includes a plurality of signal lines (31). The first end of each signal line (31) is electrically connected to each of the second signal connection portions. The second end of each signal line (31) passes through the packaging unit (1) and extends to the outside of the packaging unit (1) to extract the signal of the core chip (21).

2. The vertically packaged flexible ribbon chip box according to claim 1, characterized in that, The first signal connection part includes a first bonding bump (211), and the first signal transfer part includes a second bonding bump (221), the second bonding bump (221) being bonded to the first bonding bump (211).

3. The vertically packaged flexible ribbon chip box according to claim 2, characterized in that, The interface chip (22) has a first through-silicon via (222) extending through its thickness. One end of the first through-silicon via (222) is electrically connected to the second bonding bump (221), and the other end of the first through-silicon via (222) is electrically connected to the second signal adapter through a first wire (223).

4. The vertically packaged flexible ribbon chip box according to claim 3, characterized in that, The second signal transceiver includes a third bonding bump (224), which is electrically connected to the first wire (223).

5. The vertically packaged flexible ribbon chip box according to claim 4, characterized in that, The second signal connection portion includes a fourth bonding bump (231), which is located on the side of the circuit board (23) facing the interface chip (22). The fourth bonding bump (231) is bonded to the third bonding bump (224).

6. The vertically packaged flexible stripline chip box according to claim 5, characterized in that, The circuit board (23) has a signal terminal (232) on the side opposite to the interface chip (22). The circuit board (23) has a second through-silicon via (233) that extends through its thickness. One end of the second through-silicon via (233) is electrically connected to the fourth bonding bump (231), and the other end of the second through-silicon via (233) is electrically connected to the signal terminal (232) through a second wire (234). The signal line (31) is electrically connected to the corresponding signal terminal (232).

7. The vertically packaged flexible ribbon chip box according to claim 1, characterized in that, The signal line (31) is a flexible ribbon cable.

8. The vertically packaged flexible stripline chip box according to any one of claims 1-7, characterized in that, The packaging unit (1) includes a base (11), and the base (11) has a first storage groove (111) and a second storage groove (112) arranged sequentially along its thickness direction and communicating with each other. The core chip (21) is disposed in the first storage groove (111), the interface chip (22) is disposed in the second storage groove (112), and the circuit board (23) is disposed on the top surface of the base (11).

9. The vertically packaged flexible stripline chip box according to claim 8, characterized in that, The packaging unit (1) further includes a cover (12), which has a third storage groove (121) and a wire through hole (122). The cover (12) is sealed and closed on the base (11). The circuit board (23) is housed in the third storage groove (121). The second end of the signal line (31) passes through the wire through hole (122) and extends to the outside of the cover (12).

10. The vertically packaged flexible ribbon chip cassette according to claim 8, characterized in that, The packaging unit (1) further includes a cover (12), the cover (12) is provided with a third storage groove (121), the signal line (31) is embedded in the cover (12), the cover (12) is sealed and closed on the base (11), the circuit board (23) is housed in the third storage groove (121), and the first end of the signal line (31) extends out of the cover (12) and is electrically connected to the second signal connection part.

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