Epitaxial wafer for double-layer TVS and preparation method and application thereof

Abstract

The application discloses a double-layer epitaxial wafer for TVS, a preparation method and application thereof. The epitaxial wafer comprises an N-type substrate, a P-type heavily-doped inner layer and an N-type high-resistance outer layer. The P-type heavily-doped inner layer and the N-type high-resistance outer layer are respectively grown by using different model epitaxial equipment reaction chambers, so that the NP mutual contamination problem caused by the same machine processing is avoided; and when the N-type high-resistance outer layer is grown, a trace amount of N-type dopant is synchronously introduced to neutralize the back diffusion effect of boron impurities in the inner layer P-type layer. The application can effectively inhibit the N-type high-resistance outer layer from being back diffused into P-type by the inner layer P-type heavily-doped layer, guarantee the quality of the epitaxial wafer, and the prepared epitaxial wafer can be applied to the preparation of a low-capacitance transient voltage suppression device, and is used for electrostatic discharge protection and / or surge protection of a high-frequency signal interface.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically a bilayer TVS epitaxial wafer, its preparation method, and its application. Background Technology

[0002] A transient voltage suppressor (TVS) is a semiconductor device used for voltage transient and surge protection. It offers advantages such as low clamping coefficient, small size, fast response, low leakage current, and high reliability, making it widely used in voltage transient and surge protection. With the increasing demands for high-frequency circuit protection, low-capacitance TVS devices are composed of a high-resistivity epitaxial avalanche diode and a low-resistivity substrate-based guiding diode. The low-capacitance guiding diode requires the growth of a high-resistivity N-type epitaxial layer on a heavily doped substrate.

[0003] Epitaxial growth is a method of growing a thin single-crystal layer on the surface of a single-crystal substrate along the original crystal orientation of the substrate. In the fabrication of TVS devices, a typical epitaxial structure is a bilayer epitaxial structure consisting of an N-type heavily doped substrate / a P-type heavily doped inner layer / an N-type high-resistivity outer layer (resistivity > 300 Ω·cm). However, the following technical challenges exist in the fabrication of this structure:

[0004] First, the high-temperature environment (typically above 1000℃) during epitaxial growth makes it easy for impurity atoms in the substrate and the grown epitaxial layer to evaporate into the gas phase of the reaction chamber from the front side, substrate edge, and even the back side. Dopant atoms from the substrate are then redeposited onto the silicon wafer surface during the epitaxial reaction, forming self-doping of the epitaxial layer. The degree of self-doping depends mainly on factors such as the substrate's impurity diffusion capability, substrate impurity concentration, temperature, and the cleanliness of the reaction chamber. For a structure of N-type heavily doped As substrate / P-type heavily doped inner layer / N-type high-resistivity outer layer, the inner layer is a heavily doped P-type layer (with boron as the dopant), and the outer layer is a lightly doped N-type high-resistivity layer. During the epitaxial growth of the outer N-type high-resistivity layer, boron impurities in the inner P-type heavily doped layer undergo solid-phase outward diffusion at high temperatures—that is, the dopant diffuses from the substrate side to the epitaxial layer side at the interface between the silicon substrate and the epitaxial layer—and simultaneously evaporate into the reaction chamber in gas phase, causing gas-phase self-doping. The combined effect of these two mechanisms leads to a large influx of P-type impurities (boron) into the N-type high-resistivity epitaxial layer.

[0005] When the diffusion concentration of P-type impurities exceeds that of N-type doping, the outer N-type high-resistivity layer will be back-spread to P-type, causing device failure. This problem is particularly prominent when growing lightly doped epitaxial layers with opposite conductivity types on heavily doped substrates. Therefore, effectively suppressing the back-spreading effect of the inner heavily doped P-type layer on the outer N-type high-resistivity layer in a bilayer TVS epitaxial wafer, and ensuring that the outer layer resistivity meets the device design requirement of >300 Ω·cm, is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] To address the problems described in the background art, this invention provides a method for preparing an epitaxial wafer for bilayer TVS.

[0007] Includes the following steps:

[0008] (1) Growing a heavily doped P-type inner layer on an N-type substrate;

[0009] (2) An N-type high-resistivity outer layer is grown on the P-type heavily doped inner layer;

[0010] The P-type heavily doped inner layer is grown in the reaction chamber of the first epitaxial equipment, and the N-type high-resistivity outer layer is grown in the reaction chamber of the second epitaxial equipment. It should be noted that after the P-type heavily doped inner layer is taken out of the reaction chamber of the first epitaxial equipment, its surface is easily contaminated with particles and other impurities. After secondary epitaxy, surface defects are likely to occur, affecting product quality. Therefore, after the inner layer epitaxy is completed and the product is taken out, it needs to be cleaned before the outer layer is epitaxially grown.

[0011] Furthermore, during the growth of the N-type high-resistivity outer layer, an N-type dopant is simultaneously introduced to neutralize the P-type impurities that are back-expanded in the heavily doped P-type inner layer.

[0012] Furthermore, the first epitaxial device reaction chamber is a single-wafer epitaxial device reaction chamber, and the second epitaxial device reaction chamber is a multi-wafer epitaxial device reaction chamber.

[0013] Furthermore, the epitaxial temperature for the growth of the heavily doped P-type inner layer is 1110~1130℃, the growth rate is 2~3μm / min, the doping source is 20000ppm borane, the doping flux is 180~190sccm, the thickness of the heavily doped P-type inner layer is 2~3μm, and the resistivity is 0.01~0.02Ω*cm.

[0014] Furthermore, during the growth of the N-type high-resistivity outer layer, pure SiHCl3 is introduced into the reaction chamber for intrinsic epitaxy, and a trace amount of N-type dopant phosphine is introduced simultaneously. The concentration of the N-type dopant is 30 ppm, the introduction rate is 25 sccm ~ 35 sccm, the growth temperature is 1050 ~ 1070℃, the growth rate is 1.5 ~ 2.5 μm / min, and the effective flat region thickness of the N-type high-resistivity outer layer is 5 μm ~ 7 μm.

[0015] Furthermore, the N-type substrate is an N-type heavily doped As substrate.

[0016] The epitaxial wafer obtained by this invention has a resistivity of >300Ω·cm for the N-type high-resistivity outer layer, which can be used to prepare low-capacitance transient voltage suppression devices. These devices are used for electrostatic discharge protection and / or surge protection of high-frequency signal interfaces.

[0017] The beneficial effects achieved by adopting the above technical solution are as follows: This invention grows the P-type heavily doped inner layer and the N-type high-resistivity outer layer using different types of epitaxial equipment reaction chambers. Specifically, the inner P-type heavily doped low-resistivity layer uses a single-wafer epitaxial equipment reaction chamber, while the outer N-type high-resistivity layer uses a multi-wafer epitaxial equipment reaction chamber. This separate equipment growth method effectively avoids the problem of cross-contamination between P-type and N-type dopants due to pipeline residues when processed on the same machine. It also eliminates the influence of self-doping in the reaction chamber system on the purity of the epitaxial layer, allowing for independent and precise control of the doping type and concentration of each epitaxial layer, significantly improving product yield and batch consistency.

[0018] This invention, during the growth of the N-type high-resistivity outer layer, simultaneously incorporates a trace amount of N-type dopant while performing high-purity epitaxy. This N-type impurity targets and neutralizes the P-type impurities introduced by the solid-phase diffusion of boron impurities from the heavily doped P-type inner layer during high-temperature epitaxy. This effectively suppresses the back-diffusion effect of the heavily doped P-type inner layer onto the N-type high-resistivity outer layer, ensuring that the outer layer does not diffuse into the P-type layer. This results in the effective flat region thickness and resistivity of the N-type high-resistivity outer layer meeting device design requirements of >300 Ω·cm. The two techniques work synergistically, and the separate equipment growth avoids additional P-type impurity interference introduced by cross-contamination in the reaction chamber. This allows the simultaneously incorporated N-type dopant to effectively neutralize the solid-phase diffusion with precise dosage, jointly guaranteeing the product quality of the bilayer TVS epitaxial wafer. Attached Figure Description

[0019] Figure 1 The figures show the longitudinal resistivity distribution curves of the epitaxial wafers prepared according to various embodiments and comparative examples of the present invention (measured using the extended resistance method). Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments are described clearly and completely below. The following embodiments are used to illustrate the present invention, but are not intended to limit the scope of the present invention. Unless otherwise described, the present invention employs existing technologies.

[0021] Example 1: The present invention provides a method for preparing a bilayer TVS epitaxial wafer, comprising the following steps: (1) growing a P-type heavily doped inner layer on an N-type substrate;

[0022] (2) An N-type high-resistivity outer layer is grown on the P-type heavily doped inner layer;

[0023] The P-type heavily doped inner layer is grown in the reaction chamber of the first epitaxial equipment, and the N-type high-resistivity outer layer is grown in the reaction chamber of the second epitaxial equipment.

[0024] Furthermore, during the growth of the N-type high-resistivity outer layer, an N-type dopant is simultaneously introduced to neutralize the P-type impurities that are back-expanded in the heavily doped P-type inner layer.

[0025] The first epitaxial device reaction chamber is a single-wafer epitaxial device reaction chamber, and the second epitaxial device reaction chamber is a multi-wafer epitaxial device reaction chamber.

[0026] The epitaxial temperature of the P-type heavily doped inner layer is 1120℃, the growth rate is 2.5μm / min, the doping source is 20000ppm borane, the doping flux is 185sccm, the thickness of the P-type heavily doped inner layer is 2.5μm, and the resistivity is 0.015Ω*cm.

[0027] During the growth of the N-type high-resistivity outer layer, pure SiHCl3 is introduced into the reaction chamber for intrinsic epitaxy, and a trace amount of N-type dopant phosphine is introduced simultaneously. The concentration of the N-type dopant is 30 ppm, the introduction amount is 30 sccm, the growth temperature is 1060℃, the growth rate is 2 μm / min, and the effective flat region thickness of the N-type high-resistivity outer layer is 6 μm.

[0028] The N-type substrate is an N-type heavily doped As substrate.

[0029] The epitaxial wafer obtained by the above method has a resistivity of >300Ω·cm for the N-type high-resistivity outer layer.

[0030] Example 2: The present invention provides a method for preparing a bilayer TVS epitaxial wafer, comprising the following steps: (1) growing a P-type heavily doped inner layer on an N-type substrate;

[0031] (2) An N-type high-resistivity outer layer is grown on the P-type heavily doped inner layer;

[0032] The P-type heavily doped inner layer is grown in the reaction chamber of the first epitaxial equipment, and the N-type high-resistivity outer layer is grown in the reaction chamber of the second epitaxial equipment.

[0033] Furthermore, during the growth of the N-type high-resistivity outer layer, an N-type dopant is simultaneously introduced to neutralize the P-type impurities that are back-expanded in the heavily doped P-type inner layer.

[0034] The first epitaxial device reaction chamber is a single-wafer epitaxial device reaction chamber, and the second epitaxial device reaction chamber is a multi-wafer epitaxial device reaction chamber.

[0035] The epitaxial temperature of the P-type heavily doped inner layer is 1110℃, the growth rate is 2μm / min, the doping source is 20000ppm borane, the doping flux is 180sccm, the thickness of the P-type heavily doped inner layer is 2μm, and the resistivity is 0.01Ω*cm.

[0036] During the growth of the N-type high-resistivity outer layer, pure SiHCl3 is introduced into the reaction chamber for intrinsic epitaxy, and a trace amount of N-type dopant phosphine is introduced simultaneously. The concentration of the N-type dopant is 30 ppm, the introduction rate is 25 sccm, the growth temperature is 1050℃, the growth rate is 1.5 μm / min, and the effective flat region thickness of the N-type high-resistivity outer layer is 5 μm.

[0037] The N-type substrate is an N-type heavily doped As substrate.

[0038] The epitaxial wafer obtained by the above method has a resistivity of >300Ω·cm for the N-type high-resistivity outer layer.

[0039] Example 3: The present invention provides a method for preparing a bilayer TVS epitaxial wafer, comprising the following steps: (1) growing a P-type heavily doped inner layer on an N-type substrate;

[0040] (2) An N-type high-resistivity outer layer is grown on the P-type heavily doped inner layer;

[0041] The P-type heavily doped inner layer is grown in the reaction chamber of the first epitaxial equipment, and the N-type high-resistivity outer layer is grown in the reaction chamber of the second epitaxial equipment.

[0042] Furthermore, during the growth of the N-type high-resistivity outer layer, an N-type dopant is simultaneously introduced to neutralize the P-type impurities that are back-expanded in the heavily doped P-type inner layer.

[0043] The first epitaxial device reaction chamber is a single-wafer epitaxial device reaction chamber, and the second epitaxial device reaction chamber is a multi-wafer epitaxial device reaction chamber.

[0044] The epitaxial temperature of the P-type heavily doped inner layer is 1130℃, the growth rate is 3μm / min, the doping source is 20000ppm borane, the doping flux is 190sccm, the thickness of the P-type heavily doped inner layer is 3μm, and the resistivity is 0.02Ω*cm.

[0045] During the growth of the N-type high-resistivity outer layer, pure SiHCl3 is introduced into the reaction chamber for intrinsic epitaxy, and a trace amount of N-type dopant phosphine is introduced simultaneously. The concentration of the N-type dopant is 30 ppm, the introduction rate is 35 sccm, the growth temperature is 1070℃, the growth rate is 2.5 μm / min, and the effective flat region thickness of the N-type high-resistivity outer layer is 7 μm.

[0046] The N-type substrate is an N-type heavily doped As substrate.

[0047] The epitaxial wafer obtained by the above method has a resistivity of >300Ω·cm for the N-type high-resistivity outer layer.

[0048] The following are some of the experiments conducted during the research and development process to illustrate the research and development process of this invention and the beneficial effects obtained by this invention.

[0049] Comparative Example 1: A bilayer TVS epitaxial wafer, prepared in a manner largely the same as in Example 1, except that the amount of N-type dopant introduced is 20 sccm.

[0050] Comparative Example 2: A bilayer TVS epitaxial wafer, prepared by a method largely the same as in Example 1, wherein the N-type dopant flux is 40 sccm.

[0051] Comparative Example 3: An epitaxial wafer for a bilayer TVS, prepared in a manner largely the same as in Example 1, except that no N-type dopant is introduced during the preparation process.

[0052] This invention employs the extended resistance method to detect the longitudinal resistivity distribution of epitaxial wafer samples obtained in the above embodiments and comparative examples. Specifically, the epitaxial wafer samples are subjected to angle grinding and polishing to form a bevel with a specific angle. Then, using an extended resistance probe, the micro-area extended resistance value at each depth position is measured point by point along the bevel in a step-by-step manner. Based on the standard calibration curve between extended resistance and resistivity, the measured extended resistance value is converted into the resistivity value at the corresponding depth, thereby obtaining the longitudinal resistivity distribution curve of the epitaxial wafer from the surface to the substrate. This curve allows for a direct determination of whether the resistivity of the outer N-type high-resistivity region meets the design requirement of >300 Ω·cm, and determines the effective flat region thickness of the outer layer, i.e., the longitudinal depth range where the resistivity is stably higher than 300 Ω·cm. This detection method is a conventional extended resistance profiling technique in the art.

[0053] Test results as follows Figure 1 As shown in the figure: Comparative Example 3 (without N-type dopant): As shown by the comparison line in the figure, there is a clear PN junction between the inner layer and the substrate layer, indicating that the inner layer is the desired P-type. However, there is no PN junction between the inner layer and the outer layer, indicating that the outer layer has been completely back-expanded to P-type by the boron impurities in the heavily doped P-type layer of the inner layer, and cannot form an effective N-type high-resistivity region.

[0054] Comparative Example 1 (N-type dopant injection rate 20 sccm): As shown by the solid line in the figure, the outer layer resistivity can be maintained at >300 Ω·cm near the surface, but the effective flat region thickness is thin, less than 2 μm, which is difficult to meet the actual application requirements of the device.

[0055] Example 1 (N-type dopant injection rate 30 sccm): As shown by the solid line in the figure, the outer layer resistivity remains stable at >300 Ω·cm over a wide depth range below the surface, the effective flat region thickness is about 6 μm, and the resistivity distribution curve is smooth with a steep transition region, indicating that the N-type dopant has an excellent neutralization effect on the back diffusion of P-type impurities.

[0056] Comparative Example 2 (N-type dopant injection rate 40 sccm): As shown by the solid line in the figure, the surface resistivity is already below 300 Ω·cm, which does not meet the resistivity requirements of the high-resistivity outer layer of N-type dopant. This indicates that the injection rate of N-type dopant is too high, which has caused overcompensation for the intrinsic high-resistivity characteristics of the outer layer.

[0057] In summary, the results of the extended resistance test clearly demonstrate that the present invention, through the technique of growing in separate equipment combined with the simultaneous introduction of N-type dopant, can effectively solve the problem of reverse expansion of the P-type heavily doped inner layer onto the outer N-type high-resistivity layer, thereby obtaining a high-quality epitaxial wafer that meets the performance requirements of TVS devices.

[0058] Based on the excellent performance of the epitaxial wafer obtained by this invention, the epitaxial wafer of this invention can be used to fabricate low-capacitance transient voltage suppressors. These low-capacitance transient voltage suppressors are used for electrostatic discharge protection and / or surge protection of high-frequency signal interfaces. The junction capacitance of a transient voltage suppressor (TVS) mainly depends on the width of its PN junction depletion region, which is determined by the doping concentration (i.e., resistivity) and thickness of the epitaxial layer. Specifically, the higher the resistivity of the epitaxial layer (the lower the doping concentration) and the greater the thickness of the high-resistivity layer, the wider the depletion region and the lower the junction capacitance. For high-frequency signal interfaces (such as USB, HDMI, Ethernet, etc.), the signal transmission rate is high, and they are extremely sensitive to parasitic capacitance. Excessive capacitance can lead to signal distortion, attenuation, or even transmission failure; therefore, the protection device must have extremely low junction capacitance.

[0059] The N-type high-resistivity outer layer prepared by this invention has a stable resistivity >300 Ω·cm, belonging to the lightly doped region. This effectively widens the depletion region of the PN junction, thereby significantly reducing the junction capacitance of the device. Simultaneously, this invention effectively suppresses the back-diffusion of boron impurities in the inner heavily doped P-type layer by simultaneously introducing N-type dopant, resulting in an effective flat region thickness of approximately 6 μm in the outer N-type high-resistivity region. This thickness provides sufficient depletion region width for low capacitance while ensuring that the epitaxial layer does not punch through under the device operating voltage, thus ensuring stable and reliable breakdown voltage and clamping characteristics of the device.

[0060] Therefore, this invention, through the synergistic combination of two techniques—"separate equipment growth" and "simultaneous N-type doping"—obtains an epitaxial wafer that simultaneously possesses the advantages of high resistivity, suitable effective flat region thickness, and absence of P-type back-expansion defects. This provides an ideal material basis for fabricating low-capacitance TVS devices. The low-capacitance TVS devices fabricated based on the epitaxial wafers of this invention can effectively meet the protection requirements of high-frequency signal interfaces for low parasitic capacitance, fast response, and reliable clamping. Therefore, they are suitable for electrostatic discharge (ESD) and surge protection of high-frequency signal interfaces such as USB, HDMI, Ethernet, RS-485, and CAN bus.

[0061] It should be noted that the above-described technical content of this invention is merely an explanation and clarification to enable those skilled in the art to understand the technical essence of this invention, and therefore is not intended to limit the scope of protection of this invention. The scope of protection of this invention should be determined by the claims. Those skilled in the art should understand that any modifications, equivalent substitutions, and improvements made based on the essential spirit of this invention should be within the scope of protection of this invention.

Claims

1. A method for manufacturing an epitaxial wafer for a double-layer TVS, characterized by, Includes the following steps: (1) Growing a heavily doped P-type inner layer on an N-type substrate; (2) An N-type high-resistivity outer layer is grown on the P-type heavily doped inner layer; The P-type heavily doped inner layer is grown in the reaction chamber of the first epitaxial equipment, and the N-type high-resistivity outer layer is grown in the reaction chamber of the second epitaxial equipment. Furthermore, during the growth of the N-type high-resistivity outer layer, an N-type dopant is simultaneously introduced to neutralize the P-type impurities that are back-expanded in the heavily doped P-type inner layer.

2. The method of claim 1, wherein, The first epitaxial device reaction chamber is a single-wafer epitaxial device reaction chamber, and the second epitaxial device reaction chamber is a multi-wafer epitaxial device reaction chamber.

3. The method of claim 1, wherein, The epitaxial temperature for growing the heavily doped P-type inner layer is 1110~1130℃, the growth rate is 2~3μm / min, the doping source is 20000ppm borane, the doping flux is 180~190sccm, the thickness of the heavily doped P-type inner layer is 2~3μm, and the resistivity is 0.01~0.02Ω*cm.

4. The method of claim 1, wherein, During the growth of the N-type high-resistivity outer layer, pure SiHCl3 is introduced into the reaction chamber for intrinsic epitaxy, and a trace amount of N-type dopant phosphine is introduced simultaneously. The concentration of the N-type dopant is 30 ppm, the introduction rate is 25 sccm ~ 35 sccm, the growth temperature is 1050 ~ 1070℃, the growth rate is 1.5 ~ 2.5 μm / min, and the effective flat region thickness of the N-type high-resistivity outer layer is 5 μm ~ 7 μm.

5. The method of claim 1, wherein, The N-type substrate is an N-type heavily doped As substrate.

6. An epitaxial wafer for a double-layer TVS, characterized by The N-type high-resistivity outer layer is prepared by the preparation method according to any one of claims 1 to 5, and the resistivity is >300Ω·cm.

7. Use of an epitaxial wafer according to claim 6, characterised in that Applications in the fabrication of low-capacitance transient voltage suppression devices.

8. Use according to claim 7, characterized in that, The low-capacitance transient voltage suppression device is used for electrostatic discharge protection and / or surge protection of high-frequency signal interfaces.

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