Polycrystalline silicon layer preparation method, substrate structure and radio frequency front-end chip

Abstract

The present disclosure relates to a preparation method of a polysilicon layer, a substrate structure and a radio frequency front-end chip. In an aspect, a preparation method of a polysilicon layer is provided. The method comprises: providing a substrate; forming an amorphous silicon precursor layer on a surface of the substrate; and performing a rapid thermal treatment on the silicon precursor layer, the rapid thermal treatment comprising: heating the silicon precursor layer to an intermediate temperature lower than a crystallization temperature of the silicon precursor layer at a first heating rate, and maintaining the first preset time length to make the silicon precursor layer reach thermal equilibrium in an amorphous state; and heating the silicon precursor layer to a target temperature at a second heating rate, and maintaining the second preset time length to make the silicon precursor layer crystallize to form a polysilicon layer, wherein the second heating rate is greater than the first heating rate. Thus, the grain size can be improved, the trap capture capacity of the prepared polysilicon layer is improved, and the electrical performance of the radio frequency front-end chip is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, specifically to a method for preparing a polycrystalline silicon layer, a substrate structure, and a radio frequency front-end chip. Background Technology

[0002] Silicon-on-Insulator (SOI) has wide applications in communications, IoT, and RF front-end chips for smart devices due to its dielectric isolation structure. However, as the operating frequency of these devices continues to increase, the parasitic surface conduction layer (PSC) formed by the disordered migration of charge carriers at the substrate interface causes RF loss and crosstalk problems, thus limiting device performance.

[0003] In related technologies, a common approach is to introduce a poly-Si trap-rich layer on a silicon substrate. This layer traps free charge carriers through grain boundary traps in the poly-silicon, thereby blocking parasitic conduction paths. However, the poly-silicon layers formed by the fabrication processes in these technologies often have limited trapping capacity, making it difficult to suppress radio frequency losses and crosstalk, thus affecting the electrical performance of the device. Summary of the Invention

[0004] This section is based on the general summary of this disclosure, and not on a full disclosure of the entire scope or all features of this disclosure.

[0005] According to one aspect of this disclosure, a method for preparing a polycrystalline silicon layer is provided. The method includes: providing a substrate; forming an amorphous silicon precursor layer on the surface of the substrate; and subjecting the silicon precursor layer to rapid thermal processing, the rapid thermal processing comprising: heating the silicon precursor layer to an intermediate temperature below the crystallization temperature of the silicon precursor layer at a first heating rate, and holding it for a first preset time to allow the silicon precursor layer to reach thermal equilibrium while remaining amorphous; then heating the silicon precursor layer to a target temperature at a second heating rate, and holding it for a second preset time to allow the silicon precursor layer to crystallize and form a polycrystalline silicon layer, wherein the second heating rate is greater than the first heating rate.

[0006] According to another aspect of this disclosure, a substrate structure is provided. The substrate structure includes a substrate and a polycrystalline silicon layer disposed on the surface of the substrate. The polycrystalline silicon layer has an average grain size of 50-150 nm, and the grain size variation coefficient of the polycrystalline silicon layer is less than or equal to 20%.

[0007] According to another aspect of this disclosure, a radio frequency (RF) front-end chip is provided. The RF front-end chip includes the substrate structure described in the foregoing aspects.

[0008] This disclosure provides a method for fabricating a polycrystalline silicon layer, a substrate structure, and a radio frequency (RF) front-end chip. By first heating the amorphous silicon precursor layer at a low rate to an intermediate temperature below its crystallization temperature, fine thermal equilibrium is achieved within the film layer and at the substrate interface, preventing premature nucleation due to localized thermal stress or temperature gradients. Then, the temperature is rapidly increased to the target temperature at a higher rate and held for a short, predetermined duration, allowing the entire film layer to almost simultaneously overcome the nucleation energy barrier, achieving explosive nucleation. Simultaneously, the short holding time suppresses atomic diffusion and blocks Oswald ripening, resulting in a polycrystalline silicon layer with fine grain size, high uniformity, and low defect density. This improves the trapping capacity of the fabricated polycrystalline silicon layer and consequently enhances the electrical performance of the RF front-end chip. Attached Figure Description

[0009] The features and advantages of embodiments of the present disclosure will become more readily understood from the following description with reference to the accompanying drawings. The drawings are not drawn to scale and some features may be enlarged or reduced to show details of specific components.

[0010] In the attached diagram: Figure 1 This is a flowchart of a method for preparing a polycrystalline silicon layer according to an embodiment of the present disclosure.

[0011] Figure 2 To utilize Figure 1 The diagram shows a schematic of the preparation method for the silicon precursor layer.

[0012] Figure 3 To utilize Figure 1 The diagram shows a method for forming a polycrystalline silicon layer.

[0013] Figure 4 This is a schematic diagram showing the change in the grain size of the polycrystalline silicon layer with a second preset time when the polycrystalline silicon layer is prepared using the polycrystalline silicon layer preparation method of this disclosure at a target temperature of 700°C.

[0014] Figure 5 This is a schematic diagram showing the change in the grain size of the polycrystalline silicon layer with a second preset time during the preparation using the polycrystalline silicon layer preparation method disclosed herein.

[0015] Figure 6 This is a schematic diagram of a substrate structure according to an embodiment of the present disclosure.

[0016] In the accompanying drawings, the same or corresponding technical features, parts or components are represented by the same or corresponding reference numerals. Detailed Implementation

[0017] The present disclosure will now be described in detail with reference to the accompanying drawings and exemplary embodiments. It should be noted that the following detailed description of the present disclosure is for illustrative purposes only and is not intended to limit the scope of the disclosure.

[0018] It should be noted that, for clarity, not all features of a particular embodiment are described or shown in the specification and drawings. Furthermore, to avoid unnecessary details obscuring the technical solutions of interest in this disclosure, only the device structures and parts closely related to the technical solutions of this disclosure are described and shown in the specification and drawings, while other details that are not closely related to the technical content of this disclosure and are known to those skilled in the art are omitted.

[0019] In the semiconductor device manufacturing process of related technologies, such as the fabrication of silicon-on-insulator (SiI) radio frequency front-end chips, a polycrystalline silicon charge trapping layer is typically fabricated on a silicon substrate to suppress parasitic surface conduction (PSC). However, conventional deposition processes used in these technologies, such as deposition at high temperatures of 580–650°C, while achieving high growth rates, lead to intensified surface diffusion of polycrystalline silicon atoms at high temperatures. This intense atomic diffusion causes the Ostwald ripening process to run out of control, ultimately resulting in abnormal grain coarsening and an increase in the average grain size (typically greater than 400 nm).

[0020] This coarse grain structure leads to insufficient grain boundary density inside the polycrystalline silicon layer, which in turn results in limited trap capture capacity at the grain boundaries. This makes it impossible to effectively capture the disordered free carriers migrating at the substrate interface in the millimeter wave band (such as 28 GHz and above), and makes it difficult to solve the problems of radio frequency loss and crosstalk.

[0021] To address this, grain refinement techniques are typically employed. For example, ion implantation or doping can pin grain boundaries to some extent to suppress grain growth, but this introduces additional recombination centers, negatively impacting the electrical performance of RF devices. Another approach is low-temperature deposition to suppress surface atomic diffusion, but this leads to a sharp drop in polysilicon deposition rates, reducing production efficiency and making it difficult to meet the industrial-scale production demands of wafers (e.g., 12-inch wafers with a diameter of 300mm).

[0022] In this regard, according to the embodiments of the present disclosure, a method for preparing a polycrystalline silicon layer is provided.

[0023] First, refer to Figure 1 The method for preparing the polycrystalline silicon layer includes: Step S110: Provide a substrate.

[0024] In the initial stage of the fabrication process, a substrate 220 is first provided. The substrate 220 serves as a reference platform for fabricating the polycrystalline silicon layer. Exemplarily, the substrate 220 may be a single-crystal silicon wafer, silicon nitride, silicon oxide, or quartz, etc., and this disclosure is not limited thereto.

[0025] It is conceivable that during the substrate 220 provision stage, the substrate (e.g., an 8- to 12-inch silicon wafer) can be subjected to industry-standard semiconductor wet cleaning (e.g., RCA cleaning technology) to remove contaminants such as organic matter, metal ions, and particles from the surface of the substrate 220, thereby providing a clean interface environment for subsequent thin film deposition.

[0026] Step S120: Form an amorphous silicon precursor layer on the surface of the substrate.

[0027] It is conceivable that, in conjunction with reference Figure 2 After providing the substrate 220, an amorphous silicon precursor layer 240 can be formed on the surface of the cleaned substrate 220 by chemical vapor deposition.

[0028] It is understandable that the silicon precursor layer 240 can be a continuous, uniform amorphous silicon thin film. Here, amorphous refers to the amorphous characteristics of the silicon precursor layer 240, which exhibits short-range order and long-range disorder. Compared to directly depositing polycrystalline silicon, depositing an amorphous silicon thin film as a precursor has the following physicochemical advantages: First, amorphous silicon is thermodynamically metastable and has a higher Gibbs free energy than polycrystalline silicon. This high free energy state allows atoms in amorphous silicon to undergo a phase transition by overcoming a relatively low energy barrier during subsequent rapid heating, thereby promoting the formation of critical nuclei and increasing the nucleation density, laying the foundation for obtaining fine and dense grains.

[0029] It is also understandable that maintaining the continuous and uniform state of the silicon precursor layer 240 provides a high-quality precursor structure foundation for subsequent heat treatment stages. For example, the continuity of the silicon precursor layer 240 can be determined using a scanning electron microscope (SEM). Specifically, after the thin film is deposited, SEM images are taken at the center point of any diameter along the wafer surface, at 2 / R (i.e., half the radius from the center point), and at a point 5 mm from the edge, and the SEM image features are observed. If the SEM image shows that the thin film is dense and continuous, with no macroscopic cracks or pores on the surface, and completely covers the substrate, it can be preliminarily determined that the silicon precursor layer 240 meets the requirements for continuity.

[0030] In addition, the uniformity of the silicon precursor layer 240 can be determined using a spectroscopic ellipsometry. Specifically, multiple measurements can be taken across the entire wafer. If the ellipsometry shows that the film thickness non-uniformity is less than ±5.0% across the entire wafer, it can be preliminarily determined that the entire wafer maintains consistent heating and phase transition behavior during subsequent rapid thermal processing, meeting the requirements for uniformity.

[0031] By evaluating the continuity and uniformity of the silicon precursor layer 240, the consistency of heat absorption quality in different regions of the wafer can be improved during subsequent rapid thermal processing stages, thereby improving the consistency of phase transition stages and nucleation density.

[0032] Step S130: Perform rapid thermal treatment on the silicon precursor layer.

[0033] In the actual reaction process, the substrate 220 with the deposited amorphous silicon precursor layer 240 can be transferred to the reaction chamber of the rapid thermal processing equipment. To prevent the silicon wafer from oxidizing at high temperatures, the equipment chamber can be purged with high-purity nitrogen gas first, and the nitrogen atmosphere can be maintained continuously throughout the rapid thermal processing.

[0034] It is conceivable that, in conjunction with reference Figure 3 The aforementioned rapid heat treatment method can be either rapid thermal annealing (RTA) or laser annealing (LA). This rapid heat treatment method includes the following stepped heating process: First, the silicon precursor layer 240 is heated to an intermediate temperature below the crystallization temperature of the silicon precursor layer 240 at a first heating rate, and held for a first preset time T1, so that the silicon precursor layer 240 reaches thermal equilibrium while maintaining an amorphous state.

[0035] Next, the silicon precursor layer 240 is heated to the target temperature at a second heating rate and held for a second preset time T2 to allow the silicon precursor layer to crystallize and form a polycrystalline silicon layer 260. The second heating rate is greater than the first heating rate.

[0036] Understandably, related technologies typically employ a solid-state crystallization process involving direct heating and holding for an extended period. This results in immediate atomic diffusion following nucleation, inducing Oswald ripening and continuous grain growth. However, given the thickness of the silicon precursor layer 240, if the method of directly heating from room temperature to the target crystallization temperature at a high rate, as used in related technologies, is employed, the significant temperature difference between the initial and final temperatures, along with the thermal radiation from the heating equipment and the thermal conductivity of the substrate 220 itself, will cause uneven temperature distribution within and on the surface of the thin film. This temperature unevenness directly leads to a time difference in the crystallization process between the interior and surface of the amorphous silicon during phase transition crystallization, ultimately resulting in poor uniformity of the grain size distribution in the fabricated polycrystalline silicon layer 260.

[0037] In response, this disclosure introduces a stepped heating method that includes a first heating stage and a second heating stage.

[0038] First, a first heating stage is introduced during the rapid thermal processing. This stage involves heating the system (in this disclosure, substrate 220 and the silicon precursor layer 240 or polycrystalline silicon layer 260 formed thereon, which can also be referred to as substrate structure 200) to an intermediate temperature below the crystallization temperature of the silicon precursor layer 240 at a relatively slow first heating rate, and holding this temperature briefly for a first preset duration T1. In this way, the silicon precursor layer 240 achieves a thermally uniform state. During this stage, since the temperature has not yet reached the crystallization threshold, the silicon precursor layer 240 as a whole remains amorphous, and its internal temperature gradient is essentially eliminated, thereby achieving thermal equilibrium and preventing premature regional nucleation caused by localized thermal stress or temperature gradients.

[0039] Here, the thermal equilibrium state of the silicon precursor layer 240 can be determined by the temperature uniformity at various points on the thin film surface. For example, after the first heating stage, the overall temperature non-uniformity of the thin film should be controlled within a range of less than ±10°C. Although silicon itself has a high thermal conductivity, for micron-sized thin films, its heat transfer time is much shorter than that of rapid thermal processing. However, by introducing this intermediate temperature as a buffer, the thermal uniformity of large-size (e.g., 8 to 12 inches) wafers can be maximized across the entire surface.

[0040] After the system reaches thermal equilibrium, a second heating stage is introduced. This stage employs a faster heating rate than the first, rapidly raising the system to the target temperature within a short time. Having reached thermal equilibrium after the first heating stage, the rapid heating in the second stage allows all regions of the silicon precursor layer 240 to almost simultaneously overcome the nucleation energy barrier. Driven by high Gibbs free energy, atoms can simultaneously overcome lower energy barriers, achieving explosive synchronous nucleation in a short time, instantly forming high-density and spatially uniform critical nuclei.

[0041] After the system reaches the target temperature, it is held for a second preset time T2. Within this preset time, the energy provided by the system is only sufficient to drive the amorphous silicon to undergo a crystallization phase transition and complete nucleation. However, due to the extremely short time, the system temperature and time are insufficient to support atomic diffusion. Therefore, the already formed high-density nuclei cannot continue to grow due to the lack of sufficient atomic supply, and the long-range migration of atoms and the Oswald ripening process are effectively blocked.

[0042] The polycrystalline silicon layer fabrication method described above, which involves depositing an amorphous silicon precursor layer 240, followed by a slow-heating first stage to bring the precursor layer 240 to thermal equilibrium, and then a faster-heating second stage to rapidly raise the precursor layer 240 to the target temperature process window while maintaining a short second preset time, effectively improves grain size. This results in a polycrystalline silicon layer structure with small grain size, a large number of grains, and a complete and uniformly distributed grain boundary network. The high-density grain boundary network resulting from this structure provides sufficient charge trap centers to effectively capture parasitic carriers, thereby solving the problems of coarse grains and insufficient trap density caused by existing high-temperature polycrystalline silicon processes. This reduces device RF losses and thus improves the electrical performance of RF front-end chips.

[0043] It is conceivable that the intermediate temperature can be 300~500℃, and the first preset duration T1 can be 5~20 seconds.

[0044] It is understandable that setting the intermediate temperature reached by the silicon precursor layer 240 in the first heating stage to 300~500℃ ensures that this intermediate temperature is below the critical temperature for the phase transition and crystallization of amorphous silicon. This allows the thin film to absorb sufficient heat to reduce the temperature difference caused by rapid heating in the subsequent second heating stage. Furthermore, by setting a shorter first preset duration T1, the thermal equilibrium state of the silicon precursor layer 240 can be kept stable, and the amorphous precursor state can be maintained at all times.

[0045] It is conceivable that the first heating rate can be 30~100℃ / second, and the second heating rate can be 100~150℃ / second.

[0046] Understandably, the first heating rate of 30~100℃ / second is relatively mild and can prevent the deposited thick film from developing microcracks due to thermal stress during the initial heating stage. The second heating rate of 100~150℃ / second ensures that the system can jump from the intermediate temperature of 300~500℃ to the target crystallization temperature in a short period of time.

[0047] By setting different heating rate ranges in the first and second heating stages, the silicon precursor layer 240 can maintain a stable amorphous state while achieving thermal uniformity, and successfully form high-density critical nuclei at higher heating rates.

[0048] It is conceivable that the target temperature could be in the range of 680~720℃.

[0049] Compared to the operating temperature of traditional heat treatment processes, 680~720℃ falls within the low to medium temperature window for amorphous silicon solid-state crystallization. As shown in Table 1 below, this disclosure provides comparative data on the grain state of polycrystalline silicon layer 260 at different crystallization temperatures through multiple sets of experiments, including Comparative Examples 1 and 2, and Examples 1, 2, and 3. It should be noted that the crystallization temperatures in Table 1 have the same meaning as the target temperatures in the second heating stage of this disclosure.

[0050] Table 1

[0051] Please refer to Table 1: In Comparative Example 1, due to the low crystallization temperature, the system failed to provide enough energy to overcome the nucleation barrier, resulting in a large number of amorphous regions remaining inside the polycrystalline silicon layer 260. The grain boundary network was incomplete, and its effective resistivity at 28 GHz was only 1.2 kΩ·cm, which could not meet the isolation requirements of radio frequency devices.

[0052] In Example 1, the system began to crystallize, with the average grain size D refined to 70 nm. Although trace amounts of amorphous phase remained, the estimated grain boundary density was high, approximately 1.18 × 10⁻⁶. 4 μm - ¹, its effective resistivity at 28 GHz is increased to 7.5 kΩ·cm.

[0053] In Example 2, the system achieved complete crystallization with no amorphous residue, an average grain size D of 85 nm, and formed a complete high-density grain boundary network with a high estimated grain boundary density of approximately 1.05 × 10⁻⁶. 4 μm - ¹, its effective resistivity at 28 GHz reaches 8.7 kΩ·cm.

[0054] In Example 3, the average grain size D was slightly increased to 130 nm, and the grain boundary density was relatively high, with an estimated value of approximately 0.77 × 10⁻⁶. 4 μm - ¹, with an effective resistivity of 6.5 kΩ·cm at 28 GHz, it still maintains an excellent level.

[0055] In Comparative Example 2, due to the excessively high crystallization temperature, even with a short holding time, the excessively high temperature still promoted violent surface diffusion of atoms, leading to uncontrolled Oswald ripening and coarsening of the average grain size D to greater than 250 nm. The coarse grains resulted in a significant decrease in grain boundary density, with an estimated value of only about 0.29 × 10⁻⁶. 4 μm - ¹, the effective resistivity at 28 GHz decreases to 5.6 kΩ·cm.

[0056] As can be clearly seen from the data in Table 1, this disclosure, through the reflection of parameters such as the average grain size D, estimated grain boundary density, and effective resistivity at 28 GHz, demonstrates that when the target temperature is set within the range of 680~720℃, the energy in the system precisely meets the requirements for high-density nucleation, while effectively avoiding rapid grain coarsening caused by high temperatures. This increases the grain boundary density within the polysilicon layer 260, thereby helping to suppress parasitic surface conduction and solve the RF loss problem of the device.

[0057] The second preset duration T2 will affect crystal growth. It can be assumed that the second preset duration T2 can be 3 to 10 seconds.

[0058] Combined with reference Figure 4 and Figure 5 , Figure 4 This is a box plot showing the change in grain size D0 of polycrystalline silicon layer 260 with the second preset time T2 at a target temperature of 700°C. Figure 5 The graph shows the change in grain size D0 as a function of the second preset time T2. It can be clearly observed from the graph that the crystallization state and grain size of the polysilicon layer 260 undergo nonlinear evolution at different stages of the second preset time T2.

[0059] As shown in Table 2 below, this disclosure provides comparative data for different second preset durations T2 through multiple sets of experiments, including Comparative Examples 3 and 4, and Examples 4, 5, and 6. It should be noted that the samples in Table 2 refer to the substrate structure 200 formed in each set of experiments as described above.

[0060] Table 2

[0061] Please refer to Table 2: In Comparative Example 3, when the second preset duration T2 is 2 seconds, the system is in a partially crystalline state with a large number of amorphous regions inside. Although the average grain size D is small (about 50 nm) and the relative value of the grain boundary density is high, the grain boundary network is not completely connected and the grain boundary network presents an incomplete state.

[0062] In Example 4, when the second preset duration T2 is 5 seconds, the system reaches a fully crystalline state with no residual amorphous regions. At this time, the average grain size D reaches a locally small value (approximately 85 nm), and the relative grain boundary density is high, forming a complete high-density grain boundary network. This time point is the inflection point where nucleation is complete but significant bulk diffusion growth has not yet occurred.

[0063] In Example 5, when the second preset duration T2 is extended to 8 seconds, although the system remains fully crystallized, the grains begin to coarsen, the average grain size D increases to about 110 nm, and the relative value of grain boundary density begins to decrease.

[0064] In Example 6, when the second preset duration T2 reaches 10 seconds, the grains coarsen significantly, the average grain size D further increases to about 150 nm, and the grain boundary density further decreases.

[0065] In Comparative Example 4, when the second preset duration T2 is extended to 15 seconds or more, the grains become severely coarsened, the average grain size D increases to about 190 nm or even higher, and the grain boundary density decreases significantly.

[0066] As can be clearly seen from the data in Table 2, when the second preset duration T2 is around 5 seconds, the system is at the critical inflection point between the completion of nucleation and the onset of coarsening. When the second preset duration T2 exceeds 10 seconds, the grains begin to coarsen significantly. It is understandable that even if a certain degree of coarsening occurs within the range of 3 to 10 seconds, compared with the coarse grains larger than 400 nm formed by high-temperature deposition processes in related technologies, the grain size obtained by the preparation method disclosed in this invention still has a significant advantage in refining the grain size.

[0067] By setting the second preset duration T2 to 3 to 10 seconds, a more complete fine-grained network can be obtained, and the polycrystalline silicon layer 260 obtained by the preparation method of this disclosure can provide better electrical characteristics for subsequent products such as RF front-end chips.

[0068] As can be seen from the experimental data in Tables 1 and 2 above, the process parameters of the second heating stage are not designed independently. Specifically, the effect of the target temperature change on grain size and grain boundary density is non-monotonic. For example, during the process of the target temperature increasing from 680℃ to 720℃, the grain size increases from 70nm to 130nm, the effective resistance at 28 GHz first increases and then decreases, while the resistivity remains at a relatively high value within this target temperature range. The change of the second preset duration T2 also exhibits a non-linear change law with a clear inflection point. For example, when the second preset duration T2 is 5 seconds, the system is at the critical node where nucleation is completed and grain coarsening begins.

[0069] It is conceivable that the silicon precursor layer 240 can be formed by a low-pressure chemical vapor deposition process, in which the reaction chamber temperature can be 550~570℃ and the reaction chamber pressure can be 400~600mTorr.

[0070] In the Low Pressure Chemical Vapor Deposition (LPCVD) process, the cleaned substrate 220 is first placed in the LPCVD reaction chamber, and the temperature of the reaction chamber is stabilized in a medium-low temperature range of 550-570°C. This temperature range effectively suppresses long-range migration of silicon atoms, ensuring that the silicon precursor layer 240 always exhibits an amorphous structure. Then, silane (SiH4) is introduced as the reaction gas source, and the flow rate of the silane can be configured to be 300-500 sccm. Exemplarily, in the various embodiments and comparative examples of this disclosure, 450 sccm can be used.

[0071] It is also conceivable that the deposition process uses only nitrogen as the carrier gas. Furthermore, by controlling the reaction chamber pressure at 400~600 mTorr, the silicon precursor layer 240 can be grown continuously and uniformly on the surface of the substrate 220 at a moderate rate.

[0072] It is conceivable that the thickness of the silicon precursor layer 240 can be 1.5~2μm.

[0073] As mentioned earlier, an amorphous silicon precursor layer 240 can be formed on the surface of substrate 220 using a low-pressure chemical vapor deposition (LPCVD) process. By controlling the process parameters of the LPCVD reaction chamber during the LPCVD process, a silicon thin film with a thickness of approximately 1.5~2 μm can be generated.

[0074] In this disclosure, the thickness of the silicon precursor layer 240 affects its internal temperature uniformity. However, silicon itself has a high thermal conductivity, and for micron-sized thin films, its heat transfer time is much shorter than that of rapid thermal treatment. In this case, for thicker films, the preparation method of this disclosure can still maintain the thermal uniformity of amorphous silicon thin films.

[0075] Therefore, selecting a silicon precursor layer 240 with a thickness of approximately 1.5~2μm allows for maximizing the thermal uniformity of the amorphous silicon thin film, thereby providing a stable precursor layer structure basis for the subsequent crystallization stage.

[0076] It is conceivable that the rapid thermal processing may also include a cooling stage: after holding for a second preset time T2, the silicon precursor layer 240 is cooled to below 400°C at a cooling rate of greater than or equal to 50°C / second.

[0077] Understandably, after the first and second heating stages, fine and dense polycrystalline silicon grains have formed on substrate 220. In this situation, by means of slow cooling, such as natural cooling or a slower cooling rate, the heating equipment and the silicon wafer itself still possess a certain amount of heat energy. This residual heat causes silicon atoms at the grain boundaries to continue to diffuse microscopically, thereby restarting the previously blocked Oswald ripening process. This leads to secondary coarsening of the already formed fine grains, thus reducing the grain boundary density.

[0078] To address this, this disclosure introduces a cooling phase into the rapid heat treatment process. Specifically, heating is stopped after the second preset time T2, and the silicon precursor layer 240 is rapidly cooled at a cooling rate greater than or equal to 50°C / second. This rapid cooling method allows the silicon precursor layer 240 in the system to be cooled to below approximately 400°C in a short time, at which temperature bulk diffusion and grain boundary diffusion of silicon atoms essentially cease.

[0079] In this way, the high-density grain boundary grid formed in the second heating stage can be effectively stabilized, and the resulting polycrystalline silicon layer 260 can maintain a fine and uniform grain size, thereby allowing the trap capacity for capturing free carriers to be preserved to the maximum extent.

[0080] This disclosure also considers how to suppress abnormal grain growth in subsequent processes and how to improve the electrical properties of the polysilicon layer 260.

[0081] In this regard, it is conceivable that during the formation of the silicon precursor layer 240 on the substrate 220, an in-situ doping method can be used to introduce a concentration of 1×10⁻⁶ into the silicon precursor layer 240. 19 ~5×10 19 Dopant at atoms / cm³.

[0082] In related technologies, impurities are typically introduced into polycrystalline silicon via ion implantation. However, ion implantation introduces lattice damage and unwanted recombination centers, and it is difficult to achieve uniform depth distribution in films with micrometer-thickness.

[0083] To address this, in the formation of the silicon precursor layer 240, this disclosure introduces an in-situ doping process. The dopant element in the dopant may include, but is not limited to, at least one of boron and phosphorus. Specifically, while silane (SiH4) is introduced as the silicon source into the reaction chamber of low-pressure chemical vapor deposition, a dopant source gas can be simultaneously introduced in a specific ratio. For example, when P-type doping is required, diborane (B2H6) can be introduced; when N-type doping is required, phosphine (PH3) can be introduced.

[0084] Understandably, referring to the conventional doping levels of ordinary N-type and P-type silicon wafers, the dopant concentration introduced in this disclosure can be 1×10⁻⁶. 19 ~5×10 19 atoms / cm³. The inventors of this disclosure have experimentally determined that, after introducing this dopant, the polycrystalline silicon layer 260 formed using the stepped heat treatment method of this disclosure still maintains a good grain size. In other words, the polycrystalline silicon layer preparation method of this disclosure is also applicable to doped amorphous silicon thin films, thus possessing good process compatibility and scalability.

[0085] By controlling the flow ratio of dopant gas to silane, dopant atoms can be uniformly incorporated into the network structure of amorphous silicon during the deposition of the amorphous silicon precursor layer 240, achieving in-situ doping. Furthermore, using this homogeneous doped film formed through in-situ doping as a precursor for subsequent crystallization can meet the diverse design requirements of different RF devices for substrate electrical properties without disrupting the high-density grain boundary network.

[0086] According to another aspect of this disclosure, referring to Figure 6 A substrate structure 200 is also provided.

[0087] The substrate structure 200 includes a substrate 220 and a polysilicon layer 260 disposed on the surface of the substrate 220.

[0088] The average grain size D of the polysilicon layer 260 is 50~150nm, and the grain size variation coefficient of the polysilicon layer 260 is less than or equal to 20%.

[0089] It should be noted that the above-mentioned average grain size D is a fine grain size range stably obtained by the preparation method of this disclosure within a temperature window of 680°C to 720°C. Compared with the coarse-grained polycrystalline silicon with an average size greater than 400 nm in the related technologies described above, the grain size of this disclosure is reduced by more than approximately 78.75%.

[0090] This tiny grain size means that, within the same volume, the polycrystalline silicon layer 260 can provide a denser grain boundary network. These dense grain boundaries contain a large number of dangling bonds and lattice defects, forming high-capacity charge traps that can more efficiently capture free carriers migrating disorderedly at the substrate interface, thereby blocking high-frequency parasitic surface conduction paths for radio frequency signals.

[0091] Understandably, the average grain size D, a microstructural parameter, reflects the density of grain boundaries in the polycrystalline silicon layer 260, while the uniformity of grain size reflects the stability of grain boundaries in the polycrystalline silicon layer 260. Furthermore, the uniformity of grain size can be reflected by the coefficient of variation of grain size.

[0092] Here, the grain size variation coefficient can be defined as: (grain size standard deviation σ) / (grain size average value D1) × 100%. Wherein, the grain size average value D1 represents the average value of the grain size measured at multiple different locations along the thickness direction of the polycrystalline silicon thin film; the grain size standard deviation σ represents the corresponding grain size standard deviation measured at the aforementioned multiple different locations.

[0093] For example, the above-mentioned grain size variation parameters can be tested using the following method: First, the surface of the polycrystalline silicon thin film was imaged using a scanning electron microscope (SEM) or a transmission electron microscope (TEM). Then, it was compared with a reference... Figure 6 At least three locations at different depths (e.g., S1 near the bottom interface of the thin film, S2 in the middle, and S3 near the surface) are selected at equal intervals along the thickness direction of the polycrystalline silicon layer 260. The dimensions of at least 100 grains are randomly counted at each location, and the average grain size at that location is calculated. Then, the average grain size (i.e., the overall average size, denoted as the average grain size D1) and the standard deviation of the grain size σ are calculated together to obtain the grain size variation coefficient.

[0094] As shown in Tables 3 and 4 below, this disclosure, through the above-described testing methods and by designing Comparative Example 5 and Example 7, provides comparative data on the average grain size and grain size variation coefficient of each region of the polycrystalline silicon layer 260 under different heating strategies. It should be noted that the crystallization temperature in Table 3 has the same meaning as the target temperature in the second heating stage of this disclosure, and the crystallization time has the same meaning as the second preset duration T2 in this disclosure.

[0095] Table 3

[0096] Table 4

[0097] Please refer to Tables 3 and 4: Comparative Example 5 shows a sample prepared using a rapid heating method that directly raises the temperature from room temperature to the target temperature using related techniques. Specifically, due to significant heating time differences and temperature gradients between the inner and outer surfaces and between the center and edges of the silicon wafer, some areas reach the crystallization temperature first and begin coarsening growth, while other areas are just beginning nucleation. This method results in temperature differences between the interior and surface of the amorphous silicon film, typically with the surface temperature being higher than the interior temperature. Consequently, the grain size varies significantly along the longitudinal depth direction within the polycrystalline silicon layer, with the grain size variation coefficient often exceeding 30%, such as the 33.3% shown in Table 4.

[0098] Accordingly, Example 7 is a sample prepared using the stepped heating method of this disclosure. Because this disclosure introduces a first heating stage during rapid thermal processing, the micrometer-thick silicon precursor layer 240 reaches thermal equilibrium before crystallization. Subsequently, it is heated to the target temperature at a higher rate, allowing all regions within the film plane and along its thickness to simultaneously cross the nucleation energy barrier, achieving simultaneous nucleation and confined growth. Therefore, it can be clearly seen from Table 4 that its grain size variation coefficient is only 5.3%.

[0099] As can be seen from the differences in data between Comparative Example 5 and Example 7, the grain size variation coefficient is another microstructural parameter characterizing the uniqueness of the stepped heat treatment process disclosed herein. Through the polycrystalline silicon layer preparation method of this disclosure, the final polycrystalline silicon layer 260 not only has fine grains, but also the size of each grain is more similar in different regions of the polycrystalline silicon layer, and the grain size variation coefficient can be controlled within 20%.

[0100] It is conceivable that the aforementioned coefficient of variation could be less than or equal to 10%.

[0101] By optimizing the grain size variation coefficient of the polysilicon layer 260 to less than or equal to 10%, a more uniform grain boundary network can be obtained. This improves the consistency of RF crosstalk immunity across all regions of the RF front-end chip, thereby enhancing the yield and device performance consistency in the manufacture of large wafers (e.g., a 12-inch wafer with a diameter of 300 mm).

[0102] In the aforementioned substrate structure 200, the thickness of the polysilicon layer 260 can be 1.5~2.0 μm, and the grain boundary density of the polysilicon layer is 0.29 × 10⁻⁶. 4 ~1.18×10 4 μm -1 .

[0103] Understandably, the thickness design of the polysilicon layer 260 needs to balance charge trapping capability with manufacturing cost and stress control. If the thickness is too thin, for example less than 1.5 μm, the total number of grain boundary traps it can provide may not be sufficient to completely exhaust the parasitic carriers generated at the substrate interface, especially under high-frequency (e.g., millimeter-wave) high-power operating conditions, which can easily lead to trap saturation.

[0104] If the thickness is too thick, for example, greater than 2.0 μm, it will significantly increase the process time and manufacturing cost of low-pressure chemical vapor deposition. On the other hand, excessively thick films are prone to generating large internal stresses during heat treatment and subsequent processing, which may lead to wafer warping or even film peeling.

[0105] It is also understood that grain boundary density is used to characterize the density of the grain boundary network between grains within the polysilicon layer 260, reflecting the number of grain boundary traps in the polysilicon layer 260 that can be used to capture free charge carriers. For example, grain boundary density can be obtained through statistical analysis of the grain size of the polysilicon layer 260. Specifically, images of the grain morphology of the polysilicon layer 260 can be obtained using equipment such as scanning electron microscopes and transmission electron microscopes, and the estimated value of grain boundary density can be calculated based on the grain size and grain distribution in the images.

[0106] Since grain boundary density corresponds to grain size, when the average grain size in the polycrystalline silicon layer 260 decreases, more grain boundaries can be formed within the same volume, thereby increasing the grain boundary density. Therefore, by controlling the crystallization temperature and the second preset time T2 during the rapid thermal processing, the degree of grain growth can be adjusted, resulting in a polycrystalline silicon layer 260 with a high grain boundary density.

[0107] Specifically, referring to Table 1 above, when the target temperature is within the range of 680℃ to 720℃, the polycrystalline silicon layer 260 can form a relatively fine grain structure. In Example 1, the estimated grain boundary density is approximately 1.18 × 10⁻⁶. 4 μm -1 In Example 2, the estimated grain boundary density is approximately 1.05 × 10⁻⁶. 4 μm -1 In Example 3, the estimated grain boundary density is approximately 0.77 × 10⁻⁶. 4 μm -1 In Comparative Example 2 at 850℃, due to significant grain coarsening, the estimated grain boundary density decreased to approximately 0.29 × 10⁻⁶. 4 μm -1 .

[0108] Therefore, by employing a polysilicon layer 260 with a thickness of 1.5~2.0 μm, it is possible to improve the suppression of radio frequency losses while maintaining the mechanical stability of the wafer. Furthermore, this disclosure controls the grain boundary density of the formed polysilicon layer 260 to 0.29 × 10⁻⁶ by increasing the grain boundary density. 4 ~1.18×10 4 μm -1 Within this range, the number of trap centers at the grain boundaries can be increased, thereby improving the ability of the polysilicon layer 260 to capture free carriers and improving the isolation performance of the RF front-end chip.

[0109] In the aforementioned substrate structure 200, the polysilicon layer 260 may include a concentration of 1×10 19 ~5×10 19 The doping element is atoms / cm³, and the doping element may include at least one of boron and phosphorus.

[0110] As previously mentioned, this disclosure addresses the shortcomings of existing polycrystalline silicon ion implantation doping processes, such as the tendency to introduce lattice damage and recombination centers, and the difficulty in achieving uniform doping in micron-scale thick films. It proposes an in-situ doping process to prepare doped polycrystalline silicon layers. Specifically, during the preparation of the amorphous silicon precursor layer 240 by low-pressure chemical vapor deposition, silane is introduced as the silicon source, and simultaneously, a corresponding dopant source gas is introduced at a predetermined ratio. By adjusting the gas flow rate ratio, boron or phosphorus dopants are uniformly integrated into the amorphous silicon network, and the doping concentration is controlled to be 1 × 10⁻⁶. 19 ~5×10 19 atoms / cm³. In this way, the resulting polycrystalline silicon layer 260 also includes the aforementioned doping elements.

[0111] Experiments conducted by the inventors of this disclosure have shown that this doping concentration, combined with stepped heat treatment, can stabilize the grain size of polycrystalline silicon without damaging the high-density grain boundary network. This avoids the doping uniformity and lattice damage problems inherent in traditional processes, and can meet the diverse electrical properties of substrates required by different RF devices.

[0112] The substrate structure 200 described above can satisfy at least one of the following: an effective resistivity of not less than 8.7 kΩ·cm at 28 GHz; an effective resistivity of not less than 10.5 kΩ·cm at 10 GHz; and an effective resistivity of not less than 5.0 kΩ·cm at 77 GHz.

[0113] It is understood that, based on the aforementioned fine and uniform grain structure and high-density grain boundary network, the substrate structure 200 provided in this disclosure possesses excellent electrical isolation performance. As shown in Table 5 below, this disclosure provides a comparison of effective resistivity test data at different radio frequency frequencies. It should be noted that the crystallization process temperature in Table 5 has the same meaning as the target temperature in the second heating stage of this disclosure.

[0114] Table 5

[0115] Please refer to Table 5: Comparative Example 6 shows a coarse-grained sample prepared using a high-temperature deposition process with related technologies. Table 5 clearly shows that its effective resistivity is 7.3 kΩ·cm at 10 GHz, decays to 5.6 kΩ·cm at 28 GHz, and further decreases to 3.2 kΩ·cm at 77 GHz. This rapid decrease in effective resistivity under high-frequency conditions indicates insufficient trap capacity in coarse-grained polycrystalline silicon. Under the excitation of a millimeter-wave high-frequency electric field, parasitic carriers easily overcome the potential barrier and conduct, leading to isolation performance failure.

[0116] Accordingly, Example 8 is a fine-grained, high-grain-density sample prepared using the method disclosed herein. As can be clearly seen from the table, its effective resistivity is 10.5 kΩ·cm at 10 GHz, remains at 8.7 kΩ·cm at 28 GHz, and maintains an effective resistivity of not less than 5.0 kΩ·cm even at a high frequency of 77 GHz.

[0117] It is understandable that as the operating frequency increases, the parasitic capacitive coupling effect at the grain boundaries will be enhanced, leading to a decrease in the macroscopic effective resistivity.

[0118] This disclosure improves grain boundary density and constructs a dense grain boundary network by reducing grain size, thereby increasing the resistance to disordered carrier migration at high frequencies. This results in an effective resistivity superior to related technologies across various millimeter-wave bands, effectively reducing high-frequency RF losses in semiconductor devices.

[0119] According to another aspect of this disclosure, a radio frequency (RF) front-end chip is also provided. The RF front-end chip includes the substrate structure 200 as described in the foregoing aspects.

[0120] It is conceivable that in application scenarios such as 5G / 6G millimeter-wave communication, IoT smart devices, and smart cars (such as 77 GHz autonomous driving millimeter-wave radar), the operating frequency of RF front-end chips (such as RF switches, low-noise amplifiers (LNAs), power amplifiers (PAs), etc.) will continue to rise, thus placing more stringent requirements on the isolation of the substrate.

[0121] Applying the high grain boundary density and high effective resistivity substrate structure 200 provided in this disclosure to the manufacture of radio frequency front-end chips, such as those using radio frequency silicon-on-insulator (RF-SOI) processes, allows the dense trap network at the bottom of the polysilicon layer 260 to firmly pin parasitic free carriers at the silicon substrate interface.

[0122] This approach eliminates RF energy loss caused by parasitic surface conduction (PSC) while reducing signal crosstalk and nonlinear harmonic distortion between different RF components within the chip. Consequently, it improves the insertion loss performance, signal integrity, and linearity of RF front-end chips at high or ultra-high frequency bands, providing an excellent hardware foundation for the development of high-performance wireless communication and sensing devices.

[0123] In this disclosure, the terms "first," "second," etc., are used merely for descriptive purposes and should not be considered restrictive. Furthermore, although this disclosure has been described with reference to exemplary embodiments, it should be understood that this disclosure is not limited to the specific embodiments described and shown herein. Various changes to the exemplary embodiments can be made by those skilled in the art without departing from the scope defined by the claims of this disclosure.

[0124] The features mentioned and / or shown in the foregoing description of exemplary embodiments of this disclosure may be combined in the same or similar manner with one or more other embodiments, combined with features in other embodiments, or substituted for corresponding features in other embodiments. Such combinations or substitutions should also be considered as including within the scope of protection of this disclosure.

Claims

1. A method for preparing a polycrystalline silicon layer, characterized in that, include: Provide substrate; An amorphous silicon precursor layer is formed on the surface of the substrate; as well as The silicon precursor layer is subjected to rapid thermal processing, the rapid thermal processing including: The silicon precursor layer is heated to an intermediate temperature below the crystallization temperature of the silicon precursor layer at a first heating rate and held for a first preset time so that the silicon precursor layer reaches thermal equilibrium while remaining in an amorphous state. The silicon precursor layer is then heated to the target temperature at a second heating rate and held for a second preset duration to allow the silicon precursor layer to crystallize and form a polycrystalline silicon layer, wherein the second heating rate is greater than the first heating rate.

2. The method for preparing a polycrystalline silicon layer according to claim 1, characterized in that, The intermediate temperature is 300~500℃, and the first preset duration is 5~20 seconds.

3. The method for preparing a polycrystalline silicon layer according to claim 1 or 2, characterized in that, The first heating rate is 30~100℃ / second, and the second heating rate is 100~150℃ / second.

4. The method for preparing a polycrystalline silicon layer according to claim 1 or 2, characterized in that, The target temperature is in the range of 680~720℃.

5. The method for preparing a polycrystalline silicon layer according to claim 1 or 2, characterized in that, The second preset duration is 3 to 10 seconds.

6. The method for preparing a polycrystalline silicon layer according to claim 1, characterized in that, The silicon precursor layer is formed by a low-pressure chemical vapor deposition process, in which the reaction chamber temperature is 550~570℃ and the reaction chamber pressure is 400~600mTorr.

7. The method for preparing a polycrystalline silicon layer according to claim 1, characterized in that, The thickness of the silicon precursor layer is 1.5~2μm.

8. The method for preparing a polycrystalline silicon layer according to claim 1, characterized in that, The rapid heat treatment also includes a cooling stage: after maintaining the second preset duration, the silicon precursor layer is cooled to below 400°C at a cooling rate greater than or equal to 50°C / second.

9. The method for preparing a polycrystalline silicon layer according to claim 1, characterized in that, During the formation of the silicon precursor layer on the substrate, an in-situ doping process is used to introduce a concentration of 1×10⁻⁶ into the silicon precursor layer. 19 ~5×10 19 Dopant at atoms / cm³.

10. A substrate structure, characterized in that, include: Substrate; as well as A polycrystalline silicon layer disposed on the surface of the substrate The average grain size of the polycrystalline silicon layer is 50~150nm, and the grain size variation coefficient of the polycrystalline silicon layer is less than or equal to 20%.

11. The substrate structure according to claim 10, characterized in that, The coefficient of variation is less than or equal to 10%.

12. The substrate structure according to claim 10, characterized in that, The polycrystalline silicon layer has a thickness of 1.5~2.0 μm and a grain boundary density of 0.29 × 10⁻⁶. 4 ~1.18×10 4 μm -1 .

13. The substrate structure according to claim 10, characterized in that, The polycrystalline silicon layer contains a concentration of 1×10 19 ~5×10 19 A doping element with atoms / cm³, wherein the doping element includes at least one of boron and phosphorus.

14. The substrate structure according to claim 10, characterized in that, The substrate structure satisfies at least one of the following: an effective resistivity of not less than 8.7 kΩ·cm at 28 GHz; an effective resistivity of not less than 10.5 kΩ·cm at 10 GHz; and an effective resistivity of not less than 5.0 kΩ·cm at 77 GHz.

15. A radio frequency front-end chip, characterized in that, Includes the substrate structure according to any one of claims 10 to 14.

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