Method for manufacturing semiconductor device, semiconductor device, mask structure

Abstract

The application discloses a semiconductor device manufacturing method, a semiconductor device and a mask structure. The semiconductor device manufacturing method comprises the following steps: providing a semiconductor body; the semiconductor body has a first surface; forming a groove on the first surface of the semiconductor body; the groove is located at least one side of a preset implantation area in the semiconductor body; forming a first mask layer on the first surface of the semiconductor body and in the groove, and performing a patterning process on the first mask layer to form an implantation window which exposes the first surface of the semiconductor body; performing ion implantation on the semiconductor body through the implantation window to form a doped area in the preset implantation area of the semiconductor body; and the first mask layer filled in the groove forms a barrier layer for inhibiting lateral scattering in the ion implantation process. The technical scheme provided by the application effectively inhibits the lateral scattering of the dopant in the ion implantation process, avoids the widening of the doped area, and guarantees the working characteristics of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a method for fabricating a semiconductor device, a semiconductor device, and a mask structure. Background Technology

[0002] Silicon carbide (SiC) MOSFET devices have advantages such as fast switching speed and low on-resistance, and can achieve high breakdown voltage levels with a small drift layer thickness, making them particularly advantageous in medium and high voltage applications such as photovoltaic inverters, electric vehicles, high voltage direct current transmission, and solid-state transformers.

[0003] In the manufacturing process of SiC MOSFETs, P-type and N-type regions are typically formed by ion implantation of dopants such as aluminum (Al) and nitrogen (N). In the ion implantation process, only a hard mask (HM) is typically used as an ion implantation barrier layer, and the ion implantation area is defined by the implantation window formed in the hard mask.

[0004] However, during ion implantation, implanted ions undergo scattering, causing the dopant to extend laterally beyond the implantation window boundary defined by the hard mask. This phenomenon is called lateral straggle. The degree of lateral straggle is directly proportional to the ion implantation energy; the higher the implantation energy, the more severe the lateral straggle. (Reference) Figure 1 When ion implantation requires high energy and high dose, the lateral scattering effect is particularly significant, causing the actual doped region 02 below the hard mask 01 edge to be wider than the mask window. Lateral scattering has a severe impact on the device performance of SiC MOSFETs. For example, in N... + In injection (such as source region injection), lateral scattering can lead to N + Lateral expansion of the doped region towards the channel shortens the effective channel length, directly affecting the device's threshold voltage characteristics and short-channel effect, and in severe cases, may prevent the device from turning off. In field-limiting loop implantation, lateral scattering widens the actual doped region of the field-limiting loop, causing the terminal electric field distribution to deviate from the design value, reducing the device's breakdown voltage and reliability.

[0005] Therefore, how to effectively suppress the lateral scattering of dopants in the ion implantation process and avoid the widening of the doped region, thereby ensuring the operating characteristics of the device, has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] This application provides a method for fabricating a semiconductor device, a semiconductor device, and a mask structure to effectively suppress lateral scattering of dopants during ion implantation, avoid doped region broadening, and ensure the operating characteristics of the device.

[0007] According to one aspect of this application, a method for fabricating a semiconductor device is provided, comprising: A semiconductor body is provided; the semiconductor body has a first surface; A groove is formed on a first surface of the semiconductor body; the groove is located on at least one side of a predetermined injection region in the semiconductor body. A first mask layer is formed on the first surface of the semiconductor body and in the groove, and the first mask layer is patterned to form an injection window that exposes the first surface of the semiconductor body. Ions are implanted into the semiconductor body through the implantation window to form a doped region in a predetermined implantation area of ​​the semiconductor body; wherein, the first mask layer filling the groove constitutes a barrier layer to suppress lateral scattering during the ion implantation process.

[0008] Optionally, forming a groove on the first surface of the semiconductor body includes: A first photoresist layer is formed on the first surface of the semiconductor body; The first photoresist layer is patterned to form a first opening that exposes the first surface of the semiconductor body; Using the patterned first photoresist layer as a mask, the semiconductor body is etched to form the groove at the position corresponding to the first opening; Remove the first photoresist layer.

[0009] Optionally, forming a groove on the first surface of the semiconductor body includes: The semiconductor bodies on opposite sides of the preset injection region are etched to form the grooves on opposite sides of the preset injection region; wherein the depth of the grooves is greater than or equal to the depth of the preset injection region.

[0010] Optionally, forming the first mask layer on the first surface of the semiconductor body and in the groove includes: A mask material is deposited on the first surface of the semiconductor body and in the groove to form the first mask layer. The mask material includes at least one of silicon oxide, silicon nitride, and metal. The surface of the first mask layer away from the semiconductor body has a recess in the region corresponding to the groove.

[0011] Optionally, the step of patterning the first mask layer to form an injection window exposing the surface of the semiconductor body includes: A second photoresist layer is formed on the surface of the first mask layer away from the semiconductor body; The second photoresist layer is patterned to form a second opening on the surface of the first mask layer corresponding to the groove region; Using the patterned second photoresist layer as a mask, the first mask layer is etched to form the injection window at the position corresponding to the second opening; Remove the second photoresist layer.

[0012] Optionally, after ion implantation into the semiconductor body through the implantation window to form a doped region in the predetermined implantation region of the semiconductor body, the method further includes: A second mask layer is formed on the surface of the first mask layer away from the semiconductor body and on the surface of the doped region exposed by the first mask layer; Remove the first mask layer located in the groove and the second mask layer located above the groove to expose the groove; A semiconductor filling layer is formed in the groove; Remove the remaining second mask layer and the first mask layer.

[0013] Optionally, removing the first mask layer located in the groove and the second mask layer located above the groove to expose the groove includes: A third photoresist layer is formed on the surface of the second mask layer away from the semiconductor body; The third photoresist layer is patterned to form a third opening on the surface of the second mask layer corresponding to the groove region; Using the patterned third photoresist layer as a mask, the second mask layer and the first mask layer are etched to expose the groove; Remove the third photoresist layer.

[0014] Optionally, after removing the remaining second mask layer and the first mask layer, the method further includes: The doped region is then annealed. Alternatively, before forming the semiconductor filling layer in the groove, the method further includes: The doped region is then annealed.

[0015] According to another aspect of this application, a semiconductor device is provided, which is prepared by the semiconductor device preparation method described in any embodiment of this application, wherein the semiconductor device includes a semiconductor body; The semiconductor body has a first surface, and the semiconductor body further includes a doped region located on the first surface of the semiconductor body.

[0016] Optionally, the semiconductor body includes multiple doped regions, at least one of which is an ohmic contact region, and / or at least one of which is a field-limiting ring.

[0017] According to another aspect of this application, a mask structure is provided, comprising: A mask layer body has opposing first side surfaces and second side surfaces, wherein at least one injection window is formed in the mask layer body penetrating the first side surface and the second side surface; wherein the second side surface faces the semiconductor body to be injected; The second side surface of the mask layer body is provided with a blocking portion on at least one side of the injection window. The blocking portion protrudes from the second side surface of the mask layer body in a direction away from the first side surface. The blocking portion is used to suppress lateral scattering of ions during ion implantation so that the actual implantation area is consistent with the pattern of the injection window.

[0018] Optionally, the blocking portion is located on opposite sides of the injection window.

[0019] Optionally, a recess is formed on the first side surface of the mask layer body in the region corresponding to the blocking portion.

[0020] Optionally, the material of the mask layer body includes at least one of silicon oxide, silicon nitride, and metal.

[0021] The technical solution provided in this application involves forming a groove on the first surface of a semiconductor body, with the groove located on at least one side of a predetermined implantation region. A first mask layer is then formed on the first surface of the semiconductor body and within the groove, creating a barrier layer within the groove. This barrier layer physically blocks the implanted ions from the side of the implantation window during ion implantation, effectively suppressing lateral scattering of the dopant beyond the implantation window boundary and improving the consistency between the actual doped region and the implantation window pattern. Therefore, this application effectively solves the technical challenge of severe lateral scattering in high-energy, high-dose ion implantation through mask layer structure improvement without significantly increasing process complexity, significantly improving the electrical performance and reliability of the semiconductor device and ensuring its operating characteristics.

[0022] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of the doped region formed after ion implantation based on a mask layer during the fabrication process of a semiconductor device provided in the prior art; Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application; Figure 3 This is a cross-sectional structural diagram corresponding to step S120 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 4 This is a cross-sectional structural diagram corresponding to step S130 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 5 This is a cross-sectional structural diagram corresponding to step S140 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 6 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of this application; Figure 7 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of this application; Figure 8 This is a cross-sectional structural diagram corresponding to step S320 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 9 This is a schematic cross-sectional view of step S330 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 10 This is a cross-sectional structural diagram corresponding to step S340 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 11 This is a schematic cross-sectional view of step S360 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 12 This is a schematic cross-sectional view of step S370 in a method for fabricating a semiconductor device according to an embodiment of this application. Figure 13 This is a schematic cross-sectional view of step S380 in a method for fabricating a semiconductor device according to an embodiment of this application. Figure 14This is a schematic cross-sectional view of step S390 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 15 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of this application; Figure 16 This is a cross-sectional structural diagram corresponding to step S450 in a method for fabricating a semiconductor device provided in this application embodiment; Figures 17-19 This is a cross-sectional view of the structure of each specific step in step S460 of a semiconductor device fabrication method provided in this application embodiment; Figure 20 This is a schematic cross-sectional view of step S470 in a method for fabricating a semiconductor device according to an embodiment of this application. Figure 21 This is a schematic cross-sectional view of step S480 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 22 This is a schematic diagram of a mask structure provided in an embodiment of this application. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] This application provides a method for fabricating a semiconductor device. Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application, see reference. Figure 2 and combined Figures 3-5 The methods for fabricating semiconductor devices include: S110, Provide a semiconductor body; the semiconductor body has a first surface.

[0028] Specifically, the semiconductor body 1 has a first surface S1 and a second surface S2. The material of the semiconductor body 1 can be a semiconductor material such as silicon carbide (SiC), silicon (Si), or gallium nitride (GaN). The semiconductor body 1 can be formed by a single epitaxial layer or by multiple epitaxial layers. That is, the semiconductor body 1 can be a single semiconductor epitaxial layer 20 or a stacked structure formed by multiple semiconductor epitaxial layers 20. The semiconductor body 1 may also include a substrate 10, that is, the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer 20 formed on one side of the substrate 10. When the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer 20, the second surface S2 is the surface of the substrate 10 away from the semiconductor epitaxial layer 20, and the first surface S1 is the surface of the semiconductor epitaxial layer 20 furthest from the substrate 10 away from the substrate 10. Figure 1 An exemplary embodiment shows that the semiconductor body 1 includes a substrate 10 and a semiconductor epitaxial layer 20 located on the surface of the substrate 10.

[0029] In this embodiment, the semiconductor body 1 is preferably made of silicon carbide and has a first surface S1, which is the implantation surface for subsequent ion implantation. The semiconductor body 1 includes a preset implantation region A, which is the region where the doped region 201 needs to be formed subsequently. In some embodiments, the preset implantation region A can be the source region, drain region, well region, or termination protection ring region (such as a field limiting ring) of a MOSFET device.

[0030] S120, A groove is formed on the first surface of the semiconductor body; the groove is located on at least one side of a predetermined injection region in the semiconductor body.

[0031] For details, please refer to Figure 3 A groove 21 is formed on the first surface S1 of the semiconductor body 1. The groove 21 is located on at least one side of the predetermined injection region A in the semiconductor body 1. That is, the groove 21 is located at the edge of the predetermined injection region A, and can be located on one side of the predetermined injection region A or on opposite sides of the predetermined injection region A. The groove 21 is used to provide a receiving space for the subsequently formed barrier layer 411. Figure 3 An exemplary illustration shows that grooves 21 are disposed on opposite sides of a preset injection area A.

[0032] The formation of the groove 21 includes, but is not limited to, photolithography and etching processes. In some embodiments, a photoresist layer can be first formed on the first surface S1 of the semiconductor body 1. Then, the photoresist layer can be patterned using photolithography processes such as exposure and development to form an opening exposing the first surface S1. The patterned photoresist layer can then be used as a mask to etch the semiconductor body 1 to form the groove 21. Finally, the remaining photoresist layer is removed. The etching process can employ anisotropic dry etching, such as reactive ion etching or inductively coupled plasma etching, to obtain a groove 21 with steep sidewalls. The depth and width of the groove 21 can be set according to actual process requirements; this embodiment does not specifically limit this.

[0033] S130. A first mask layer is formed on the first surface of the semiconductor body and in the groove, and the first mask layer is patterned to form an injection window that exposes the first surface of the semiconductor body.

[0034] For details, please refer to Figure 4 A mask material can be deposited from the side of the first surface S1 of the semiconductor body 1 using a deposition process to form a first mask layer 41. Due to the presence of the groove 21, the first mask layer 41 forms a protrusion in the region where the groove 21 is located, thereby forming a barrier layer 411. The first mask layer 41 covers the first surface S1 of the semiconductor body 1 and fills the groove 21. The first mask layer 41 filled in the groove 21 is a laterally scattering barrier layer 411. That is, the surface of the first mask layer 41 near the semiconductor body 1 to be implanted has a barrier portion, which protrudes and extends from the surface of the first mask layer 41 near the semiconductor body 1 to be implanted toward the semiconductor body 1 to be implanted and inserts into the semiconductor body 1. The material of the first mask layer 41 is a hard mask material, including but not limited to at least one of silicon oxide, silicon nitride, or metal. The thickness of the first mask layer 41 can be selected according to the energy and dose of ion implantation to ensure effective blocking of ion penetration during subsequent ion implantation processes.

[0035] Next, the first mask layer 41 is patterned to form an injection window C1. The injection window C1 penetrates the first mask layer 41, exposing the first surface S1 of the semiconductor body 1, and the injection window C1 corresponds to the position of the preset injection region A in the vertical direction. That is, the preset injection region A is located directly below the injection window C1. The formation of the injection window C1 includes, but is not limited to, photolithography and etching processes. In some embodiments, a photoresist layer can be formed on the surface of the first mask layer 41, and the photoresist layer can be patterned by photolithography to form an opening exposing the surface of the first mask layer 411. Then, the patterned photoresist layer is used as a mask to etch the first mask layer 41 to form the injection window C1, and finally the remaining photoresist layer is removed. The etching process can employ anisotropic dry etching to ensure that the sidewalls of the injection window C1 are steep.

[0036] S140. Ions are implanted into the semiconductor body through the implantation window to form a doped region in the preset implantation area of ​​the semiconductor body; wherein, the first mask layer filled in the groove constitutes a barrier layer to suppress lateral scattering during the ion implantation process.

[0037] For details, please refer to Figure 5 Ions are implanted into the semiconductor body 1 through the implantation window C1, forming a doped region 201 in the preset implantation region A of the semiconductor body 1. Depending on the type of the preset implantation region A, the implanted ions can be donor-type dopants (such as nitrogen or phosphorus ions) or acceptor-type dopants (such as aluminum or boron ions). The energy and dose of ion implantation are selected according to the device design requirements. For example, in SiC MOSFETs, high-energy and high-dose nitrogen ion implantation can be used for N+ source region implantation; high-energy and high-dose aluminum ion implantation can be used for P+ type field-limiting ring implantation. During ion implantation, the implanted ions are scattered upon entering the semiconductor body 1, resulting in a lateral scattering effect. Lateral scattering causes some ions to move laterally beyond the boundary of the implantation window C1. If this is not suppressed, the actual doped region 201 will be wider than the pattern of the implantation window C1, causing the doped region 201 to widen. In this embodiment, the first mask layer 41 filled in the groove 21 constitutes a barrier layer 411. The barrier layer 411 is located laterally to the implantation window C1, forming a physical barrier to the implanted ions. When implanted ions are laterally scattered towards the implantation window C1, the ions are blocked by the blocking layer 411 and cannot continue to expand laterally, which helps to keep the pattern of the actual doped region 201 consistent with that of the implantation window C1.

[0038] The technical solution provided in this application involves forming a groove 21 on the first surface S1 of the semiconductor body 1, with the groove 21 located on at least one side of a preset implantation region A. A first mask layer 41 is then formed on the first surface S1 of the semiconductor body 1 and in the groove 21, such that the first mask layer 41 filling the groove 21 constitutes a barrier layer 411. This barrier layer 411 physically blocks the implanted ions from the side of the implantation window C1 during ion implantation, effectively suppressing lateral scattering of the dopant outside the boundary of the implantation window C1, and improving the consistency between the actual doped region 201 and the pattern of the implantation window C1. Therefore, this application effectively solves the technical problem of severe lateral scattering in high-energy, high-dose ion implantation by improving the mask layer structure without significantly increasing process complexity, significantly improving the electrical performance and reliability of the semiconductor device, and ensuring the device's operating characteristics.

[0039] Figure 6 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of this application, see reference. Figure 6 The methods for fabricating semiconductor devices include: S210, Provide a semiconductor body; the semiconductor body has a first surface.

[0040] S220, Etch the semiconductor bodies on both sides of the preset injection region to form grooves on both sides of the preset injection region; wherein the depth of the grooves is greater than or equal to the depth of the preset injection region.

[0041] S230. A first mask layer is formed on the first surface of the semiconductor body and in the groove, and the first mask layer is patterned to form an injection window that exposes the first surface of the semiconductor body.

[0042] S240. Ions are implanted into the semiconductor body through the implantation window to form a doped region in the preset implantation area of ​​the semiconductor body; wherein, the first mask layer filled in the groove constitutes a barrier layer to suppress lateral scattering during the ion implantation process, so that the actual doped region is consistent with the pattern of the implantation window.

[0043] In this embodiment of the application, reference is made to Figure 3 The step of forming a groove 21 on the first surface S1 of the semiconductor body 1 includes etching the semiconductor body 1 on opposite sides of the preset implantation region A to form grooves 21 on opposite sides of the preset implantation region A; wherein the depth of the groove 21 is greater than or equal to the depth of the preset implantation region A. Thus, the first mask layer 41 filling the groove 21 forms a barrier layer 411 of sufficient depth on both sides of the implantation window C1, extending from the first surface S1 of the semiconductor body 1 to below the bottom of the preset implantation region A. When implanted ions undergo lateral scattering, the barrier layer 411 forms a complete physical barrier for the ions on both sides of the implantation window C1 and throughout the entire depth of the doped region 201, effectively preventing the dopant from spreading laterally across the barrier layer 411 into the channel region or terminal region. This confines the dopant within the area defined by the implantation window C1, ensuring that the edge of the actual doped region 201 remains consistent with the pattern of the implantation window C1 and does not widen to either side of the implantation window C1, thereby avoiding device performance degradation caused by the widening of the doped region 201.

[0044] Figure 7 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of this application, see reference. Figure 7 The methods for fabricating semiconductor devices include: S310, provides a semiconductor body; the semiconductor body has a first surface.

[0045] S320, A first photoresist layer is formed on the first surface of the semiconductor body.

[0046] For details, please refer to Figure 8Photoresist can be coated onto the first surface S1 of the semiconductor body 1 using a spin coating process, followed by pre-baking curing to form a first photoresist layer 31. The thickness of the first photoresist layer 31 can be selected according to the requirements of subsequent etching processes; this embodiment does not impose specific limitations on this.

[0047] S330. The first photoresist layer is patterned to form a first opening that exposes the first surface of the semiconductor body.

[0048] For details, please refer to Figure 9 Using photolithography, the first photoresist layer 31 is exposed and developed through a photomask to remove the photoresist at least one corresponding position of the preset injection region A, forming a first opening K1. The width of the first opening K1 corresponds to the target width of the subsequently formed groove 21. In some embodiments, the first opening K1 is located on opposite sides of the preset injection region A, that is, the first opening K1 is formed on both sides of the preset injection region A.

[0049] S340. Using the patterned first photoresist layer as a mask, the semiconductor body is etched to form a groove at the position corresponding to the first opening.

[0050] For details, please refer to Figure 10 Using the patterned first photoresist layer 31 as a mask, the semiconductor body 1 is etched to form a groove 21 at the position corresponding to the first opening K1. The etching process can employ anisotropic dry etching, such as reactive ion etching or inductively coupled plasma etching, to obtain a groove 21 with steep sidewalls. Taking silicon carbide as an example, the etching gas can be an SF6 / O2 or CF4 / O2 gas system. The depth of the groove 21 is greater than or equal to the depth of the preset implantation region A to ensure that the subsequently formed barrier layer 411 can cover the entire depth range of the doped region 201. The angle between the sidewall of the groove 21 and the first surface S1 of the semiconductor body 1 is 70°~90°.

[0051] S350, Remove the first photoresist layer.

[0052] For details, please refer to Figure 3 The remaining first photoresist layer 31 is removed using a wet photoresist removal process. After the first photoresist layer 31 is removed, the first surface S1 of the semiconductor body 1 is exposed, and a groove 21 is formed in the semiconductor body 1.

[0053] S360. A mask material is deposited on the first surface of the semiconductor body and in the groove to form a first mask layer. The mask material includes at least one of silicon oxide, silicon nitride, and metal. The surface of the first mask layer away from the semiconductor body has a recess in the region corresponding to the groove.

[0054] For details, please refer to Figure 11A mask material is deposited on the first surface S1 of the semiconductor body 1 and in the groove 21 to form a first mask layer 41. The mask material includes at least one of silicon oxide, silicon nitride, and metal. In this embodiment, the material of the first mask layer 41 is preferably silicon nitride, which has advantages such as good density, strong anti-diffusion ability, and matching thermal expansion coefficient with silicon carbide. The first mask layer 41 can be formed by processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The first mask layer 41 covers the first surface S1 of the semiconductor body 1 and fills the groove 21. Due to the presence of the groove 21, when depositing the first mask layer 41, a recess 412 is formed on the surface of the first mask layer 41 away from the semiconductor body 1 in the region corresponding to the groove 21. That is, the surface of the first mask layer 41 has a concave shape above the groove 21.

[0055] S370, a second photoresist layer is formed on the surface of the first mask layer away from the semiconductor body.

[0056] For details, please refer to Figure 12 The second photoresist layer 32 can be formed by spin coating the surface of the first mask layer 41 and pre-baking curing.

[0057] S380. The second photoresist layer is patterned to form a second opening on the surface of the first mask layer corresponding to the exposed groove area.

[0058] For details, please refer to Figure 13 The second photoresist layer 32 is exposed and developed using photolithography to remove the photoresist at the corresponding position above the preset injection area A, forming the second opening K2. The width of the second opening K2 corresponds to the target width of the subsequently formed injection window C1. That is, the second opening K2 is directly opposite the preset injection area A in the vertical direction.

[0059] S390. Using the patterned second photoresist layer as a mask, etch the first mask layer to form an injection window at the position corresponding to the second opening.

[0060] For details, please refer to Figure 14 Using the patterned second photoresist layer 32 as a mask, the first mask layer 41 is etched to form an injection window C1 at the position corresponding to the second opening K2. The etching process can employ anisotropic dry etching, such as reactive ion etching or inductively coupled plasma etching. The injection window C1 penetrates the first mask layer 41, exposing the first surface S1 of the semiconductor body 1, and the injection window C1 corresponds to the position of the preset injection region A in the vertical direction.

[0061] S3100, Remove the second photoresist layer.

[0062] For details, please refer to Figure 4The remaining second photoresist layer 32 is removed using a wet photoresist removal process. After the second photoresist layer 32 is removed, the first mask layer 41 is exposed, and the injection window C1 is formed in the first mask layer 41.

[0063] S3110. Ion implantation is performed into the semiconductor body through the implantation window to form a doped region in a predetermined implantation area of ​​the semiconductor body; wherein, the first mask layer filling the groove constitutes a barrier layer to suppress lateral scattering during the ion implantation process, so that the actual doped region is consistent with the pattern of the implantation window. (Reference) Figure 5 ) In this embodiment, based on the above embodiments, the step of forming a groove 21 on the first surface S1 of the semiconductor body 1 includes: forming a first photoresist layer 31 on the first surface S1 of the semiconductor body 1; patterning the first photoresist layer 31 to form a first opening K1 exposing the first surface S1 of the semiconductor body 1; using the patterned first photoresist layer 31 as a mask, etching the semiconductor body 1 to form a groove 21 at the position corresponding to the first opening K1; and removing the first photoresist layer 31. Based on the above process, the position and morphology of the groove 21 are precisely controlled by the photolithography and etching processes. On the one hand, the high precision of the photolithography process ensures that the groove 21 can be accurately positioned on at least one side of the preset injection region A, so that the first mask layer 41 subsequently filled in the groove 21 can form a precisely positioned barrier layer 411. On the other hand, the anisotropic dry etching process makes the sidewalls of the groove 21 steep, which is beneficial for the first mask layer 41 to form a uniform and dense coverage on the sidewalls of the groove 21, thereby improving the suppression effect of the barrier layer 411 on lateral scattering.

[0064] Furthermore, the step of patterning the first mask layer 41 to form an implantation window C1 exposing the surface of the semiconductor body 1 includes: forming a second photoresist layer 32 on the surface of the first mask layer 41 away from the semiconductor body 1; patterning the first photoresist layer 31 to form a second opening K2 on the surface of the first mask layer 41 corresponding to the area of ​​the exposed groove 21; using the patterned second photoresist layer 32 as a mask, etching the first mask layer 41 to form the implantation window C1 at the position corresponding to the second opening K2; and removing the second photoresist layer 32. Based on the above process, the positional and dimensional accuracy of the implantation window C1 is effectively guaranteed, providing a precise process basis for ensuring that the actual doped region 201 and the implantation window C1 pattern remain consistent during subsequent ion implantation, thereby further ensuring that the threshold voltage characteristics and breakdown voltage of the device meet the design expectations.

[0065] Figure 15 A flowchart of another method for fabricating a semiconductor device provided in the embodiments of the invention is shown below. Figure 15 The fabrication methods for physical devices include: S410, provides a semiconductor body; the semiconductor body has a first surface.

[0066] S420, A groove is formed on the first surface of the semiconductor body; the groove is located on at least one side of a predetermined injection region in the semiconductor body.

[0067] S430. A first mask layer is formed on the first surface of the semiconductor body and in the groove, and the first mask layer 41 is patterned to form an injection window that exposes the first surface of the semiconductor body.

[0068] S440. Ions are implanted into the semiconductor body through the implantation window to form a doped region in the preset implantation area of ​​the semiconductor body; wherein, the first mask layer filled in the groove constitutes a barrier layer to suppress lateral scattering during the ion implantation process, so that the actual doped region is consistent with the pattern of the implantation window.

[0069] S450, a second mask layer is formed on the surface of the first mask layer away from the semiconductor body and on the surface of the doped region exposed by the first mask layer.

[0070] For details, please refer to Figure 16 A second mask layer 42 is formed using a deposition process. The second mask layer 42 covers the upper surface of the first mask layer 41 and the surface of the doped region 201 exposed by the implantation window C1. The material of the second mask layer 42 can be silicon oxide, silicon nitride, or other suitable mask materials. Furthermore, the material of the first mask layer 41 and the second mask layer 42 can be the same, which facilitates subsequent overall etching and removal.

[0071] S460, Remove the first mask layer located in the groove and the second mask layer located above the groove to expose the groove.

[0072] Specifically, the step of removing the first mask layer 41 located in the groove 21 and the second mask layer 42 located above the groove 21 to expose the groove 21 includes: (Refer to...) Figure 17 A third photoresist layer 33 is formed on the surface of the second mask layer 42 away from the semiconductor body 1, and the third photoresist layer 33 is patterned to form a third opening K3 on the surface of the second mask layer 42 corresponding to the exposed groove 21 region; Reference Figure 18 Using the patterned third photoresist layer 33 as a mask, the second mask layer 42 and the first mask layer 41 are etched to expose the groove 21; Reference Figure 19 Remove the third photoresist layer 33.

[0073] Photoresist can be coated onto the surface of the second mask layer 42 using a spin-coating process and then pre-baked to form a third photoresist layer 33. The third photoresist layer 33 is then exposed and developed using a photolithography process to remove the photoresist above the groove 21 area, forming a third opening K3. The third opening K3 corresponds vertically to the position of the groove 21. During etching, the second mask layer 42, which penetrates the bottom of the third opening K3, is etched first, and then the first mask layer 41 (i.e., the barrier layer 411 filling the groove 21) below is etched until the bottom and sidewalls of the groove 21 are exposed. Because the third photoresist layer 33 covers other areas, the portions of the second mask layer 42 and the first mask layer 41 outside the groove 21 area are retained. The remaining third photoresist layer 33 can be removed using a wet stripping process. After removing the third photoresist layer 33, the groove 21 is exposed.

[0074] S470, A semiconductor filling layer is formed in the groove.

[0075] For details, please refer to Figure 20 Semiconductor material can be filled into the groove 21 using epitaxial growth or deposition processes to form a semiconductor filling layer 22. The material of the semiconductor filling layer 22 is the same as that of the semiconductor body 1. In some embodiments, a selective epitaxial growth process can be used to grow semiconductor material only in the groove 21, with the upper surface of the semiconductor filling layer 22 flush with the first surface S1 of the semiconductor body 1. In other embodiments, semiconductor material can be deposited first to cover the entire device surface, and then planarization can be performed using a chemical mechanical polishing process to remove excess semiconductor material, making the upper surface of the semiconductor filling layer 22 flush with the upper surface of the second mask layer 42. The semiconductor filling layer 22 is used to fill the groove 21, which can restore the flatness of the first surface S1 of the semiconductor body 1 and provide a flat process surface for subsequent device manufacturing processes (such as gate formation, electrode contact, etc.).

[0076] S480, Remove the remaining second mask layer and first mask layer.

[0077] For details, please refer to Figure 21 The remaining second mask layer 42 and first mask layer 41 can be removed using wet etching or dry etching processes. After removing the remaining mask layers, the first surface S1 of the semiconductor body 1 is exposed, the doped region 201 is formed in the preset implantation region A, the groove 21 is filled by the semiconductor filling layer 22, and the first surface S1 of the semiconductor body 1 is restored to flatness.

[0078] In this embodiment, based on the above embodiments, ion implantation is performed into the semiconductor body 1 through the implantation window C1. After forming a doped region 201 in the preset implantation region A of the semiconductor body 1, the method further includes: forming a second mask layer 42 on the surface of the first mask layer 41 away from the semiconductor body 1 and on the surface of the doped region 201 exposed by the first mask layer 41; removing the first mask layer 41 located in the groove 21 and the second mask layer 42 located above the groove 21 to expose the groove 21; forming a semiconductor filling layer 22 in the groove 21; and removing the remaining second mask layer 42 and first mask layer 41. Through the above steps, the semiconductor device fabrication method provided by this embodiment not only effectively suppresses lateral scattering during ion implantation by using the first mask layer 41 filled in the groove 21 as a barrier layer 411, but also restores the groove 21 to a flat state after ion implantation, providing a good process surface for subsequent processes.

[0079] Furthermore, after step S440, before step S470, or after step S480, annealing can be performed on the doped region 201 as needed to activate the dopant in the doped region 201. The temperature and time of the annealing process can be selected according to the material of the semiconductor body 1 and the type of implanted ions; this embodiment does not specifically limit this. Specifically, annealing after step S440 utilizes the barrier layer 411 to block the lateral diffusion of ions in the doped region 201, ensuring that the doped region 201 remains consistent with the implantation window C1 pattern after annealing. Annealing after step S470 utilizes the grooves 21 on both sides of the doped region 201 to block the lateral diffusion of ions in the doped region 201, ensuring that the doped region 201 remains consistent with the implantation window C1 pattern after annealing.

[0080] This application also provides a semiconductor device, which is prepared by the semiconductor device preparation method described in any embodiment of this application. The semiconductor device includes a semiconductor body 1; the semiconductor body 1 has a first surface S1, and the semiconductor body 1 further includes a doped region 201 located on the first surface S1 of the semiconductor body 1.

[0081] Specifically, the doped region 201 is the doped region 201 domain formed by the ion implantation step in the above preparation method. During the ion implantation process, since the first mask layer 41 filling the groove 21 constitutes a barrier layer 411, it effectively suppresses the lateral scattering of ion implantation, so that the edge of the doped region 201 is consistent with the pattern of the implantation window C1, and the boundary of the doped region 201 is precisely controllable.

[0082] In some embodiments, the semiconductor body 1 includes a plurality of doped regions 201. At least one doped region 201 is an ohmic contact region, and / or, at least one doped region 201 is a field limiting ring.

[0083] Specifically, the ohmic contact region refers to the doped region 201 used to form the ohmic contact, typically a heavily doped region 201 (e.g., N+ or P+ type doped region 201). Located in the source or drain region of the MOSFET device, it reduces the contact resistance between the metal electrode and the semiconductor body 1, achieving excellent ohmic contact characteristics. Because lateral scattering is effectively suppressed, the boundary of the ohmic contact region does not extend towards the channel, ensuring the designed channel length and thus guaranteeing key performance parameters such as the device's threshold voltage and on-resistance.

[0084] A field-limiting ring (FLR) refers to a doped region 201 located in the terminal region of the semiconductor body 1, typically a P-type or P+ type doped region 201. The FLR forms multiple ring-shaped P-type doped regions 201 in the device terminal region, utilizing the space charge region broadening of the PN junction to alleviate the electric field concentration effect at the main junction edge, thereby improving the device's breakdown voltage. Because lateral scattering is effectively suppressed, the boundaries of the doped regions 201 in the FLR are precisely controllable, preventing the terminal electric field distribution from deviating from the design value due to lateral scattering broadening, thus ensuring the device's breakdown voltage and long-term reliability.

[0085] This application also provides a mask structure, see reference. Figure 22 The mask structure includes: The mask layer body 100 has a first side surface 101 and a second side surface 102 facing each other, and at least one injection window C1 is formed in the mask layer body 100 through the first side surface and the second side surface; wherein, the second side surface 102 faces the semiconductor body to be injected. The second side surface 102 of the mask layer body 100 has a blocking portion 110 on at least one side of the injection window C1. The blocking portion 110 protrudes from the second side surface 102 of the mask layer body 100 in a direction away from the first side surface 101. The blocking portion 110 is used to suppress lateral scattering of ions during ion implantation so that the actual implantation area is consistent with the pattern of the implantation window.

[0086] Specifically, the mask layer body 100 has a first side surface 101 and a second side surface 102. The second side surface 102 is oriented toward the semiconductor body to be implanted, that is, the second side surface 102 is the side facing the semiconductor body when the mask layer is used; the first side surface 101 is the side away from the semiconductor body when the mask layer is used, that is, the incident side for ion implantation.

[0087] At least one implantation window C1 is formed in the mask layer body 100, penetrating the first side surface 101 and the second side surface 102. The implantation window C1 is used to define the ion implantation area during ion implantation. The number and distribution of the implantation windows C1 are determined according to the actual device design requirements, and for example, there may be one or more. The second side surface 102 of the mask layer body 100 has a blocking portion 110 on at least one side of the implantation window C1. The blocking portion 110 protrudes from the second side surface 102 of the mask layer body 100 in a direction away from the first side surface 101. That is, the blocking portion 110 protrudes outward from the second side surface 102 of the mask layer body 100, and the extension direction is opposite to the first side surface 101. The mask layer body 100 and the blocking portion 110 are made of the same material, that is, they are integrally formed. The blocking portion 110 is used as a blocking layer to suppress lateral ion scattering during ion implantation, so that the actual implantation area is consistent with the pattern of the implantation window C1.

[0088] Optionally, the blocking portions 110 are located on opposite sides of the implantation window C1. By providing blocking portions 110 on opposite sides of the implantation window C1, the blocking portions 110 simultaneously suppress lateral ion scattering from both sides of the implantation window C1, thereby ensuring that the actual implantation area is consistent with the pattern of the implantation window C1 on both sides. The spacing between the blocking portions 110 corresponds to the width of the implantation window C1.

[0089] Optionally, a recess is formed on the first side surface 101 of the mask layer body 100 in the region corresponding to the blocking portion 110. That is, the first side surface 101 of the mask layer body 100 has a concave shape corresponding to the position of the blocking portion 110.

[0090] Optionally, the material of the mask layer body 100 includes at least one of silicon oxide, silicon nitride, and metal.

[0091] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provide semiconductor body; The semiconductor body has a first surface; A groove is formed on the first surface of the semiconductor body; The groove is located on at least one side of a predetermined injection region in the semiconductor body; A first mask layer is formed on the first surface of the semiconductor body and in the groove, and the first mask layer is patterned to form an injection window that exposes the first surface of the semiconductor body. Ions are implanted into the semiconductor body through the implantation window to form a doped region in a predetermined implantation area of ​​the semiconductor body; wherein, the first mask layer filling the groove constitutes a barrier layer to suppress lateral scattering during the ion implantation process.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The process of forming a groove on the first surface of the semiconductor body includes: A first photoresist layer is formed on the first surface of the semiconductor body; The first photoresist layer is patterned to form a first opening that exposes the first surface of the semiconductor body; Using the patterned first photoresist layer as a mask, the semiconductor body is etched to form the groove at the position corresponding to the first opening; Remove the first photoresist layer.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The process of forming a groove on the first surface of the semiconductor body includes: The semiconductor bodies on opposite sides of the preset injection region are etched to form the grooves on opposite sides of the preset injection region; wherein the depth of the grooves is greater than or equal to the depth of the preset injection region.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The formation of the first mask layer on the first surface of the semiconductor body and in the groove includes: A mask material is deposited on the first surface of the semiconductor body and in the groove to form the first mask layer. The mask material includes at least one of silicon oxide, silicon nitride, and metal. The surface of the first mask layer away from the semiconductor body has a recess in the region corresponding to the groove.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of patterning the first mask layer to form an injection window exposing the surface of the semiconductor body includes: A second photoresist layer is formed on the surface of the first mask layer away from the semiconductor body; The second photoresist layer is patterned to form a second opening on the surface of the first mask layer corresponding to the groove region; Using the patterned second photoresist layer as a mask, the first mask layer is etched to form the injection window at the position corresponding to the second opening; Remove the second photoresist layer.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, After ion implantation into the semiconductor body through the implantation window to form a doped region in the predetermined implantation region of the semiconductor body, the process further includes: A second mask layer is formed on the surface of the first mask layer away from the semiconductor body and on the surface of the doped region exposed by the first mask layer; Remove the first mask layer located in the groove and the second mask layer located above the groove to expose the groove; A semiconductor filling layer is formed in the groove; Remove the remaining second mask layer and the first mask layer.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The removal of the first mask layer located in the groove and the second mask layer located above the groove to expose the groove includes: A third photoresist layer is formed on the surface of the second mask layer away from the semiconductor body; The third photoresist layer is patterned to form a third opening on the surface of the second mask layer corresponding to the groove region; Using the patterned third photoresist layer as a mask, the second mask layer and the first mask layer are etched to expose the groove; Remove the third photoresist layer.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, After removing the remaining second mask layer and the first mask layer, the process further includes: The doped region is then annealed. Alternatively, before forming the semiconductor filling layer in the groove, the method further includes: The doped region is then annealed.

9. A semiconductor device, characterized in that, The semiconductor device is prepared by the method of any one of claims 1 to 8, wherein the semiconductor device comprises a semiconductor body; The semiconductor body has a first surface, and the semiconductor body further includes a doped region located on the first surface of the semiconductor body.

10. The semiconductor device according to claim 9, characterized in that, The semiconductor body includes multiple doped regions, at least one of which is an ohmic contact region, and / or at least one of which is a field-limiting ring.

11. A mask structure, characterized in that, include: A mask layer body has opposing first side surfaces and second side surfaces, wherein at least one injection window is formed in the mask layer body penetrating the first side surface and the second side surface; wherein the second side surface faces the semiconductor body to be injected; The second side surface of the mask layer body is provided with a blocking portion on at least one side of the injection window. The blocking portion protrudes from the second side surface of the mask layer body in a direction away from the first side surface. The blocking portion is used to suppress lateral scattering of ions during ion implantation so that the actual implantation area is consistent with the pattern of the injection window.

12. The mask structure according to claim 11, characterized in that, The blocking portions are located on opposite sides of the injection window.

13. The mask structure according to claim 11, characterized in that, The first side surface of the mask layer body has a recess formed in the region corresponding to the blocking portion.

14. The mask structure according to claim 11, characterized in that, The material of the mask layer body includes at least one of silicon oxide, silicon nitride, and metal.

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