A method for manufacturing a wide-width inkjet printing chip, a chip, a device, electronic equipment and a storage medium

Abstract

The application relates to a wide-width ink-jet printing chip manufacturing method, a chip, an apparatus, electronic equipment and a storage medium. The wide-width ink-jet printing chip manufacturing method comprises the following steps: firstly, acquiring width requirement information; then, determining target chip size information according to the width requirement; performing scribe calculation based on the target chip size information and wafer substrate information to obtain cutting strategy information; and finally, cutting the wafer substrate by using the cutting strategy information to obtain the target chip. It can be seen that, in the printing chip manufacturing process, the wafer substrate is directly adaptively cut to obtain the target chip meeting the requirement, the technical problems of poor stability and poor printing quality in the wide-width printing scene caused by the fixed size of the traditional ink cartridge driving chip are solved, the target chip meeting the required size can be adaptively cut according to the requirement, and the printing effect with high stability and high printing quality is achieved.

Description

Technical Field

[0001] This application relates to the field of printing, and more specifically, to a method for manufacturing a wide-format inkjet printing chip, a chip, an apparatus, an electronic device, and a storage medium. Background Technology

[0002] In the printing industry, inkjet printing has always been a prevalent printing method. The basic principle of inkjet printing is that the printing chip works with the ink cartridge to control the printing process. The size of existing ink cartridge driver chips is generally less than 1 inch, which limits the size of a single printer ink cartridge printhead to 1 inch.

[0003] However, with the continuous development of printing needs, more and more printing scenarios require wide-format printing. The existing printing chip configurations that require wide-format printing usually adopt a solution of single printhead lateral movement or multiple printhead splicing.

[0004] Single-head traverse printing requires the printhead to move repeatedly on the printing medium, resulting in low printing efficiency, insufficient positioning accuracy, and easy mechanical vibration and wear, affecting the stability of print quality. While multi-head splicing can improve printing speed, it requires precise alignment of multiple printheads, significantly increasing system complexity and manufacturing costs. At the same time, uneven ink droplet distribution and image stitching defects often occur in the splicing area. In other words, existing wide-format printing scenarios generally suffer from poor stability and poor print quality. Summary of the Invention

[0005] To address the common technical problems of poor stability and poor print quality in wide-format printing scenarios, this application provides a method for manufacturing a wide-format inkjet printing chip, a chip, an apparatus, an electronic device, and a storage medium.

[0006] In a first aspect, this application provides a method for manufacturing a wide-format inkjet printed chip, comprising: Obtain width requirement information; Determine the target chip size information based on the width requirements; Based on the target chip size information and the wafer substrate information, the scribing calculation is performed to obtain the slitting strategy information; The wafer substrate is cut using a slitting strategy to obtain the target chip.

[0007] Furthermore, this application also proposes to perform scribing calculations based on the target chip size information and wafer substrate information to obtain slicing strategy information, including: Based on the wafer substrate information, determine the unit chip size information and unit chip layout information; The unit chip size information is matched and calculated with the target chip size information to obtain the unit chip combination information; By combining unit chip combination information and unit chip layout information, the target division area information is determined; Based on the target region information, line delineation calculations are performed to generate segmentation strategy information.

[0008] Furthermore, this application also proposes to use dicing strategy information to dice the wafer substrate to obtain the target chip, and then further includes: Based on the width requirement information, determine the number of thermal spray units; Based on the number of thermal spray units, combined with the circuit array information and target chip size information corresponding to the target chip, thermal spray unit layout analysis is performed to obtain thermal spray unit circuit layout information; Based on the thermal spray unit circuit layout information, the target chip is fabricated using a thermal spray circuit to obtain an inkjet printed chip.

[0009] Furthermore, this application also proposes to perform thermal spray unit layout analysis based on the number of thermal spray units, combined with the circuit array information and target chip size information corresponding to the target chip, to obtain thermal spray unit circuit layout information, including: Based on the number of thermal spray units and the size of the target chip, the positional arrangement of the thermal spray units is analyzed to obtain the positional information of the thermal spray units. Based on the location information of the thermal spray unit and the circuit array information, circuit matching analysis is performed to determine the circuit connection method information; Based on the location information of the thermal spray unit and the circuit connection information, the circuit layout information of the thermal spray unit is generated.

[0010] Furthermore, this application also proposes to analyze the positional arrangement of the thermal spray units based on the number of thermal spray units and the target chip size information to obtain the positional information of the thermal spray units, including: Based on the target chip size information, determine the chip body size information and the scribing groove size information, where the scribing groove size information is used to represent the size of the scribing groove between unit chips; Based on the chip body size information and the scribing groove size information, the thermal spray unit position layout analysis is performed to determine the first position information corresponding to the chip body size information and the second position information corresponding to the scribing groove size information. The first position information represents the position information of the thermal spray unit at the chip body position, and the second position information represents the position information of the thermal spray unit at the scribing groove position. Based on the first and second position information, the position information of the thermal spray unit is generated.

[0011] Furthermore, this application also proposes to perform circuit matching analysis based on the location information of the thermal spray unit and the circuit array information to determine the circuit connection method information, including: Based on the circuit array information, determine the row selection signal pins and column selection signal pins; Based on the position information of the thermal spray unit and combined with the row selection signal pins, the row selection signal circuit matching analysis of the thermal spray unit is performed to obtain the row selection signal connection information; Based on the position information of the thermal spray unit and combined with the column selection signal pins, the column selection signal circuit matching analysis of the thermal spray unit is performed to obtain the column selection signal connection information; Based on the row selection signal connection method information and the column selection signal connection method information, the circuit connection method information is generated.

[0012] In a second aspect, this application provides a wide-format inkjet printing chip, which is manufactured by the method of manufacturing a wide-format inkjet printing chip in the first aspect. The wide-format inkjet printing chip includes: a target chip and a thermal spray unit electrically connected to the target chip. The target chip includes at least two unit chips, wherein scribe lines are reserved between each unit chip; The thermal spraying unit is used to perform inkjet printing according to the control of the target chip, and the thermal spraying unit is continuously arranged between each of the unit chips and the scribing groove.

[0013] Thirdly, this application provides an apparatus for fabricating a wide-format inkjet printed chip, comprising: The acquisition module includes acquiring width requirement information; The determining module includes determining the target chip size information based on the width requirement; The scribing calculation module includes scribing calculation based on the target chip size information and the wafer substrate information to obtain slicing strategy information; The dicing module includes dicing a wafer substrate using the dicing strategy information to obtain a target chip.

[0014] Fourthly, an electronic device is provided, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; The processor, when executing a program stored in memory, implements the method for manufacturing a wide-format inkjet printing chip as described in any of the first aspects.

[0015] Fifthly, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method for manufacturing a wide-format inkjet printing chip as described in any of the first aspects.

[0016] The method for manufacturing a wide-format inkjet printed chip provided in this application first obtains the width requirement information, then determines the target chip size information based on the width requirement, and then performs scribing calculations based on the target chip size information and wafer substrate information to obtain slicing strategy information. Finally, the wafer substrate is cut using the slicing strategy information to obtain the target chip. It is evident that this application solves the technical problem of poor stability and poor print quality in wide-format printing scenarios caused by relying on traditional ink cartridges to drive fixed chip sizes by directly and adaptively slicing the wafer substrate during the chip manufacturing process. It can adaptively slicing according to requirements yields a target chip of the required size, achieving high stability and high print quality. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic flowchart illustrating a method for fabricating a wide-format inkjet printed chip, provided in an embodiment of this application; Figure 2 This is a schematic diagram of the overall structure of a wide-format inkjet printing chip provided in an embodiment of this application; Figure 3 This application provides a schematic diagram of the structure of a unit chip in a wide-format inkjet printing chip. Figure 4 A schematic diagram of a wafer substrate structure for a wide-format inkjet printed chip provided in this application embodiment; Figure 5 A schematic diagram illustrating the fabrication structure of a wide-format inkjet printing chip provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0020] Figure labels: 1. Target chip; 11. First pin layer; 12. Driver circuit layer; 13. Second pin layer; 2. Thermal spray unit; 3. Scribing groove; 4. Ink cartridge structure; Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] In traditional inkjet printing technology, the physical size of the driver chip is limited by wafer manufacturing processes, preventing a single ink cartridge printhead from covering a wide printing area exceeding 1 inch. Existing technologies must employ multi-printhead stitching or single-printhead lateral movement mechanisms to meet wide-format printing requirements, introducing mechanical complexity and printhead alignment errors, thus affecting printing accuracy and system reliability. Specifically, the size limitation of the driver chip stems from the physical constraints of the individual manufacturing process, preventing the ink cartridge from completing continuous printing of a wide area with a single printhead, thus forcing the system to rely on external mechanical compensation solutions.

[0023] For example, in industrial-grade advertising banner printing scenarios, when the required width reaches 1.5 inches, existing systems require deploying two adjacent printheads for horizontal splicing. During this process, due to the fixed size of the driver chip, minute displacements during installation and operation of each printhead unit can cause misalignment and discontinuous color transitions in the splicing area, resulting in detectable defects in the visual consistency of the printed product. Furthermore, this problem is particularly pronounced in high-speed printing modes, as mechanical vibration and thermal expansion exacerbate printhead positional deviations, necessitating frequent system calibration and adjustments, thus increasing the risk of operational interruptions.

[0024] If the aforementioned limitations in driver chip size are not resolved, printing systems will continue to rely on mechanical splicing mechanisms. This not only increases the complexity of equipment maintenance but may also lead to wider fluctuations in print quality. Accumulated mechanical errors will reduce the overall stability of the system, increasing the frequency of production interruptions and potentially affecting continuous operation capabilities due to the need for repeated calibration. Therefore, this technological bottleneck severely restricts the applicability of wide-format printing technology in high-precision applications, highlighting the necessity of addressing the flexibility issue of driver chip size.

[0025] The core reason for these technological bottlenecks lies in the limited size of the driver chip for a single inkjet printhead. Existing semiconductor manufacturing processes cannot directly produce a single driver chip wider than 1 inch, thus failing to support wide-format printing with a single printhead in a single pass. Developing a single large-size printhead for one-pass printing would effectively circumvent these mechanical defects. However, current technology lacks a driver chip design method that can flexibly adapt to arbitrary width requirements without altering wafer substrate production conditions. Particularly in the design and manufacturing of driver chips exceeding 1 inch, challenges arise in chip size expansion and circuit layout compatibility, severely restricting the performance improvement and application expansion of wide-format inkjet printing equipment.

[0026] Figure 1 This is a schematic flowchart illustrating a method for fabricating a wide-format inkjet printed chip, as provided in an embodiment of this application.

[0027] like Figure 1 As shown in the illustration, this application discloses an embodiment of a method for manufacturing a wide-format inkjet printed chip, comprising: S110: Obtain width requirement information; S120: Determine the target chip size information based on the width requirements; S130: Based on the target chip size information and the wafer substrate information, perform scribing calculations to obtain slicing strategy information; S140: The chip substrate is cut using the slicing strategy information to obtain the target chip.

[0028] For ease of understanding, the following explains some key terms in this embodiment: Width requirement information refers to the width of the printing area that an inkjet printer needs to cover in a single printing process. This is usually determined by the application scenario of the final product, such as large-format advertising printing, industrial printing, etc., and its value can be a specific unit of length, such as inches or millimeters.

[0029] The target chip size information refers to the overall physical dimensions of the wide-format inkjet printable chip that needs to be constructed to meet the aforementioned width requirements, including its length, width, and other parameters. This information is converted and determined based on the width requirements; for example, if the width requirements determine the print width to be 1 inch, then, considering the edge portion, the target chip size information indicates that the target chip size can be 1.14 inches.

[0030] Wafer substrate information refers to the raw material used to manufacture semiconductor chips, typically silicon wafers. This information includes the wafer's diameter, thickness, available effective area, and manufacturing parameters such as the layout and dimensions of existing cell chips on it.

[0031] Scribing calculation refers to the process in semiconductor manufacturing where, based on predetermined chip dimensions and wafer layout, the specific paths and methods for cutting (scribing) on ​​the wafer are calculated. Its purpose is to precisely separate multiple chip units on the wafer.

[0032] The slitting strategy information refers to the results of the scribing calculations, which includes specific instructions and parameters for slitting the wafer substrate, such as the coordinates of the slitting lines, the slitting sequence, and the slitting depth. This information guides the slitting equipment to perform precise operations.

[0033] In this embodiment, a wafer substrate refers to a wafer that has completed semiconductor manufacturing processes and on which multiple unit chips are integrated. It awaits being diced into individual target chips.

[0034] The target chip refers to a wide-format inkjet printing chip manufactured using this method that can meet specific width requirements. This chip is typically composed of multiple unit chips spliced ​​together to achieve a printing width exceeding the size of a single unit chip.

[0035] This application proposes a method for fabricating a wide-format inkjet printed chip, which aims to break the physical limitations of single-chip manufacturing processes on size by directly cutting target chips of different sizes on a wafer substrate, thereby enabling the fabrication of single-cartridge driver chips with arbitrary size requirements.

[0036] Specifically, firstly, the required print width information is obtained. This information can be manually entered by the operator through a human-machine interface. For example, the operator inputs the required print width, such as "2 inches" or "50 millimeters," into the system based on the print job requirements. Alternatively, this information can be obtained by reading a preset configuration file or job order. For instance, the system automatically loads a configuration file containing print width parameters to obtain this information. Furthermore, it can also be received through communication with external devices or systems. For example, the printer control system receives a print job instruction from a host computer, which includes the print width requirement.

[0037] Furthermore, based on the aforementioned width requirement information, the target chip size information is determined. This target chip size information can be simply linearly converted according to a preset scaling factor or conversion rule. For example, if the width requirement is X, the width of the target chip is set to X, or X is multiplied by a fixed scaling factor. As a preferred implementation, this information can also be determined by consulting a predefined size lookup table. For example, the system maintains a mapping table between width requirements and target chip sizes; when the width requirement is obtained, the corresponding target chip size is directly looked up from the table. Alternatively, through simple mathematical calculations, the width requirement can be directly used as a certain dimension of the target chip, while other dimensions are set based on empirical values ​​or fixed values.

[0038] Based on this, and using the target chip size information combined with the wafer substrate information, dicing calculations are performed to obtain dicing strategy information. This dicing calculation can be done manually, with engineers drawing the dicing lines in the design software based on the target chip size and wafer substrate information, and generating the dicing strategy. This method relies on the engineer's experience and judgment. As an alternative, calculations can also be performed using simple geometric matching algorithms. For example, the target chip size is compared with the sizes of existing unit chips on the wafer, and then multiple unit chips are simply arranged and combined to approximate the target chip size, thereby determining the dicing lines. Alternatively, matching can be performed using preset dicing templates. For example, the system stores multiple dicing templates; based on the target chip size information, the closest template is selected and fine-tuned using the wafer substrate information to generate the dicing strategy information.

[0039] Finally, the wafer substrate is diced using the dicing strategy information to obtain the target chip. This dicing process can employ traditional mechanical cutting methods, such as using diamond blades or saw blades to physically cut along the path indicated by the dicing strategy information. Alternatively, laser cutting technology can be used, where a high-energy laser beam ablates dicing lines on the wafer substrate to separate the chip. Furthermore, a combination of chemical and physical methods, such as plasma etching, can be used to selectively etch specific areas to achieve chip dicing.

[0040] The following example will provide a more detailed explanation of the above technical solution: Suppose a printing equipment manufacturer needs to develop a wide-format inkjet printing chip for a new industrial printer, requiring a printing width of 4 inches. Traditionally, a single inkjet printing chip is typically 1 inch wide, meaning that to achieve a 4-inch printing width, four 1-inch chips would need to be physically joined together, or a complex mechanical scanning mechanism would be required.

[0041] To address this issue, the manufacturing method described in this application is applied. First, the chip manufacturer's system receives a "4-inch" width requirement from the printing equipment manufacturer. Based on this width requirement, the system converts it into the physical dimensions of the target chip. For example, the system determines that the target chip's width should be 101.6 mm (i.e., 4 inches), while its length is set to 20 mm according to standard design. Thus, the target chip size information is determined to be "101.6 mm x 20 mm".

[0042] Subsequently, the system performs scribing calculations based on the target chip size information and the wafer substrate information. It is assumed that each unit chip on the chip manufacturer's wafer substrate measures 25.4mm x 20mm (i.e., 1 inch wide). (Reference) Figure 4 , Figure 4 The image shows the dimensions of a die-on-a-chip (DIE) on a wafer substrate (25.4mm x 20mm). The system matches the target chip size (101.6mm x 20mm) with the dimensions of the die-on-a-chip on the wafer substrate (25.4mm x 20mm). Through calculation, the system finds that four die-on-a-chips need to be combined along the width direction to achieve a width of 101.6mm. The system further considers the overall wafer layout and dicing losses, precisely calculating how to scribe lines on the wafer to cut out these four die-on-a-chips and ensure that they can be combined into a whole. This generates detailed dicing strategy information, including the precise coordinates and dicing depth of each dicing line.

[0043] Finally, the wafer substrate is fed into a dicing machine. Based on the dicing strategy information generated above, the dicing machine precisely cuts the wafer substrate. For example, the dicing machine uses a high-precision diamond saw blade to cut along a calculated scribe line, separating multiple unit chips on the wafer and ultimately obtaining a wide target chip of 101.6mm x 20mm, composed of four unit chips. Thus, without changing the existing unit chip manufacturing process, an inkjet-printed chip meeting the 4-inch width requirement was successfully manufactured.

[0044] The aforementioned manufacturing method effectively solves the problem of traditional inkjet-printed chips being unable to achieve wide-format printing with a single printhead due to size limitations by intelligently planning during the wafer dicing stage. Compared to existing technologies that require physical splicing of multiple independently packaged chips later, the method in this application completes the "pre-splitting" planning at the wafer substrate level, thereby avoiding problems such as alignment accuracy, electrical connection complexity, and mechanical structure stability that may arise from later splicing. By obtaining the width requirement and converting it into the target chip size, and then combining it with wafer substrate information for scribing calculations, this method achieves customized mapping from the demand side to the manufacturing side. This allows for flexible construction of single-cartridge driver chips that meet specific width requirements by reasonably dividing and recombining existing unit chips without changing the existing production line process conditions. This wafer-level dicing strategy optimization significantly simplifies the manufacturing process of wide-format inkjet-printed chips, reduces production costs, and improves the integration and reliability of the final product.

[0045] In some of the solutions mentioned above in this application, a slicing strategy is proposed to be obtained by slicing based on the target chip size information combined with the wafer substrate information. However, in the actual production process, there is a lack of specific logic mapping and layout planning methods to efficiently and accurately combine the existing unit chips on the wafer and transform them into target chips that meet specific width requirements. This makes it impossible to directly utilize existing wafer substrate resources to flexibly customize large-size chips.

[0046] To address this, this application further proposes a method for calculating slicing strategies based on target chip size information and wafer substrate information. This process includes: determining unit chip size information and unit chip layout information based on wafer substrate information; matching and calculating the unit chip size information with the target chip size information to obtain unit chip combination information; determining target segmentation region information by combining the unit chip combination information and the unit chip layout information; and performing slicing calculations based on the target segmentation region information to generate slicing strategy information.

[0047] Specifically, based on wafer substrate information, the unit chip size information and unit chip layout information are determined, aiming to obtain the specifications and arrangement of the unit chips already fabricated on the wafer. The unit chip size information represents the size of each unit chip on the wafer substrate, for example... Figure 4 The dimensions of the unit cells (DIEs) are specified, while the unit cell layout information indicates the specific arrangement of the unit cells (DIEs) on the wafer substrate, such as... Figure 4 As shown.

[0048] Specifically, in one example, the precise dimensions (length, width, thickness, etc.) of the unit chips and their layout information on the wafer, such as coordinates, spacing, and array pattern, can be obtained by reading design files (such as GDSII files and layout files) from the wafer manufacturing process. Alternatively, the wafer can be scanned and image processed using optical inspection equipment (such as an automated optical inspection (AOI) system) to automatically identify and measure the actual dimensions of each unit chip on the wafer and its relative position on the wafer, thereby generating unit chip size information and unit chip layout information.

[0049] The system matches and calculates the unit chip size information with the target chip size information to obtain unit chip combination information. The aim is to identify a set of unit chips that can be spliced ​​or combined into the target size from existing standard unit chips on the wafer, based on the expected size requirements of the wide-format inkjet-printed chip, using mathematical logic and optimization algorithms. For example, a two-dimensional arrangement algorithm can be used to decompose the target chip size into combinations of multiple unit chip sizes to minimize wafer waste or maximize utilization. Alternatively, a preset combination template library can be used for matching. This library stores various unit chip combination patterns and their corresponding total sizes. The system compares the target chip size with the templates in the library and selects the closest or most perfectly matching combination pattern.

[0050] Combining unit chip combination information and unit chip layout information, target partitioning region information is determined. This target partitioning region information represents an area on the wafer substrate that meets the target chip size information corresponding to the width requirement information. This area can contain at least two unit chips. The aim is to accurately delineate the area to be cut on the wafer after determining which unit chips need to be combined, using the actual physical location information of the unit chips on the wafer, in order to obtain the required target chip. This can be achieved by logically mapping unit chip combination information to unit chip layout information. For example, if the combination information specifies unit chips in a specific row and column on the wafer, then the target partitioning region information is a rectangular area enclosed by the outer boundaries of these unit chips. Alternatively, it can be determined interactively through a graphical interface. The system highlights the candidate unit chips on the wafer layout diagram based on the unit chip combination information, and the operator can manually adjust or confirm the boundaries of these unit chips and merge them into one or more contiguous areas.

[0051] Based on the target region information, scribing calculations are performed to generate slitting strategy information. This aims to generate specific cutting paths and parameters based on the determined target region, guiding the cutting equipment to accurately separate the target chip from the wafer. For example, CAD / CAM software can be used for automated scribing calculations. This software receives the geometric data of the target region and automatically generates slitting strategy information containing detailed information such as the cutting start point, end point, path coordinates, and cutting sequence according to preset cutting rules (such as cutting tool width, cutting speed, cutting depth, and cutting path optimization algorithms). Alternatively, scribing calculations can be performed using a rule-based expert system. This system has built-in various cutting scenarios and corresponding scribing rules, such as prioritizing cutting wafer edge areas, avoiding cutting critical circuits, and optimizing the cutting path to reduce cutting time. The system intelligently generates slitting strategy information based on the target region information and these rules.

[0052] This solution utilizes the size and layout information of unit chips as a computational benchmark to achieve the logical construction from micro-units to macro-target chips. First, by determining the size and layout of the unit chips on the wafer substrate, it provides fundamental data support for subsequent assembly, ensuring a high degree of consistency between the computational process and the actual physical substrate. Second, it performs matching calculations between the unit chip size and the target chip size. The core of this step lies in using mathematical logic to determine how to cover the target size through the arrangement and combination of multiple unit chips, thereby transforming the abstract size requirement into a concrete chip assembly scheme. Next, it combines the assembly information with the original layout information to determine the target partitioning region. This process clarifies the specific physical range for dicing on the wafer, avoiding resource waste caused by blind dicing. Finally, based on the determined partitioning region, it performs line calculations to generate a dicing strategy, ensuring the accuracy and rationality of the dicing path. Through this series of steps, this solution successfully transforms the size requirements of wide-format printing into executable wafer dicing instructions, enabling subsequent wafer substrate dicing to accurately obtain the target chip.

[0053] The following is a concrete example. Suppose we need to fabricate a 50mm wide inkjet-printed chip, while the existing unit chips on the wafer are 10mm x 10mm in size, with a 0.1mm scribing gap between them. First, the system determines the size of each unit chip to be 10mm x 10mm based on the wafer substrate information and records their precise layout coordinates on the wafer. Next, it matches the 50mm width of the target chip with the 10mm width of the unit chips to obtain the combination information of 5 unit chips arranged along the width direction. Then, combining the combination information of these 5 unit chips with their actual layout information on the wafer, the system determines a rectangular area containing these 5 unit chips and the scribing gaps between them as the target partitioning area. Finally, based on this target partitioning area information, the scribing calculation software generates a series of precise cutting instructions according to preset cutting parameters (such as tool width, cutting speed, etc.), forming slitting strategy information. These instructions can be directly imported into the wafer dicing equipment to guide it in cutting the wafer substrate, thereby obtaining the required wide inkjet-printed chip.

[0054] Through the above technical solution, this application successfully transforms the size requirements of wide-format printing into executable wafer dicing instructions, enabling the flexible customization of target chips that meet the wide-format printing requirements by recombining and dicing existing unit chips. This effectively solves the technical bottleneck of driver chip size limiting the size of a single ink cartridge, and improves wafer utilization and production efficiency.

[0055] In some of the solutions mentioned above in this application, a slicing strategy is proposed to cut the wafer substrate to obtain the target chip. However, after obtaining the target chip, how to transform the target chip into an inkjet printing chip with actual inkjet printing function, that is, how to effectively integrate the physically cut chip with the circuit logic and thermal spraying unit required for inkjet printing to achieve wide-format printing function, remains a key problem that needs to be solved.

[0056] In response, this application proposes a method for fabricating a wide-format inkjet-printed chip. After cutting the wafer substrate using dicing strategy information to obtain the target chip, the method further includes the following steps: Based on the width requirement information, determine the number of thermal spray units; Based on the number of thermal spray units, combined with the circuit array information and target chip size information corresponding to the target chip, thermal spray unit layout analysis is performed to obtain thermal spray unit circuit layout information; Based on the thermal spray unit circuit layout information, the target chip is fabricated using a thermal spray circuit to obtain an inkjet printed chip.

[0057] Specifically, when determining the number of thermal spray units based on the width requirement information, this step aims to calculate the total number of thermal spray units required by the inkjet printing chip according to the preset printing width requirement. In other words, the thermal spray unit number information represents the required number of thermal spray units corresponding to the width requirement information. A thermal spray unit refers to the unit structure in the inkjet printing control chip used to control thermal inkjet printing. For example, the total number of thermal spray units can be obtained by multiplying the required thermal spray unit density per unit length (e.g., per inch) by the actual width requirement information. Alternatively, the required number of thermal spray units can be derived by working backward from the required printing resolution and width requirement information, combined with the inkjet dot size of a single thermal spray unit.

[0058] When analyzing the thermal spray unit layout based on the number of thermal spray units, combined with the circuit array information and target chip size information, to obtain the thermal spray unit circuit layout information, the circuit array information can represent the circuit array contained in the wafer substrate, such as the pin layout array (as shown in the reference). Figure 3 In the middle, TSRA to TSRB, H1-H176), the drive circuit layout array (as shown in the reference). Figure 3 For details on the driving circuit, etc., please refer to [the relevant documentation]. Figure 3 The process involves TSRA to TSRB. This step is crucial for the effective integration of the thermal spray unit with the chip. Its purpose is to rationally arrange the required number of thermal spray units onto the physical space of the target chip and ensure effective electrical connections between them and the internal circuit array. For example, specialized computer-aided design (CAD) software can be used to import the 3D model of the thermal spray unit, the dimensional model of the target chip, and the layout information of the internal circuit array for virtual arrangement and connection path planning, thereby optimizing the arrangement density of the thermal spray unit and the circuit connection efficiency. Alternatively, a preset arrangement algorithm can automatically generate the precise coordinate positions of the thermal spray unit and its corresponding circuit connection points based on the number of thermal spray units, the effective area of ​​the target chip, and the distribution pattern of the circuit array.

[0059] When fabricating a thermal spray circuit on a target chip based on the thermal spray unit circuit layout information to obtain an inkjet-printed chip, this step involves actually manufacturing the thermal spray units and their driving circuits on the target chip according to the detailed layout information obtained from the previous analysis, thereby transforming the physical chip into a functional inkjet-printed chip. For example, mature semiconductor manufacturing processes, such as photolithography, etching, and thin film deposition, can be used to build the heating resistors, nozzle structures, and metal traces connecting to the circuit array of the thermal spray units layer by layer on the surface of the target chip. Alternatively, microelectromechanical systems (MEMS) processes, combined with precision assembly technology, can be used to precisely integrate the pre-fabricated thermal spray unit array onto the target chip and complete the electrical connections.

[0060] This application's solution achieves the transformation from a physical chip to a functional printed chip by introducing subsequent circuit integration and layout logic after physically cutting the target chip. First, the number of thermal spray units is determined based on the width requirement information, ensuring that the final inkjet printed chip's printing width meets design requirements. Then, this thermal spray unit number information is combined with the obtained physical characteristics of the target chip (target chip size information) and its internal circuit array information to perform a detailed thermal spray unit layout analysis. This analysis process is crucial; it goes beyond simply stacking thermal spray units on the chip, considering the physical location of the thermal spray units, the feasibility of their electrical connections to the chip's internal drive circuitry, and the overall layout efficiency and reliability. Through this analysis, detailed thermal spray unit circuit layout information is obtained, including the precise location of each thermal spray unit and its connection method to the chip's internal circuitry. Finally, based on this precise thermal spray unit circuit layout information, the actual thermal spray circuit is fabricated on the target chip, including the heating elements forming the thermal spray units, the nozzle structure, and the wires connecting these units to the chip's internal drive circuitry. Through the above steps, the solution of this application effectively transforms a target chip obtained through physical cutting into an inkjet printing chip with complete inkjet printing capabilities. This method cleverly combines front-end chip cutting with back-end circuit integration and functional implementation, ensuring consistency and feasibility from width requirements to the final product's functionality. It solves the technical challenge of how to efficiently and accurately integrate the thermal spraying unit with the chip's internal circuitry after obtaining the target chip, thereby achieving wide-format printing functionality.

[0061] The following is a concrete example. Assume that after obtaining the required print width, the desired print width is determined to be 2 inches. First, based on this width requirement, the number of thermal spray units is determined. For example, if 176 thermal spray units are needed per inch, the calculated number of thermal spray units is 352. Next, based on this number of thermal spray units, combined with the circuit array information and target chip size information, a thermal spray unit layout analysis is performed to obtain the thermal spray unit circuit layout information. For example, the target chip is 250mm long and 10mm wide, and has a specific area reserved for drive circuits and pin distribution inside. At this point, professional CAD software can be used to import the model of the 352 thermal spray units and perform a virtual layout based on the target chip size and circuit array layout. For example, an interleaved layout can be used to improve print density and optimize droplet ejection uniformity. Simultaneously, the connection path between each thermal spray unit and the nearest drive circuit unit in the circuit array is analyzed to ensure the integrity and low loss of electrical signal transmission. The final generated thermal spray unit circuit layout information may include the XY coordinates of each thermal spray unit, its corresponding driver circuit unit ID, and the geometry and hierarchy of the connecting traces. Finally, based on this thermal spray unit circuit layout information, thermal spray circuitry is fabricated on the target chip to obtain an inkjet-printed chip. For example, by importing the above layout information into a semiconductor manufacturing device, firstly, a heating resistance layer for the thermal spray unit is formed on the surface of the target chip using photolithography and etching processes. Then, a nozzle structure and ink cavity are formed through thin film deposition and etching. Next, metallization processes are used to fabricate metal traces and pins connecting the thermal spray unit to the internal driver circuitry of the chip, based on the layout information. Finally, passivation and encapsulation are performed to obtain an inkjet-printed chip with complete inkjet printing functionality.

[0062] Through the above technical solutions, this application achieves an effective transformation from a physical chip to a functional inkjet printing chip, ensuring that the printing width of the inkjet printing chip is highly consistent with actual needs, and avoiding insufficient or redundant printing width due to chip size limitations. Simultaneously, through meticulous analysis of the thermal spray unit layout, the problem of precise matching between the thermal spray units and the drive circuit on wide-format chips is solved, improving the integration density of the thermal spray units and the reliability of circuit connections. Ultimately, this integration method provides a solid technical foundation for achieving wide-format, high-performance inkjet printing, effectively overcoming the problem of limited printhead size in individual ink cartridges in traditional solutions, thereby avoiding complex mechanical splicing structures and improving the overall performance and stability of the printing system.

[0063] In some of the solutions mentioned above in this application, a method is proposed to obtain a slitting strategy by performing scribing calculations based on the target chip size information and wafer substrate information, thereby realizing the fabrication of wide-width inkjet printed chips. However, after determining the slitting strategy and completing the chip cutting, how to effectively integrate the dispersed unit chips with the thermal spraying unit, and ensure that the thermal spraying unit achieves accurate circuit layout and interconnection on the target chip to meet the circuit driving requirements of wide-width printing, remains a key challenge in realizing the design of large-size driver chips.

[0064] In response, this application further proposes to perform thermal spray unit layout analysis based on the number of thermal spray units, combined with the circuit array information and target chip size information corresponding to the target chip, to obtain thermal spray unit circuit layout information. This analysis includes: performing thermal spray unit position layout analysis based on the number of thermal spray units and the target chip size information to obtain thermal spray unit position information; performing circuit matching analysis based on the thermal spray unit position information and the circuit array information to determine the circuit connection method information; and generating thermal spray unit circuit layout information based on the thermal spray unit position information and the circuit connection method information.

[0065] This process involves analyzing the placement of thermal spray units based on their number and target chip size. The goal is to determine the physical layout of these units on the target chip. This analysis can be implemented in various ways. For example, it can be done using a pre-defined layout template. Based on the number of thermal spray units and the target chip size, a uniform distribution or a concentrated layout in a specific area can be selected to calculate the center coordinates of each thermal spray unit. Alternatively, optimization algorithms can be used, such as greedy or genetic algorithms, to find the optimal thermal spray unit placement while satisfying the constraints of the number of thermal spray units and the target chip size, thereby maximizing print coverage or minimizing trace length.

[0066] Based on the location information of the thermal spraying units and the circuit array information, circuit matching analysis is performed to determine the circuit connection method information. This aims to establish the electrical connection relationship between the thermal spraying units and the internal circuit array of the target chip. Since the circuit array information is the circuitry inherent in the unit chip, and the number of thermal spraying units is determined according to requirements, the thermal spraying units can be connected in different ways depending on the needs. For example, a 2-inch target chip composed of four unit chips contains 354 related control circuits, but only 300 thermal spraying units are required. In this case, the 300 thermal spraying units can be selectively connected to 300 of the 354 related control circuits. That is, the circuit connection method information can represent the specific connection method between the thermal spraying units and the circuit array. This matching analysis can be based on lookup tables or predefined rules. For example, based on the physical location of the thermal spraying unit, it can be mapped to the nearest or preset drive port in the circuit array to determine its connection path. Alternatively, matching analysis can be performed using routing algorithms, such as maze algorithms or A* algorithms, to find the optimal circuit connection path for each thermal spraying unit while considering the wiring resources and signal integrity requirements of the circuit array.

[0067] Based on the location information and circuit connection information of the thermal spraying units, the circuit layout information of the thermal spraying units is generated. This aims to integrate the physical location and electrical connection logic of the thermal spraying units to form a complete circuit layout scheme. This generation process can be achieved through data integration and formatting. For example, the coordinate data of the thermal spraying units, corresponding circuit port numbers, connection paths, and other information can be stored and output using specific data structures (such as CAD file formats or text description files). Alternatively, it can be generated through graphical interface tools. For instance, in design software, based on the input location and connection method of the thermal spraying units, the circuit layout diagram can be automatically drawn, and the corresponding manufacturing documents can be generated.

[0068] This application's solution, through a hierarchical and progressive logic, achieves a precise mapping from macroscopic requirements to microscopic circuit layout, solving the problem of complex and difficult-to-unify control of circuit connections after multi-unit chip splicing. First, by analyzing the positional arrangement based on the number of thermal spray units and the target chip size, the specific spatial coordinates of the thermal spray units on the chip can be determined. This size-constrained arrangement ensures that the thermal spray units can cover the effective printing area of ​​the target chip, providing a physical basis for subsequent circuit connections. Second, after obtaining the thermal spray unit position information, circuit matching analysis is performed in conjunction with circuit array information to determine the circuit connection method in a targeted manner. The unique feature of this matching analysis is that it is not blind wiring, but rather dynamically adjusts the connection path of the circuit array according to the actual position of the thermal spray units on the chip, thereby ensuring that each thermal spray unit can be accurately addressed and driven. Finally, based on the position information and connection method, thermal spray unit circuit layout information is generated, organically combining physical location with electrical connection logic. This approach enables the construction of a complete and efficient circuit network even in the complex structure of multi-unit chip splicing, ensuring the synchronization and stability of inkjet control during wide-format printing and effectively overcoming the circuit design and wiring challenges brought about by the increase in chip size. The detailed analysis of the thermal spray unit layout described above provides precise guidance for subsequent thermal spray circuit fabrication, ensuring that the target chip can effectively integrate the thermal spray unit and achieve wide-format printing functionality.

[0069] The following is a specific example. As a concrete implementation, when analyzing the placement of thermal spray units, the target chip size can be set to 50mm x 10mm, requiring 2000 thermal spray units. The system can arrange these 2000 thermal spray units evenly along the long side of the target chip according to preset placement rules, and set a fixed row spacing along the short side. For example, the thermal spray units can be divided into 4 rows of 500 units each, and the precise center coordinates of each thermal spray unit can be calculated. When performing circuit matching analysis, it is assumed that the target chip's circuit array uses matrix addressing, with 64 row select signal pins and 32 column select signal pins. For each determined thermal spray unit position, the system can map it to a specific row and column in the circuit array based on its relative coordinates on the target chip, thereby determining its corresponding row select signal pins and column select signal pins, and thus determining its wiring method. For example, a thermal spray unit located in the i-th row and j-th column is connected to the i-th row select signal pin and the j-th column select signal pin. Finally, when generating the thermal spray unit circuit layout information, the system integrates the physical coordinates of each thermal spray unit, the corresponding row selection signal pin number, column selection signal pin number, and the specific wiring path (e.g., the wiring layer and trace geometry information from the thermal spray unit to the pin) to generate a database file or graphic design file containing all this information, such as a GDSII format file, for subsequent mask fabrication and thermal spray circuit fabrication.

[0070] Through the above technical solution, this application can achieve precise arrangement and circuit connection of thermal spray units in wide-format inkjet printing chips, effectively solving the complex wiring and unified control problems faced when integrating thermal spray units with circuit arrays after splicing multiple unit chips. This refined arrangement analysis and circuit matching mechanism ensures that each thermal spray unit can be accurately addressed and driven, thereby guaranteeing the printing accuracy and stability of wide-format inkjet printing chips. In addition, this solution also significantly improves the flexibility and scalability of wide-format inkjet printing chip design, enabling the flexible implementation of single-cartridge driver chip designs of any size without changing the existing driver chip production conditions, thereby overcoming the size limitations of traditional cartridge driver chips and providing key technical support for achieving wide-format inkjet printing exceeding 1 inch in a single print.

[0071] In the manufacturing process of traditional wide-format inkjet printing chips, due to the physical gaps, i.e., scribe lines, between the unit chips, if the thermal spraying units are simply arranged on the chip body, inkjet blind spots will appear in the scribe line area, making it impossible to achieve continuous inkjet printing across the scribe lines and wasting scribe line space.

[0072] To address this, this application further proposes to analyze the positional arrangement of thermal spray units based on the number of thermal spray units and the target chip size information to obtain thermal spray unit positional information. This analysis includes: determining the chip body size information and the scribing groove size information based on the target chip size information, wherein the scribing groove size information is used to represent the size of the scribing grooves between unit chips; performing thermal spray unit positional arrangement analysis based on the chip body size information and the scribing groove size information to determine first positional information corresponding to the chip body size information and second positional information corresponding to the scribing groove size information, wherein the first positional information represents the positional information of the thermal spray units arranged at the chip body position, and the second positional information represents the positional information of the thermal spray units arranged at the scribing groove position; and generating thermal spray unit positional information based on the first and second positional information.

[0073] Specifically, target chip size information refers to the overall geometric dimensions of the final wide-format inkjet-printed chip, including its length, width, and other macroscopic parameters. Its purpose is to provide the overall physical boundaries and reference basis for subsequent chip structure disassembly and thermal spray unit arrangement. This can be achieved through design drawings, computer-aided design (CAD) model data, or preset specifications. Another approach is to obtain precise physical dimension data by performing optical measurements or electronic scanning on the diced wafer substrate. Chip body size information refers to the actual usable area of ​​each unit chip constituting the target chip, i.e., the size after removing the scribing groove area. Its purpose is to clarify the effective area on each unit chip that can be used to arrange the thermal spray units. This can be calculated by subtracting the scribing groove size information from the target chip size information, or directly obtained from the unit chip design specifications. Another approach is to predefine the effective working area size of each unit chip during the chip design phase and store and retrieve it as chip body size information. The scribing groove size information refers to the size of the physical gaps used for cutting and separating individual unit chips in the target chip. In other words, the scribing groove size information represents the size of the scribing grooves between unit chips. Its function is to accurately define the geometric parameters of these gaps so that thermal spraying units can be arranged in these areas subsequently. In traditional techniques, the scribing grooves are waste areas that are cut. However, since this invention cuts multiple unit chips as a whole, the scribing groove area can also be configured with thermal spraying units, thus ensuring the continuity of the thermal spraying unit distribution. Furthermore, compared to the subsequent splicing operations of traditional methods, this invention directly obtains a whole target chip containing multiple unit chips on the wafer substrate. Its flatness and alignment are at the wafer level, solving the problem of low flatness and alignment that occurs in the later splicing of traditional methods.

[0074] Determining the chip's main dimensions and the dimensions of the scribe lines can be achieved by obtaining parameters such as the width and depth of the scribe lines as defined in the chip manufacturing process specifications. Alternatively, a high-precision measuring device can be used to scan the actually diced wafer substrate to obtain the actual width and position information of the scribe lines.

[0075] Thermal spray unit placement analysis refers to planning the specific spatial coordinates and layout of the thermal spray units on the entire target chip based on the dimensions of the chip body and the scribe lines. Its purpose is to ensure that the thermal spray units can continuously and uniformly cover the entire print width, including the traditionally ignored scribe line area. This can be achieved through computer-aided design (CAD) software combined with preset placement algorithms (e.g., equal-spacing, matrix placement, etc.) for simulation calculations. Another approach is to use specialized layout optimization software, inputting chip geometry parameters and thermal spray unit specifications, to automatically generate the optimal placement scheme. The primary positional information refers to the specific placement of the thermal spray units within the main body area of ​​each unit chip. Its purpose is to define the traditional layout of the thermal spray units, ensuring the printing function within the unit chip. One approach is to divide the main body area of ​​the unit chip into several grids and place the thermal spray units at specific grid centers or edges. Another approach is to arrange the thermal spray units at equal or staggered intervals within the main body area of ​​the chip, based on their size and number, and record the coordinates of each thermal spray unit. The second positional information refers to the specific arrangement of the thermal spray units within the scribe groove area between unit chips. Its function is to innovatively utilize the scribe groove space, eliminate printing blind spots, and achieve continuous wide-width printing. One implementation method is to treat the scribe groove area as an independent arrangement space and arrange one or more thermal spray units within it according to the width of the scribe groove and the size of the thermal spray units. Another implementation method is to arrange the thermal spray units along the center line or both sides of the scribe groove at the same spacing as or at a specific spacing to the thermal spray units in the main chip area, and record their coordinates. Generating thermal spray unit positional information involves integrating the first positional information of the main chip area and the second positional information of the scribe groove area to form a complete thermal spray unit layout diagram or coordinate dataset covering the entire target chip. Its function is to provide a unified and comprehensive thermal spray unit arrangement scheme to guide subsequent thermal spray circuit fabrication. This can be achieved by merging the two sets of positional data into a single data structure, such as a two-dimensional array or list, containing the X and Y coordinates of each thermal spray unit. Another approach is to convert this location information into graphic data files, such as the GDSII format, that can be used for photomask fabrication, so that it can be directly used in chip manufacturing.

[0076] This solution first determines the chip's main body dimensions and scriber groove dimensions through a refined breakdown of the target chip's size information. This step is fundamental to achieving precise layout, clarifying the overall geometric parameters of the target chip and subdividing it into an effective main body area suitable for inkjet printing and a traditionally neglected scriber groove area, ensuring that subsequent calculations cover the entire physical space of the chip. Based on this, and using the determined chip main body and scriber groove dimensions, a thermal spray unit placement analysis is performed. This analysis aims to determine the first position information corresponding to the chip main body dimensions and the second position information corresponding to the scriber groove dimensions. The ingenuity of this differentiated processing method lies in extending the thermal spray unit placement logic from a single chip main body area to the entire area including the scriber groove. The first position information is responsible for planning the thermal spray unit layout on the chip main body, ensuring the printing function of the core chip area. The second position information specifically plans the position for the scriber groove area, breaking the limitations of traditional spliced ​​chips where scriber groove space is wasted and printheads cannot be placed, allowing the scriber groove area to effectively accommodate thermal spray units. Finally, the first and second position information are integrated to generate the final thermal spray unit position information. This integration step ensures that the thermal spray units can be continuously and uniformly distributed across the entire wide-format chip, effectively solving the problems of wasted scribing space caused by physical cutting and the inability to fabricate wide-format chips at the chip level. In this way, this solution provides spatial layout technical support for continuous printing of large-size single-cartridge driver chips, making it possible to flexibly design single-cartridge driver chips of any size without changing existing driver chip production conditions through die design, thus solving the problem of driver chips limiting the size of single-cartridge chips.

[0077] As a specific implementation method, after obtaining the target chip size information, the chip body size information can first be determined by reading a preset chip design parameter file. For example, if the target chip is composed of two 10mm x 10mm unit chips spliced ​​together, and a 0.1mm wide scribe groove is reserved between each unit chip, then the chip body size information is 10mm x 10mm, and the scribe groove size information is 0.1mm wide. Subsequently, when performing thermal spray unit position layout analysis, the following method can be used: For the first position information corresponding to the chip body size information, the precise coordinates of each thermal spray unit inside the unit chip can be calculated based on the effective printing area of ​​each unit chip, according to a preset nozzle density and arrangement method (e.g., staggered arrangement or linear arrangement). For example, 1000 thermal spray units can be evenly arranged on a 10mm x 10mm unit chip body, and their X and Y coordinates can be recorded. For the second position information corresponding to the scribe groove size information, the thermal spraying units can be arranged along the center line or both sides of the scribe groove at the same spacing or a specific spacing as the thermal spraying units in the chip body area, based on the width of the scribe groove and the size of the thermal spraying units. For example, if the scribe groove width is 0.1mm and the thermal spraying unit width is 0.05mm, one thermal spraying unit can be arranged at the center line of the scribe groove, or one thermal spraying unit can be arranged on each side of the scribe groove, and their coordinates can be recorded. Finally, the coordinate data of all thermal spraying units calculated in the chip body area and the scribe groove area are merged to generate a complete position list or layout diagram containing all thermal spraying units. This list or layout diagram is the thermal spraying unit position information, which can be directly used for subsequent photolithography mask fabrication and thermal spraying circuit fabrication.

[0078] Through the above technical solution, this application enables a refined disassembly of the physical structure of a wide-format inkjet printing chip, achieving seamless integration between the main body area and the scriber groove area of ​​the target chip. By clearly defining the chip body size and scriber groove size, a comprehensive geometric parameter basis is provided for the precise arrangement of the thermal spraying units. Furthermore, by determining the first position information corresponding to the chip body and the second position information corresponding to the scriber groove, this solution innovatively extends the arrangement range of the thermal spraying units to the traditionally neglected scriber groove area. This approach effectively breaks the limitations of traditional spliced ​​chips where scriber groove space is wasted and printheads cannot be arranged, eliminating inkjet blind spots caused by physical cutting, and ensuring that the thermal spraying units can be continuously and uniformly distributed across the entire wide-format chip. This not only improves the chip's space utilization but also fundamentally solves the problem of not being able to fabricate wide-format chips at the chip level, providing key spatial layout technology support for achieving continuous and seamless printing of large-size single-cartridge drive chips, thereby effectively improving the overall performance and reliability of wide-format inkjet printing.

[0079] In some of the embodiments described above in this application, circuit matching analysis is proposed to determine the circuit connection method by combining the position information of the thermal spray unit with the circuit array information. However, in the process of combining multiple unit chips and scribing slot areas to achieve wide-width printing, how to accurately allocate the row selection signal and column selection signal to each thermal spray unit to ensure efficient and accurate circuit connection under complex chip layout is still a technical challenge that needs to be solved.

[0080] To address this, this application further proposes a method for determining circuit connection information by performing circuit matching analysis based on the location information of the thermal spray unit and the circuit array information. This process includes: determining the row selection signal pins and column selection signal pins based on the circuit array information; performing row selection signal circuit matching analysis of the thermal spray unit based on the location information of the thermal spray unit and the row selection signal pins to obtain row selection signal connection information; performing column selection signal circuit matching analysis of the thermal spray unit based on the location information of the thermal spray unit and the column selection signal pins to obtain column selection signal connection information; and generating circuit connection information based on the row selection signal connection information and the column selection signal connection information.

[0081] The circuit array information refers to the structural and functional layout of electrical components on the chip, including the arrangement of transistors, resistors, capacitors, and interconnects that form the driving logic for the thermal spray unit. This information provides a blueprint for how electrical signals are routed and processed. This circuit array information can be obtained from the chip's design specifications (e.g., GDSII files, schematics, netlists) or from a predefined library of circuit modules. Row select signal pins and column select signal pins are specific electrical terminals or connection points in the circuit array used to transmit row select signals and column select signals, for example... Figure 2-3 In the diagram, A1-A22 represent row select signal pins, and P1-P8 represent column select signal pins. In matrix addressing systems such as inkjet printheads, these pins are crucial for individually addressing and activating specific thermal spray units. These pins can be identified by their physical location on the chip layout, their logical function in the circuit design, or specific tags / identifiers in the circuit array information. For example, they could be output pins of the row and column decoders, or dedicated input / output pads on the chip periphery.

[0082] Thermal spray cell location information describes the precise physical coordinates or relative position of each thermal spray cell on the target chip. This information is crucial for understanding how to physically connect each cell to the driver circuitry. This information can be obtained from the thermal spray cell layout design, coordinate mapping table, or geometric description file. It can be represented as a set of (x, y) coordinates for each cell or a grid-based index. Row select signal circuit matching analysis determines the optimal electrical connection between the identified row select signal pins and the thermal spray cells based on their respective locations. The goal is to ensure that each thermal spray cell can be correctly addressed via row signals. This analysis can involve algorithms that calculate the shortest path between row select pins and a group of thermal spray cells, or algorithms that optimize signal integrity, power distribution, or routing density. It can use graph theory or geometric algorithms to map physical locations to logical connections. Row select signal wiring information is the output of the row select signal circuit matching analysis, detailing how row select signals are physically routed and connected to the thermal spray cells. It specifies which row select pin is connected to which thermal spray cell or group of cells. This information can be represented as a netlist, routing plan, or a set of connection rules. For example, it can specify "row select pin A is connected to thermal spray unit 1, thermal spray unit 2, etc.", or provide the coordinates of the wiring trace.

[0083] Column select signal circuit matching analysis is similar to row select signal analysis, focusing on establishing electrical connections between column select signal pins and thermal spray cells. It ensures that each thermal spray cell can be correctly addressed via the column signal. This analysis can employ algorithms similar to those used in row select signal analysis, but applied to the column dimension. It may involve optimizing parallel data transmission or minimizing signal delay across columns. Column select signal wiring information is the output of column select signal circuit matching analysis, detailing how the column select signals are physically routed and connected to the thermal spray cells. Similar to row select signals, this can be a netlist, routing plan, or connection rule specifying "column select pin X connects to thermal spray cell A, thermal spray cell B, etc." Circuit wiring information is a comprehensive set of instructions or data defining all the electrical connections required to drive the thermal spray cells, combining row and column select signal routing. It represents a complete wiring diagram of the thermal spray cells on the chip. This information can be a complete netlist of the entire thermal spray cell array, a layout design file (e.g., GDSII), or a set of manufacturing instructions for interconnect fabrication. It can also be a hierarchical description where individual cell connections are aggregated into a global routing plan.

[0084] This application's solution achieves effective management of complex circuit layouts in wide-format printed chips through refined disassembly and matching of the circuit array. First, by determining row and column selection signal pins based on the circuit array information, the foundation for subsequent circuit wiring is laid, ensuring the clarity of the signal source. Second, by matching and analyzing the thermal spray unit position information with the row and column selection signal pins respectively, targeted row and column selection signal connection method information can be generated. This step-by-step matching method can accurately address situations where the thermal spray units are unevenly distributed or have complex layouts within the unit chip and scriber area, ensuring that each thermal spray unit receives the correct drive signal. Finally, by integrating the row and column selection connection information, the final circuit connection is generated. This achieves logical mapping and physical connection of the internal circuitry of the large-size chip after die assembly, without altering existing production conditions. This effectively solves the problems of complex circuit connections and difficult signal transmission path planning after multi-chip splicing, ensuring the synergy and stability of the wide-format printed chip during overall operation. Furthermore, it allows for adaptive determination of the connection methods for row and column selection signal pins based on specific application scenarios and requirements, improving flexibility. Combining this method with the aforementioned wide-format inkjet printed chip fabrication method, after the target chip is cut from the wafer substrate, precise circuit fabrication can be performed for the thermal spray units on the target chip. This enables the wide-format inkjet printed chip, composed of multiple unit chips, to work collaboratively as a whole, achieving wide-format printing functionality.

[0085] The following is a concrete example. Assume the target chip is composed of two unit chips arranged side-by-side. Circuit array information might indicate that row select signals are driven by the decoder module on the left side of the combined chip, while column select signals are driven by the bottom multiplexer module. Row select signal pins could be A1, A2, ..., An, and column select signal pins could be P1, P2, ..., Pm. The thermal spray unit location information would be a list of (x, y) coordinates for each thermal spray unit, including those located in the scribe lines between the two unit chips. For row select signal circuit matching, an algorithm can be used to group the thermal spray units according to their y-coordinate (row) and assign them to the nearest available row select signal pin, or assign them to specific row signals according to a predefined addressing scheme. For example, all thermal spray units in a specific horizontal band could be connected to R1. Similarly, for column select signal circuit matching, thermal spray units can be grouped according to their x-coordinate (column) and assigned to column select signal pins. For example, the thermal spray units in the first vertical segment could be connected to C1, the next segment to C2, and so on. The final row select signal wiring information will be specified, for example, "A1 is connected to the thermal spray unit at (x1, y1), (x2, y1), etc." The column select signal wiring information will specify "P1 is connected to the thermal spray unit at (x1, y1), (x1, y2), etc." Finally, these two sets of information are combined to create complete circuit wiring information, which can be a GDSII file used for photolithography, defining all metal traces connecting the row / column drivers to each individual thermal spray unit.

[0086] The above technical solution effectively solves the technical challenge of accurately allocating row and column selection signals to achieve efficient and accurate circuit connectivity in wide-format inkjet printing chips, especially when multiple unit chips are combined and thermal spray units are continuously arranged in the unit chip and scriber area. This solution, through refined analysis of the circuit array and matching of thermal spray unit position information, ensures that each thermal spray unit receives the correct drive signal, thereby guaranteeing the overall functionality and stability of the wide-format inkjet printing chip under complex layouts. This enables flexible design of single-cartridge driver chips with arbitrary size requirements without changing existing production conditions, effectively overcoming the limitation of single-cartridge printhead size and providing a reliable circuit connection solution for achieving wide-format printing exceeding 1 inch in a single print.

[0087] Firstly, this application provides a wide-format inkjet printing chip, the technical solution of which is as follows: A wide-format inkjet printing chip includes a target chip 1 and a thermal spray unit 2 electrically connected to the target chip 1; the target chip 1 includes at least two unit chips 10, wherein a scribing groove 3 is reserved between each unit chip 10; the thermal spray unit 2 is used to perform inkjet printing according to the control of the target chip 1, and the thermal spray unit 2 is continuously arranged between each unit chip 10 and the scribing groove 3.

[0088] It should be noted that since the scribing groove 3 is the area on the wafer substrate used to separate each unit chip 10, the unit chips 10 in this embodiment retain the scribing groove 3, indicating that the target chip 1 in this embodiment is a chip body obtained by simultaneously cutting at least two adjacent unit chips 10 on the wafer substrate; for example Figure 4 As shown, the wafer substrate contains multiple unit chips 10 (DIEs), and the multiple unit chips 10 are divided into target chips 1 according to requirements.

[0089] As can be seen, this embodiment combines multiple unit chips 10 while retaining the scribing grooves 3, and continuously arranges the thermal spraying units 2 between each unit chip 10 and the scribing grooves 3, thereby overcoming the physical size limitations of a single-chip driver. Specifically, the target chip 1 is composed of at least two unit chips 10, and the scribing grooves 3 retained between each unit chip 10 are inherent cutting areas in the semiconductor manufacturing process, which originally belong to functional waste areas. By continuously arranging the thermal spraying units 2 across the unit chips 10 and the scribing grooves 3, not only is the space resource of the scribing groove area effectively utilized, but it also ensures that the print head forms a continuous and seamless inkjet coverage path across the entire width of the target chip 1, avoiding inkjet breaks caused by physical segmentation.

[0090] In traditional techniques, the scribing groove 3 is the waste area to be cut. However, since this embodiment cuts multiple unit chips 10 as a whole, the scribing groove 3 area can also be configured with thermal spraying units 2, thereby achieving the function of continuous distribution of thermal spraying units 2. Moreover, compared with the subsequent splicing operation of traditional methods, the present invention directly obtains a whole target chip 1 containing multiple unit chips 10 on the wafer substrate. Its flatness and alignment are at the wafer level, solving the problem of low flatness and alignment in the later splicing of traditional methods.

[0091] Based on this, the solution of this application achieves flexible size expansion without changing the existing driver chip manufacturing process by modularly combining the unit chip 10 and continuously arranging the thermal spray unit 2 across regions. Since the thermal spray unit 2 maintains a continuous layout between the unit chip 10 and the scribing groove 3, there is no need to rely on external mechanical structures for multi-nozzle alignment during the printing process, which fundamentally eliminates the cumulative error caused by the independent packaging of the unit chip 10 in the traditional splicing method, thereby ensuring the horizontal consistency and edge smoothness of the printed area.

[0092] Furthermore, this application also proposes that the target chip 1 has at least two unit chips 10 arranged in a first direction, and a first pin layer 11, a driving circuit layer 12 and a second pin layer 13 arranged sequentially in a second direction; wherein, the first end of the first pin layer 11 is electrically connected to an external control device, the second end of the first pin layer 11 is electrically connected to the first end of the driving circuit layer 12, the second end of the driving circuit layer 12 is electrically connected to the first end of the second pin layer 13, and the second end of the second pin layer 13 is electrically connected to the control end of the thermal spray unit 2.

[0093] Specifically, the target chip 1 has at least two unit chips 10 arranged in a first direction, where the first direction can represent the printing width direction. The aim is to combine multiple smaller unit chips 10 into a large chip that meets the requirements of wide-width printing through physical splicing. This arrangement can be a linear arrangement of multiple unit chips 10 along the horizontal direction to expand the printing width, or a matrix arrangement along both the horizontal and vertical directions to accommodate more complex wide-width requirements. This design is the foundation for achieving wide-width printing, overcoming the inherent limitations of a single chip size. In a second direction, a first pin layer 11, a driving circuit layer 12, and a second pin layer 13 are arranged sequentially. Here, the second direction typically refers to the chip's thickness direction. In specific implementation scenarios, the above layer distribution can be adaptively adjusted according to requirements. For example, the first pin layer 11 and the second pin layer 13 can be considered as the same top layer, in which case the driving circuit layer 12 can be distributed in a multi-layer structure in the second direction to form a multi-layer circuit structure. This embodiment does not specifically limit this. This stacked layout is an efficient circuit integration method used to implement complex signal input, processing, and output functions within a limited chip area. It can be built inside the chip using multilayer metal wiring technology, or vertically integrated with different functional chip layers using three-dimensional stacking technology. The first end of the first pin layer 11 is electrically connected to an external control device. This first pin layer 11 serves as the interface between the chip and an external control system (e.g., a printer main control board), and its first end is responsible for receiving control signals and data from the outside. This connection can be achieved using traditional gold wire bonding technology, connecting the chip pads to external package pins or a flexible circuit board, or it can be directly connected to an external substrate using flip-chip technology. The second end of the first pin layer 11 is electrically connected to the first end of the drive circuit layer 12. This connection ensures that externally input control signals can be accurately transmitted to the drive circuit layer 12 inside the chip for subsequent processing. This internal connection is typically achieved through internal metal interconnects or vertical vias. The second end of the drive circuit layer 12 is electrically connected to the first end of the second pin layer 13. The drive circuit layer 12 is the core processing unit of the chip, responsible for logically processing, amplifying, and shaping the received signals to generate the precise electrical signals required to drive the thermal spray unit 2. Its second end outputs the processed drive signal to the second pin layer 13. This connection can also be achieved through internal metal interconnects or microbumps. The second end of the second pin layer 13 is electrically connected to the control terminal of the thermal spray unit 2. The second pin layer 13 acts as a bridge between the drive circuit layer 12 and the thermal spray unit 2, and its second end distributes and transmits the final drive signal to each thermal spray unit 2, enabling it to perform inkjet operation according to the control signal. This connection is typically achieved by directly connecting to the electrodes of the thermal spray unit 2 via fine metal traces.

[0094] The present application constructs the physical foundation required for wide-format printing by physically splicing at least two unit chips 10 in a first direction. Based on this, a first pin layer 11, a driving circuit layer 12, and a second pin layer 13 are sequentially arranged in a second direction, forming a layered and efficient electrical signal transmission and processing architecture. Control signals from an external control device first enter the chip through the first terminal of the first pin layer 11 and are then transmitted to the first terminal of the driving circuit layer 12 via its second terminal. Upon receiving the signals, the driving circuit layer 12 performs necessary logic processing and power amplification to generate the precise signals required to drive the thermal spray unit 2. Subsequently, these driving signals are output from the second terminal of the driving circuit layer 12 and transmitted to the first terminal of the second pin layer 13. Finally, the second pin layer 13 precisely distributes and transmits the driving signals to the thermal spray units 2 distributed on each unit chip 10 and the scribing groove 3 via its second terminal, thereby achieving precise control of the thermal spray unit 2. This hierarchical circuit layout not only effectively manages the complex signal routing issues after multiple unit chips 10 are spliced ​​together, but also reduces signal attenuation and interference during long-distance transmission by shortening the signal transmission path, ensuring that each thermal spray unit 2 can obtain synchronous and stable drive control during wide-format printing. Combined with the characteristics of the target chip 1 in the aforementioned wide-format inkjet printing chip, which contains at least two unit chips 10, and the thermal spray units 2 being continuously arranged between each unit chip 10 and the scribing slot 3, this hierarchical circuit architecture can efficiently support the driving of a continuous array of thermal spray units 2 across unit chips 10 and scribing slots 3, solving the wide-format printing problem caused by chip size limitations and signal transmission complexity in traditional solutions.

[0095] Furthermore, this application also proposes that the first pin layer 11 be electrically connected between adjacent unit chips 10.

[0096] Specifically, the unit chip 10 refers to an independent chip module constituting the target chip 1. In the fabrication of wide-format inkjet printed chips, to achieve large-size printing, multiple smaller unit chips 10 are usually spliced ​​together in a die-like manner to form a larger target chip 1. These unit chips 10 are functionally independent but need to work together. The unit chip 10 can be a pre-manufactured independent chip with complete driving circuitry and part of the inkjet unit interface, or it can be a bare chip obtained after wafer dicing that is not yet fully packaged. The first pin layer 11 is one of the layers sequentially arranged in the second direction of the target chip 1. Its first end is electrically connected to an external control device, and its second end is electrically connected to the first end of the driving circuit layer 12. It is mainly responsible for receiving signals from the external control device and transmitting these signals to the driving circuit layer 12. The first pin layer 11 can be a metal wiring layer, such as conductive materials like copper or aluminum, formed by semiconductor processes such as photolithography and etching; or, the first pin layer 11 can also be conductive traces on a flexible printed circuit board (FPC) or a multilayer ceramic substrate (LTCC) for connecting the internal circuitry of the chip with the external interface. The electrical connection refers to connecting two or more circuit points or components through conductive materials or structures to achieve the transmission of electrical signals. The electrical connection can be achieved by connecting corresponding pads on the first pin layer 11 of adjacent unit chips 10 through bonding wires; or by directly connecting the first pin layers 11 of adjacent unit chips 10 using solder bumps through flip-chip technology; or by setting bridging circuits or interconnection structures between unit chips 10, such as flexible connectors or wiring on intermediate substrates.

[0097] The solution in this application ensures that control signals from an external control device can be smoothly transmitted from one unit chip 10 to the next by electrically connecting the first pin layer 11 between adjacent unit chips 10. In the aforementioned wide-format inkjet printing chip, the target chip 1 consists of at least two unit chips 10, and a first pin layer 11, a drive circuit layer 12, and a second pin layer 13 are sequentially arranged in the second direction. The first pin layer 11 serves as the signal transmission hub between the external control device and the internal drive circuit, and its continuity is crucial for the unified driving of the entire wide-format inkjet printing chip. By establishing an electrical connection of the first pin layer 11 between physically spliced ​​unit chips 10, the drive signal can be transmitted across multiple unit chips 10, thereby logically integrating multiple independent unit chips 10 into a unified driving unit. This design not only solves the signal discontinuity problem caused by multi-chip splicing, but also ensures, through physical interconnection, that the drive signals of each region of the entire wide-format printing chip can maintain a high degree of consistency and synchronization during inkjet control, providing the necessary circuit foundation for achieving large-size, high-precision single printing.

[0098] Furthermore, this application also proposes a second pin layer, wherein the first end face of the target chip 1 extends to the second end face.

[0099] The second pin layer 13 is a key conductive layer in the wide-width inkjet printed chip. Its main function is to receive control signals from the driving circuit layer 12 and effectively transmit these signals to the control terminal of the thermal spray unit 2 to achieve precise control of the thermal spray unit 2. This layer is usually made of conductive materials (such as copper, aluminum, etc.) through semiconductor processes such as photolithography and etching. Its layout and design directly affect the integrity, speed, and coverage of signal transmission. One implementation method is to use a specific metal layer in a multilayer wiring structure as the second pin layer 13. This metal layer is connected to the driving circuit layer 12 and the control terminal of the thermal spray unit 2 through vertical interconnects (such as vias or through-holes). Another implementation method is to use flexible printed circuit board (FPC) technology, designing the second pin layer 13 as a conductive line on a flexible substrate, and integrating it with the chip body through bonding or soldering to adapt to the overall structure and signal transmission requirements of the chip.

[0100] "The first end face of target chip 1 extends to the second end face" means that the second pin layer 13, in the physical structure of target chip 1, extends continuously from one edge (first end face) of the chip to the opposite edge (second end face). For example... Figure 2-3As shown, the second pin layer 13 includes H1-H176, where H175 is the second pin located on the first end face and H176 is the second pin located on the second end face. This extended layout not only allows the thermal spray unit 2 within the scribe groove 3 to have a second pin for connection, but also ensures the continuity and coverage of the signal transmission path, enabling the signal to travel through the entire length or width of the target chip 1. One implementation method is to plan the wiring path of the second pin layer 13 as a straight line or curve that runs through the entire length or width of the chip during the chip design stage, ensuring that its physical connection extends from one end to the other and connects with the driving circuit layer 12 and the thermal spray unit 2 along the way. Another implementation method is to use edge wiring technology, designing some or all of the lines of the second pin layer 13 in the edge area of ​​the chip, and using chip packaging technology to ensure that the electrical continuity from the first end face to the second end face is maintained after packaging.

[0101] The solution of this application aims to solve the connectivity and coverage problem of signal transmission within a large-size chip by designing the second pin layer 13 to extend from the first end face to the second end face of the target chip 1. In a wide-width chip formed by assembling at least two unit chips 10, due to the increased chip size, the driving signal needs to be effectively distributed across multiple unit chips 10. The aforementioned wide-width inkjet printing chip includes a target chip 1 and a thermal spray unit 2 electrically connected to the target chip 1. The target chip 1 includes at least two unit chips 10, with scribe lines 3 reserved between each unit chip 10. The thermal spray unit 2 is used to perform inkjet printing according to the control of the target chip 1, and the thermal spray unit 2 is continuously arranged between each unit chip 10 and the scribe lines 3. The target chip 1 has at least two unit chips 10 arranged in a first direction, and a first pin layer 11, a driving circuit layer 12, and a second pin layer 13 arranged sequentially in a second direction. The first end of the first pin layer 11 is electrically connected to an external control device, the second end of the first pin layer 11 is electrically connected to the first end of the drive circuit layer 12, the second end of the drive circuit layer 12 is electrically connected to the first end of the second pin layer 13, and the second end of the second pin layer 13 is electrically connected to the control terminal of the thermal spray unit 2. By extending the second pin layer 13 between its end faces, it is ensured that the control signal output by the drive circuit layer 12 can pass through the entire chip body without obstruction, thereby providing a unified and stable signal source for the thermal spray units 2 distributed in different positions on the chip and within the scribing groove 3. This extended pin layer structure not only optimizes the circuit wiring space inside the chip, but also ensures the integrity of the signal along the overall length of the chip through the physical extension path, so that no matter where the thermal spray unit 2 is located on the chip, it can obtain precise control through the extended second pin layer 13, thereby effectively supporting the need for ultra-large size printing with a single ink cartridge driver chip.

[0102] Furthermore, this application also proposes a scheme in which at least one thermal spray unit 2 is configured in the scribing groove 3.

[0103] Furthermore, since the scribe groove 3 typically does not contain a driving circuit, it is difficult to extend the second pin layer 13 into the scribe groove 3 region. Therefore, in conjunction with the above embodiments and Figure 2-3 As shown, the second pin layer 13 can be extended to the second end face of the unit chip 10. At this time, the second end face represents the end face of the unit chip 10 that is adjacent to the scribing groove 3. Thus, the second pin in the second end face can be electrically connected to the thermal spray unit 2 in the scribing groove 3, which can greatly reduce the layout difficulty and at the same time ensure that the thermal spray unit 2 in the scribing groove 3 can be effectively electrically connected.

[0104] The scribing groove 3 is a physical spacing area reserved between the various unit chips 10 on the wafer in semiconductor manufacturing processes, used for subsequent dicing and separation. Its main function is to provide operating space for dicing tools (such as dicing blades or laser beams) to avoid damaging adjacent chip bodies during dicing. The width of the scribing groove 3 is usually determined according to the dicing process and equipment precision. The thermal spray unit 2 is the core functional component of the inkjet printed chip. Its working principle is usually to generate instantaneous high temperature through an electrically heated resistor, causing the ink to vaporize and form bubbles. The expansion of the bubbles ejects ink droplets from the nozzle. The configuration of the thermal spray unit 2 "at least one" means that one or more thermal spray units 2 can be set in the scribing groove 3 area to meet different printing precision and coverage requirements. There are several ways to configure the thermal spray unit 2 in the scribing groove 3. For example, one way is to directly manufacture the nozzle structure and heating resistor of the thermal spray unit 2 on the substrate in the scribing groove 3 area using the same microelectromechanical systems (MEMS) process as on the unit chip 10 body. Another approach is to extend the ink channels and nozzle structures on the main body of the unit chip 10 into the scribing groove 3 region through precise microfluidic design, so that the nozzle opening is located within the scribing groove 3. Alternatively, an additional functional thin film can be deposited in the scribing groove 3 region, and the thermal spraying unit 2 can be constructed on this thin film.

[0105] The solution of this application utilizes at least one thermal spray unit 2 within the scribe lines 3 between the unit chips 10, effectively making use of the printing blind spots originally created by physical cutting requirements. In a wide-format inkjet printing chip, the target chip 1 includes at least two unit chips 10, with scribe lines 3 between them. In conventional designs, these scribe lines 3 are blank areas where inkjet printing is impossible, resulting in broken or discontinuous printed images. By extending the thermal spray units 2 into the scribe lines 3, these units can perform inkjet printing under the control of the target chip 1, thereby establishing functional continuity between the physically separated unit chips 10. This layout allows the thermal spray units 2 to be continuously arranged between the unit chips 10 and the scribe lines 3, ensuring seamless ink droplet spraying across the entire wide-format chip. When the print command reaches the target chip 1, regardless of whether the ink droplets need to be ejected from the main area of ​​the unit chip 10 or from the scribing groove 3 area, the corresponding thermal spray unit 2 will respond, thereby eliminating the printing gap caused by the presence of the scribing groove 3 and ensuring the uniformity and integrity of the print output.

[0106] Furthermore, this application also proposes that the thermal spray unit 2 in the scribing groove 3 is electrically connected to the unit chip 10 adjacent to the scribing groove 3.

[0107] In this context, the thermal spray unit 2 within the scribing groove 3 refers to the inkjet printing execution component integrated within the reserved area (i.e., the scribing groove 3) used for chip dicing. Traditionally, the scribing groove 3 area typically does not contain functional circuitry; however, this application extends the effective printing width of the printed chip by configuring the thermal spray unit 2 in this area. This can be achieved by fabricating microfluidic structures and heating resistors in the scribing groove 3 area to ensure the physical presence of the thermal spray unit 2; or by extending the microstructure of the thermal spray unit 2 into the scribing groove 3 area to achieve its functional integration.

[0108] The unit chip 10 adjacent to the scribing groove 3 refers to the unit chip 10 in the target chip 1 that is directly adjacent to the scribing groove 3. These unit chips 10 are the basic functional modules constituting the target chip 1. Each unit chip 10 typically contains an independent driving circuit and a partial thermal spray unit 2 array, and serves as the driving source for the thermal spray unit 2 within the scribing groove 3. They can be two physically closely arranged unit chips 10 with their edges adjacent to the scribing groove 3; or they can be unit chips 10 electrically adjacent through micro-interconnect technology.

[0109] Furthermore, this application also proposes that the unit chip 10 further includes a temperature sensor; Temperature sensors are electrically connected between adjacent unit chips 10.

[0110] In wide-format inkjet printing chips, by placing temperature sensors in each unit chip 10, precise and real-time monitoring of the temperature in various regions within the chip is achieved, effectively solving the problem of localized temperature control blind spots caused by heat accumulation in large-size spliced ​​chips. The temperature sensors between adjacent unit chips 10 are electrically connected, constructing a distributed temperature monitoring network. This allows for the exchange and aggregation of temperature data from each unit chip 10, simplifying the wiring complexity of external control circuits. This design enables the control system to analyze and manage the temperature field of the entire printing chip based on the temperature correlation between adjacent areas, thereby dynamically adjusting the driving parameters of each thermal spray unit 2 according to the real-time monitored temperature distribution. Ultimately, while ensuring printing consistency, this effectively improves the operational stability and lifespan of the wide-format inkjet printing chip, preventing print quality degradation or chip damage caused by localized overheating.

[0111] Furthermore, this application proposes that the width of the scribing groove 3 is greater than the width of the thermal spray unit 2, so that at least one thermal spray unit 2 can be configured within the scribing groove 3, maintaining the continuity of the thermal spray unit 2.

[0112] This application also provides a wide-format inkjet printer, the technical solution of which is as follows: Wide-format inkjet printers, including the aforementioned wide-format inkjet printing chip.

[0113] Furthermore, this application also proposes to include a cartridge structure 4; The output end of the thermal spray unit 2 is connected to the ink cartridge structure 4.

[0114] In this embodiment, the ink cartridge structure 4 works in conjunction with the output end of the thermal spray unit 2 to complete the inkjet printing operation.

[0115] like Figure 5 As shown, this application also discloses an embodiment that provides a television-based information processing device applied to a television. The television-based information processing device applied to the television side may include the following modules: Module 510 includes acquiring width requirement information; The determining module 520 includes determining the target chip size information based on the width requirement; The scribing calculation module 530 includes scribing calculation based on the target chip size information and the wafer substrate information to obtain slitting strategy information; The cutting module 540 includes cutting the wafer substrate using the cutting strategy information to obtain the target chip.

[0116] The specific implementation process of the functions and roles of each module in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0117] like Figure 6 As shown, this application provides an electronic device including a processor 610, a communication interface 620, a memory 630, and a communication bus 640, wherein the processor 610, the communication interface 620, and the memory 630 communicate with each other through the communication bus 640. Memory 630 is used to store computer programs; In one embodiment of this application, the processor 610, when executing the program stored in the memory 630, implements the method for manufacturing a wide-format inkjet printing chip provided in any of the foregoing method embodiments.

[0118] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the method for manufacturing a wide-format inkjet printing chip as provided in any of the foregoing method embodiments.

[0119] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0120] The foregoing has described specific embodiments of the embodiments described in this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0121] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for manufacturing a wide-format inkjet printed chip, characterized in that, include: Obtain width requirement information; Based on the width requirement, determine the target chip size information; Based on the target chip size information and the wafer substrate information, the scribing calculation is performed to obtain the slitting strategy information; The wafer substrate is cut using the aforementioned slicing strategy information to obtain the target chip.

2. The method for manufacturing a wide-format inkjet printed chip according to claim 1, characterized in that, The process of calculating the slicing strategy based on the target chip size information and the wafer substrate information to obtain the slicing strategy information includes: Based on the wafer substrate information, determine the unit chip size information and unit chip layout information; The unit chip size information is matched and calculated with the target chip size information to obtain the unit chip combination information; By combining the unit chip combination information and the unit chip layout information, the target division region information is determined; Based on the target region information, line drawing calculations are performed to generate the segmentation strategy information.

3. The method for manufacturing a wide-format inkjet printed chip according to claim 1, characterized in that, The process of cutting the wafer substrate using the aforementioned slicing strategy information to obtain the target chip further includes: Based on the width requirement information, the number of thermal spray units is determined; Based on the number of thermal spray units, combined with the circuit array information corresponding to the target chip and the size information of the target chip, thermal spray unit layout analysis is performed to obtain thermal spray unit circuit layout information; Based on the thermal spray unit circuit layout information, the target chip is fabricated using a thermal spray circuit to obtain an inkjet printed chip.

4. The method for manufacturing a wide-format inkjet printed chip according to claim 3, characterized in that, The step involves analyzing the thermal spray unit layout based on the number of thermal spray units, combined with the circuit array information corresponding to the target chip and the size information of the target chip, to obtain the thermal spray unit circuit layout information, including: Based on the number of thermal spray units and the size of the target chip, the positional arrangement of the thermal spray units is analyzed to obtain the positional information of the thermal spray units. Based on the location information of the thermal spray unit and the circuit array information, circuit matching analysis is performed to determine the circuit connection method information; Based on the location information of the thermal spray unit and the circuit connection information, the circuit layout information of the thermal spray unit is generated.

5. The method for manufacturing a wide-format inkjet printed chip according to claim 4, characterized in that, The step involves analyzing the positional arrangement of the thermal spray units based on the quantity information of the thermal spray units and the size information of the target chip to obtain the positional information of the thermal spray units, including: Based on the target chip size information, the chip body size information and the scribing groove size information are determined, wherein the scribing groove size information is used to represent the size of the scribing groove between unit chips; Based on the chip body size information and the scribing groove size information, the thermal spray unit position layout analysis is performed to determine the first position information corresponding to the chip body size information and the second position information corresponding to the scribing groove size information. The first position information represents the position information of the thermal spray unit at the chip body position, and the second position information represents the position information of the thermal spray unit at the scribing groove position. The position information of the thermal spray unit is generated based on the first position information and the second position information.

6. The method for manufacturing a wide-format inkjet printed chip according to claim 4, characterized in that, The step of performing circuit matching analysis based on the location information of the thermal spray unit and the circuit array information to determine the circuit connection method information includes: Based on the circuit array information, determine the row selection signal pin and the column selection signal pin; Based on the position information of the thermal spray unit and in conjunction with the row selection signal pin, a matching analysis of the row selection signal circuit of the thermal spray unit is performed to obtain the row selection signal connection method information. Based on the position information of the thermal spray unit and the column selection signal pin, the column selection signal circuit matching analysis of the thermal spray unit is performed to obtain the column selection signal connection method information; The circuit connection information is generated based on the row selection signal connection method information and the column selection signal connection method information.

7. A wide-format inkjet printing chip, characterized in that, The wide-format inkjet printing chip is manufactured by the method for manufacturing a wide-format inkjet printing chip according to any one of claims 1-6, and the wide-format inkjet printing chip includes: a target chip and a thermal spray unit electrically connected to the target chip; The target chip includes at least two unit chips, wherein scribe lines are reserved between each unit chip; The thermal spraying unit is used to perform inkjet printing according to the control of the target chip, and the thermal spraying unit is continuously arranged between each of the unit chips and the scribing groove.

8. An apparatus for fabricating a wide-format inkjet printed chip, characterized in that, include: The acquisition module includes acquiring width requirement information; The determining module includes determining the target chip size information based on the width requirement; The scribing calculation module includes scribing calculation based on the target chip size information and the wafer substrate information to obtain slicing strategy information; The dicing module includes dicing a wafer substrate using the dicing strategy information to obtain a target chip.

9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in a memory, implements a method for manufacturing a wide-format inkjet printing chip as described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements a method for manufacturing a wide-format inkjet printing chip as described in any one of claims 1-7.

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