Wafer mapping apparatus

Abstract

A wafer mapping apparatus is disclosed. The wafer mapping apparatus comprises a light source designed to emit light towards a wafer carrier, an imaging device to capture light reflected from the wafer carrier, and a plate arranged to partially block the emitted light.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor processing methods and related structures and apparatus, and specifically to the field of device and integrated circuit manufacturing. More specifically, the invention generally relates to wafer mapping tools. Background Technology

[0002] Batch semiconductor processing equipment, such as vertical furnaces, offers an alternative to single-wafer equipment in semiconductor manufacturing. One of the main advantages of batch processing equipment is its ability to process multiple wafers simultaneously, thereby increasing productivity and reducing overall production time.

[0003] In batch semiconductor processing equipment, wafers are typically loaded into wafer boats, which are then inserted into processing chambers for processing. This method allows for the efficient processing of multiple wafers in a single cycle, thus improving overall production efficiency. However, it is crucial to ensure proper wafer positioning within the wafer boat to guarantee uniform processing and prevent any potential defects. Incorrect wafer positioning can occur in various forms, such as overloading of wafer boat slots, where multiple wafers are accommodated in a single slot or support location; cross-slotting of wafers, where wafers are not properly aligned within the wafer boat, leading to uneven processing; and empty slots within the wafer boat, where no wafers are present.

[0004] Correcting these errors requires careful monitoring of the wafer boat and processing equipment. Maintaining accurate wafer positioning within the wafer boat is crucial for ensuring consistent processing results and maximizing overall throughput.

[0005] Therefore, it is necessary to ensure the accurate positioning of the wafer within the wafer boat in order to achieve improved productivity, reduced production costs, and improved product quality.

[0006] Any discussion set forth in this section (including discussions of problems and solutions) is included in this disclosure for the purpose of providing background information and should not be construed as an admission that any or all of the discussions were known at the time of making this invention or otherwise constitute prior art. Summary of the Invention

[0007] This invention provides a simplified overview of some concepts, which will be described in further detail below. This invention is not intended to require the identification of key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0008] According to a first aspect of the invention, a wafer mapping apparatus is provided, comprising: a light source configured to emit light toward a wafer carrier; an imaging device configured to receive light emitted by the light source and reflected at the wafer carrier; and a plate arranged to partially block the light emitted by the light source.

[0009] By providing a plate arranged to partially block light from the light source, the beam emitted by the light source toward the wafer to be mapped can be narrowed in the vertical direction, thereby reducing reflections from other components near the wafer carrier that could otherwise cause noise in the image acquired by the imaging device. This reduction in noise and / or artifacts in the image allows for more accurate mapping of the wafer contained within the wafer carrier.

[0010] The plate can be movable to change the degree of obstruction of light emitted by the light source.

[0011] The plate can be positioned at the wafer carrier to provide a beam height less than three times the spacing between adjacent wafer receiving positions in the wafer carrier.

[0012] The light emitted by the light source toward the wafer boat can have a beam angle of at least ten degrees in the horizontal direction.

[0013] The light source can be positioned above the imaging device.

[0014] The light source can be partially supported by the imaging device.

[0015] The imaging device and light source may be partially contained within a support, wherein a plate is attached to the support.

[0016] The board can be attached to a light source.

[0017] The light source may include a light-emitting surface having a width and a height, wherein the width is at least five times the height.

[0018] A wafer mapping device may include a computer-readable medium having stored on it one or more sets of instructions or software that, when executed by a computer, cause the computer to perform operations for determining parameters of an image of a wafer carrier acquired by an imaging device.

[0019] The operation may include: acquiring an image of the wafer carrier; and detecting the presence or absence of contours in the image.

[0020] The operation may include: if a contour is detected in the image, fitting a line to the contour.

[0021] The operation may include determining the parameters of the image based on the lines fitted to the contour.

[0022] The parameters indicate the position of the wafer within the wafer carrier.

[0023] According to a second aspect of the invention, a wafer handling apparatus is provided, comprising a wafer handling robot and a wafer mapping device according to a first aspect, wherein a set of one or more sets of instructions or software, when executed by a computer, causes the computer to perform operations for controlling the position of the wafer handling robot based on parameters of an image of a wafer carrier.

[0024] According to the second aspect, the wafer handling apparatus can be configured such that a set of one or more sets of instructions or software, when executed by a computer, further cause the computer to determine the calibrated exposure time by: determining the rate of change of the detected wafer width relative to the exposure time, identifying a first sequence of exposure settings with a rate of change lower than a predetermined threshold, and selecting the calibrated exposure time from the first sequence.

[0025] According to a third aspect of the invention, a wafer handling apparatus is provided, comprising: a wafer handling robot including at least two rotatably connected arms, an end effector attached to one of the arms, and a lifter for changing the vertical position of the at least two rotatably connected arms and the end effector; and a wafer mapping apparatus according to a first aspect, wherein a light source, an imaging device, and a plate are supported on the lifter.

[0026] The wafer handling equipment may also include a controller configured to control the position of the wafer mapping equipment in the vertical direction by controlling a lifter, wherein the controller is further configured to repeat the following steps at least once: causing the wafer mapping equipment to acquire an image of the wafer carrier using an imaging device and determine the parameters of the image of the wafer carrier; and causing the position of the wafer mapping equipment in the vertical direction to change.

[0027] According to a fourth aspect of the present invention, a semiconductor processing apparatus including a wafer transport space is provided, wherein the wafer transport space includes a wafer mapping apparatus according to a first aspect or a wafer transport apparatus according to a second or third aspect.

[0028] Other technical features will be obvious to those skilled in the art based on the following figures, description and claims.

[0029] For the purpose of summarizing the invention and its advantages relative to the prior art, certain objects and advantages of the invention have been described above. It should be understood, of course, that not all of these objects or advantages may necessarily be achieved according to any particular embodiment of the invention. Therefore, for example, those skilled in the art will recognize that the invention may be embodied or implemented in a manner that achieves or optimizes one or more advantages taught or suggested herein, without necessarily achieving other objects or advantages that may be taught or suggested herein.

[0030] All these embodiments are intended to fall within the scope of the invention disclosed herein. Those skilled in the art will readily appreciate these and other embodiments from the following detailed description of certain embodiments with reference to the accompanying drawings; however, the invention is not limited to any particular embodiment disclosed. Attached Figure Description

[0031] Some embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which:

[0032] Figure 1 This is a schematic horizontal cross-sectional view of a semiconductor processing apparatus for batch processing of multiple substrates, which may include a wafer mapping apparatus or a wafer handling apparatus according to embodiments of the present invention.

[0033] Figure 2 This is a schematic perspective view of a wafer mapping apparatus according to an embodiment of the present invention;

[0034] Figure 3 This is a front view of an imaging apparatus and a light source included in a wafer mapping device according to an embodiment of the present invention;

[0035] Figure 4 This is a side view of a wafer mapping apparatus and a wafer carrier according to an embodiment of the present invention;

[0036] Figure 5 This is a schematic perspective view of a wafer handling device according to an embodiment of the present invention;

[0037] Figure 6 This is an example image showing a portion of a wafer carrier supported within the wafer carrier;

[0038] Figure 7 This is an example image showing a portion of a wafer carrier that is supported by a wafer carrier, where one wafer receiving position contains two wafers (double slot).

[0039] It should be understood that the elements in the accompanying drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements to aid in understanding the embodiments shown in this disclosure. Detailed Implementation

[0040] The following description of exemplary embodiments of the methods and compositions is merely illustrative and for purposes of explanation only. The following description is not intended to limit the scope of this disclosure or the claims. Furthermore, the description of multiple embodiments having indicated features or steps is not intended to exclude other embodiments having additional features or steps or other embodiments including different combinations of said features or steps.

[0041] In this disclosure, when two or more elements are referred to as being "fluidly connected," this means that a fluid, such as a gas or liquid or a mixture thereof, can flow between the elements in one or both directions. Fluid connection can be achieved, for example, through gas lines, conduits, pipes, inlets, outlets, or any combination thereof. Fluid connection can be interruptible; for example, valves or other flow control elements may be present.

[0042] In this disclosure, any two numbers of a variable may constitute a feasible range of the variable, and any range indicated may include or exclude endpoints. Furthermore, any value of the indicated variable (whether or not it is indicated by “about”) may refer to an exact value or an approximate value and includes equivalents, and in some embodiments may refer to an average, median, representative value, multi-value, etc. Additionally, in this disclosure, the terms “comprising,” “consisting of,” and “having” may, in some embodiments, independently mean “generally or broadly comprising,” “including,” “substantially consisting of,” or “consisting of.” The meaning of any definition in this disclosure does not necessarily exclude the common and customary meaning in some embodiments. In some cases, percentages indicated herein may be relative or absolute percentages.

[0043] Numerous example materials are given throughout the embodiments of this disclosure. It should be noted that the chemical formulas given for each example material should not be interpreted as limiting, and the non-limiting example materials given should not be limited by the given example stoichiometry.

[0044] In this specification, it will be understood that the terms "on" or "above" may be used to describe relative positional relationships. Another element, film, or layer may be directly on the mentioned layer, or another layer (intermediate layer) or element may be inserted between them, or a layer may be disposed on the mentioned layer but not completely cover the surface of the mentioned layer. Therefore, unless the term "directly" is used alone, the terms "on" or "above" will be interpreted as relative concepts. Similarly, it will be understood that the terms "below," "under," or "beneath" will be interpreted as relative concepts.

[0045] This invention provides a wafer mapping tool that can be deployed in the wafer handling chamber of a semiconductor processing facility. (Reference) Figure 1 A schematic horizontal cross-sectional view of an exemplary semiconductor processing apparatus 101 for batch processing of multiple substrates is shown. The semiconductor processing apparatus 101 may be, for example, a vertical furnace. The semiconductor processing apparatus 101 may include a cassette transport space 102 and a wafer transport space 103. A wafer mapping apparatus or wafer transport apparatus according to an embodiment of the present invention may be included in the wafer transport space.

[0046] The cassette transport space 102 may be provided with a cassette storage 104 configured to store a plurality of wafer cassettes 105, each wafer cassette 105 containing a plurality of wafers. The cassette transport space 102 may be provided with a cassette transporter 106 configured to transfer wafer cassettes 105 between the cassette storage 104 and the wafer transfer location 107.

[0047] The wafer cassette 105 can be implemented as a front-opening wafer transfer cassette (FOUP). FOUPs are considered the standard wafer housing in the industry. Using a FOUP facilitates the interchangeability of the wafer cassette 105 between semiconductor processing equipment 101 and other semiconductor processing equipment 101.

[0048] Semiconductor processing apparatus 101 may include an inner wall 111 separating a cassette transport space 102 and a wafer transport space 103. The inner wall 111 may be provided with a wafer transfer opening 112 adjacent to a wafer transfer location 107 for transferring a wafer from or transferring a wafer from the wafer cassette 105 to the wafer cassette 105.

[0049] The wafer handling space 103 may include a wafer handling robot 108 configured to transfer wafers between a wafer cassette 105 in wafer transfer location 107 and a wafer boat 109 in wafer boat transfer location 110. The wafer boat 109 may be configured to support multiple substrates in a spaced-apart configuration (e.g., a vertically spaced configuration). The wafer boat 109 may be configured to support, for example, at least 100, at least 120, or at least 150 wafers. The wafers may include any combination of product wafers, test wafers, and / or thermal shielding.

[0050] The wafer handling robot 108 can be configured to transfer wafers one by one (i.e., individually) from the wafer cassette 105 to a first wafer boat 109 located in a wafer boat transfer position 110 for receiving wafers. This can be performed until each wafer receiving position of the wafer boat 109 contains a wafer. In some embodiments, some wafer receiving positions can be designated as not requiring wafer insertion. The wafer handling robot 108 can be configured to transfer wafers to a predetermined group of wafer receiving positions.

[0051] The wafer boat 109 can be positioned on the wafer boat transport device 113. The wafer boat transport device 113 may include a wafer boat transfer position 110.

[0052] Once loaded with wafers, the wafer boat 109 can be transferred to the processing chamber 114 for wafer processing. The wafer boat transport device 113 can be positioned in the processing chamber 114 (in... Figure 1Below (shown by dashed lines). The wafer boat transport device 113 may include a wafer boat lift (not shown) configured to transfer the wafer boat 109 from the wafer boat transport device 113 to the processing chamber 114 and vice versa. The wafer boat transport device 113 may include more than one wafer boat position, including a wafer boat transfer position 110. For example, the wafer boat transport device 113 may include one or more of a cooling position and a loading position. The wafer boat transport device 113 may include a rotatable stage for rotating the wafer boat 109 between the wafer boat transfer position 110 and another position (e.g., a loading position where the wafer boat 109 may be loaded (e.g., raised) into the processing chamber 114).

[0053] The semiconductor processing apparatus 101 may include one or more processing chambers 114 and corresponding wafer boat transport devices 113.

[0054] The wafer mapping apparatus according to embodiments of the present invention can be disposed in a semiconductor processing apparatus, for example, but not limited to, regarding Figure 1 The semiconductor processing apparatus 101 is described. The wafer mapping apparatus may include: a light source configured to emit light toward a wafer carrier; an imaging device configured to receive light emitted by the light source and reflected at the wafer carrier; and a plate that partially blocks the light emitted by the light source. The wafer mapping apparatus may be configured to acquire an image of the wafer carrier (e.g., a wafer boat (such as wafer boat 109)) and determine parameters of the image of the wafer carrier. In some embodiments, the parameters may indicate the presence of a wafer at a wafer receiving position in the wafer carrier. In some embodiments, the parameters may indicate the absence of a wafer at a wafer receiving position in the wafer carrier. In some embodiments, the parameters may indicate the presence of more than one wafer at the same wafer receiving position in the wafer carrier. In some embodiments, the parameters may indicate a cross-slotted wafer, i.e., a non-horizontal position accommodated in the wafer carrier. Once the parameters of the image of the wafer carrier are determined, operations can be performed to correct incorrect wafer positioning, such as by removing a wafer from a double-slotted wafer receiving position; by removing and optionally re-inserting a cross-slotted wafer; or by inserting a wafer into an empty wafer receiving position. Such operations may be performed, for example, by a wafer handling robot 108.

[0055] The wafer handling apparatus according to embodiments of the present invention can be disposed in a semiconductor processing apparatus, for example, but not limited to, the following: Figure 1The semiconductor processing apparatus 101 is described. The wafer handling equipment may include: a wafer handling robot 108 supported on a lift for vertical movement; and a wafer mapping device 115, wherein a light source, an imaging device, and a board are supported on the lift. The vertical position of the wafer mapping device 115 can be controlled by controlling the lift, and thus the position of the wafer carrier imaged by the imaging device, to move the wafer mapping device 115 to a specific vertical position. This allows all wafer receiving positions of the wafer carrier to be imaged. By imaging the wafer carrier, determining one or more parameters of the image, and, for example, using the wafer handling robot to correct incorrect wafer positioning, a wafer carrier with correct wafer positioning can be provided to the processing chamber (e.g., processing chamber 114) of the semiconductor processing apparatus (e.g., semiconductor processing apparatus 101). This can allow for increased throughput and reduced wafer breakage or damage.

[0056] refer to Figure 2 and Figure 3 A wafer mapping apparatus 115 according to an embodiment of the present invention includes a light source 116, an imaging device 117, and a plate 118. The light source 116 is configured to emit light toward a wafer carrier (e.g., a wafer boat). In some embodiments, the light source 116 is configured to emit light toward a wafer boat 109 in a semiconductor processing apparatus 101. In some embodiments, the light source 116 is configured to emit white light. In some embodiments, the light source 116 is configured to emit light in the ultraviolet wavelength range. In some embodiments, the light source 116 is configured to emit light in the infrared wavelength range. The emission spectrum of the light source 116 can be selected according to the properties of the wafer to be imaged. For example, if the wafer is made of silicon carbide, a light source 116 configured to emit light in the ultraviolet wavelength range can be used. The light source 116 can be a diffuse light source. The light source 116 can include light-emitting diodes (LEDs). The light source 116 can include fluorescent tubes. The light source 116 can include a non-diffuse light-emitting component and a diffuser placed in front of the non-diffuse light-emitting component to provide diffused light after the diffuser. Light source 116 can be configured to emit a beam having a beam width in a horizontal (e.g., x) direction, the beam width being at least two, three, four, or five times the beam height in a vertical (e.g., z) direction. Light source 116 may include a light-emitting surface 119 through which light is emitted. The light-emitting surface 119 may have a width w in the horizontal direction and a height h in the vertical direction. The width w may be at least five times the height h.

[0057] Imaging device 117 is configured to receive light emitted by light source 116 and reflected at a wafer carrier. Imaging device 117 may include, for example, a camera, a CCD sensor, a CMOS sensor, or a photodiode array. Imaging device 117 may include one or more filters, such as bandpass filters, high-pass filters, low-pass filters, polarizers, spatial filters, or neutral density filters. Imaging device 117 may be positioned below light source 116. Light source 116 may be partially supported by imaging device 117, for example, by positioning light source 116 directly on imaging device 117. Light source 116 may be positioned on a support element (not shown), and the support element may be positioned on imaging device 117.

[0058] The wafer mapping device 115 includes a plate 118 arranged to partially block light emitted by the light source 116.

[0059] The wafer mapping apparatus 115 according to an embodiment of the invention includes a plate 118 arranged to partially block light emitted by a light source 116, allowing for the limitation or suppression of back reflections from elements other than the wafer carrier and the wafer supported therein. This allows for the acquisition of a clearer image of the wafer carrier and the wafer supported therein, with reduced noise due to back reflections from elements other than the wafer carrier and the wafer supported therein. This can be particularly advantageous in semiconductor processing apparatuses that include various highly reflective components close to the wafer carrier. For example, a wafer boat transporter may be made of metal such as stainless steel; emitting light toward the wafer carrier supported on the wafer boat transporter may cause the emitted light to be reflected by the wafer boat transporter and the wafer carrier and the wafer supported therein. The light reflected by the wafer boat transporter can be detected by an imaging device and results in noise in the wafer carrier image, leading to poor image quality and difficulty in extracting information about the wafer supported in the wafer carrier from the image. Processing chambers may have an outer surface made of a reflective material such as metal and may have similar problems. These problems can be solved by providing a plate 118 arranged to partially block light emitted by the light source 116.

[0060] Plate 118 can be movable to allow for changes in the degree of light obstruction. For example, plate 118 can be rotatably attached to light source 116 at edge 120 and can rotate about edge 120. In this way, the beam emitted by light source 116 can be made narrower in the vertical direction.

[0061] refer to Figure 4This illustrates the narrowing of the beam in the vertical direction due to the controllable beam obstruction by plate 118. Light source 116 emits light toward wafer boat 109, which contains wafer 121 at wafer receiving position 122. Beam 123, if obstructed by plate 118, has a height H1 near wafer boat 109. If not obstructed by plate 118, beam 123 has a height H1+H2 near wafer boat 109 at the same position in the y-direction as the measured height H1. It can be seen that, if only the wafer illuminated by the beam in the obstructed state is considered, the back reflection from uninterested objects (e.g., other wafers or other parts of wafer boat 109) provided by obstructing the beam to a height H1 near wafer boat 109 is less than when the beam is unobstructed (having a height H1+H2 near wafer boat 109). Height H1 can be, for example, between one and five times the distance between adjacent wafer receiving positions 122. Height H1 can also be between one and three times the distance between adjacent wafer receiving positions 122.

[0062] Refer again Figure 2 In some embodiments, the imaging device 117 and the light source 116 may be partially included by a support member 125. The support member 125 may be configured to hold the imaging device 117 and the light source 116 in a fixed position relative to each other. The support member 125 allows the imaging device 117 and the light source 116 to move together without changing their positions relative to each other. A plate 118 may be attached to the support member at edge 120. This plate may be attached to the light source at edge 120.

[0063] Plate 118 may be generally planar in shape. Plate 118 may have a light-blocking edge 124 opposite to edge 120, and plate 118 may be attached to light source 116 or support 125 at edge 120. Light-blocking edge 124 may be a straight edge. Light-blocking edge may be arranged substantially parallel to a direction perpendicular to the vertical direction and the normal to the light-emitting surface 119. This allows the emitted light to be blocked in a uniform manner, thereby producing a uniform beam of light behind plate 118.

[0064] refer to Figure 5Embodiments of the present invention provide a wafer handling apparatus 136, which includes a wafer handling robot 108 and a wafer mapping device 115. The wafer handling robot 108 may include a first arm 127 and a second arm 128, an end effector 129, and a lifter 130. The wafer handling robot 108 may include a support plate 126 on the top of the lifter 130. The first arm 127 may have a first end 131 and a second end 132 opposite to the first end 131. The first end 131 of the first arm 127 may be rotatably linked to the support plate 126. The second arm 128 may have a first end 133 and a second end 134 opposite to the first end 133. The first end 133 of the second arm 128 may be rotatably connected to the second end 132 of the first arm 127. The second end 134 of the second arm 128 may be rotatably connected to the end effector 129. The end effector 129 may be configured to support a wafer. The end effector 129 may have, for example, a fork shape or a triangular shape. Other end effector shapes and forms may be used in the embodiments. The lift 130 may be supported by the base 135.

[0065] Refer again Figure 4 The wafer mapping apparatus 115 may include a controller 137 for controlling the operation of the wafer mapping apparatus 115. The controller 137 may be configured to cause the imaging apparatus 117 to acquire an image of a wafer carrier (e.g., wafer boat 109) and determine parameters of the image of the wafer carrier. For example, the controller 137 may include a computer-readable medium storing one or more sets of instructions or software that, when executed by a computer included in the controller 137, cause the computer to perform operations for determining parameters of the image of the wafer carrier acquired by the imaging apparatus. The one or more sets of instructions or software may cause the computer to perform operations that change the position and / or orientation of the wafer handling robot 108 based on the image parameters of the wafer carrier. For example, the one or more sets of instructions or software may cause the computer to send signals, data, or instructions to a controller configured to control the wafer handling robot 108 and / or the lift 130.

[0066] Figure 6 An example image of a wafer carrier acquired by imaging device 117 is shown. The wafer is presented as a bright horizontal line. Figure 6 In the image, three wafers A, B and C are correctly slotted, with each wafer receiving a wafer at a designated location. Figure 7Another example of an image of a wafer carrier acquired by imaging apparatus 117 is shown. Wafers A', B', C', and D are seen in the image. Double slotting is observed in this image because the spacing between the top two wafers D and A' is smaller than the spacing between two single-slotted wafers in adjacent wafer receiving positions, such as the spacing between wafers A' and B' or B' and C'. By imaging the wafer carrier in a direction substantially parallel to the plane of the wafer receiving position, for example at an angle of up to 10°, more preferably at an angle of up to 5°, and even more preferably at an angle of 0°, the wafer (if present in the wafer receiving position) can be imaged substantially along its edges. This allows for easier determination of the wafer position in the wafer carrier compared to imaging the wafer in a direction substantially non-parallel to the wafer receiving position.

[0067] Operations for determining image parameters may include detecting the presence or absence of a contour in the image. Operations for determining image parameters may include detecting the presence or absence of a contour at a specific location in the image. Operations for determining image parameters may include detecting the presence or absence of a contour at a central location in the image. In some embodiments, the imaging device 117 may be positioned to acquire an image in which a wafer is expected to be detected at its center, and therefore the detection of a contour at the center of the image may indicate the presence or absence of a wafer at the expected location. If no contour is detected, it can be inferred that no wafer is present at the expected location. Contours can be detected by applying any suitable algorithm or method.

[0068] Operations used to determine the parameters of an image can include detecting all contours in the image. A threshold can be applied to detect only the contours of the wafer; for example, if the image includes reflections from portions of the wafer boat, these may be less intense than reflections from the wafer edges.

[0069] Operations used to determine the parameters of an image may include: if a contour is detected, fitting a line to the contour. By fitting the line to the contour and comparing that line to a reference (e.g., a vertical line aligned with the z-direction or a horizontal line perpendicular to the z-direction), the orientation of the wafer corresponding to the contour can be determined. For example, if the angle between the contour and the horizontal direction is greater than a threshold, it can be determined that the wafer is cross-slotted, i.e., one edge of the wafer is located at a first wafer receiving position, and a second edge of the wafer is located at a second wafer receiving position different from the first wafer receiving position, such that the wafer is not oriented so that its plane is perpendicular to the vertical direction.

[0070] In some embodiments, a reference that can be compared to the fitted line can be a line intersecting the opposite end of the fitted line, and the determined parameters can represent the curvature or warping of the wafer. For example, the deviation of the fitted line from the line intersecting the opposite end of the fitted line can be determined as a function of the distance along the fitted line. For example, the maximum deviation of the fitted line from the line intersecting the opposite end of the fitted line can be determined. In some embodiments, under the assumption that the wafer is correctly slotted and not warped or bent, the wafer can be expected to be located at a specific position in the image. The position of the fitted line in the vertical direction can be compared with the expected wafer position, and if the difference between the two positions is greater than a first threshold and less than a second threshold, it can be determined that the wafer is correctly slotted (because the difference is less than the second threshold) but warped or bent (because the difference is greater than the first threshold).

[0071] Operations used to determine the parameters of an image may include detecting all contours in the image, fitting lines to each contour, and comparing the positions of the contours in the image to a reference. For example, it may be expected that each wafer receiving position contains exactly one wafer. An image of a portion of the wafer boat 109 spanning multiple wafer receiving positions (e.g., one wafer receiving position, or between one and ten wafer receiving positions) can be acquired via imaging device 117. All contours in the image can be detected, and lines can be fitted to each of the contours, each fitted line representing a wafer. If all wafers are correctly slotted, the positions of the fitted lines in the image can be compared to the expected positions of the wafers. Deviation from the expected wafer configuration can be determined based on, for example, if the fitted lines of a wafer are more than a threshold distance away from their expected positions.

[0072] The operation of determining image parameters may include feeding an image to a neural network configured to receive an image of the wafer carrier as input and output the image parameters. The neural network may be a neural network trained on a set of images of the wafer carrier and corresponding image parameters for each image. For example, the neural network may have been trained on a set of images of the wafer carrier, each image associated with a parameter indicating the presence or absence of a wafer at a specific location in the image. The neural network may have been trained on a set of images of the wafer carrier, each image associated with a parameter indicating whether a wafer in the image has been correctly slotted in a horizontal plane or has been cross-slotted. The neural network may have been trained on a set of images of the wafer carrier, each image associated with a parameter indicating whether a single wafer or more wafers have been slotted at a specific location in the image. The neural network may have been trained on a set of images of the wafer carrier, each image associated with a parameter representing the shape of a wafer in the image.

[0073] Refer again Figure 5In the wafer mapping apparatus 115 according to an embodiment of the present invention, the light source 116, imaging device 117, and plate 118 of the wafer mapping apparatus 115 can be supported on the lifter 130 of the wafer handling robot 108. The light source 116, imaging device 117, and plate 118 of the wafer mapping apparatus 115 can be supported on the support plate 126, and the support plate can be supported on the lifter 130.

[0074] The wafer handling equipment 136 may include a controller 137 for controlling the operation of the wafer handling equipment 136. The controller 137 may be configured to cause the imaging device 117 to acquire an image of the wafer carrier (e.g., wafer boat 109) and determine parameters of the image of the wafer carrier. For example, the controller 137 may include a computer-readable medium storing one or more sets of instructions or software that, when executed by a computer (which may be included in the controller 137), cause the computer to perform operations for determining parameters of the image of the wafer carrier acquired by the imaging device 117. The one or more sets of instructions or software may cause the computer to perform operations for controlling the position and / or posture of the wafer handling robot 108 based on the image parameters of the wafer carrier. For example, if the parameters of the determined image of the wafer carrier indicate that there is more than one wafer at a single wafer receiving position in the wafer carrier, the computer can perform operations to control the position and / or orientation of the wafer handling robot 108, such as moving the end effector slightly below the position of the top wafer of the two wafers present at the single wafer receiving position, moving the end effector 129 upward, for example by causing a lift to move the wafer handling robot 108 upward so that the top wafer is supported on the end effector 129, moving the end effector 129 to a position adjacent to a wafer storage location (e.g., wafer cassette 105), and storing the wafer in the wafer storage location. In some embodiments, the position and / or orientation of the wafer handling robot 108 can be controlled to position the end effector supporting the top wafer near an empty wafer receiving position and store the wafer in the empty wafer receiving position.

[0075] In some embodiments, if the parameters of the determined image of the wafer carrier indicate that the wafer is cross-slotted in the wafer carrier, the computer can perform operations to control the position and / or orientation of the wafer handling robot 108 to move the end effector slightly below the cross-slotted wafer, move the end effector 129 upward, for example by causing a lift to move the wafer handling robot 108 upward so that the wafer is supported on the end effector 129, move the end effector 129 to a position adjacent to a wafer storage location (e.g., wafer cassette 105), and store the wafer in the wafer storage location. In some embodiments, the position and / or orientation of the wafer handling robot 108 can be controlled to position the end effector supporting the wafer near an empty wafer receiving location in the wafer carrier and store the wafer in the empty wafer receiving location.

[0076] In some embodiments, a set of or more sets of instructions or software stored in the controller 137 can cause a computer to perform operations for controlling the vertical position of the wafer mapping device 115. For example, in some embodiments, the wafer mapping device 115 may be mounted on a lift 130, and the vertical position of the wafer mapping device 115 can be controlled by controlling the operation of the lift 130. The set of or more sets of instructions or software stored in the controller 137 can cause the computer to perform the following operations: i) causing the wafer mapping device 115 to acquire an image of the wafer carrier using the imaging device 117 and determine the parameters of the image of the wafer carrier; and ii) causing the wafer mapping device 115 to change its position in the vertical direction. Steps i) and ii) can be repeated to acquire and analyze images of the wafer carrier at different vertical positions on the wafer carrier. In this way, images of the wafer carrier and the wafer supported therein can be acquired.

[0077] In some embodiments, controller 137 may execute an exposure time calibration routine for imaging device 117 prior to wafer mapping. Exposure time can determine the amount of reflected light captured during image acquisition, and the calibration routine can be configured to reduce the likelihood of acquiring overly bright or dark images, and thus unsuitable for subsequent contour detection or other image analysis. In some embodiments, exposure time calibration may be performed using representative wafer cassette 105 locations and representative wafer boat 109 locations, for example, where background reflection is expected to be substantially similar to that at other corresponding locations. In some embodiments, additionally or alternatively, location-specific calibration data may be stored for one or more specific wafer boat locations. The calibration wafer may be placed in a selected slot for the calibration routine, and the wafer may be oriented such that the notch or flat portion is not positioned towards imaging device 117 to reduce the influence of wafer orientation on the calibration results.

[0078] In some embodiments, the controller 137 may first verify the correct operation of the imaging device 117 before determining the exposure time, for example by having the imaging device 117 acquire multiple images at zero exposure time. If a wafer outline, spot, or other image feature is detected in one or more of the images acquired at zero exposure time, the controller 137 may determine that the imaging device 117 has malfunctioned. If correct operation is verified, the controller 137 may acquire multiple images at each of a plurality of incremental exposure settings. For each exposure setting, the controller 137 may determine the width of the detected wafer feature and may ignore exposure settings where no wafer feature is detected, or exposure settings where the width variation detected in multiple images exceeds a threshold, indicating insufficient repeatability. In some embodiments, a representative width for each exposure setting may be determined as the median of the detected widths to reduce the impact of outliers.

[0079] In some embodiments, controller 137 may determine a calibrated exposure time based on the detected change in wafer width as exposure time increases. As exposure time increases, the detected width may initially increase, then approach a stable level corresponding to substantially all light reflected by the sensor from the wafer edge toward imaging device 117. At higher exposure times, the detected width may increase again due to contributions from reflections from components surrounding the wafer (e.g., reflective surfaces on the interior of semiconductor processing device 101). Therefore, controller 137 may be configured to determine the rate of change of the detected width relative to exposure time and may identify a first sequence of exposure settings with a rate of change below a predetermined threshold. A calibrated exposure time can then be selected from within this sequence, for example, from the median exposure setting in the sequence, to avoid selecting exposure settings at the edges of stable regions. This exposure time calibration enables controller 137 to select exposure times at which the wafer edge is adequately illuminated for repeatable and reliable detection, while avoiding exposure settings where the detected width changes within the set exposure time due to insufficient illumination or is artificially increased due to reflections from components surrounding the wafer.

[0080] The threshold and number of consecutive exposure settings considered can be selected empirically and may depend on the imaging device 117 and the wafer handling environment. In some embodiments, the calibrated exposure time may be determined once before the wafer mapping device 115 is enabled for wafer mapping and may be stored by the controller 137 for subsequent image acquisition.

[0081] In some embodiments, prior to performing wafer mapping, controller 137 may execute a calibration routine to correlate image measurements generated by imaging device 117 with the physical displacement of wafer mapping device 115 in the vertical direction. During pixel-to-distance calibration, wafer mapping device 115 may be moved relative to wafer boat 109 via lift 130 to multiple z-positions while imaging device 117 acquires images at the corresponding z-positions. Controller 137 may detect one or more wafer profiles in the acquired images and may determine the apparent displacement of the wafer profiles relative to the commanded z-displacement of wafer mapping device 115 in pixels. Based on these measurements, controller 137 may determine a conversion factor representing pixels per unit distance or distance per pixel. In some embodiments, the conversion factor may be determined based on the average of measurements acquired at a nominal z-position and at offset positions above and below the nominal z-position. The conversion factor may be stored and subsequently used for post-processing of the acquired images and for determining wafer position, slot occupancy, wafer curvature, or other image parameters.

[0082] In some embodiments, the controller 137 may also perform pose calibration in the vertical direction and in a rotational (θ) direction about the z-axis to establish an observation pose in which the wafer 121 is located near the central region of the image, thereby improving wafer edge detection. The rotational direction θ corresponds to rotation about a z-axis extending along the z-direction and centered on the wafer handling robot 108 or its wafer manipulator. Calibration may begin with a nominal pose and may include changing z and θ while the wafer handling robot 108 acquires an image and determining one or more image parameters from the acquired image. The θ position may be adjusted to increase the width or range of detection of wafer edge features in the image, which may correspond to an improved observation for edge detection. The z position may be adjusted to reduce the offset between the measured wafer position and the expected wafer position in the image, for example, until the residual error is less than a predetermined threshold. Positioning the wafer near the central region of the image reduces distortion and can improve the repeatability of contour detection and line fitting.

[0083] In some embodiments, calibration data obtained by controller 137 may be stored as a portion of calibration data associated with a selected wafer mapping scenario. The calibration data may be associated with a specific wafer carrier configuration, cassette configuration, and / or wafer size, allowing different conversion factors or orientation settings to be used for different wafer handling conditions. When processing a given wafer carrier and wafer size, controller 137 may retrieve the stored calibration data and use the retrieved calibration values ​​to operate wafer mapping device 115. This can improve the consistency of wafer detection and mapping across different hardware configurations and wafer formats.

[0084] The wafer handling equipment 136 may include a first controller for controlling the operation of the wafer mapping equipment 115 and a second controller for controlling the operation of the wafer handling robot 108. The first controller may be configured to send instructions to the second controller based on determined parameters of an image of the wafer carrier acquired by the wafer mapping equipment 115.

[0085] For the purpose of summarizing the invention and its advantages relative to the prior art, certain objects and advantages of the invention have been described above. It should be understood, of course, that not all of these objects or advantages may necessarily be achieved according to any particular embodiment of the invention. Therefore, for example, those skilled in the art will recognize that the invention may be embodied or implemented in a manner that achieves or optimizes one or more advantages taught or suggested herein, without necessarily achieving other objects or advantages that may be taught or suggested herein.

[0086] All these embodiments are intended to fall within the scope of the invention disclosed herein. Those skilled in the art will readily appreciate these and other embodiments from the following detailed description of certain embodiments with reference to the accompanying drawings; however, the invention is not limited to any particular embodiment disclosed.

Claims

1. A wafer mapping apparatus, comprising: A light source configured to emit light toward the wafer carrier; An imaging device configured to receive light emitted by a light source and reflected at a wafer carrier; as well as The plate is arranged to partially block the light emitted by the light source.

2. The wafer mapping apparatus according to claim 1, wherein, The plate is movable to change the degree of obstruction of light emitted by the light source.

3. The wafer mapping apparatus according to claim 1 or 2, wherein, The light source is positioned above the imaging device.

4. The wafer mapping apparatus according to claim 3, wherein, The light source is partially supported by the imaging device.

5. The wafer mapping apparatus according to any one of claims 1 to 4, wherein, The imaging device and the light source are partially included in a support member, wherein the plate is attached to the support member.

6. The wafer mapping apparatus according to any one of claims 1 to 4, wherein, The plate is attached to the light source.

7. The wafer mapping apparatus according to any one of claims 1 to 5, wherein, The light source includes a light-emitting surface having a width and a height, wherein the width is at least five times the height.

8. The wafer mapping apparatus according to any one of claims 1 to 7, comprising a computer-readable medium having stored thereon one or more sets of instructions or software that, when executed by a computer, cause the computer to perform operations for determining parameters of an image of a wafer carrier acquired by the imaging apparatus.

9. The wafer mapping apparatus according to claim 8, wherein, The operation includes: Obtaining an image of the wafer carrier; and Detect the presence or absence of contours in an image.

10. The wafer mapping apparatus according to claim 9, wherein, The operation includes: if a contour is detected in the image, fitting a line to the contour.

11. The wafer mapping apparatus according to claim 10, wherein, The operation includes determining parameters of the image based on the line fitted to the contour.

12. The wafer mapping apparatus according to claim 11, wherein, The parameter indicates the position of the wafer within the wafer carrier.

13. A wafer handling device, comprising a wafer handling robot and a wafer mapping device according to any one of claims 8 to 12, wherein, The set of one or more instructions or software, when executed by a computer, cause the computer to perform operations to control the position of the wafer handling robot based on parameters of the image of the wafer carrier.

14. The wafer handling apparatus according to claim 13, wherein, When executed by the computer, the set of instructions or software further enables the computer to determine the calibrated exposure time by: determining the rate of change of the detected wafer width relative to the exposure time, identifying a first sequence of exposure settings with a rate of change below a predetermined threshold, and selecting the calibrated exposure time from the first sequence.

15. A wafer handling device, comprising: A wafer handling robot includes at least two rotatably connected arms, an end effector attached to one of the arms, and a lifter for changing the vertical position of the at least two rotatably connected arms and the end effector; as well as The wafer mapping apparatus according to any one of claims 1 to 12, wherein the light source, imaging device and plate are supported on a lifter.

16. The wafer handling apparatus of claim 15, further comprising a controller configured to control the position of the wafer mapping apparatus in the vertical direction by controlling the lifter, wherein, The controller is also configured to repeat the following steps at least once: The wafer mapping device uses the imaging apparatus to acquire an image of the wafer carrier and determine the parameters of the image of the wafer carrier; This causes the position of the wafer mapping device to change in the vertical direction.

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