Adhesive tape sheet and method of manufacturing semiconductor device using the same

Abstract

A method of manufacturing a semiconductor device includes classifying a plurality of semiconductor chips into a plurality of grades by performing wafer testing on a wafer on which the plurality of semiconductor chips are formed, the plurality of semiconductor chips including first semiconductor chips of a first grade; transferring each of the first semiconductor chips to a tape sheet; and separating the first semiconductor chips from the tape sheet and stacking the first semiconductor chips in order on a base wafer. The tape sheet includes a thixotropic adhesive layer including a polymer composition including a thixotropic agent.

Description

Cross-reference to related applications

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2025-0057022, filed with the Korean Intellectual Property Office on April 30, 2025, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to adhesive tape sheets and methods for manufacturing semiconductor devices using the adhesive tape sheets. Background Technology

[0003] As electronic devices are designed to have reduced weight and high performance, research and development are ongoing to create semiconductor devices that are miniaturized and possess high performance and reliability. To meet these demands, research and development are also underway on adhesive tapes that enable precise handling of semiconductor chips. Summary of the Invention

[0004] Some exemplary embodiments of this disclosure involve providing a tape sheet with thixotropic properties and a method for manufacturing a semiconductor device using the tape sheet.

[0005] According to some exemplary embodiments of this disclosure, a method of manufacturing a semiconductor device includes: forming a plurality of semiconductor chips on a wafer; classifying the plurality of semiconductor chips into first semiconductor chips and second semiconductor chips by performing wafer testing on the wafer; providing a first adhesive tape and a second adhesive tape; transferring the first semiconductor chip to the first adhesive tape and transferring the second semiconductor chip to the second adhesive tape; and providing a first substrate wafer and a second substrate wafer, separating the first semiconductor chip from the first adhesive tape and forming the first semiconductor chip on the first substrate wafer, and separating the second semiconductor chip from the second adhesive tape and forming the second semiconductor chip on the second substrate wafer, wherein each of the first adhesive tape and the second adhesive tape includes an adhesive layer, wherein the adhesive layer includes a first portion to which the respective semiconductor chip is adhered and a second portion to which a support structure is adhered surrounding the first portion, wherein the first portion includes a polymer composition containing a thixotropic agent, and wherein the adhesive force of the second portion is greater than the adhesive force of the first portion.

[0006] According to some exemplary embodiments of this disclosure, a method of manufacturing a semiconductor device includes: forming a plurality of semiconductor chips on a wafer; classifying the plurality of semiconductor chips into a first semiconductor chip group and a second semiconductor chip group by performing wafer testing on the wafer; providing a first adhesive tape and a second adhesive tape to transfer the first semiconductor chip group to the first adhesive tape and to transfer the second semiconductor chip group to the second adhesive tape; and providing a first substrate wafer and a second substrate wafer, separating the first semiconductor chip in the first semiconductor chip group from the first adhesive tape and sequentially stacking the first semiconductor chip on the first substrate wafer, and separating the second semiconductor chip in the second semiconductor chip group from the second adhesive tape and sequentially stacking the second semiconductor chip on the second substrate wafer, wherein each of the first adhesive tape and the second adhesive tape includes an adhesive layer comprising a polymer composition containing a thixotropic agent.

[0007] According to some exemplary embodiments of this disclosure, a method of manufacturing a semiconductor device includes: performing wafer testing on a wafer on which a plurality of semiconductor chips are formed, classifying the plurality of semiconductor chips into a plurality of grades, the plurality of semiconductor chips including first semiconductor chips of a first grade; transferring each first semiconductor chip onto an adhesive tape; and separating the first semiconductor chips from the adhesive tape and sequentially stacking the first semiconductor chips onto a substrate wafer, wherein the adhesive tape includes a thixotropic adhesive layer comprising a polymer composition containing a thixotropic agent, and wherein the weight ratio of the thixotropic agent relative to the polymer composition is in the range of about 1 wt% to about 5 wt%. Attached Figure Description

[0008] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 This is a vertical cross-sectional view of an adhesive tape sheet according to some exemplary embodiments of the present disclosure.

[0010] Figure 2 This is a plan view showing an adhesive tape sheet according to some example embodiments of the present disclosure.

[0011] Figure 3 This is a plan view showing an adhesive tape sheet according to some example embodiments of the present disclosure.

[0012] Figure 4A This is a plan view showing an adhesive tape sheet according to some example embodiments of the present disclosure.

[0013] Figure 4B It is along Figure 4A The cross-sectional view taken from line I-I' in the diagram.

[0014] Figure 5AThis is a plan view showing an adhesive tape sheet according to some example embodiments of the present disclosure.

[0015] Figure 5B It is along Figure 5A The cross-sectional view taken from line I-I' in the diagram.

[0016] Figure 6 This is a plan view showing an adhesive tape sheet according to some example embodiments of the present disclosure.

[0017] Figure 7 This is a flowchart illustrating a process for manufacturing semiconductor devices using adhesive tape according to some exemplary embodiments of the present disclosure.

[0018] Figure 8 , Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 11C , Figure 12 , Figure 13 , Figure 14A , Figure 14B and Figure 14C This is a vertical cross-sectional view illustrating a method for manufacturing a semiconductor device using adhesive tape according to some exemplary embodiments of the present disclosure.

[0019] Figure 15A This is a perspective view showing a semiconductor device according to some example embodiments of the present disclosure.

[0020] Figure 15B It is along Figure 15A The cross-sectional view taken from line II-II' in the diagram.

[0021] Figure 15C It shows Figure 15B An enlarged view of region "A" in the image.

[0022] Figure 16A This is a perspective view showing a semiconductor device according to some example embodiments of the present disclosure.

[0023] Figure 16B It is along Figure 16A The cross-sectional view taken from line III-III' in the diagram.

[0024] Figure 16C It shows Figure 16B An enlarged view of region "B" in the image.

[0025] Figure 17 This is a perspective view showing a semiconductor device according to some example embodiments of the present disclosure.

[0026] Figure 18AThis is a plan view illustrating a semiconductor device according to some example embodiments of the present disclosure.

[0027] Figure 18B It is along Figure 18A The cross-sectional view taken from line IV-IV' in the diagram. Detailed Implementation

[0028] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0029] Figure 1 This is a cross-sectional view of an adhesive tape sheet 1 according to some example embodiments.

[0030] Figure 2 This is a plan view of an adhesive tape sheet according to some example embodiments, showing... Figure 1 The adhesive layer 10 of the tape sheet 1 in the middle.

[0031] refer to Figure 1 The tape sheet 1 may include a base layer 20, an adhesive layer 10 on the base layer 20, and a cover layer 30 on the adhesive layer 10. The base layer may be referred to as a base film, the adhesive layer may be referred to as an adhesive film, and the cover layer may be referred to as a cover film.

[0032] In an example embodiment, the tape sheet 1 can protect or support an object to which it may be temporarily adhered. The tape sheet 1 may be a tape sheet used in semiconductor processes, but some example embodiments are not limited thereto. When the tape sheet 1 is used in a semiconductor process, the adhered object may include semiconductor chips 100C1, 100C2, and 100C3 (e.g., Figure 14A "100C1" in Figure 14B "100C2" and Figure 14C (referring to "100C3" in the text). In the following text, for ease of description, we will use the example of tape sheet 1 being used in semiconductor processes.

[0033] The adherend can be temporarily adhered to the adhesive layer 10, and the adhesive layer 10 can protect or support the adherend. In an example embodiment, adherends classified into the same grade through predetermined tests can be temporarily adhered to the adhesive layer 10. In an example embodiment, the adherend may include a semiconductor chip (e.g., Figure 14A "100C1" in Figure 14B "100C2" and Figure 14C (100C3 in the text).

[0034] The adhesive layer 10 may include a polymer composition and additives added to the polymer composition. The additives may include thixotropic agents for controlling the flow properties of the adhesive layer 10.

[0035] In an example embodiment, the thixotropic agent may include oil-based thixotropic agents and water-based (i.e., water-based) thixotropic agents, and the polymer composition may be selected according to the characteristics of the thixotropic agent.

[0036] In an example embodiment, the oil-based thixotropic agent may include inorganic, organic, or composite thixotropic agents. Inorganic thixotropic agents may be selected from the group consisting of: fumed silica, bentonite, ultrafine precipitated calcium carbonate (PCC), or synthetic aluminum silicate hexahydrate. Organic thixotropic agents may be selected from the group consisting of: metal soaps, hydrogenated castor oil, polyamide waxes, oxidized polyethylene, vegetable oils, or linseed oil. Composite thixotropic agents may be selected from the group consisting of: organobentonite or surface-treated calcium carbonate.

[0037] When an oil-based thixotropic agent is added, the polymer composition may be selected from the group consisting of silicone polymers, propylene polymers, ethylene polymers, styrene polymers, polyurethane polymers, or ester polymers.

[0038] In an example implementation, an aqueous thixotropic agent may include an inorganic agent, an organic agent, or a composite thixotropic agent.

[0039] Inorganic thixotropic agents can be at least one or more selected from the group consisting of synthetic silica or bentonite. Synthetic silica can include, for example, water-soluble alkali silicates. Organic thixotropic agents can be at least one or more selected from the group consisting of cellulose derivatives, casein, polyethylene, polyacrylic acid, or anhydrous maleic acid copolymers. Cellulose derivatives can include, for example, hydroxyethyl cellulose (HEC) and hydroxypropyl cellulose. Composite thixotropic agents can include organobentonite.

[0040] When adding an aqueous thixotropic agent, the polymer composition can be selected from the group consisting of: vinyl alcohol polymers, acrylic polymers, or polyurethane polymers.

[0041] In the adhesive layer 10 of the example embodiment, the additives that may be included may be present in a weight ratio of about 5.0 wt% or less relative to the polymer composition. In some example embodiments, the additives that may be included may be present in a weight ratio of about 1.0 wt% to about 5.0 wt% relative to the polymer composition. In some example embodiments, the additives that may be included may be present in a weight ratio of about 3.0 wt% to about 5.0 wt% relative to the polymer composition. In the example embodiments, this weight ratio may represent the ratio of the weight of the additive to the weight of the polymer composition.

[0042] In an example implementation, when the weight ratio is less than about 1.0 wt%, the semiconductor chip may detach from the tape, or when picking up the semiconductor chip, residue of the adhesive layer may remain between the bonding pads.

[0043] In the example implementation, when the weight ratio is greater than about 5.0 wt%, the adhesive layer may be excessively stretched when picking up the semiconductor chip, or the semiconductor chip may not be easily separated, resulting in damage to the semiconductor chip or difficulty in picking up the semiconductor chip.

[0044] In some example embodiments, adhesive layer 10 may include a non-UV adhesive composition that is not cured by ultraviolet (UV) light. In another embodiment, adhesive layer 10 may include an adhesive component that is not cured or crosslinked in response to UV light and whose adhesive strength or physical properties do not change upon exposure to UV light. In yet another embodiment, adhesive layer 10 may not include commonly used UV-curable acrylic adhesives, UV-sensitive polyurethane adhesives, or photosensitive resins containing photoinitiators.

[0045] According to this disclosure, since the adhesive layer 10 comprises a non-UV adhesive composition, problems that may arise due to the partial curing of the adhesive layer 10 by UV light can be reduced or prevented. In an example embodiment, problems may include: the semiconductor chip failing to be properly picked up from the tape, and residue remaining between the bonding pads of the semiconductor chip even after it has been separated.

[0046] In some example implementations, the adhesive layer 10 (or tape 1) can be reused after the semiconductor process is performed.

[0047] In some example embodiments, the thickness of the adhesive layer 10 may be about 100 μm or less. In some example embodiments, the thickness of the adhesive layer 10 may be in the range of about 10 μm or more and about 100 μm or less. In some example embodiments, the thickness of the adhesive layer 10 may be in the range of about 10 μm or more and about 50 μm or less.

[0048] The adhesive layer 10 may include a first portion 10p1 to which the adhesive is adhered and a support structure (e.g., Figure 11A The second part 10p2 to which the “RF” in the text is adhered. In an example embodiment, the support structure RF may include an annular frame, which is secured by adhesive tape (…). Figure 11A The “1S” in the figure provides stable support for the adhered object.

[0049] The first part 10p1 may include the central portion of the adhesive layer 10 and may be the area to which the adhesive is temporarily adhered.

[0050] The second part 10p2 may include the edge region of the adhesive layer 10 and may be the region to which the support structure is adhered. In a plan view, the second part 10p2 may be formed around the first part 10p1.

[0051] The adhesive strength of the second part 10p2 can be greater than that of the first part 10p1, which allows the support structure to stably support the adhered objects. The adhesive strength of the first part 10p1 can be provided by a polymer composition including a thixotropic agent. The adhesive strength of the second part 10p2 can be provided by applying an adhesive with adhesive strength to the edge region of the adhesive layer 10. The material of the adhesive is not limited, as long as its adhesive strength is greater than that of the first part 10p1.

[0052] The substrate layer 20 may be a support disposed on one surface of the adhesive layer 10 and supporting the adhesive layer 10. The substrate layer 20 can provide structural stability to the adhesive layer 10. The substrate layer 20 can provide stability, for example, maintaining the physical shape of the adhesive layer 10 and withstanding mechanical forces applied from the outside. The substrate layer 20 can provide heat resistance and chemical resistance to withstand various environmental conditions of semiconductor processes.

[0053] The substrate 20 may include materials suitable for the purposes described above. The substrate 20 may include materials with excellent flexibility, chemical resistance, and heat resistance. The substrate 20 may include, for example, one of polyimide (PI), polyester (PET), polyurethane (PU), polyvinyl chloride (PVC), or polyolefin (PO).

[0054] The thickness of the substrate layer 20 can be about 100 μm or less. In some example embodiments, the thickness of the substrate layer 20 can be in the range of about 25 μm or more and about 100 μm or less. In some example embodiments, the thickness of the substrate layer 20 can be in the range of about 50 μm or more and about 100 μm or less.

[0055] The cover layer 30 may be a cover film disposed on another surface of the adhesive layer 10 opposite to the first surface and covering that other surface of the adhesive layer 10. The cover layer 30 can protect the adhesive layer 10 from contact with the external environment. The cover layer 30 can protect the adhesive layer 10 from the effects of, for example, dust, contaminants, moisture, etc.

[0056] The cover layer 30 may include materials suitable for the purposes described above. The cover layer 30 may include materials that have excellent chemical and heat resistance and are easily separable from the adhesive layer 10. The cover layer 30 may include, for example, polyethylene (PE), polypropylene (PP), polyester (PET), or silicone-treated film.

[0057] The thickness of the capping layer 30 can be about 50 μm or less. In some example embodiments, the thickness of the capping layer 30 can be in the range of about 30 μm or more and about 50 μm or less.

[0058] The tape sheet 1 can be provided in a state where the cover layer 30 covers the adhesive layer 10. The cover layer 30 can be separated from the adhesive layer 10, such that one surface of the adhesive layer 10 is exposed, and the object to be adhered to the exposed surface of the adhesive layer 10.

[0059] In some example embodiments, the tape sheet 1 may include a base layer 20 and an adhesive layer 10. In other words, the tape sheet 1 may include a base layer 20 and an adhesive layer 10, but not a cover layer 30.

[0060] Figure 3 This is a plan view of an adhesive tape sheet 1a according to some example embodiments, showing the adhesive layer 10a of the adhesive tape sheet 1a.

[0061] refer to Figure 3 In addition to the configuration including an adhesive layer 10a with DMR of the adhesive region and NMR of the non-adhesive region, the tape sheet 1a can be used with a reference. Figure 1 and Figure 2 The examples described are the same or similar.

[0062] The first portion 10p1 of the adhesive layer 10a may include an adhesive region DMR to which the adhered object is adhered and a non-adhesive region NMR to which the adhered object is not adhered. When the adhered object includes a semiconductor chip, the adhesive region DMR may be referred to as the mounting region, and the non-adhesive region NMR may be referred to as the non-mounting region.

[0063] Non-adhesive region NMR can be formed by selectively performing laser irradiation or other marking techniques on the first portion 10p1 of the adhesive layer 10a. For example, marking techniques can be performed by providing visual or physical markings on the surface of the first portion 10p1, wherein the visual or physical markings can delineate or identify the non-adhesive region NMR.

[0064] The DMR of the bonded region can be distinguished from each other by the NMR of the non-bonded region, and the DMR of the bonded region can be set into a grid pattern.

[0065] The non-adhesive region NMR may include a portion extending in a first direction D1 and a portion extending in a second direction D2 perpendicular to the first direction. The width d of the non-adhesive region NMR can range from about 50 μm to about 100 μm.

[0066] Non-adhesive region NMR can be formed by selectively performing laser irradiation or other marking techniques on the first portion 10p1 of the adhesive layer 10a. For example, marking techniques can be performed by providing visual or physical markings on the surface of the first portion 10p1, wherein the visual or physical markings can delineate or identify the non-adhesive region NMR.

[0067] Therefore, NMR of the non-adhesive region can be used as a reference for the positional alignment or arrangement of the adhered objects, and can help ensure the positional consistency of multiple adhered objects that can be precisely aligned or fixed. Furthermore, NMR of the non-adhesive region can improve the accuracy of subsequent processes after the bonding process (e.g., the separation of semiconductor chips).

[0068] Figure 4A This is a plan view of an adhesive tape sheet 1b according to some example embodiments, showing the adhesive layer 10b of the adhesive tape sheet 1b. Figure 4B It is along Figure 4A The cross-sectional view taken from line I-I' in the diagram.

[0069] refer to Figure 4A and Figure 4B Except for the configuration where the adhesive region DMR can be separated by the partition wall W, this example implementation can be compared with the reference. Figures 1 to 3 The examples described are the same or similar.

[0070] In an example embodiment, the non-adhesive region NMR may be defined by a partition wall W. The partition wall W may protrude vertically D3 from the upper surface of the first portion 10p1 of the adhesive layer 10b. The upper surface of the partition wall W may be at a height higher than the upper surface of the adhesive region DMR. The partition wall W may be formed as part of the adhesive layer 10b and may comprise the same material as the adhesive layer 10b.

[0071] In the example implementation, the width d of the non-adhesive region NMR can be defined as the maximum width of the partition wall W in the horizontal direction D1 or D2.

[0072] Figure 5A This is a plan view of an adhesive tape sheet 1c according to some example embodiments, showing the adhesive layer 10c of the adhesive tape sheet 1c. Figure 5B It is along Figure 5A The cross-sectional view taken from line I-I' in the diagram.

[0073] refer to Figure 5A and Figure 5B Apart from the configuration where the adhesive region DMR can be distinguished by the groove G, this example implementation can be compared with the reference. Figures 1 to 4B The examples described are the same or similar.

[0074] In an example embodiment, the non-adhesive region NMR may be defined by a groove G. The groove G may be a structure formed by a vertical indentation extending downward from the upper surface of the first portion 10p1 of the adhesive layer 10c. The bottom surface of the groove G may be at a height lower than the height of the upper surface of the adhesive region DMR.

[0075] In the example implementation, the width d of the non-adhesive region NMR can be defined as the maximum width of the groove G in the horizontal direction D1 or D2.

[0076] Figure 6 This is a plan view of an adhesive tape sheet 1d according to some example embodiments, showing the adhesive layer 10d of the adhesive tape sheet 1d.

[0077] refer to Figure 6 In addition to the adhesive layer 10d further including a third portion 10p3 surrounding the second portion 10p2 and different from the second portion 10p2, the tape sheet 1d can be with reference to Figures 1 to 5B The examples described are the same or similar.

[0078] The third portion 10p3 may be the area surrounding the second portion 10p2 at the edge of the adhesive layer 10d. The third portion 10p3 may include a material substantially the same as the first portion 10p1. Alternatively, the third portion 10p3 may be defined as the area where the adhesive forming the second portion 10p2 is not coated.

[0079] Figure 7 This is a flowchart illustrating a process for manufacturing a semiconductor device using tape sheets 1, 1a, 1b, 1c and 1d according to some example embodiments.

[0080] Figure 8 , Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 11C , Figure 12 , Figure 13 , Figure 14A , Figure 14B and Figure 14C This is a vertical cross-sectional view illustrating a method for manufacturing a semiconductor device using tape sheets 1, 1a, 1b, 1c and 1d according to some example embodiments.

[0081] refer to Figure 7 and Figure 8 It can provide a wafer W (S10), and multiple semiconductor chips 100C (S20) can be formed on the wafer W.

[0082] A wafer W (S10) may be provided. Wafer W may include a semiconductor wafer. For example, wafer W may include semiconductor elements such as silicon and germanium, or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Wafer W may be defined as including a front surface FS on which bonding pads 132 are formed and a back surface BS on which at least a portion has been removed by a back-side grinding process.

[0083] Multiple semiconductor chips 100C can be formed on wafer W (S20). Each of the multiple semiconductor chips 100C may include a substrate, a circuit layer, and multiple connection pads 132. The substrate may include semiconductor elements or compound semiconductors. The circuit layer may be configured to be adjacent to one surface of the substrate (e.g., the front surface FS of wafer W).

[0084] Multiple connection pads 132 may be formed on the front surface FS of the wafer W. In some example embodiments, the multiple connection pads 132 may be referred to as front pads. The multiple connection pads 132 may include at least one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). For example, the connection pads 132 may include at least one of copper (Cu) or an alloy thereof.

[0085] A scribing line SL can be formed between multiple semiconductor chips 100C. The scribing line SL can be a region defining the space between multiple adjacent semiconductor chips 100C and can serve as a dicing path for separating individual semiconductor chips 100C from the wafer W through subsequent dicing processes. The scribing line SL typically does not perform electrical functions and can be portions in which circuit patterns are not typically formed. In some example embodiments, alignment marks, test patterns, or identification marks for device identification can be formed on the scribing line SL.

[0086] refer to Figure 7 and Figure 9 By performing wafer testing on wafer W, multiple semiconductor chips 100C can be classified into multiple semiconductor chip groups of different grades (S30).

[0087] It can perform wafer testing on wafer W.

[0088] Wafer testing can include electrical die sorting (EDS) testing.

[0089] Wafer testing may include classifying multiple semiconductor chips 100C into different grades of semiconductor chipsets based on at least one of parameters such as operating speed, current consumption, or threshold voltage range.

[0090] For example, a semiconductor chipset may include a first semiconductor chipset SS, a second semiconductor chipset TT, and a third semiconductor chipset FF. The first semiconductor chipset SS may include at least one first semiconductor chip 100C1 classified as a first level. The second semiconductor chipset TT may include at least one second semiconductor chip 100C2 classified as a second level. The third semiconductor chipset FF may include at least one third semiconductor chip 100C3 classified as a third level. Each of at least one of the first to third semiconductor chips 100C1, 100C2, and 100C3 may include multiple semiconductor chips.

[0091] In the example implementation, the first level can be a higher level than the second level, and the second level can be a higher level than the third level. In the example implementation, a higher level may indicate a better quality or performance level of the semiconductor chip. For example, a first-level semiconductor chip 100C1 may have relatively improved electrical or reliability performance compared to a second-level semiconductor chip 100C2. A second-level semiconductor chip 100C2 may have relatively improved electrical or reliability performance compared to a third-level semiconductor chip 100C3.

[0092] refer to Figure 7 and Figure 10 Multiple semiconductor chips 100C can be individualized by cutting wafer W (S40).

[0093] A tape T can be formed on the front surface FS of wafer W, and a portion of the back surface BS of wafer W can be removed by performing a backside grinding process. Subsequently, multiple semiconductor chips 100C can be individualized by dicing wafer W.

[0094] refer to Figure 7 , Figure 11A , Figure 11B and Figure 11C It can provide multiple tape sheets 1S, 1T and 1F, and can transfer multiple individualized semiconductor chipsets to multiple tape sheets 1S, 1T and 1F respectively (S50).

[0095] The plurality of tape sheets 1S, 1T, and 1F may include, for example, a first tape sheet 1S, a second tape sheet 1T, and a third tape sheet 1F. Each of the first to third tape sheets 1S, 1T, and 1F may include a reference. Figures 1 to 6 One of the tape sheets 1, 1a, 1b, 1c and 1d described.

[0096] First semiconductor chipsets classified into different levels ( Figure 9The first semiconductor chip 100C1 and the second semiconductor chipset (SS) in the figure. Figure 9 The second semiconductor chip 100C2 and the third semiconductor chipset ("TT") Figure 9 The third semiconductor chip 100C3 ("FF") can be transferred to different adhesive tape sheets. For example, the first semiconductor chip 100C1 can be transferred to the first adhesive tape sheet 1S (see [reference]). Figure 11A The second semiconductor chip 100C2 can be transferred onto the second adhesive tape 1T (see...). Figure 11B Furthermore, the third semiconductor chip 100C3 can be transferred onto the third adhesive tape 1F (see [reference]). Figure 11C ).

[0097] A support structure RF can be formed at the edges of the first to third adhesive tape sheets 1S, 1T, and 1F. The support structure RF may include an annular frame that stably supports the first to third semiconductor chips 100C1, 100C2, and 100C3. (Reference) Figure 2 The support structure RF can be formed on the second part 10p2.

[0098] The transfer of the first to third semiconductor chips 100C1, 100C2, and 100C3 onto the corresponding first to third adhesive tapes 1S, 1T, and 1F can be performed under a first pressure F_d. The first pressure F_d can be applied in a downward direction perpendicular to the upper surface of each of the first to third adhesive tapes 1S, 1T, and 1F.

[0099] Furthermore, the first shear force F_s1 can be applied in the direction toward the point where the first pressure F_d is applied. At least a portion of the first shear force F_s1 can be applied substantially parallel to the upper surfaces of the first to third adhesive tape sheets 1S, 1T, and 1F. It is understood that the first shear force F_s1 may arise due to the physical property that the viscosity of the first to third adhesive tape sheets 1S, 1T, and 1F changes according to external force or deformation conditions because they comprise polymer compositions containing thixotropic agents.

[0100] The viscosity of each adhesive layer 10 from the first to the third adhesive tapes 1S, 1T, and 1F can be reduced by a first pressure F_d and a first shear force F_s1. Therefore, the adhesive layer 10 can fill the space between the bonding pads 132 without gaps. This improves the mounting stability of each of the first to the third semiconductor chips 100C1, 100C2, and 100C3.

[0101] refer to Figure 7 and Figure 12 In execution Figures 11A to 11CFollowing the transfer process, the preliminary semiconductor structure can be maintained for a predetermined period of time without external force or action alone. In the example embodiment, for ease of description, the first semiconductor chip 100C1 transferred onto the first adhesive tape 1S will be described primarily.

[0102] A preliminary semiconductor structure can refer to a reference. Figures 11A to 11C The transfer described is from the first tape sheet to the third tape sheet ( Figure 11A The "1S" in Figure 11B "1T" and Figure 11C The first semiconductor chip to the third semiconductor chip on “1F” (in the text) Figure 11A "100C1" in Figure 11B "100C2" and Figure 11C (100C3 in the text).

[0103] In this case, the viscosity of the adhesive layer 10 of each of the first to third adhesive tape sheets 1S, 1T and 1F may increase again over time.

[0104] refer to Figure 7 and Figure 13 Multiple semiconductor chips (e.g., 100C1, 100C2, and 100C3) can be separated from multiple adhesive tape sheets 1S, 1T, and 1F respectively (S60). In the example embodiment, for ease of description, the first semiconductor chip 100C1 transferred onto the first adhesive tape sheet 1S can be described with the first semiconductor chip 100C1 as the center.

[0105] The separation of the first semiconductor chip 100C1 from the first adhesive tape 1S can be performed under a first tensile force. The first semiconductor chip 100C1 can be picked up using a pickup device PS. The first tensile force can be applied in an upward direction D3 perpendicular to the upper surface of the first adhesive tape 1S.

[0106] Furthermore, the second shear force F_s2 can be applied in a direction away from the point where the first tensile force is applied. At least a portion of the second shear force F_s2 can be applied substantially parallel to the upper surface of the first tape sheet 1S. It is understood that the second shear force F_s2 may arise due to the following material properties: the viscosity of the first tape sheet 1S changes according to external force or deformation conditions because it comprises a polymer composition containing a thixotropic agent.

[0107] The viscosity of the adhesive layer 10 of the first tape sheet 1S can be reduced by the first pressure F_d and the second shear force F_s2. Therefore, at least a portion of the adhesive layer 10 can be elongated in the upward direction D3, for example, by being stretched.

[0108] The adhesive layer 10 can be completely removed from the first semiconductor chip 100C1, and no residue is left between the bonding pads 132.

[0109] refer to Figure 7 , Figure 14A , Figure 14B and Figure 14C Multiple substrate wafers 200W1, 200W2 and 200W3 can be provided, and each of the multiple separate semiconductor chips (e.g. 100C1, 100C2 and 100C3) can be formed on the multiple substrate wafers 200W1, 200W2 and 200W3 respectively (S70).

[0110] Multiple substrate wafers 200W1, 200W2, and 200W3 may be provided. The multiple substrate wafers 200W1, 200W2, and 200W3 may include, for example, a first substrate wafer to a third substrate wafer 200W1, 200W2, and 200W3. Each of the first to third substrate wafers 200W1, 200W2, and 200W3 may include multiple preliminary substrate chips distinguished from each other by scribing lines SL.

[0111] You can refer to Figure 13 Each of the described separate first to third semiconductor chips 100C1, 100C2, and 100C3 has a lower passivation layer formed around the connection pad 132 (e.g., Figure 15C "PSV1" or Figure 16C (PSV11 in the text). Subsequently, the first semiconductor chip to the third semiconductor chips 100C1, 100C2, and 100C3 can be formed on the first substrate wafer to the third substrate wafer 200W1, 200W2, and 200W3, respectively. For example, the first semiconductor chip 100C1 can be formed on the first substrate wafer 200W1 (see...). Figure 14A The second semiconductor chip 100C2 can be formed on the second substrate wafer 200W2 (see...). Figure 14B Furthermore, the third semiconductor chip 100C3 can be formed on the third substrate wafer 200W3 (see [reference]). Figure 14C ).

[0112] Each of the first to third substrate wafers 200W1, 200W2, and 200W3 may include a preliminary substrate chip classified at a level substantially the same as the level assigned to the corresponding first to third semiconductor chips 100C1, 100C2, and 100C3. For example, the first substrate wafer 200W1 may include a first preliminary substrate chip classified at a first level (see [link to documentation]). Figure 14A The second substrate wafer 200W2 may include a second preliminary substrate chip classified as a second level (see [link to relevant documentation]). Figure 14B ), and the third substrate wafer 200W3 may include a third preliminary substrate chip classified as the third level (see Figure 14C ).

[0113] Subsequently, in some example embodiments, the first substrate wafer 200W1 can be diced along the scribing line SL, and a molding layer can be formed. Figure 15A "260" in the middle and connecting bump ( Figure 15A The “236” in the middle, thus forming a semiconductor device ( Figure 15A (Refer to "1000Sa" in the original text). Figure 15A and Figure 15B A more detailed description of the semiconductor device 1000Sa.

[0114] Subsequently, in some example embodiments, a plurality of first semiconductor chips 100C1 can be formed on the first semiconductor chip 100C1, and the first substrate wafer 200W1 can be cut along the scribing line SL, and a molding layer can be formed. Figure 16A "260" in the middle and connecting bump ( Figure 16A (236 in the text). Therefore, a first substrate chip ( Figure 16A The semiconductor device 1000Sb consists of "200" in the figure and multiple first semiconductor chips 100C1 stacked on a first substrate chip. See also: Figure 16A , Figure 16B and Figure 16C The semiconductor device 1000Sb is described in more detail. A semiconductor device comprising a second substrate chip and a plurality of second semiconductor chips 100C2 stacked on the second substrate chip, and a semiconductor device comprising a third substrate chip and a plurality of third semiconductor chips 100C3 stacked on the third substrate chip, can also be formed in substantially the same manner as the semiconductor device 1000Sb.

[0115] Figure 15A This is a perspective view showing a semiconductor device 1000Sa according to some example embodiments. Figure 15B It is along Figure 15A The cross-sectional view taken from line II-II' in the diagram. Figure 15C It shows Figure 15B An enlarged view of region "B" in the image.

[0116] refer to Figure 15A , Figure 15B and Figure 15C The semiconductor device 1000Sa may include two or more semiconductor chips, for example, a first semiconductor chip 100C1 and a substrate chip 200 facing each other in the vertical direction D3. In some example embodiments, the semiconductor device 1000Sa may be referred to as a semiconductor chip stack structure.

[0117] In an example implementation, the first semiconductor chip 100C1 may include a reference. Figure 8 , Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 11C , Figure 12 , Figure 13 , Figure 14A , Figure 14B and Figure 14C The first semiconductor chip 100C1 is described.

[0118] In an example implementation, the substrate chip 200 may include a reference. Figure 14A , Figure 14B and Figure 14C The first substrate wafer 200W1 is described as having multiple substrate chips.

[0119] Two or more first semiconductor chips 100C1 may be disposed on a substrate chip 200. The first semiconductor chips 100C1 and the substrate chip 200 may include chiplets forming a multi-chip module (MCM). In an example embodiment, the semiconductor device 1000Sa may also include a molding layer 260 that encapsulates at least a portion of each of the first semiconductor chips 100C1 and the substrate chip 200. The molding layer 260 may include, for example, an epoxy molding compound (EMC), but the material of the molding layer 260 is not limited to any particular example.

[0120] The first semiconductor chip 100C1 and the substrate chip 200 can be bonded and coupled to each other via metal-to-metal bonding and dielectric bonding. The semiconductor device 1000Sa may have a bonding surface BS, at which the first lower pad PD1 and the first passivation layer PSV1 of the first semiconductor chip 100C1 are bonded and coupled to the second upper pad PD22 and the second passivation layer PSV2 of the substrate chip 200.

[0121] The first semiconductor chip 100C1 may include a first substrate 110, a first circuit layer 120, a first passivation layer PSV1, and a plurality of first lower pads PD1.

[0122] The first substrate 110 may be a semiconductor substrate. For example, the first substrate 110 may include semiconductor elements such as silicon and germanium, or compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The first substrate 110 may include a conductive region 112 and an isolation region 113 formed on a surface 110S. The conductive region 112 may be, for example, a doped well or a doped structure. The isolation region 113 may be a device isolation structure with a shallow trench isolation (STI) structure and may include silicon oxide.

[0123] The first circuit layer 120 may be disposed on a surface 110S of the first substrate 110 where a conductive region 112 is formed. The first circuit layer 120 may include a separate device ID, a first insulating layer IL1, and a first interconnect IC1. Hereinafter, the first insulating layer IL1 may be referred to as a front insulating layer or interlayer insulating layer 121. The first interconnect IC1 may be referred to as an interconnect structure 125.

[0124] A separate device ID may be disposed on a surface 110S of the first substrate 110. The separate device ID may be electrically connected to the conductive region 112. The separate device ID may include various active and / or passive devices, such as FETs (e.g., planar FETs or FinFETs), memory devices (e.g., flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, FeRAM, RRAM), logic devices (e.g., AND, OR, NOT), system LSIs, CIS, MEMS, etc.

[0125] Interlayer insulating layer 121 can be formed to cover individual device IDs and interconnect structures 125, and can electrically isolate the individual device IDs disposed on the first substrate 110. Interlayer insulating layer 121 may include flowable oxide (FOX), TOSZ, undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate-phosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluorinated silicate glass (FSG), high-density plasma oxide (HDP), plasma-enhanced oxide (PEOX), flowable chemical vapor deposition (FCVD) oxide, or combinations thereof. At least a portion of the region of interlayer insulating layer 121 surrounding interconnect structure 125 may be configured as a low-k dielectric layer. Interlayer insulating layer 121 can be formed using chemical vapor deposition (CVD), flowable CVD processes, or spin-coating processes.

[0126] The interconnect structure 125 can be formed as a multilayer structure including multiple interconnect patterns and multiple vias, for example, formed of aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or combinations thereof. A barrier film (not shown) including titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) can be provided between the interconnect patterns and / or vias and the interlayer insulating layer 121. The interconnect structure 125 can be electrically connected to individual devices ID via interconnect portions 123 (e.g., contact plugs). The interconnect structure 125 can include signal interconnects, power interconnects, and ground interconnects.

[0127] The first interconnect IC1 may include a first intermediate conductor MC1 and a first uppermost conductor TC1. Hereinafter, the first uppermost conductor TC1 may be referred to as a "connector conductor". The first intermediate conductor MC1 may be disposed in the first insulating layer IL1. The first intermediate conductor MC1 may be located between a surface 110S of the first substrate 110 and the first uppermost conductor TC1. The first uppermost conductor TC1 may be located in the vertical direction D3 between the first intermediate conductor MC1 and a plurality of first lower pads PD1. The first uppermost conductor TC1 may include aluminum (Al) or an alloy thereof, but some exemplary embodiments are not limited thereto. In exemplary embodiments, the first uppermost conductor TC1 may include a material similar to the first intermediate conductor MC1, such as copper (Cu) or an alloy thereof.

[0128] Multiple first lower pads PD1 can be disposed on the first interconnect IC1. The multiple first lower pads PD1 can be electrically connected to the first interconnect IC1 via a first uppermost conductor TC1. The multiple first lower pads PD1 can include at least one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). For example, the multiple first lower pads PD1 can include at least one of copper (Cu) or its alloys. The multiple first lower pads PD1 can correspond to a reference. Figure 8 , Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 11C , Figure 12 , Figure 13 , Figure 14A , Figure 14B and Figure 14C The connection pad 132 is described. In some example embodiments, for ease of description, the connection pad 132 may be referred to as the front pad. At least a portion of the plurality of first lower pads PD1 may be in direct contact with the second upper pad PD22 of the substrate chip 200.

[0129] Multiple second upper pads PD22 may be disposed on the through electrode 240. The multiple second upper pads PD22 may be electrically connected to the second interconnect IC2 via the through electrode 240. The multiple second upper pads PD22 may include at least one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). For example, the multiple second upper pads PD22 may include at least one of copper (Cu) or its alloys. To distinguish the positions of components in the substrate chip 200, the multiple second upper pads PD22 may be referred to as back surface pads 252. The back surface pads 252 may be electrically connected to the second interconnect IC2 and / or the second upper surface pads 232 via the through electrode 240.

[0130] A first passivation layer PSV1 may be formed to surround the side surfaces of a plurality of first lower pads PD1. The first passivation layer PSV1 may form a bonding surface BS to provide dielectric bonding between the plurality of first lower pads PD1. The first passivation layer PSV1 may include, for example, silicon oxide (SiO) and / or silicon carbonitride (SiCN). The first passivation layer PSV1 may be in direct contact with a second passivation layer PSV2 of the substrate chip 200.

[0131] A second passivation layer PSV2 may be formed to surround the side surface of the second upper pad PD22. The second passivation layer PSV2 may form a bonding surface BS to provide dielectric bonding between the plurality of second upper pads PD22. The second passivation layer PSV2 may include, for example, silicon oxide (SiO) and / or silicon carbonitride (SiCN).

[0132] The substrate chip 200 can be disposed on one surface of the first semiconductor chip 100C1. The substrate chip 200 can be disposed in the direction along which a plurality of second upper pads PD22 are opposite to the front pads 132 of the first semiconductor chip 100C1.

[0133] The substrate chip 200 may include a second substrate 210, a second circuit layer 220, a second passivation layer PSV2, a plurality of second upper pads PD22, a through electrode 240, and a plurality of second lower pads PD21. The substrate chip 200 may include elements substantially similar to those of the first semiconductor chip 100C1, such as the second substrate 210, the second circuit layer 220, the second passivation layer PSV2, and the plurality of second lower pads PD21. Therefore, the same or similar elements may be referred to by the same or similar terms and / or reference numerals, and will not be described repeatedly below. The second insulating layer IL2 may be referred to as the front insulating layer or interlayer insulating layer 221, and the second interconnect portion IC2 may be referred to as the interconnect structure 225.

[0134] The through electrode 240 can penetrate one surface 210S1 and another surface 210S2 of the second substrate 210, and can electrically connect the second interconnect IC2 to a plurality of second upper pads PD22. One surface 210S1 of the second substrate 210 may be referred to as the front surface or the back surface depending on whether an active region 112 is formed therein. The through electrode 240 may include a via plug 245 and a side barrier layer 241 surrounding its side surface. The via plug 245 may include, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu), and may be formed by electroplating, PVD, or CVD processes. The side barrier layer 241 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and may be formed by electroplating, PVD, or CVD processes. A side insulating film (not shown) may be formed between the side barrier layer 241 and the second substrate 210. The side insulating film includes an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride (e.g., high aspect ratio process (HARP) oxide).

[0135] The through electrode 240 can penetrate an insulating protective layer 213 formed on a surface 210S1 of the second substrate 210. The insulating protective layer 213 may include, for example, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), or silicon carbonitride (SiCN). A buffer film 214 (e.g., a polishing stop layer or a barrier layer) may be disposed on the insulating protective layer 213. For example, the buffer film may include silicon nitride, silicon carbide, silicon oxynitride, or silicon carbonitride.

[0136] Multiple second lower pads PD21 may be disposed on another surface 210S2 of the second substrate 210. The multiple second lower pads PD21 may be referred to as front pads 232. The multiple second lower pads PD21 may be connected to a connection bump 236. The connection bump 236 may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or alloys thereof.

[0137] Figure 16A This is a perspective view showing a semiconductor device 1000Sb according to some example embodiments. Figure 16B It is along Figure 16A The cross-sectional view taken from line III-III' in the diagram. Figure 16C It shows Figure 16B An enlarged view of region "B" in the image.

[0138] refer to Figure 16A , Figure 16B and Figure 16C The semiconductor device 1000Sb can be configured to be related to a reference. Figures 15A to 15CThe described examples are the same or similar, except for the configuration in which multiple first semiconductor chips 100C11, 100C12, 100C13, and 100C14 are stacked on the substrate chip 200 in the vertical direction D3. In some example embodiments, the semiconductor device 1000Sb may be referred to as a semiconductor chip stack structure.

[0139] In an example implementation, each of the plurality of first semiconductor chips 100C11, 100C12, 100C13, and 100C14 may include a reference. Figure 8 , Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 11C , Figure 12 , Figure 13 , Figure 14A , Figure 14B and Figure 14C The first semiconductor chip 100C1 is described.

[0140] In an example implementation, the substrate chip 200 may include a reference. Figure 14A , Figure 14B and Figure 14C The first substrate wafer 200W1 is described as having multiple substrate chips.

[0141] The plurality of first semiconductor chips 100C11, 100C12, 100C13, and 100C14 may include the uppermost first semiconductor chip 100C14 and the first semiconductor chips 100C11, 100C12, and 100C13 between the uppermost first semiconductor chip 100C14 and the substrate chip 200. The plurality of first semiconductor chips 100C11, 100C12, 100C13, and 100C14 may include reference... Figures 15A to 15C The components of the first semiconductor chip 100C1 described are the same or similar. However, some of the first semiconductor chips 100C11, 100C12, and 100C13, other than the topmost first semiconductor chip 100C14, may also include a first through electrode 140, a first upper pad PD12, and a first upper passivation layer PSV12. The upper surface of the topmost first semiconductor chip 100C14 may not be covered by the molding layer 260, or in the example embodiment, the upper surface may be covered by the molding layer 260. The number of semiconductor chips stacked on the substrate chip 200 is not limited. For example, the number of semiconductor chips may include 8, 12, or 20.

[0142] The first through electrode 140 can penetrate one surface 110S1 and another surface 110S2 of the first substrate 110, and can electrically connect the first interconnect IC1 to the first upper pad PD12. The first through electrode 140 may include a via plug 145 and a side barrier layer 141 surrounding its side surface. The via plug 145 may include, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu), and can be formed by electroplating, PVD, or CVD processes. The side barrier layer 141 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and can be formed by electroplating, PVD, or CVD processes. A side insulating film (not shown) may be formed between the side barrier layer 141 and the first substrate 110, the side insulating film comprising an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride (e.g., HARP oxide).

[0143] The first upper pad PD12 may be disposed on the first through electrode 140. The first upper pad PD12 may be electrically connected to the first interconnect IC1 via the first through electrode 140. The first upper pad PD12 may include at least one of copper (Cu), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). For example, the first upper pad PD12 may include at least one of copper (Cu) or its alloys. To distinguish the positions of components in the first semiconductor chip 100, the first upper pad PD12 may be referred to as the back surface pad 152. The first upper pad PD12 may contact the first lower pad PD11 that is adjacent to each other in the vertical direction D3.

[0144] A first upper passivation layer PSV12 may be formed to surround the side surface of the second upper pad PD22. The first upper passivation layer PSV12 may form a bonding surface to provide dielectric bonding between the second upper pads PD22. The first upper passivation layer PSV12 may include, for example, silicon oxide (SiO) and / or silicon carbonitride (SiCN). The first upper passivation layer PSV12 may contact a first lower passivation layer PSV11 adjacent in the vertical direction D3.

[0145] In an example implementation, the substrate chip 200 may be a buffer chip or control chip including multiple logic devices and / or memory devices. The substrate chip 200 can transmit signals from the first semiconductor chips 100C11, 100C12, 100C13, and 100C14 stacked thereon to an external entity, and can also transmit signals and power from the external entity to the first semiconductor chips 100C11, 100C12, 100C13, and 100C14. The first semiconductor chips 100C11, 100C12, 100C13, and 100C14 may be memory chips including volatile memory devices such as DRAM and SRAM, or non-volatile memory devices such as PRAM, MRAM, FeRAM, or RRAM.

[0146] Figure 17 This is a perspective view showing a semiconductor device 1000Sc according to some example embodiments.

[0147] refer to Figure 17 The semiconductor device 1000Sc can be configured to be related to a reference. Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B and Figure 16C The described examples are the same or similar, except that they include a configuration of multiple first semiconductor chips 100C11, 100C12, and 100C13 disposed on the substrate chip 200 along horizontal directions D1 and D2. In some example embodiments, the semiconductor device 1000Sc may be referred to as a semiconductor chip stack structure.

[0148] In an example implementation, each of the plurality of first semiconductor chips 100C11, 100C12, and 100C13 may include a reference. Figure 8 , Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 11C , Figure 12 , Figure 13 , Figure 14A , Figure 14B and Figure 14C The first semiconductor chip 100C1 is described.

[0149] In an example implementation, the substrate chip 200 may include a reference. Figure 14A , Figure 14B and Figure 14C The first substrate wafer 200W1 is described as having multiple substrate chips.

[0150] Multiple first semiconductor chips 100C11, 100C12, and 100C13, along with the substrate chip 200, can be chips included in a multi-chip module (MCM). The multiple first semiconductor chips 100C11, 100C12, and 100C13 may include a first chip 100C11, a second chip 100C12, and a third chip 100C13. For example, the first chip 100C11 may be configured as a central processing unit (CPU), the second chip 100C12 may be configured as a graphics processing unit (GPU), and the third chip 100C13 may be configured as a field-programmable gate array (FPGA) chip. The substrate chip 200 may include I / O chips or active interposers. For example, the substrate chip 200 may include I / O devices, DC / DC converters, sensors, test circuits, etc.

[0151] The first chip 100C11, the second chip 100C12, and the third chip 100C13 can be bonded to each other on the substrate chip 200.

[0152] Figure 18A This is a plan view of a semiconductor device 1000Sd according to some example embodiments. Figure 18B It is along Figure 18A The cross-sectional view taken from line IV-IV' in the diagram.

[0153] refer to Figure 18A and Figure 18B The semiconductor device 1000Sd may include a packaging substrate 600, an interposer substrate 700, and at least one packaging structure PS1 and PS2. The number of at least one packaging structure PS1 and PS2 may be more or less than the example shown in the figure. In some example embodiments, the semiconductor device 1000Sd may be referred to as a semiconductor chip stack structure.

[0154] At least one package structure PS1 and PS2 may include a first package structure PS1 and a second package structure PS2, which are interconnected through an interposer substrate 700.

[0155] The first package structure PS1 can be a high-performance memory device, such as a high-bandwidth memory (HBM), a hybrid memory cube (HMC), etc. For example, the first package structure PS1 can be understood as being configured to be used with a reference... Figure 16A , Figure 16B and Figure 16C The examples described are the same as or similar semiconductor devices. The first package structure PS1 can be connected to the interposer substrate 700 via metal bumps BP.

[0156] The second package structure PS2 can be a bare chip or a packaged chip in which logic circuitry or memory circuitry is formed. In the example embodiment, the second package structure PS2 can be understood as being configured to be connected to a reference... Figure 17 The described example uses the same or similar stacked chip structure. The second package structure PS2 can be connected to the interposer substrate 700 via metal bumps BP. The second package structure PS2 may include semiconductor chips of a different type than the first package structure PS1. For example, the first package structure PS1 may include logic chips, and the second package structure PS2 may include memory chips.

[0157] The packaging substrate 600 may be a support substrate on which an interposer substrate 700 is mounted, and may be a substrate used for semiconductor packaging, including printed circuit boards (PCBs), ceramic substrates, glass substrates, tape interconnect substrates, etc. The packaging substrate 600 may include a lower pad 612, an upper pad 611, and interconnect circuitry 613. External connection bumps 620 connected to the lower pad 612 may be disposed on the lower surface of the packaging substrate 600. The external connection bumps 620 may include, for example, solder balls.

[0158] The interposer substrate 700 may include a substrate 701, a lower protective layer 703, a lower terminal 705, an interconnect structure 710, conductive bumps 720, and vias 730. The first package structure PS1 and the second package structure PS2 can be electrically connected to each other through the interposer substrate 700.

[0159] The substrate 701 can be formed as, for example, a silicon substrate, an organic substrate, a plastic substrate, and a glass substrate. When the substrate 701 is a silicon substrate, the interposer substrate 700 can be referred to as a silicon interposer. Unlike the example shown in the figure, when the substrate 701 is an organic substrate, the interposer substrate 700 can be referred to as a panel interposer.

[0160] The lower terminal 705 can be connected to the through-hole 730. The lower terminal 705 can be electrically connected to the package substrate 600 via the conductive bump 720.

[0161] Interconnect structure 710 may be disposed on the upper surface of substrate 701 and may include interlayer insulating layer 711 and single-layer or multi-layer interconnect structure 712. When interconnect structure 710 is configured as a multi-layer interconnect structure, interconnect patterns on different layers can be connected to each other through contact vias. Upper terminal 704 connected to interconnect structure 710 may be disposed on interconnect structure 710.

[0162] A via 730 can extend from the upper surface to the lower surface of substrate 701 and can penetrate substrate 701. For example, via 730 can extend into interconnect structure 710 and can be electrically connected to the interconnect portion of interconnect structure 710. When substrate 701 is a silicon substrate, via 730 can be referred to as TSV.

[0163] According to the foregoing exemplary embodiments, a tape sheet including an adhesive layer and a method for manufacturing a semiconductor device using the tape sheet can be provided, wherein the adhesive layer includes a polymer composition containing a thixotropic agent.

[0164] As used herein, the term “at least one of…” may refer to and cover any and all possible combinations of one or more of the associated listed terms. For example, the term “at least one of A, B or C” means: (i) at least one of A; (ii) at least one of B; (iii) at least one of C; (iv) at least one of A and at least one of B; (v) at least one of B and at least one of C; (vi) at least one of A and at least one of C; or (vii) at least one of A, at least one of B and at least one of C, wherein A, B and C may be singular or plural.

[0165] Although this specification contains numerous specific implementation details, these details should not be construed as limiting the scope of the claims or any invention, but rather as descriptions of features that may be specific to particular embodiments of the invention. In a single embodiment, certain features described in this specification within the context of separate embodiments may also be implemented in combination. Conversely, the various features described in the context of a single embodiment may also be implemented individually in multiple embodiments, or in any suitable sub-combination. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination may be removed from the combination in some cases, and combinations may be for sub-combinations or variations of sub-combinations.

[0166] While exemplary embodiments have been shown and described above, it will be clear to those skilled in the art that modifications and alterations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: Multiple semiconductor chips are formed on a wafer; By performing wafer testing on the wafer, the plurality of semiconductor chips are classified into a first semiconductor chip and a second semiconductor chip; Provide a first tape sheet and a second tape sheet; Transfer the first semiconductor chip to the first adhesive tape sheet; Transfer the second semiconductor chip to the second adhesive tape; and Provide a first substrate wafer and a second substrate wafer; Separating the first semiconductor chip from the first adhesive tape and forming the first semiconductor chip on the first substrate wafer; and The second semiconductor chip is separated from the second adhesive tape and formed on the second substrate wafer. Each of the first tape sheet and the second tape sheet includes an adhesive layer. The adhesive layer includes: The first part to which the corresponding semiconductor chip is adhered; and The second part, to which the first part and the supporting structure are attached. The first portion comprises a polymer composition containing a thixotropic agent, and The adhesive force of the second part is greater than that of the first part.

2. The method according to claim 1, wherein, The wafer testing includes Electrical Die Sorting (EDS) testing.

3. The method according to claim 1, wherein, The wafer testing includes classifying the plurality of semiconductor chips into multiple grades based on at least one of operating speed, current consumption, or threshold voltage range.

4. The method according to claim 1, wherein, The thixotropic agent is present in a weight ratio of 1 wt% to 5 wt% relative to the polymer composition.

5. The method according to claim 1, wherein, The thixotropic agent includes an oil-based thixotropic agent or an aqueous thixotropic agent.

6. The method according to claim 5, wherein, The oil-based thixotropic agent is selected from one or more of the following: fumed silica, polyamide wax, and hydrogenated castor oil.

7. The method according to claim 5, wherein, The aqueous thixotropic agent is selected from one or more of the following: synthetic silica and cellulose derivatives.

8. The method according to claim 1, in, Each of the first and second tape sheets further includes a base layer, and the adhesive layer is located on the base layer. The thickness of the adhesive layer is in the range of 10 μm to 50 μm, and The thickness of the substrate layer is in the range of 50 μm to 100 μm.

9. The method according to claim 1, in, The first semiconductor chip includes a lower passivation layer and a lower pad. The first substrate wafer includes an upper passivation layer and an upper pad. Wherein, the lower pad is bonded to the upper pad, and The lower passivation layer is bonded to the upper passivation layer.

10. The method according to claim 1, further comprising: A first semiconductor chip structure is formed by cutting the first substrate wafer into multiple first substrate chips; as well as The second semiconductor chip structure is formed by cutting the second substrate wafer into multiple second substrate chips.

11. The method according to claim 1, wherein, The first portion of the adhesive layer includes: The mounting area to which the corresponding semiconductor chip is adhered; and Non-installation areas other than the installation area.

12. The method according to claim 11, in, The non-installation area includes a portion extending along a first direction and a portion extending along a second direction perpendicular to the first direction, and The width of the non-installation area is in the range of 50μm to 100μm.

13. A method for manufacturing a semiconductor device, the method comprising: Multiple semiconductor chips are formed on a wafer; By performing wafer testing on the wafer, the plurality of semiconductor chips are classified into a first semiconductor chip group and a second semiconductor chip group; Provide a first tape sheet and a second tape sheet; Transfer the first semiconductor chipset to the first adhesive tape sheet; Transfer the second semiconductor chipset to the second adhesive tape sheet; Provide a first substrate wafer and a second substrate wafer; Separate the first semiconductor chip in the first semiconductor chip group from the first tape sheet; The first semiconductor chip is stacked sequentially on the first substrate wafer; Separate the second semiconductor chip from the second tape sheet in the second semiconductor chip assembly; and The second semiconductor chip is stacked sequentially on the second substrate wafer. Each of the first tape sheet and the second tape sheet includes an adhesive layer comprising a polymer composition containing a thixotropic agent.

14. The method according to claim 13, wherein, The transfer of the first semiconductor chipset and the second semiconductor chipset to the first tape and the second tape is performed under a first pressure.

15. The method according to claim 14, wherein, The viscosity of the adhesive layer decreases under the first pressure.

16. The method according to claim 13, wherein, The separation of the first semiconductor chip in the first semiconductor chip group and the second semiconductor chip in the second semiconductor chip group from the first tape and the second tape is performed under a first pulling force.

17. The method according to claim 16, wherein, The viscosity of the adhesive layer decreases under the first tensile force.

18. The method according to claim 16, wherein, At least a portion of the adhesive layer elongates in the vertical direction under the first tensile force.

19. A method for manufacturing a semiconductor device, the method comprising: By performing wafer testing on a wafer on which multiple semiconductor chips are formed, the multiple semiconductor chips are classified into multiple grades, and the multiple semiconductor chips include a first semiconductor chip of a first grade. Transfer each of the first semiconductor chips onto the adhesive tape; separate the first semiconductor chips from the adhesive tape; as well as The first semiconductor chip is stacked sequentially on the substrate wafer. The tape sheet includes a thixotropic adhesive layer, which comprises a polymer composition containing a thixotropic agent. The thixotropic agent is present in a weight ratio of 1 wt% to 5 wt% relative to the polymer composition.

20. The method according to claim 19, wherein, The substrate wafer includes multiple preliminary substrate chips, each of which is at the same level as the first level.

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