Display panel, test method thereof and display device

Abstract

The application discloses a display panel and a testing method thereof and a display device. The display panel has a display area and a frame area surrounding the display area at least partially. The display panel comprises a substrate, conductive layers arranged in a stack and insulated from each other, crack detection traces in each layer for the frame area, and the crack detection traces in different conductive layers overlap in the orthographic projection of the substrate. Light emitting units in the display area are arranged in an array along an intersecting direction. Data signal lines are connected to the light emitting units in the same column and are insulated and spaced. The testing circuit connects the crack detection traces in different conductive layers to different data signal lines respectively. When a crack causes the traces in a layer to break, the corresponding data signal line is disabled, triggering a light and dark line anomaly in the display area. The broken conductive layer and the crack extension direction are directly located by the abnormal position. Through the layered mapping of the crack detection traces and the data signal lines in the vertical stack, the crack position and the extension direction are accurately judged by the display feedback while the frame width is reduced, and the crack detection efficiency and accuracy are improved.

Description

Technical Field

[0001] This application relates to the field of display device technology, and in particular to a display panel and its testing method, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display panels and other flat panel display devices using light-emitting diode (LED) devices are widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED products needs to be improved. Summary of the Invention

[0004] This application provides a display panel and its testing method and display device, which can determine the specific location and extension direction of cracks in the display panel by observing display anomalies of light-emitting units at different positions within the display area.

[0005] In a first aspect, embodiments of this application provide a display panel having a display area and a border area at least partially surrounding the display area. The display panel further includes: a substrate; conductive layers disposed on one side of the substrate, at least two conductive layers being stacked and insulated from adjacent conductive layers, each conductive layer having a crack detection trace located in the border area, and at least two crack detection traces located in different conductive layers having their orthogonal projections on the substrate at least partially overlapping; light-emitting units located in the display area, a plurality of light-emitting units being arrayed along a first direction and a second direction, the first direction and the second direction intersecting; data signal lines connected to the light-emitting units in the same column, a plurality of data signal lines being arranged side-by-side with spacing and insulation; and a test circuit connected between the crack detection traces and the data signal lines, with the crack detection traces in different conductive layers being connected to different data signal lines through the test circuit.

[0006] The display panel provided in the first aspect of this application, by setting multiple conductive layers and arranging crack detection traces in different conductive layers in the frame area, makes the orthogonal projection portions of at least two traces located in different conductive layers overlap on the substrate, thereby narrowing the width of the frame area. At the same time, by combining the test circuit, the crack detection traces of different conductive layers are connected to different data signal lines respectively. The display anomalies of light-emitting units at different positions realize high-precision detection of the location of the fractured conductive layer and the direction of crack extension.

[0007] According to any embodiment of the first aspect of this application, the display panel further includes a touch module, the touch module includes touch electrodes located in the display area, and at least one conductive layer is simultaneously provided with crack detection traces and touch electrodes.

[0008] According to any embodiment of the first aspect of this application, the conductive layer includes a first type of conductive layer and a second type of conductive layer, the second type of conductive layer is disposed on the side of the first type of conductive layer away from the substrate, and the touch electrode is disposed in the second type of conductive layer;

[0009] According to any embodiment of the first aspect of this application, the first type of conductive layer includes a first conductive layer, a second conductive layer and a third conductive layer stacked sequentially along the direction away from the substrate, and the crack detection trace includes a first sub-trace, a second sub-trace and a third sub-trace, wherein the first sub-trace is located in the first conductive layer, the second sub-trace is located in the second conductive layer and the third sub-trace is located in the third conductive layer.

[0010] According to any embodiment of the first aspect of this application, the data signal line includes a first data line, a second data line, and a third data line extending along a second direction and spaced apart along a first direction. A plurality of light-emitting units form at least a first column light-emitting group, a second column light-emitting group, and a third column light-emitting group arranged along the second direction. The first data line is sequentially connected to the light-emitting units in the first column light-emitting group, the second data line is sequentially connected to the light-emitting units in the second column light-emitting group, and the third data line is sequentially connected to the light-emitting units in the third column light-emitting group. The first sub-line, the second sub-line, and the third sub-line are respectively connected to the first data line, the second data line, and the third data line through a test circuit.

[0011] According to any embodiment of the first aspect of this application, the second type of conductive layer includes a fourth conductive layer and a fifth conductive layer stacked along the direction away from the substrate, the crack detection trace further includes a fourth sub-trace and a fifth sub-trace, and the touch electrode includes a first sub-electrode and a second sub-electrode, the first sub-electrode and the fourth sub-trace are located in the fourth conductive layer, and the second sub-electrode and the fifth sub-trace are located in the fifth conductive layer.

[0012] According to any embodiment of the first aspect of this application, the data signal line further includes a fourth data line and a fifth data line extending along the second direction and spaced apart along the first direction. A plurality of light-emitting units form a fourth light-emitting group and a fifth light-emitting group arranged along the second direction. The fourth data line is sequentially connected to the light-emitting units in the fourth light-emitting group, and the fifth data line is sequentially connected to the light-emitting units in the fifth light-emitting group. The fourth sub-line and the fifth sub-line are respectively connected to the fourth data line and the fifth data line through a test circuit.

[0013] According to any embodiment of the first aspect of this application, in any two conductive layers, the width of the crack detection trace in the conductive layer facing away from the substrate is smaller than the width of the crack detection trace in the conductive layer facing closer to the substrate.

[0014] According to any embodiment of the first aspect of this application, in any two conductive layers, the orthogonal projection of the crack detection trace in the conductive layer facing away from the substrate onto the substrate is located within the orthogonal projection of the crack detection trace in the conductive layer facing closer to the substrate onto the substrate.

[0015] According to any embodiment of the first aspect of this application, the border area further includes a first border sub-area and a second border sub-area located on opposite sides of the display area along the first direction, and the crack detection wiring further includes a first wiring group and a second wiring group, the first wiring group being located in the first border sub-area and the second wiring group being located in the second border sub-area.

[0016] According to any embodiment of the first aspect of this application, the first wiring group includes a plurality of first wiring segments located in different conductive layers, and the second wiring group includes a plurality of second wiring segments located in different conductive layers, wherein the orthographic projections of at least two first wiring segments or at least two second wiring segments on the substrate at least partially overlap.

[0017] According to any embodiment of the first aspect of this application, the display area is square, and the first and second trace segments located in the same conductive layer in the first and second trace groups are symmetrical about the central axis of the display area along the second direction.

[0018] According to any embodiment of the first aspect of this application, the display panel further includes a control signal line and a test signal line. The test signal line is connected to the end of the crack detection trace away from the test circuit. The test circuit includes at least one switch. The switch is connected between the data signal line and the crack detection trace. The control terminal of the switch is connected to the control signal line. The switch responds to the control signal of the control signal line to turn on or off the data signal line and the crack detection trace.

[0019] According to any embodiment of the first aspect of this application, the switches include a plurality of switches, and are arranged in a one-to-one correspondence with the data signal lines;

[0020] According to any embodiment of the first aspect of this application, the switch includes a transistor, the first electrode of the transistor is connected to a crack detection trace, the second electrode of the transistor is connected to a data signal line, and the gate of the transistor is connected to a control signal line.

[0021] Secondly, embodiments of this application provide a display device, including the display panel provided in any of the embodiments of the first aspect of this application.

[0022] Thirdly, embodiments of this application provide a method for testing a display panel, employing the display panel provided in any of the embodiments of the first aspect of this application. The method for testing the display panel includes:

[0023] Turn on the test circuit;

[0024] The test circuit responded, and the crack detection traces and data signal lines became connected. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the overall structure of a display panel provided in the first aspect embodiment of this application;

[0027] Figure 2 This is a schematic planar structure diagram of one conductive layer of a display panel provided in the first aspect embodiment of this application;

[0028] Figure 3 This is a schematic diagram of the bezel area stacking structure of a display panel provided in the first aspect embodiment of this application;

[0029] Figure 4 This is a schematic diagram of the structure of the conductive layer of another display panel provided in the first aspect embodiment of this application;

[0030] Figure 5 This is a schematic diagram of the overall structure of a display device provided in the second aspect embodiment of this application;

[0031] Figure 6 This is a schematic flowchart of a testing method for a display panel provided in the third aspect embodiment of this application.

[0032] Marker explanation:

[0033] 100 - Display panel; AA - Display area; NA - Bezel area; NA1 - First bezel sub-area; NA2 - Second bezel sub-area;

[0034] 10-Substrate;

[0035] 20 - Conductive layer; 21 - First type of conductive layer; 211 - First conductive layer; 212 - Second conductive layer; 213 - Third conductive layer; 22 - Second type of conductive layer; 224 - Fourth conductive layer; 225 - Fifth conductive layer;

[0036] 201 - Crack detection trace; 201a - First sub-trace; 201b - Second sub-trace; 201c - Third sub-trace; 201d - Fourth sub-trace; 201e - Fifth sub-trace;

[0037] 2011 - First wiring group; 2011a - First wiring segment; 2012 - Second wiring group; 2012a - Second wiring segment;

[0038] 30 - Light-emitting unit; 31 - First column of light-emitting group; 32 - Second column of light-emitting group; 33 - Third column of light-emitting group; 34 - Fourth column of light-emitting group; 35 - Fifth column of light-emitting group;

[0039] 40 - Data signal line; 41 - First data line; 42 - Second data line; 43 - Third data line; 44 - Fourth data line; 45 - Fifth data line;

[0040] 50 - Test circuit; 51 - Switch; 511 - First electrode; 512 - Second electrode; 513 - Gate;

[0041] 60 - Touch module; 61 - Touch electrode; 611 - First sub-electrode; 612 - Second sub-electrode;

[0042] 70 - Control signal line;

[0043] 80 - Test signal line;

[0044] 200 - Display device;

[0045] X - First direction; Y - Second direction. Detailed Implementation

[0046] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0047] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0048] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations of the invention that fall within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0049] In the field of display panel manufacturing, the narrow bezel design of liquid crystal display (LCD) and organic light-emitting diode (OLED) panels has become an industry trend. However, this has led to a significant increase in the risk of cracks in the bezel area due to collisions or compression during the processing, transportation, and assembly of the panels.

[0050] Traditional panel crack detection (PCD) technology mainly relies on two methods:

[0051] One approach is to set up resistance test pads in the border area to determine the breakage by measuring the impedance change of the crack detection trace, such as an abnormal increase in impedance or a direct break.

[0052] Secondly, the crack detection trace is connected to the display control circuit. When the trace breaks, a bright or dark line appears in the corresponding display area, and the location of the crack is fed back through the display screen.

[0053] However, as panel bezel widths continue to shrink, traditional planar single-layer crack detection wiring designs are difficult to adapt to the requirements of ultra-narrow bezels due to their excessive horizontal space occupation.

[0054] In existing technologies, to solve the space constraint problem, a multi-layer metal stacked trace layout is usually adopted, and its implementation methods can be divided into two categories:

[0055] First, the wiring on each layer is arranged independently in the vertical direction, and is isolated by an insulation layer to achieve parallel connection without interference;

[0056] Secondly, by connecting the traces of different layers in series through the transponder (Via), a continuous and extended detection path is formed.

[0057] Among them, the mainstream solutions mostly adopt a series stacked structure, that is, the multi-layer crack detection traces are connected in series into a single detection loop through the wire replacement hole, and then the fracture film layer is located by impedance measurement.

[0058] For example, if a PCD trace breaks in a certain layer, the overall loop impedance will change significantly, and the layer where the break occurs can be roughly inferred through segmented testing.

[0059] However, this tandem stacking scheme has obvious drawbacks:

[0060] First, the design of multiple windings and wire replacement holes increases the complexity of the process and is prone to short circuit risk due to misalignment between layers.

[0061] Secondly, the series circuit can only determine whether a fracture has occurred, but cannot accurately locate the specific film layer of the fracture and the direction of crack propagation. Especially in the multi-layer overlapping area, it can only detect individual film layers where microcracks occur, but cannot detect the direction of crack propagation and other film layers affected, leading to misjudgment or missed detection.

[0062] Furthermore, if the existing technology adopts a parallel independent trace design, the detection circuits of each layer do not interfere with each other. Although the fracture layer can be located by measuring the layer impedance, test pads need to be set separately for each trace, which further encroaches on the bezel space and goes against the goal of narrow bezel design.

[0063] Therefore, how to achieve spatial optimization of crack detection traces under extremely narrow frame conditions, and simultaneously improve the accuracy of fracture film positioning and crack propagation direction judgment, has become a technical challenge that the industry urgently needs to overcome.

[0064] In view of the consideration and technical needs of solving the above-mentioned technical problems, the present application provides a display panel and its testing method and display device.

[0065] The following is combined Figures 1 to 5 The present application provides a detailed description of the display panel, its testing method, and the display device provided in the embodiments.

[0066] Figure 1 This illustrates the overall structure of a display panel 100 provided in the first aspect embodiment of this application. Figure 2 This illustration shows a planar structure of one conductive layer 20 of a display panel 100 provided in the first aspect embodiment of this application. Figure 3This illustrates a border area NA layered structure of a display panel 100 provided in a first aspect embodiment of this application.

[0067] Please see Figures 1 to 3 In a first aspect, embodiments of this application provide a display panel 100 having a display area AA and a border area NA that at least partially surrounds the display area AA. The display panel 100 also includes a substrate 10, a conductive layer 20, a light-emitting unit 30, a data signal line 40, and a test circuit 50.

[0068] A conductive layer 20 is disposed on one side of the substrate 10. At least two conductive layers 20 are stacked and insulated from each other. Each conductive layer 20 has a crack detection line 201. The crack detection line 201 is located in the border area NA, and the orthogonal projections of at least two crack detection lines 201 located in different conductive layers 20 on the substrate 10 at least partially overlap.

[0069] The light-emitting unit 30 is located in the display area AA. Multiple light-emitting units 30 are arranged in an array along the first direction X and the second direction Y, and the first direction X and the second direction Y intersect.

[0070] Data signal lines 40 are connected to light-emitting units 30 in the same column, and multiple data signal lines 40 are arranged side by side with spacing and insulation.

[0071] The test circuit 50 is connected between the crack detection trace 201 and the data signal line 40, and the crack detection trace 201 in different conductive layers 20 is connected to different data signal lines 40 through the test circuit 50.

[0072] The display panel 100 provided in the first aspect embodiment of this application, by setting multiple conductive layers 20 and arranging crack detection traces 201 in different conductive layers 20 in the frame area NA, makes the orthogonal projection portions of at least two traces located in different conductive layers 20 overlap on the substrate 10, thereby narrowing the width of the frame area NA. At the same time, in conjunction with the test circuit 50, the crack detection traces 201 of different conductive layers 20 are respectively connected to different data signal lines 40. The display anomalies of the light-emitting units 30 at different positions realize high-precision detection of the position of the fractured conductive layer 20 and the direction of crack extension.

[0073] When a crack detection trace 201 of a conductive layer 20 breaks due to a crack in the bezel area NA of the display panel 100, the data signal line 40 corresponding to the conductive layer 20 cannot drive the light-emitting unit 30 of the corresponding column due to the interruption of the test circuit 50, resulting in an abnormal display of bright and dark lines in a specific column of the display area AA.

[0074] By observing the location of the display anomaly in the display panel 100, the fractured conductive layer 20 can be directly located. At the same time, by combining the display anomalies in multiple areas, the propagation path of the crack between the multiple conductive layers 20 can be determined.

[0075] The display panel 100 provided in the first aspect embodiment of this application upgrades the traditional planar layout of single detection to layered positioning by using the layered mapping relationship between the vertically stacked crack detection traces 201 and the data signal lines 40. This not only solves the problem of insufficient space under narrow bezels, but also uses the display feedback mechanism to intuitively reveal the location and extension trend of the conductive layer 20 where the crack is located, significantly improving detection efficiency and accuracy.

[0076] The substrate 10 serves as a basic support film layer, supporting other functional film layers in the display panel 100 and playing a basic support role.

[0077] Optionally, the substrate 10 may include a rigid substrate 10 material such as glass or a flexible substrate 10 material such as polyimide (PI).

[0078] The conductive layer 20 is used to set the multi-layer array lines and metal traces in the display panel 100. The multi-layer traces or lines are patterned by etching or vapor deposition processes and separated by insulating materials. The traces or lines that need to be connected to each other are connected across layers through the line exchange holes opened on the insulating layer.

[0079] The data signal line 40 carries the driving signal and injects it into the light-emitting unit 30, driving the light-emitting unit 30 to realize the functions of light emission and display.

[0080] For example, the test circuit 50 is located in the bezel area NA and serves as a detection line in the module stage of the display panel 100, enabling various detection functions. The specific configuration and functions of the test circuit 50 will be further described in the following embodiments of the first aspect of this application.

[0081] In the display panel 100 provided in the first aspect embodiment of this application, the technical feature that "at least two crack detection traces 201 located in different conductive layers 20 have at least partially overlapping orthogonal projections on the substrate 10" should be understood as specifically referring to the fact that the layout of crack detection traces 201 in different conductive layers 20 in the vertical direction has a projection overlap area. By replacing the lateral expansion of the traditional single-layer planar traces with vertical spatial superposition, the horizontal width of the bezel area NA is significantly reduced, thereby realizing the narrow bezel design of the display product.

[0082] Among them, adjacent conductive layers 20 are isolated by an insulating layer to ensure that the crack detection traces 201 of each layer are arranged independently and do not short-circuit with each other. At the same time, the vertical stacking of the overlapping area maximizes the use of the limited space of the border area NA.

[0083] The technical feature that “crack detection traces 201 in different conductive layers 20 are connected to different data signal lines 40 through test circuit 50” should be understood as that test circuit 50 binds each crack detection trace 201 in conductive layer 20 to an independent data signal line 40 in display area AA in a one-to-one correspondence.

[0084] When a crack detection trace 201 in a certain conductive layer 20 breaks due to a crack in the frame area NA, the corresponding data signal line 40 cannot provide a driving signal to the connected light-emitting unit 30 due to the interruption of the test circuit 50, resulting in a display abnormality in the column or area associated with the data signal line 40 in the display area AA.

[0085] For example, if the display panel 100 is normally in a dark state, such as the OLED panel in a screen-off state, the failure of the data signal line 40 corresponding to the broken conductive layer 20 will prevent the column of light-emitting units 30 from being turned off, thus presenting an abnormal bright line against a dark background.

[0086] Conversely, if the normal state is bright, such as the full-screen display state of the OLED panel, the failure of the data signal line 40 corresponding to the broken conductive layer 20 will prevent the light-emitting unit 30 in that column from lighting up, resulting in an abnormal dark line against the bright background.

[0087] By identifying the specific location of the bright / dark line anomaly in display area AA, it can be directly mapped to the layer where the fractured conductive layer 20 is located. For example, a fracture in the upper conductive layer 20 corresponds to an anomaly in the left light-emitting unit 30, and a fracture in the lower layer corresponds to an anomaly in the right light-emitting unit 30. At the same time, by combining the anomaly's expansion trend to adjacent columns or areas, such as bright / dark lines distributed in adjacent columns or areas, the longitudinal propagation path of the fracture between the multiple conductive layers 20 can be deduced.

[0088] Furthermore, the technical features of the test circuit 50 can reuse the original panel test circuit 50 (CellTest, CT) in the display panel 100. By using the switch 51 element in the shared test circuit 50, the connection between the data signal line 40 and the crack detection trace 201 is controlled. During the detection phase, the switch 51 is closed to establish a connection, and during the normal display phase, the switch 51 is opened to avoid interference. This reduces the space occupied by additional circuits and combines the crack detection function with the display driver through a layered mapping mechanism, thereby achieving a coordinated response between the detection signal and the display feedback.

[0089] Please continue reading. Figures 1 to 3 In some embodiments, the display panel 100 further includes a touch module 60, which includes a touch electrode 61 located in the display area AA, and at least one conductive layer 20 simultaneously provides a crack detection trace 201 and a touch electrode 61.

[0090] In these embodiments, the display panel 100 further integrates a touch module 60, wherein at least one conductive layer 20 simultaneously provides a crack detection trace 201 and a touch electrode 61. By reusing the space of the conductive layer 20, the touch electrode 61 and the crack detection trace 201 are arranged in the same layer. The touch electrode 61 is distributed in the display area AA for sensing user touch operations, while the crack detection trace 201 is located in the bezel area NA for detecting cracks. The two avoid signal interference through insulated trace spacing or cross-winding design.

[0091] In addition, the co-layer design of the touch electrode 61 and the crack detection trace 201 reduces the need for additional film layers through in-layer functional integration, avoiding the increase in border width and width due to the separate addition of touch layer or detection layer.

[0092] Please continue reading. Figures 1 to 3 In some embodiments, the conductive layer 20 includes a first conductive layer 21 and a second conductive layer 22, the second conductive layer 22 being disposed on the side of the first conductive layer 21 away from the substrate 10, and the touch electrode 61 being disposed within the second conductive layer 22.

[0093] In these embodiments, the touch electrode 61 is integrated within the second type of conductive layer 22.

[0094] The first type of conductive layer 21 is mainly used to arrange the array lines of the display area AA and the crack detection traces 201 of the border area NA, and the horizontal space is reduced by vertical overlapping design.

[0095] The second type of conductive layer 22 has a touch electrode 61 disposed on the upper layer away from the substrate 10, which not only avoids the touch signal being attenuated due to interference from the underlying circuit, but also utilizes the upper layer space to optimize touch sensitivity.

[0096] When touch electrodes 61 are simultaneously arranged in the second type of conductive layer 22, they form a layered functional partition with the crack detection trace 201 of the first type of conductive layer 21. The first type of conductive layer 21 is used for display signal transmission, and the second type of conductive layer 22 is used for touch signal transmission.

[0097] If the crack detection trace 201 of the first type of conductive layer 21 and the second type of conductive layer 22 breaks due to the crack in the frame, the light-emitting unit 30 in the display panel 100 can display the abnormality and accurately locate the specific conductive layer in the first type of conductive layer 21 and the second type of conductive layer 22.

[0098] In addition, the second conductive layer 22 is located on the side away from the substrate 10, and the touch electrode 61 is closer to the panel surface, which can improve touch accuracy.

[0099] Meanwhile, the insulation and isolation design between the second type of conductive layer 22 and the first type of conductive layer 21 can prevent crosstalk between touch signals and crack detection signals.

[0100] Please continue reading. Figures 1 to 3 In some embodiments, the first type of conductive layer 21 includes a first conductive layer 211, a second conductive layer 212, and a third conductive layer 213 stacked sequentially along the direction away from the substrate 10. The crack detection trace 201 includes a first sub-trace 201a, a second sub-trace 201b, and a third sub-trace 201c. The first sub-trace 201a is located in the first conductive layer 211, the second sub-trace 201b is located in the second conductive layer 212, and the third sub-trace 201c is located in the third conductive layer 213.

[0101] In these embodiments, the first type of conductive layer 21 is further refined into a first conductive layer 211, a second conductive layer 212 and a third conductive layer 213 stacked sequentially along the direction away from the substrate 10, and a first sub-trace 201a, a second sub-trace 201b and a third sub-trace 201c are respectively provided in each layer as crack detection traces 201.

[0102] The first sub-line 201a is located in the layer closest to the substrate 10, the second sub-line 201b is in the middle, and the third sub-line 201c is located in the layer furthest from the substrate 10. The three are isolated by an insulating layer to form a three-layer independent detection network in the vertical direction.

[0103] The first sub-trace 201a, the second sub-trace 201b, and the third sub-trace 201c extend horizontally in the border area NA and partially overlap in the orthographic projection area of ​​the substrate 10. By compressing the horizontal space through vertical stacking, the border width is reduced, thus achieving a narrow border design.

[0104] The first sub-trace 201a, the second sub-trace 201b, and the third sub-trace 201c are connected to independent data signal lines 40 through the test circuit 50. For example, the first sub-trace 201a corresponds to one of the data signal lines 40 on the left, the second sub-trace 201b corresponds to one of the data signal lines 40 in the middle, and the third sub-trace 201c corresponds to one of the data signal lines 40 on the right.

[0105] When a crack appears in the border area NA, if the break is located at the third sub-trace 201c of the third conductive layer 213, the corresponding data signal line 40 on the right side will be interrupted, triggering an abnormal bright / dark line display in the light-emitting unit 30 on the right side of the display area AA. If the crack penetrates to the second sub-trace 201b of the second conductive layer 212, the data signal line 40 in the middle will fail, and the abnormal display area AA will extend towards the light-emitting unit 30 in the middle. By observing the distribution hierarchy of the display abnormality, the longitudinal extension path of the crack in different directions can be determined.

[0106] In addition, the vertical coverage of the first sub-trace 201a, the second sub-trace 201b, and the third sub-trace 201c is wider, which can detect microcracks at different depths in the border area NA and avoid missed detection.

[0107] Please continue reading. Figures 1 to 3 In some optional embodiments, the data signal line 40 includes a first data line 41, a second data line 42, and a third data line 43 extending along the second direction Y and spaced apart along the first direction X. Multiple light-emitting units 30 form at least a first column light-emitting group 31, a second column light-emitting group 32, and a third column light-emitting group 33 arranged along the second direction Y. The first data line 41 is sequentially connected to the light-emitting units 30 in the first column light-emitting group 31, and the third data line 43 is sequentially connected to the light-emitting units 30 in the third column light-emitting group 33. The first sub-line 201a, the second sub-line 201b, and the third sub-line 201c are respectively connected to the first data line 41, the second data line 42, and the third data line 43 via the test circuit 50.

[0108] In these optional embodiments, the data signal lines 40 extend along the second direction Y and are arranged at intervals along the first direction X as first data lines 41, second data lines 42, and third data lines 43. The light-emitting units 30 of the display area AA are correspondingly divided into a first column light-emitting group 31, a second column light-emitting group 32, and a third column light-emitting group 33 arranged along the second direction Y. The first data lines 41 are sequentially connected to the light-emitting units 30 in the first column light-emitting group 31, the second data lines 42 are sequentially connected to the light-emitting units 30 in the second column light-emitting group 32, and the third data lines 43 are sequentially connected to the light-emitting units 30 in the third column light-emitting group 33, forming a column-type architecture with independently driven signals.

[0109] Meanwhile, the first sub-trace 201a, the second sub-trace 201b, and the third sub-trace 201c in the first type of conductive layer 21 are respectively bound to the first data line 41, the second data line 42, and the third data line 43 through the test circuit 50. When a crack in the NA frame area causes a sub-trace to break, for example, when the third sub-trace 201c breaks, the third data line 43 cannot drive the third column of light-emitting group 33 because the test circuit 50 is disconnected, and the column displays abnormally, which can directly map the position of the third conductive layer 213 where the broken third sub-trace 201c is located.

[0110] If the crack simultaneously penetrates the second sub-trace 201b, the second column of light-emitting groups 32 will show abnormal expansion, indicating that the crack extends longitudinally from the third conductive layer 213 to the second conductive layer 212. By observing the order and range of abnormalities displayed in the columns corresponding to different data signal lines 40, the propagation direction and depth of the crack in the stacked conductive layers can be accurately determined.

[0111] In addition, the data signal lines 40 extend along the second direction Y and are arranged at intervals, so that the first column of light-emitting groups 31, the second column of light-emitting groups 32 and the third column of light-emitting groups 33 form an independent and controllable area in the display area AA, avoiding signal crosstalk and ensuring the positioning accuracy of abnormal displays.

[0112] The test circuit 50 can simultaneously detect the multi-layer crack state by activating the pathways between the first sub-trace 201a, the second sub-trace 201b, and the third sub-trace 201c and the first data line 41, the second data line 42, and the third data line 43, thereby reducing parallel signal interference.

[0113] Please continue reading. Figures 1 to 3 In some embodiments, the second type of conductive layer 22 includes a fourth conductive layer 224 and a fifth conductive layer 225 stacked along the direction away from the substrate 10, the crack detection trace 201 further includes a fourth sub-trace 201d and a fifth sub-trace 201e, and the touch electrode 61 includes a first sub-electrode 611 and a second sub-electrode 612. The first sub-electrode 611 and the fourth sub-trace 201d are located in the fourth conductive layer 224, and the second sub-electrode 612 and the fifth sub-trace 201e are located in the fifth conductive layer 225.

[0114] In these embodiments, crack detection traces 201 are provided in both the fourth conductive layer 224 and the fifth conductive layer 225 where the first sub-electrode 611 and the second sub-electrode 612 in the touch electrode 61 are located. The crack detection traces 201 are distributed in the fourth sub-trace 201d and the fifth sub-trace 201e of the fourth conductive layer 224 and the fifth conductive layer 225, which further increases the number of conductive layers that can be used to detect cracks and further improves the accuracy of crack detection.

[0115] The second type of conductive layer 22 is further refined into a fourth conductive layer 224 and a fifth conductive layer 225 stacked sequentially along the direction away from the substrate 10. A fourth sub-trace 201d and a fifth sub-trace 201e are respectively provided in each layer as crack detection traces 201.

[0116] The fourth sub-line 201d is located in the layer closest to the substrate 10, and the fifth sub-line 201e is located in the layer furthest from the substrate 10. The two are isolated by an insulating layer, forming two independent detection networks in the vertical direction.

[0117] The fourth sub-trace 201d and the fifth sub-trace 201e extend horizontally in the border area NA and partially overlap in the orthographic projection area of ​​the substrate 10. By compressing the horizontal space through vertical stacking, the border width is reduced, thus achieving a narrow border design.

[0118] The fourth sub-trace 201d and the fifth sub-trace 201e are respectively connected to independent data signal lines 40 through the test circuit 50. For example, the fourth sub-trace 201d corresponds to one of the data signal lines 40 on the left, and the fifth sub-trace 201e corresponds to one of the data signal lines 40 on the right.

[0119] When a crack appears in the border area NA, if the break is located at the fourth sub-trace 201d of the fourth conductive layer 224, the corresponding data signal line 40 on the left will be interrupted, triggering an abnormal bright / dark line display in the light-emitting units 30 on the left column of the display area AA. If the crack extends to the fifth sub-trace 201e of the fifth conductive layer 225, the data signal line 40 on the right will fail, and the abnormal display area AA will extend to the light-emitting units 30 on the right column. By observing the distribution hierarchy of the display abnormalities, the longitudinal extension path of the crack in different directions can be determined.

[0120] In addition, the fourth sub-trace 201d and the fifth sub-trace 201e have a wider vertical coverage range, which can detect microcracks at different depths in the border area NA and avoid missed detection.

[0121] Please continue reading. Figures 1 to 3 In some optional embodiments, the data signal line 40 further includes a fourth data line 44 and a fifth data line 45 extending along the second direction Y and spaced apart along the first direction X. A plurality of light-emitting units 30 form a fourth column light-emitting group 34 and a fifth column light-emitting group 35 arranged along the second direction Y. The fourth data line 44 is sequentially connected to the light-emitting units 30 in the fourth column light-emitting group 34, and the fifth data line 45 is sequentially connected to the light-emitting units 30 in the fifth column light-emitting group 35. The fourth sub-line 201d and the fifth sub-line 201e are connected to the fourth data line 44 and the fifth data line 45 respectively through the test circuit 50.

[0122] In these optional embodiments, the data signal lines 40 extend along the second direction Y and are arranged at intervals along the first direction X as fourth data lines 44 and fifth data lines 45. The light-emitting units 30 of the display area AA are correspondingly divided into a fourth column of light-emitting groups 34 and a fifth column of light-emitting groups 35 arranged along the second direction Y. The fourth data lines 44 are sequentially connected to the light-emitting units 30 in the fourth column of light-emitting groups 34, and the fifth data lines 45 are sequentially connected to the light-emitting units 30 in the fifth column of light-emitting groups 35, forming a column-type architecture with independently driven signals.

[0123] Meanwhile, the fourth sub-trace 201d and the fifth sub-trace 201e in the second conductive layer 22 are respectively bound to the fourth data line 44 and the fifth data line 45 through the test circuit 50. When a crack in the frame area NA causes a sub-trace to break, for example, the fourth sub-trace 201d breaks, the fourth data line 44 cannot drive the fourth column of light-emitting group 34 because the test circuit 50 is disconnected, and the column displays abnormally, which can directly map the position of the fourth conductive layer 224 where the broken fourth sub-trace 201d is located;

[0124] If a crack simultaneously penetrates the fifth sub-trace 201e, the fifth column of light-emitting groups 35 will show abnormal expansion, indicating that the crack extends longitudinally from the fourth conductive layer 224 to the fifth conductive layer 225. By observing the order and extent of the abnormality displayed in the columns corresponding to different data signal lines 40, the propagation direction and depth of the crack in the stacked conductive layers can be accurately determined.

[0125] In addition, the data signal line 40 extends along the second direction Y and is arranged at intervals, so that the fourth column of light-emitting group 34 and the fifth column of light-emitting group 35 form an independent and controllable area in the display area AA, avoiding signal crosstalk and ensuring the positioning accuracy of abnormal display.

[0126] The test circuit 50 can simultaneously detect the multi-layer crack state by activating the pathway between the fourth sub-trace 201d, the fifth sub-trace 201e and the fourth data line 44 and the fifth data line 45, thereby reducing parallel signal interference.

[0127] Please continue reading. Figure 3 In some embodiments, in any two conductive layers 20, the width of the crack detection trace 201 in the conductive layer 20 facing away from the substrate 10 is smaller than the width of the crack detection trace 201 in the conductive layer 20 closer to the substrate 10.

[0128] In these embodiments, the width of the crack detection traces 201 located in different conductive layers 20 varies depending on their position within the conductive layer 20. Specifically, in any two conductive layers 20, the width of the crack detection traces 201 in the conductive layer 20 facing away from the substrate 10 is smaller than the width of the traces in the conductive layer 20 closer to the substrate 10. The gradient width reduction design of the crack detection traces 201 optimizes the space ratio of each layer's traces, achieving a multi-layer compatible layout under narrow bezels. The narrower traces in the upper layer adapt to a more compact vertical stacking space, avoiding an increase in overall thickness due to multi-layer stacking, while the wider traces in the lower layer enhance resistance to mechanical stress, reducing false detections of non-crack fractures caused by panel bending or compression.

[0129] Meanwhile, reducing the width of the upper crack detection trace 201 can improve the sensitivity to micro-cracks. Because the upper crack detection trace 201 has a narrower line width, even a micro-crack can cause an open circuit, triggering the failure of the corresponding data signal line 40 and the display abnormality of the light-emitting unit 30, thereby quickly capturing shallow cracks.

[0130] The wider crack detection traces 201 in the lower layer are more resistant to the propagation of deep cracks, ensuring that cracks can still be reliably detected even if they extend to the bottom layer.

[0131] In addition, the width gradient design can balance process accuracy and yield. The upper crack detection trace 201 uses a high-precision etching process to achieve a micron-level linewidth, while the lower crack detection trace 201 uses conventional processes to control costs.

[0132] The test circuit 50 uses a layered bonding mechanism to independently connect traces of different widths to the corresponding data signal lines 40, so that the display anomaly feedback is accurately correlated with the physical characteristics of the traces.

[0133] Please continue reading. Figure 3 In some optional embodiments, in any two conductive layers 20, the orthogonal projection of the crack detection trace 201 in the conductive layer 20 facing away from the substrate 10 onto the substrate 10 is located within the orthogonal projection of the crack detection trace 201 in the conductive layer 20 facing away from the substrate 10 onto the substrate 10.

[0134] In these optional embodiments, the orthographic projections of the crack detection traces 201 in different conductive layers 20 onto the substrate 10 are arranged in a nested layout. The projections of the crack detection traces 201 in the conductive layer 20 facing away from the substrate 10 are completely located within the projections of the crack detection traces 201 in the conductive layer 20 closest to the substrate 10. The nested design concentrates the horizontal coverage of the multiple traces onto the same longitudinal axis of the border area NA through hierarchical projection contraction, avoiding the lateral expansion of the border due to projection dispersion, thereby further compressing the border width.

[0135] The crack detection traces 201 within each conductive layer 20 form a convergent distribution from the outside to the inside in the vertical stack. The wider crack detection traces 201 in the lower layer are close to the outer edge of the frame to enhance the resistance to mechanical shock, while the narrower crack detection traces 201 in the upper layer are recessed to adapt to the space constraints of the narrow frame. At the same time, the insulating layer ensures that there is no risk of short circuit between the conductive layers 20.

[0136] In addition, the nested projection layout enables the multi-layer crack detection traces 201 to form a protective layer structure in the vertical stack. The wider crack detection traces 201 in the lower layer act as a buffer layer to absorb external stress, reducing the probability of the narrower crack detection traces 201 in the upper layer breaking due to mechanical damage. Meanwhile, the narrower upper crack detection traces 201 are more likely to detect fine cracks due to the concentrated projection.

[0137] The test circuit 50 uses a layered binding mechanism to independently connect the crack detection traces 201 of each layer of nested projection to the corresponding data signal lines 40, so that the displayed abnormal position corresponds strictly to the crack level, thereby achieving accurate detection of crack position, depth and extension direction under extremely narrow bezels.

[0138] Please continue reading. Figures 1 to 3In some embodiments, the border area NA further includes a first border sub-area NA1 and a second border sub-area NA2 located on opposite sides of the display area AA along the first direction X. The crack detection wiring 201 further includes a first wiring group 2011 and a second wiring group 2012, with the first wiring group 2011 located in the first border sub-area NA1 and the second wiring group 2012 located in the second border sub-area NA2.

[0139] In these embodiments, the border area NA is further divided into a first border sub-region NA1 and a second border sub-region NA2 located on opposite sides of the display area AA along the first direction X, respectively, with a first wiring group 2011 and a second wiring group 2012. The first wiring group 2011 is distributed within the multilayer conductive layer 20 of the first border sub-region NA1, and the second wiring group 2012 is arranged in the second border sub-region NA2 in the same vertical stacking manner. The orthographic projections of both wiring groups on the substrate 10 adopt a nested design, and the projection ranges on both sides are symmetrically distributed on both sides of the display area AA.

[0140] When the panel is subjected to external stress, cracks may start from any frame sub-area. For example, when the first frame sub-area NA1 breaks, the crack detection trace 201 corresponding to the conductive layer 20 in the first trace group 2011 is interrupted, triggering the failure of the data signal line 40 bound to the crack detection trace 201, resulting in abnormal bright and dark lines in the corresponding light-emitting unit 30 in the display area AA.

[0141] If the crack extends laterally to the second frame sub-region NA2, the crack detection trace 201 in the same layer of the second trace group 2012 will break. After the data signal line 40 is interrupted in both the first frame sub-region NA1 and the second frame sub-region NA2 on both sides, the abnormal display area AA will expand from one side to the entire column. The lateral extension trend of the crack can be determined by the change in the abnormal range.

[0142] The independent layout of the first wiring group 2011 and the second wiring group 2012 in the first frame sub-area NA1 and the second frame sub-area NA2 on both sides not only avoids blind spots in single-sided detection, but also maximizes the use of the longitudinal space of the frame area NA by arranging the first wiring group 2011 and the second wiring group 2012 on both sides respectively, making the detection area more comprehensive.

[0143] Please continue reading. Figures 1 to 3 In some optional embodiments, the first wiring group 2011 includes multiple first wiring segments 2011a located in different conductive layers 20, and the second wiring group 2012 includes multiple second wiring segments 2012a located in different conductive layers 20. The orthogonal projections of at least two first wiring segments 2011a or at least two second wiring segments 2012a on the substrate 10 at least partially overlap.

[0144] In these alternative embodiments, the orthographic projections of at least two of the first trace segment 2011a in the first trace group 2011 or the second trace segment 2012a in the second trace group 2012 at least partially overlap, which can further narrow the width of the border area NA and realize the narrow border design of the border area NA in all directions.

[0145] Please continue reading. Figures 1 to 3 In some optional embodiments, the display area AA is square, and the first trace segment 2011a and the second trace segment 2012a located in the same conductive layer 20 of the first trace group 2011 and the second trace group 2012 are symmetrical about the central axis of the display area AA along the second direction Y.

[0146] In these optional embodiments, the first trace segment 2011a and the second trace segment 2012a within the same conductive layer 20 are arranged symmetrically, which can further simplify the process difficulty. The first trace segment 2011a and the second trace segment 2012a within the same conductive layer 20 can be fabricated simultaneously, improving the fabrication efficiency.

[0147] Figure 4 This illustrates a planar structure of the conductive layer 20 of another display panel 100 provided in the first aspect embodiment of this application.

[0148] Please see Figure 4 In some embodiments, the display panel 100 further includes a control signal line 70, and the test circuit 50 includes at least one switch 51. The switch 51 is connected between the data signal line 40 and the crack detection trace 201. The control terminal of the switch 51 is connected to the control signal line 70, and the switch 51 connects or disconnects the data signal line 40 and the crack detection trace 201 according to the control signal of the corresponding control signal line 70.

[0149] In these embodiments, switch 51 injects control signals through control signal line 70, which can selectively realize the on / off state of test circuit 50, thereby selectively injecting power signals in test signal line 80 into data signal line 40, and selectively realizing the on / off state of detection function.

[0150] Please continue reading. Figure 4 In some alternative embodiments, the switches 51 include multiple switches, which are arranged in a one-to-one correspondence with the data signal lines 40.

[0151] In these optional embodiments, switch 51 individually controls the connection and disconnection between crack detection traces 201 and data signal lines 40 within each conductive layer 20, further making the detection lines of crack detection traces 201 within each conductive layer 20 independent of each other and avoiding mutual coupling interference.

[0152] Please continue reading. Figure 4In some alternative embodiments, switch 51 includes a transistor, the first electrode 511 of which is connected to crack detection trace 201, the second electrode 512 of which is connected to data signal line 40, and the gate 513 of which is connected to control signal line 70.

[0153] In these alternative embodiments, switch 51 is implemented using a transistor, with the first electrode 511 of the transistor connected to crack detection trace 201, the second electrode 512 connected to data signal line 40, and the gate 513 receiving on / off commands via control signal line 70.

[0154] For example, when a high-level signal is applied to the control signal line 70, the transistor is turned on, and the crack detection trace 201 and the data signal line 40 form a path. At this time, the detection function is activated, and the state of the crack detection trace 201 is transmitted to the display driving circuit of the light-emitting unit 30 through the data signal line 40.

[0155] When the control signal line 70 is low, the transistor is turned off, and the data signal line 40 is disconnected from the crack detection trace 201 to avoid interference from the detection circuit to the data signal during the normal display stage.

[0156] For example, when a low-level signal is applied to the control signal line 70, the transistor is turned on, and the crack detection trace 201 and the data signal line 40 form a path. At this time, the detection function is activated, and the state of the crack detection trace 201 is transmitted to the display driving circuit of the light-emitting unit 30 through the data signal line 40.

[0157] When the control signal line 70 is high, the transistor is turned off, and the data signal line 40 is disconnected from the crack detection trace 201 to avoid interference from the detection circuit to the data signal during the normal display stage.

[0158] By arranging multiple transistors in a one-to-one correspondence with data signal lines 40, the crack detection traces 201 in each conductive layer 20 can be independently controlled to switch on and off, achieving independent detection of each layer.

[0159] This design ensures that the detection signals of each conductive layer 20 are not coupled to each other. Even if the crack detection trace 201 in a certain conductive layer 20 is broken or short-circuited, the detection function of the crack detection trace 201 in other conductive layers 20 can still operate normally, avoiding false judgments.

[0160] Figure 5 The overall structure of a display device 200 provided in the second aspect embodiment of this application is shown.

[0161] Please see Figure 5 Secondly, embodiments of this application provide a display device 200, including the display panel 100 provided in any of the embodiments of the first aspect of this application.

[0162] The display device 200 provided in the second aspect embodiment of this application has the beneficial effects of the display panel 100 provided in any of the first aspect embodiments, since the display device 200 provided in the second aspect embodiment of this application includes the display panel 100 provided in any of the first aspect embodiments. Therefore, it will not be described again here.

[0163] The display device 200 in this application embodiment includes, but is not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0164] Figure 6 A flowchart illustrating a testing method for a display panel provided in a third aspect embodiment of this application is shown.

[0165] Please see Figure 6 Thirdly, embodiments of this application provide a method for testing a display panel, employing the display panel provided in any one of the embodiments of the first aspect of this application. The method for testing the display panel includes:

[0166] Step S10: Turn on the test circuit;

[0167] Step S20: Test the circuit response and ensure the crack detection trace and data signal line are connected.

[0168] The display panel testing method provided in the third aspect of this application has the beneficial effects of the display panel provided in any of the first aspect embodiments, since the display panel testing method provided in the third aspect of this application includes the display panel provided in any of the first aspect embodiments. Therefore, it will not be described again here.

[0169] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit the invention. Any person skilled in the art to which this application pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

[0170] The above description is merely a specific embodiment of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, substitutions for other connection methods described above can be made by referring to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application.

Claims

1. A display panel, characterized in that, The display panel, having a display area and a border area at least partially surrounding the display area, further includes: Substrate; A conductive layer is disposed on one side of the substrate. At least two conductive layers are stacked and insulated from each other. Each conductive layer contains a crack detection trace located in the frame area. At least two crack detection traces located in different conductive layers have their orthogonal projections on the substrate at least partially overlapping. A light-emitting unit is located in the display area, and a plurality of light-emitting units are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect. Data signal lines are connected to the light-emitting units in the same column, and multiple data signal lines are arranged side by side with spacing and insulation. A test circuit is connected between the crack detection traces and the data signal lines, and the crack detection traces in different conductive layers are connected to different data signal lines through the test circuit.

2. The display panel according to claim 1, characterized in that, The display panel also includes a touch module, which includes touch electrodes located in the display area, and the crack detection traces and the touch electrodes are simultaneously disposed within at least one conductive layer.

3. The display panel according to claim 2, characterized in that, The conductive layer includes a first type of conductive layer and a second type of conductive layer, wherein the second type of conductive layer is disposed on the side of the first type of conductive layer away from the substrate, and the touch electrode is disposed within the second type of conductive layer.

4. The display panel according to claim 3, characterized in that, The first type of conductive layer includes a first conductive layer, a second conductive layer and a third conductive layer stacked sequentially along the direction away from the substrate. The crack detection trace includes a first sub-trace, a second sub-trace and a third sub-trace. The first sub-trace is located in the first conductive layer, the second sub-trace is located in the second conductive layer and the third sub-trace is located in the third conductive layer. Preferably, the data signal line includes a first data line, a second data line, and a third data line extending along a second direction and spaced apart along a first direction. Multiple light-emitting units at least form a first column light-emitting group, a second column light-emitting group, and a third column light-emitting group arranged along the second direction. The first data line is sequentially connected to the light-emitting units in the first column light-emitting group, the second data line is sequentially connected to the light-emitting units in the second column light-emitting group, and the third data line is sequentially connected to the light-emitting units in the third column light-emitting group. The first sub-trace, the second sub-trace, and the third sub-trace are respectively connected to the first data line, the second data line, and the third data line via the test circuit.

5. The display panel according to claim 3, characterized in that, The second type of conductive layer includes a fourth conductive layer and a fifth conductive layer stacked along the direction away from the substrate. The crack detection trace also includes a fourth sub-trace and a fifth sub-trace. The touch electrode includes a first sub-electrode and a second sub-electrode. The first sub-electrode and the fourth sub-trace are located in the fourth conductive layer, and the second sub-electrode and the fifth sub-trace are located in the fifth conductive layer. Preferably, the data signal line further includes a fourth data line and a fifth data line extending along the second direction and spaced apart along the first direction. The plurality of light-emitting units form a fourth light-emitting group and a fifth light-emitting group arranged along the second direction. The fourth data line is sequentially connected to the light-emitting units in the fourth light-emitting group, and the fifth data line is sequentially connected to the light-emitting units in the fifth light-emitting group. The fourth sub-trace and the fifth sub-trace are respectively connected to the fourth data line and the fifth data line through the test circuit.

6. The display panel according to claim 1, characterized in that, In any two conductive layers, the width of the crack detection trace in the conductive layer facing away from the substrate is smaller than the width of the crack detection trace in the conductive layer facing closer to the substrate. Preferably, in any two conductive layers, the orthogonal projection of the crack detection trace in the conductive layer facing away from the substrate onto the substrate lies within the orthogonal projection of the crack detection trace in the conductive layer facing closer to the substrate onto the substrate.

7. The display panel according to claim 1, characterized in that, The border area also includes a first border sub-area and a second border sub-area located on opposite sides of the display area along the first direction. The crack detection wiring also includes a first wiring group and a second wiring group, with the first wiring group located in the first border sub-area and the second wiring group located in the second border sub-area. Preferably, the first wiring group includes multiple first wiring segments located in different conductive layers, and the second wiring group includes multiple second wiring segments located in different conductive layers, wherein at least two first wiring segments or at least two second wiring segments have their orthogonal projections on the substrate at least partially overlapping; Preferably, the display area is square, and the first trace segment and the second trace segment located in the same conductive layer in the first trace group and the second trace group are symmetrical about the central axis of the display area along the second direction.

8. The display panel according to claim 1, characterized in that, The display panel further includes a control signal line and a test signal line. The test signal line is connected to the end of the crack detection trace away from the test circuit. The test circuit includes at least one switch. The switch is connected between the data signal line and the crack detection trace. The control terminal of the switch is connected to the control signal line. The switch responds to the control signal of the control signal line to turn on or off the data signal line and the crack detection trace. Preferably, the switches include multiple switches, and are arranged in a one-to-one correspondence with the data signal lines; Preferably, the switch includes a transistor, the first electrode of the transistor is connected to the crack detection trace, the second electrode of the transistor is connected to the data signal line, and the gate of the transistor is connected to the control signal line.

9. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 8.

10. A method for testing a display panel, characterized in that, Using the display panel according to any one of claims 1 to 8, the testing method for the display panel includes: Turn on the test circuit; In response to the test circuit, the crack detection trace becomes connected to the data signal line.

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