A test structure for semiconductor etch residue, a method of manufacture and a method of testing
Patent Information
- Application Number
- CN202611202096.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-10
- Publication Date
- 2026-10-30
AI Technical Summary
因此，该结构仅在物理上测试了接触孔与有源区的电学导通性，其内部并不包含横跨浅沟槽隔离区与有源区交界台阶的多晶硅栅极层，导致无法对由交界台阶处多晶硅栅极刻蚀残留所引起的栅极层与有源区之间漏电缺陷进行有效监控，使得该工艺异常的监控敏感度较低
[0031]本发明的技术方案，通过主动构建有源区与浅沟槽隔离区交界处500Å~700Å的物理台阶差，能够为跨台阶的多晶硅栅极层提供较高的物理落差。在干法刻蚀过程中，物理遮蔽效应会随台阶高度的增加而增强，使得多晶硅栅极的刻蚀残留更容易在该交界台阶的侧壁及底角处形成；同时，由于接触孔布设于交界处并沿四周分布，当有源区与浅沟槽隔离区交界处的栅极层刻蚀残留将上方栅极层与下方有源区边缘短接时，布设于此的接触孔能够与有源区边缘建立直接的电学接触。相较于常规测试结构，有效提升了测试结构对多晶硅栅极跨台阶刻蚀残留异常工艺的检出灵敏度，避免了因接触孔远离台阶风险区域而导致的漏检问题。
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Figure CN123022209A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a test structure, preparation method, and test method for semiconductor etching residue. Background Technology
[0002] In the manufacturing process of semiconductor devices, the fabrication of the polysilicon gate layer is a key step that affects device performance. Since the shallow trench isolation region and the active region are distributed adjacently on the semiconductor substrate, due to the difference in material removal rate during the chemical mechanical polishing process, the dielectric layer on the surface of the shallow trench isolation region is usually slightly higher than the silicon layer on the surface of the active region, thus forming a natural physical step difference with a certain height at the interface between the two.
[0003] In subsequent etching processes, due to the physical shielding effect, the polysilicon gate layer spanning the boundary step is prone to forming etching residues on the sidewalls and bottom corners of the step. The residual conductive polysilicon will connect the gate layer and the active region when the device is working, forming a leakage path, thereby reducing the electrical yield of the device.
[0004] Currently, the wafer manufacturing industry typically uses conventional monitoring structures arranged within wafer dicing channels to assess such process risks, such as contact chain test structures within active regions. Conventional test structures usually employ active region patterns with low pattern density and large areas. In these relatively isolated process regions, the natural step difference at the boundary between the shallow trench isolation region and the active region is relatively small, typically only 0-200 Å. However, in the dense digital logic regions of actual chips, due to the extremely dense arrangement of numerous tiny active regions, the pitting effect of chemical mechanical polishing is significantly amplified, causing the actual step difference at this boundary to deteriorate to 200-300 Å. Therefore, the physical morphology simulated by conventional test structures is significantly deviated from the actual process environment of the device.
[0005] On the other hand, existing active region internal contact chain test structures typically design contact holes inside the active region to avoid the risk of steps at the boundary. Therefore, this structure only physically tests the electrical conductivity between the contact hole and the active region. It does not contain a polysilicon gate layer that spans the boundary step between the shallow trench isolation region and the active region. This makes it impossible to effectively monitor leakage defects between the gate layer and the active region caused by polysilicon gate etching residue at the boundary step, resulting in low sensitivity to process anomalies. Summary of the Invention
[0006] The main objective of this invention is to provide a test structure, preparation method, and test method for semiconductor etching residues, which aims to improve the detection capability of etching residue defects.
[0007] To achieve the above objectives, the present invention proposes a test structure for semiconductor etching residues, the test structure comprising a semiconductor substrate, wherein adjacent active regions and shallow trench isolation regions are disposed on the semiconductor substrate;
[0008] A gate layer is disposed on the active region, and the gate layer is located at the boundary between the active region and the shallow trench isolation region.
[0009] A plurality of contact holes are spaced apart at the boundary between the active region and the shallow trench isolation region;
[0010] The boundary between the active region and the shallow trench isolation region has a height difference of 500 Å to 700 Å.
[0011] In some embodiments of the present invention, a doped buried layer is disposed below the active region.
[0012] In some embodiments of the present invention, one or more active region protection rings are provided at intervals around the outer periphery of the active region.
[0013] In some embodiments of the present invention, the gate layer extends above the active region guard ring;
[0014] The contact hole is provided at the junction between the active area protection ring and the shallow trench isolation area.
[0015] In some embodiments of the present invention, the number of active region protection rings is multiple; the spacing between adjacent active region protection rings is 1.0 μm to 2.25 μm.
[0016] This invention also discloses a method for preparing a semiconductor etching residue test structure, the method comprising:
[0017] A semiconductor substrate is provided, and an active region is defined in the semiconductor substrate;
[0018] The semiconductor substrate is etched to form trenches, and shallow trench isolation regions are formed in the trenches, with the shallow trench isolation regions distributed adjacent to the active region;
[0019] A gate layer is formed on the active region, such that the gate layer spans across the boundary between the active region and the shallow trench isolation region;
[0020] A contact hole is formed at the boundary between the active region and the shallow trench isolation region;
[0021] The boundary between the active region and the shallow trench isolation region has a height difference of 500 Å to 700 Å.
[0022] In some embodiments of the present invention, the preparation method includes: implanting and forming a doped buried layer directly below the active region before etching the semiconductor substrate to form a trench.
[0023] In some embodiments of the present invention, the preparation method includes: the implantation dose of the doped buried layer is... .
[0024] In some embodiments of the present invention, the etching of the semiconductor substrate to form trenches includes: etching two or more trenches at intervals around the periphery of the active region, and forming an active region protection ring between adjacent trenches.
[0025] This invention also discloses a method for testing semiconductor etching residues, the method comprising:
[0026] S101: Provides the above test structure;
[0027] S102: Connect each of the contact holes in series to the first test terminal, and connect the gate layer to the second test terminal;
[0028] S103: Apply a bias test voltage between the first test terminal and the second test terminal;
[0029] S104: Detect the leakage current value flowing between the first test terminal and the second test terminal;
[0030] S105: Compare the detected leakage current value with a preset standard threshold. If the leakage current value exceeds the preset threshold, it is determined that there is an abnormality in the gate layer etching process at the junction of the gate layer and the shallow trench isolation region.
[0031] The technical solution of this invention, by actively constructing a physical step difference of 500Å~700Å at the boundary between the active region and the shallow trench isolation region, can provide a higher physical drop for the polysilicon gate layer across the step. During dry etching, the physical shielding effect increases with the step height, making it easier for etching residues of the polysilicon gate to form on the sidewalls and bottom corners of the boundary step. Simultaneously, since the contact holes are arranged at the boundary and distributed around the perimeter, when the gate layer etching residue at the boundary between the active region and the shallow trench isolation region short-circuits the upper gate layer and the lower active region edge, the contact holes arranged here can establish direct electrical contact with the active region edge. Compared with conventional test structures, this effectively improves the detection sensitivity of the test structure for abnormal processes involving etching residues across the polysilicon gate, avoiding missed detections caused by contact holes being far from the step risk area. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0033] Figure 1 This is a schematic cross-sectional view of the test structure for semiconductor etching residues according to the present invention.
[0034] Figure 2 This is a top view of the layout of the test structure for semiconductor etching residues according to the present invention;
[0035] Figure 3 This invention relates to a method for preparing a test structure for semiconductor etching residues.
[0036] Figure 4 This invention provides a test method for semiconductor etching residue.
[0037] Figure 5 A schematic cross-sectional view of the test structure showing the residue from existing semiconductor etching.
[0038] Figure 6 This is a top view of the layout of the test structure with existing semiconductor etching residue.
[0039] Figure label:
[0040] 100 Semiconductor substrate; 200 Active region; 300 Shallow trench isolation region; 400 Gate layer; 500 Contact hole; 600 Doped buried layer; 700 Active region guard ring;
[0041] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0043] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.
[0044] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, the user should consider such a combination of technical solutions to be non-existent and not within the scope of protection claimed by this invention.
[0045] See appendix Figure 1-2 This invention proposes a test structure for semiconductor etching residue. The test structure includes a semiconductor substrate 100, on which adjacent active regions 200 and shallow trench isolation regions 300 are disposed. The test structure is formed on the semiconductor substrate 100, which typically includes a bottom substrate and an epitaxial layer. The adjacent active regions 200 and shallow trench isolation regions 300 are formed on the substrate through trench etching and dielectric filling processes.
[0046] A gate layer 400 is disposed on the active region 200, and the gate layer 400 is located at the boundary between the active region 200 and the shallow trench isolation region 300.
[0047] Several contact holes 500 are spaced apart at the boundary between the active zone 200 and the shallow trench isolation zone 300;
[0048] There is a height difference at the boundary between the active region 200 and the shallow trench isolation region 300, which is 500 Å to 700 Å.
[0049] Based on the aforementioned technical features, by actively constructing a physical step difference of 500Å~700Å at the boundary between the active region 200 and the shallow trench isolation region 300, a higher physical drop can be provided for the polysilicon gate layer 400 across the step. During dry etching, the physical shielding effect increases with the step height, making it easier for etching residues of the polysilicon gate to form on the sidewalls and bottom corners of the boundary step. Simultaneously, since the contact holes 500 are located at the boundary and distributed around the perimeter, when the etching residues of the gate layer 400 at the boundary between the active region 200 and the shallow trench isolation region 300 short-circuit the upper gate layer 400 and the lower active region 200 edge, the contact holes 500 located there can establish direct electrical contact with the edge of the active region 200. Compared to conventional test structures, this effectively improves the detection sensitivity of the test structure for abnormal processes involving etching residues across the polysilicon gate, avoiding missed detections caused by the contact holes 500 being far from the step risk area.
[0050] Furthermore, the contact holes 500 are spaced apart along the boundary line around the active region 200, which further ensures that when cross-step etching residue occurs in any direction of the step, a physical connection can be formed through the adjacent contact holes 500, thereby realizing multi-directional leakage signal capture.
[0051] See appendix Figure 1 Optionally, a doped buried layer 600 is disposed below the active region 200. Through the thermal oxidation process of the shallow trench isolation region 300, the enhanced oxidation effect caused by the high concentration of impurities in the doped buried layer 600 increases the silicon consumption on the surface of the active region 200, generating a thicker oxide layer than usual. When this oxide layer is removed by a subsequent lift-off process, the silicon surface of the active region 200 will be recessed relative to the initial coplanarity, forming the basis for the height difference at the interface between the active region 200 and the shallow trench isolation region 300.
[0052] The active region 200 is provided with one or more active region guard rings 700 at intervals around its outer periphery. These guard rings are primarily composed of unetched single-crystal silicon mesa surfaces of the semiconductor substrate 100. During the chemical mechanical polishing (CMP) process to form the shallow trench isolation region 300, the guard rings act as fulcrums for physical support, effectively suppressing the indentation effect of the polishing pad in the core region. Through this support, the dielectric layer on the surface of the shallow trench isolation region 300 can retain a higher thickness compared to a design without guard ring support, thus creating a physical lift of the shallow trench isolation region 300 relative to conventional structures. This lift also forms the basis for the height difference at the boundary between the active region 200 and the shallow trench isolation region 300.
[0053] In this embodiment, the lifting effect generated by the active region protection ring 700 and the sinking effect caused by the doped buried layer 600 are combined to achieve a relative sinking of the active region 200 by utilizing the enhanced oxidation effect of the doped buried layer 600. This, combined with the physical support provided by the outer active region protection ring 700 in the CMP process, forms the lifting of the front trench isolation region. The two combined create the required total step difference of 500Å-700Å. Since the resulting step difference is 2 to 3 times greater than in typical deterioration cases, under this height difference, the polysilicon gate crossing the step is prone to etching residues on the step sidewalls and bottom corners after etching. Once residues are formed, the gate layer 400 and the edge of the active region 200 are directly short-circuited through these residues. By placing the contact holes 500 on the boundary line around the active region 200 and applying a bias voltage, even weak leakage currents can be accurately captured. When the leakage current exceeds the preset threshold, the system immediately alarms, indicating that there is an abnormality in the etching process, thus achieving precise interception before the wafer yield collapses.
[0054] Furthermore, the gate layer 400 extends above the active region guard ring 700; a contact hole 500 is provided between the active region guard ring 700 and the shallow trench isolation region 300. This expands the span of the gate layer 400, allowing it to not only cross the boundary step of the core active region 200 but also the boundary step at the outer active region guard ring 700. By also adding a contact hole 500 between the guard ring and the shallow trench isolation region 300, even if etching residue occurs at the edge of the outer guard ring far from the core active region 200, this extended structure can still capture leakage signals through the added contact hole 500. This arrangement helps to further expand the monitoring coverage area of this test structure for etching residue defects and improve the fault tolerance of the test structure.
[0055] Specifically, there are multiple active area protection rings 700; compared with a single active area protection ring 700 structure, this multi-ring array can provide more and more evenly distributed physical support points in the CMP process, which helps to further suppress the local concave deformation of the polishing pad above the shallow trench isolation area 300.
[0056] Preferably, the spacing between adjacent active region guard rings 700 is 1.0 μm to 2.25 μm. This allows for the construction of a pattern density close to that of a real dense digital logic region within a local area of the test structure. In actual process verification, the physical behavior of chemical mechanical polishing under different pattern densities can be simulated by adjusting the spacing between adjacent guard rings. This allows the height difference characteristics exhibited by the monitoring structure to better fit the process environment of specific products, improving the applicability and relevance of the test structure of this invention to different product process nodes; and facilitating flexible configuration of the test structure of this invention by wafer foundries based on specific process characteristics.
[0057] See appendix Figure 3 The present invention also discloses a method for preparing a semiconductor etching residue test structure, comprising:
[0058] S100: Provide a semiconductor substrate 100, and define an active region 200 in the semiconductor substrate 100;
[0059] S200: Etching the semiconductor substrate 100 to form trenches, forming shallow trench isolation regions 300 within the trenches, the shallow trench isolation regions 300 being distributed adjacent to the active regions 200;
[0060] S300: A gate layer 400 is formed on the active region 200, such that the gate layer 400 spans across the boundary between the active region 200 and the shallow trench isolation region 300;
[0061] S400: A contact hole 500 is formed at the junction of the active region 200 and the shallow trench isolation region 300;
[0062] The boundary between the active region 200 and the shallow trench isolation region 300 has a height difference of 500 Å to 700 Å.
[0063] The preparation method of the semiconductor etching residue test structure of the present invention will be described in further detail below.
[0064] In step S100, in one embodiment of the present invention, the semiconductor substrate 100 may include a bottom substrate and an epitaxial layer formed on the bottom substrate. An active region 200 is defined on the semiconductor substrate 100 by photolithography.
[0065] Next, step S200 is performed to etch the semiconductor substrate 100 to form a trench, and fill the trench with an isolation medium to form a shallow trench isolation region 300. After this step, the shallow trench isolation region 300 and the active region 200 are distributed adjacent to each other.
[0066] In step S300, polysilicon is deposited on the active region 200 and photolithography is performed to form the gate layer 400. The physical arrangement of this step requires the gate layer 400 to span the boundary between the active region 200 and the shallow trench isolation region 300.
[0067] Next, step S400 is performed to create and fill a hole with metal at the junction of the active area 200 and the shallow trench isolation area 300 to form a contact hole 500.
[0068] In this basic embodiment, a height difference of 500 Å to 700 Å is created at the boundary between the active region 200 and the shallow trench isolation region 300. This height difference can be achieved through the preferred embodiments described below to enhance the physical shielding effect of the cross-step gate layer 400 during dry etching.
[0069] To specifically achieve the aforementioned physical height difference of 500 Å to 700 Å, the preparation method of this application further includes the following preferred refined process steps:
[0070] Optionally, before performing step S200, i.e. before etching the semiconductor substrate 100 to form a trench, a doped buried layer 600 is pre-implanted and formed directly below the active region 200.
[0071] Specifically, due to the introduction of the doped buried layer 600, the high-temperature oxidation process of the subsequent shallow trench isolation region 300 utilizes the enhanced oxidation effect caused by the high concentration of impurities. When the doped buried layer 600 region undergoes the subsequent high-temperature process, the silicon atoms above this region oxidize at a higher rate than in the undoped region, consuming more underlying silicon and thus generating a thicker oxide layer. When this oxide layer is stripped in a subsequent step, the surface of the active region 200 experiences a relative physical depression relative to the initial coplanarity.
[0072] In the step of forming the doped buried layer 600 described above, the implantation dose of the doped buried layer 600 is preferably configured as follows: to This implantation dose range provides the impurity concentration that triggers enhanced oxidation during the preparation process. By limiting the implantation dose within this range, it helps to stably control the depression depth of the active region 200 within the required process window, thereby ensuring good process repeatability and controllability of the final physical step difference.
[0073] Optionally, during step S200, i.e., etching the semiconductor substrate 100 to form trenches, two or more trenches can be formed at intervals around the active region 200. During this process, an active region protection ring 700, composed of unetched areas of the epitaxial layer, is maintained between adjacent trenches.
[0074] When performing the CMP process to planarize the shallow trench isolation region 300, these solid mesa surfaces can serve as physical support fulcrums. This fulcrum effectively suppresses localized concave deformation of the polishing pad above the trench isolation region, thereby preventing over-polishing of the media in the shallow trench isolation region 300 at the edge of the core active region 200. Therefore, the surface media of the shallow trench isolation region 300 can retain a higher physical thickness, resulting in a relative physical lift after polishing.
[0075] In this embodiment, the enhanced oxidation effect caused by the implantation of the doped buried layer 600 and the stripping process cause the surface of the active region 200 to be recessed downward by 200 Å to 400 Å relative to the initial coplanarity; the physical support provided by the active region protection ring 700 in CMP polishing causes the surface of the shallow trench isolation region 300 to be raised upward by 200 Å to 400 Å relative to the original scheme.
[0076] Since the downward indentation of the active region 200 and the upward elevation of the shallow trench isolation region 300 are a bidirectional absolute superposition in terms of physical height, the two work together to achieve a total height difference of 500Å to 700Å at the junction of the active region 200 and the shallow trench isolation region 300. This creates a narrower process window for the gate layer 400 that crosses the junction step during dry etching, thereby transforming the originally hidden cross-step etching residue into a leakage defect that can be captured by the contact hole 500, and improving the overall ability of the test structure to identify etching process anomalies.
[0077] The existing conventional structure is shown in the appendix. Figure 5 and 6Because of the undoped buried layer 600 implantation and the absence of an active region protection ring 700, the interface between the front trench isolation region and the active region 200 has only a natural step difference of 0 Å to 200 Å, which is much smaller than the actual deterioration step of 200 Å to 300 Å under dense digital region layout. This low step difference structure means that even if the polysilicon etching equipment experiences process drift, severe etching residue cannot form at the interface. Therefore, the electrical data measured by the monitoring equipment cannot be effectively monitored, resulting in the inability to capture real-time equipment degradation. Furthermore, because the contact hole 500 is located in the active region 200, it is impossible to effectively monitor leakage defects between the gate layer 400 and the active region 200 caused by polysilicon gate etching residue at the interface step.
[0078] See appendix Figure 4 The present invention also discloses a method for testing semiconductor etching residues, the method comprising:
[0079] S101: Provides a test structure for semiconductor etching residue;
[0080] S102: Connect each contact hole 500 in series to the first test terminal, and connect the gate layer 400 to the second test terminal.
[0081] S103: Apply a bias test voltage between the first test terminal and the second test terminal;
[0082] S104: Detects the leakage current value flowing between the first test terminal and the second test terminal;
[0083] S105: Compare the detected leakage current value with the preset standard threshold. If the leakage current value exceeds the preset threshold, it is determined that there is an abnormality in the etching process of gate layer 400 at the junction of gate layer 400 and shallow trench isolation region 300.
[0084] After the test begins, each contact hole 500 is electrically connected in series to the first test terminal, and the gate layer 400 is electrically connected to the second test terminal. By connecting the first and second test terminals with external probes, a monitoring path can be established under the control of the test equipment.
[0085] Subsequently, a bias test voltage is applied between the first test terminal and the second test terminal. The bias voltage applied by the external instrument can activate any existing electrical path between the gate layer 400 and the active region 200.
[0086] Next, the leakage current value flowing between the first test terminal and the second test terminal is detected by the current detection module in the test machine.
[0087] Finally, the processor inside the testing equipment compares the detected leakage current value with a preset standard threshold. If the leakage current value does not exceed the preset threshold, it indicates that no short circuit has occurred and the current gate etching process is normal. If the detected leakage current value exceeds the preset threshold, it indicates that a certain degree of electrical connection has been formed between the gate layer 400 and the active region 200. This suggests that there is an abnormality in the etching process of the gate layer 400 at the junction of the gate layer 400 and the shallow trench isolation region 300, indicating that the etching equipment needs to be adjusted.
[0088] It should be noted that the test structure of this invention can be fully extended to 90nm, 55nm, 45nm, 28nm and other more advanced process nodes. Meanwhile, the number of active region guard rings 700 can be adjusted to 3 or 5, etc., according to actual monitoring needs; the implantation dose of the doped buried layer 600 can also be adjusted while ensuring the sink depth; the size of the contact hole 500 and the spacing of the active region guard rings 700 can be flexibly changed according to the monitoring scenario, all within the protection scope of this invention.
[0089] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
Claims
1. A test structure for semiconductor etching residue, characterized in that, The test structure includes a semiconductor substrate, on which adjacent active regions and shallow trench isolation regions are disposed; A gate layer is disposed on the active region, and the gate layer is located at the boundary between the active region and the shallow trench isolation region. A plurality of contact holes are spaced apart at the boundary between the active region and the shallow trench isolation region; The boundary between the active region and the shallow trench isolation region has a height difference of 500 Å to 700 Å.
2. The test structure for semiconductor etching residue as described in claim 1, characterized in that, A doped buried layer is disposed below the active region.
3. The test structure for semiconductor etching residue as described in claim 1 or 2, characterized in that, One or more active region protection rings are provided at intervals around the outer periphery of the active region.
4. The test structure for semiconductor etching residue as described in claim 3, characterized in that, The gate layer extends above the active region guard ring; The contact hole is provided at the junction between the active area protection ring and the shallow trench isolation area.
5. The test structure for semiconductor etching residue as described in claim 3, characterized in that, The number of active region protection rings is multiple; the spacing between adjacent active region protection rings is 1.0μm~2.25μm.
6. A method for preparing a semiconductor etching residue test structure, characterized in that, The preparation method includes: A semiconductor substrate is provided, and an active region is defined in the semiconductor substrate; The semiconductor substrate is etched to form trenches, and shallow trench isolation regions are formed in the trenches, with the shallow trench isolation regions distributed adjacent to the active region; A gate layer is formed on the active region, such that the gate layer spans across the boundary between the active region and the shallow trench isolation region; A contact hole is formed at the boundary between the active region and the shallow trench isolation region; The boundary between the active region and the shallow trench isolation region has a height difference of 500 Å to 700 Å.
7. The preparation method according to claim 6, characterized in that, Before etching the semiconductor substrate to form a trench, the process includes: implanting and forming a doped buried layer directly below the active region.
8. The preparation method according to claim 7, characterized in that, The preparation method includes: the implantation dose of the doped buried layer is... .
9. The preparation method according to any one of claims 6-8, characterized in that, The etching of the semiconductor substrate to form trenches includes: etching two or more trenches at intervals around the periphery of the active region, and forming an active region protection ring between adjacent trenches.
10. A method for testing semiconductor etching residue, characterized in that, The testing method includes: S101: Provide the test structure according to any one of claims 1-5; S102: Connect each of the contact holes in series to the first test terminal, and connect the gate layer to the second test terminal; S103: Apply a bias test voltage between the first test terminal and the second test terminal; S104: Detect the leakage current value flowing between the first test terminal and the second test terminal; S105: Compare the detected leakage current value with a preset standard threshold. If the leakage current value exceeds the preset threshold, it is determined that there is an abnormality in the gate layer etching process at the junction of the gate layer and the shallow trench isolation region.