Wafer test defect chip marking method, device and storage medium

Abstract

The application provides a wafer test defect chip marking method, device and storage medium, relates to the chip test marking method technical field, and the energy factor of the defect cluster is quantified by dividing the gathered defect chips into defect clusters, combining the detection parameters of the chips and the defect severity, and calculating the shape factor and the influence coefficient according to the total area and the peripheral perimeter of the defect cluster, so as to quantitatively evaluate the damage degree of the defect cluster to the wafer; the real state of the normal chips around the defect is evaluated by calculating the distance attenuation and the performance score of the normal chips from two dimensions of the neighbor layer order and the spatial topology intersection; finally, the performance score of all the normal chips is divided into threshold interval grades, and the corresponding marking color is mapped back to the digital model, so that the physical quality distribution of each region of the wafer is intuitively presented, and the quality control precision and the production efficiency of the detection marking link are improved.

Description

Technical Field

[0001] This invention relates to the field of chip testing and marking methods, specifically to a method, apparatus, and storage medium for marking defective chips during wafer testing. Background Technology

[0002] In the field of semiconductor wafer manufacturing and packaging testing, wafer quality inspection is a core step in ensuring chip yield and reliability. Typically, after completing the front-end processes, wafers require automated optical inspection equipment to collect macroscopic physical morphology data, and electrical testing equipment such as probe stations to collect microscopic electrical parameters, thereby determining the quality of each chip on the wafer. Traditional techniques treat defective chips as isolated bad spots, completely ignoring the spatial physical continuity and morphological characteristics between defect points. Furthermore, traditional techniques lack dynamic assessment of the spatial topological environment of qualified chips, failing to identify potentially risky chips that are adjacent to heavily defective areas or have passed initial electrical testing but have been exposed to residual stress or contamination radiation.

[0003] In the prior art, CN118588601A discloses a method and apparatus for quality grading of automotive-grade wafer dies, relating to the field of automotive-grade chip testing. It improves the regional parameter average testing of automotive-grade chip dies, avoiding the problem in current testing where dies with potential quality risks around defective areas caused by wafer substrate defects or surface damage are not fully removed. The aforementioned method for quality grading of automotive-grade wafer dies includes: statistically determining the proportion of normal dies from batch wafer test data, and calculating the average distance R between faulty dies; calculating a quality grading threshold A based on the length, width, and R value of the dies; reading in a wafer test result map, and calculating the fault degree of each faulty die based on the distance and R value between faulty dies; calculating the fault degree of each normal die based on the distance between normal dies and each faulty die, the R value, and the fault degree of each faulty die; and assigning a quality grade to each normal die based on its fault degree and the threshold A. While this scheme takes into account the potential risks of faulty dies to normal dies, it ignores the further impact of the distribution of faulty dies and defect morphology on such risks. It can only reflect a limited amount of real physical effects, and it uses a full traversal calculation for all independent faulty dies, resulting in high computational complexity and making it difficult to meet the real-time requirements of industry.

[0004] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a method, apparatus, and storage medium for marking defective chips during wafer testing, in order to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A method for marking defective chips during wafer testing, comprising the following steps: S1: Perform quality inspection on the wafer, collect quality data of all chips on the wafer, establish a parameter matrix based on chip coordinates and quality data, and embed the parameter matrix into a two-dimensional digital model; S2: Based on the parameter matrix, all defective chips that fail the test are screened out. In the digital model, connected component analysis is performed on all defective chips, and they are divided into several defect clusters. S3: Based on the number of defective chips, defect type, and severity of all defective chips in each defect cluster, generate the impact coefficient of that defect cluster; S4: Divide the normal chip into several neighboring layers with any qualified chip as the center, and calculate the performance score of the normal chip together based on the number of defect clusters and the influence coefficient in the neighboring layers. S5: Traverse all normal chips, classify all normal chips into grades based on performance scores, map the grades of all normal chips back to the digital model, and use different colors to mark the grades.

[0007] Preferably, the quality inspection includes automatic optical inspection and probe station electrical inspection. The quality data includes chip inspection parameters, defect type, defect number and severity. The inspection parameters include chip size, defect area, leakage current and contact resistance. The defect types include no defects, surface defects, size defects and functional defects, and each defect type corresponds to a preset defect number and severity.

[0008] Preferably, the digital model is a uniform two-dimensional grid, and each grid in the two-dimensional grid corresponds to an element in the parameter matrix.

[0009] Preferably, the logic for performing connected component analysis on defective chips is as follows: Chips with no defects are classified as normal chips, while chips with other defect types are classified as defective chips. Binary labels are used to distinguish between normal chips and defective chips, with normal chips having a value of 0 and defective chips having a value of 1. The two-dimensional mesh is also binarized. Based on binary labels, all defective chips and their corresponding grids in the two-dimensional grid are identified, and the connected component analysis of the defective chips is performed using the 8-neighborhood two-pass scanning method to obtain several defect clusters.

[0010] Preferably, for any defect cluster, the logic for generating its influence coefficient is as follows: The detection parameters of all defective chips within the defect cluster are normalized. The product of the normalized detection parameters and the severity is defined as the defect feature value of the corresponding defective chip. The energy factor of the defective cluster is obtained by summing the defect feature values ​​of all defective chips in the defect cluster. Based on the number of defective chips within the defect cluster and the area of ​​a single chip, calculate the total area of ​​the defect cluster and simultaneously collect the perimeter of the defect cluster. Based on the total area and perimeter of the defect cluster, and combined with the thermodynamic interface energy theory, the shape factor of the defect cluster is calculated. Based on the total area of ​​the defect cluster, and combined with Saint-Venant's principle, the equivalent stress radius of the defect cluster is calculated, and the product of the energy factor, shape factor, and equivalent stress radius is used as the influence coefficient of the defect cluster.

[0011] Preferably, the shape factor is expressed as a fraction, with the numerator being the outer perimeter and the denominator being the square root of the product of the total area and the constant π, multiplied by two.

[0012] Preferably, the neighbor layer is a concentric square topology ring. For any normal chip, the logic for obtaining its performance score is as follows: An initial score is preset for a normal chip, and then the corresponding distance attenuation factor is calculated based on the order of the neighboring layers. The magnitude of the distance attenuation factor is negatively correlated with the order of the neighboring layers. Perform topological judgment on each neighbor layer and all defect clusters. If a neighbor layer and any defect cluster have an intersection in the digital model, then the defect cluster is considered to fall into that neighbor layer. The product of the distance attenuation factor of each neighboring layer and the sum of the influence coefficients of all defect clusters falling into that neighboring layer is calculated sequentially, and then summed over all neighboring layers to obtain the penalty score of the normal chip. Subtracting the penalty score from the initial score yields the performance rating of the normal chip.

[0013] Preferably, a threshold interval method is used when classifying normal chips, with each chip grade corresponding to a performance scoring interval and a marking color.

[0014] A wafer testing defect chip marking device, the defect chip marking device being used to perform the above-described defect chip marking method, comprising: The data acquisition module is used to perform quality inspection on the wafer, collect quality data of all chips on the wafer, establish a parameter matrix based on chip coordinates and quality data, and embed the parameter matrix into a two-dimensional digital model. The data analysis module is used to filter out all defective chips that fail the test based on the parameter matrix, perform connected component analysis on all defective chips in the digital model, and divide them into several defect clusters. The coefficient calculation module is used to generate the influence coefficient of each defect cluster based on the number, defect type and severity of all defective chips in each defect cluster. The performance evaluation module is used to divide a normal chip that has passed the test into several neighboring layers, and to jointly calculate the performance score of the normal chip based on the number of defect clusters and the influence coefficient in the neighboring layers. The chip marking module is used to traverse all normal chips, classify all normal chips into grades based on performance scores, map the grades of all normal chips back to the digital model, and mark the grades with different colors.

[0015] A storage medium for storing a computer program that, when executed by a processor, implements the above-described defect chip marking method.

[0016] Compared with the prior art, the beneficial effects of the present invention are: This invention quantifies the energy factor of defect clusters by combining chip detection parameters and defect severity, and calculates their shape factor and influence coefficient based on the total area and perimeter of the defect clusters. While capturing the omnidirectional diffusion characteristics of defects, it also comprehensively reflects the potential threat of defects of different morphologies to surrounding chips, thereby quantifying the degree of damage to the wafer caused by defective regions. Furthermore, by jointly calculating the distance attenuation and performance score of normal chips from two dimensions—neighbor layer order and spatial topological intersection—it can assess the true state of normal chips surrounding defects, reducing the risk of mixing chips with latent damage into high-reliability products. Finally, by classifying the performance scores of all normal chips into threshold ranges and mapping the corresponding marker colors back to the digital model, it not only intuitively presents the physical quality distribution of each region of the wafer but also achieves refined classification and sorting of normal chips, thereby greatly improving the quality control accuracy and automated production efficiency in the semiconductor packaging and testing process. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall method flow of the present invention; Figure 2 This is a schematic diagram of the module structure of the defect chip marking device in this invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0019] It should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0020] Example: Please see Figure 1 The present invention provides a technical solution: A method for marking defective chips during wafer testing, comprising the following steps: S1: Perform quality inspection on the wafer, collect quality data of all chips on the wafer, establish a parameter matrix based on chip coordinates and quality data, and embed the parameter matrix into a two-dimensional digital model.

[0021] Quality inspection includes automated optical inspection and probe station electrical inspection. Quality data includes chip inspection parameters, defect types, defect numbers, and severity. Inspection parameters include chip size, defect area, leakage current, and contact resistance. Defect types include no defects, surface defects, dimensional defects, and functional defects, with each defect type corresponding to a preset defect number and severity. The digital model is a uniform two-dimensional grid, where each grid cell corresponds to an element in the parameter matrix.

[0022] Understandably, chip size reflects the stress uniformity of mechanical cutting, wafer thinning, and chemical mechanical polishing; dimensional anomalies are usually accompanied by microcracks in the internal structure. Defect area reflects the macroscopic coverage of dust, chemical drips, or physical scratches during photolithography; a large defect area directly indicates severe physical / chemical contamination in that area. Leakage current reflects lattice dislocations, semiconductor PN junction damage, or gate oxide breakdown; abnormal leakage current indicates defects in the chip's internal lattice. Contact resistance reflects open vias, metal layer peeling, or abnormal silicide formation; high contact resistance indicates localized stress accumulation or potential electromigration. Therefore, these parameters actually reflect the chip's state from both the macroscopic physical level and the microscopic lattice level. In practical applications, more detection parameters can be added according to engineering needs; this is only for illustrative purposes and not as a limitation.

[0023] Furthermore, as can be seen from the above records, the essence of a digital model is actually to establish a tensor grid system that strictly maps high-dimensional physical properties to two-dimensional geometric space in a one-to-one manner, which can be constructed as follows: First, using the physical positioning notch of the wafer as the reference direction and the center of the bottom left corner of the effective chip area of ​​the wafer as the origin, a two-dimensional Cartesian coordinate grid is established. Let the maximum number of chips in the wafer's horizontal direction be... The maximum number of chips in the vertical direction is , build a A two-dimensional uniform grid array, where each cell in the grid... The geometric dimensions are strictly bound to the width and height of the physical chip in a 1:1 ratio; Next, the various detection parameters obtained from the chip through automatic optical inspection and probe station electrical inspection are compared with a preset defect mapping table to automatically determine the chip's defect type and assign a corresponding defect number and severity. When there is no defect, the severity is 0. The more a defect affects the core function of the chip, the higher its severity. For example, a defect-free chip has a defect number of 0, a surface defect has a defect number of 1 and a severity of 1, a dimensional defect has a defect number of 2 and a severity of 2, and so on. Furthermore, for subtypes under the same defect type, different sub-item numbers can be used, but the same severity can be maintained. Taking surface defects as an example, common forms include dust and scratches. Dust defects can be numbered 2.1, scratches 2.2, and both have a severity of 1. Other defect types follow the same pattern. This allows for more detailed chip management and easier traceability. Finally, the detection parameters, defect numbers, and severity of each chip are combined into a feature vector, and all feature vectors are embedded into each cell of a two-dimensional grid in coordinate order.

[0024] S2: Based on the parameter matrix, all defective chips that fail the test are screened out. In the digital model, connected component analysis is performed on all defective chips, and they are divided into several defect clusters.

[0025] The logic for performing connected component analysis on defective chips is as follows: Chips with no defects are classified as normal chips, while chips with other defect types are classified as defective chips. Binary labels are used to distinguish between normal chips and defective chips, with normal chips having a value of 0 and defective chips having a value of 1. The two-dimensional mesh is also binarized. Based on binary labels, all defective chips and their corresponding grids in the two-dimensional grid are identified, and the connected component analysis of the defective chips is performed using the 8-neighborhood two-pass scanning method to obtain several defect clusters.

[0026] Stress release, chemical scratches, and vapor deposition anomalies in semiconductor wafers typically spread along the physical 360° direction (including the diagonal direction). The 4-neighborhood method misses diagonally connected defects, while the 8-neighborhood method can accurately capture topological continuity. Furthermore, the two-pass scanning method has linear time complexity and is more computationally efficient.

[0027] Specifically, the first scan traverses the matrix from left to right and from top to bottom. If the current grid contains a defective chip, it checks its four scanned neighbors (left, top-left, top, and top-right) in its 8-neighborhood. If none of them are marked, a new cluster label is assigned. If there are labels, the smallest label is taken, and the conflict label is added to the set of equivalent pairs. The second scan uses a union-find set to combine all equivalent labels, merging all defective chips within the same connected component into the first cluster. A cluster of defects It can be expressed in functional form as: In the formula Represents a grid The binary labels are set to 0 for normal chips and 1 for defective chips. Indicates the grid after the second scan. The defect cluster label corresponding to the defective chip. Indicates the first A identifier for a defect cluster.

[0028] Understandably, traditional testing techniques treat defective chips as isolated bad spots, completely ignoring the spatial physical continuity between them. Using machine learning clustering algorithms like DBSCAN and K-Means significantly increases computational complexity and requires manual parameter tuning, easily leading to unstable clustering results, making it unsuitable for the demands of industrial automated production. Therefore, this approach uses 8-neighborhood judgment, which not only accurately captures the physical micro-connectivity along the diagonal, ensuring a high degree of consistency between the clustered defect clusters and the actual physical damage areas, but also eliminates the need for iteration and manual hyperparameter adjustment. It can complete full-disk clustering of wafers containing a large number of chips in a short time, greatly improving the real-time processing efficiency of the packaging and testing plant.

[0029] S3: Generate the impact coefficient of each defect cluster based on the number of defective chips, defect type, and severity in each defect cluster.

[0030] For any defect cluster, the logic for generating its influence coefficient is as follows: The detection parameters of all defective chips within the defect cluster are normalized. The product of the normalized detection parameters and the severity is defined as the defect feature value of the corresponding defective chip. The energy factor of the defective cluster is obtained by summing the defect feature values ​​of all defective chips within the defect cluster, and its expression is: In the formula Indicates the first The energy factor of a defect cluster Indicates the first The number of defective chips in a defect cluster, subscript Indicates the index of the defective chip. This indicates the total number of defect types. Index representing the defect type, This represents the corresponding detection parameter after normalization. This indicates the severity of the defect type.

[0031] Based on the number of defective chips within the defect cluster and the area of ​​a single chip, calculate the total area of ​​the defect cluster and simultaneously collect the perimeter of the defect cluster. Based on the total area and perimeter of the defect cluster, and combined with the thermodynamic interfacial energy theory, the shape factor of the defect cluster is calculated. The shape factor is expressed as a fraction, with the numerator being the perimeter and the denominator being the square root of the product of the total area and the constant π, multiplied by two. Its expression is: In the formula Indicates the first The shape factor of a defect cluster , These represent the perimeter and total area of ​​the defect cluster, respectively.

[0032] Based on the total area of ​​the defect cluster and using Saint-Venant's principle, the equivalent stress radius of the defect cluster is calculated. Its expression is: The product of the energy factor, shape factor, and equivalent stress radius is used as the influence coefficient of this defect cluster. Its expression is: It is understandable that the potential physical damage of defect clusters to surrounding qualified chips (such as thermal stress concentration, lattice dislocation diffusion, and CMP chemical residue penetration) follows Saint-Venant's principle in elasticity and the thermodynamic theory of interface boundary energy diffusion. For the same area, the perimeter of the interface of a long, narrow, or serrated defect cluster (such as CMP scratches or lithographic stripes) is much larger than that of a circle. The longer the perimeter, the larger the contact area for the outward penetration and diffusion of the defect physical field (such as crack propagation or charge accumulation), and the higher the risk. Therefore, a shape factor is needed to reflect this actual physical situation. After introducing the shape factor, under the premise of the same number of defective chips, when connected into a long, narrow strip-shaped defect cluster, the total area remains unchanged, but the outer perimeter increases. This causes the shape factor and the influence coefficient to increase simultaneously, consistent with the physical phenomenon that long, narrow scratches will affect more normal, qualified chips.

[0033] S4: Divide the normal chip into several neighboring layers centered on any qualified chip, and calculate the performance score of the normal chip based on the number of defect clusters and the influence coefficient in the neighboring layers.

[0034] The neighboring layers form a concentric square topology ring. For any normal chip, the logic for obtaining its performance score is as follows: An initial score is preset for a normal chip, and then the corresponding distance attenuation factor is calculated based on the order of the neighboring layers. The magnitude of the distance attenuation factor is negatively correlated with the order of the neighboring layers, and is usually set as a power function. ,in Indicates the order of the neighboring layer. This represents the attenuation parameter, which is usually set to 2; Perform topological judgment on each neighbor layer and all defect clusters. If a neighbor layer and any defect cluster have an intersection in the digital model, then the defect cluster is considered to fall into that neighbor layer. For any normal chip Its neighboring layers can be represented in the following form: In the formula This indicates the first [chip] centered on the normal chip. The set of neighboring layers, This represents the coordinates of any chip in the neighboring layer. Overall equivalent to and The Chebyshev distance between the two neighbors is set to 1 for the first-order neighbor layer, representing the 8-neighborhood around the center; and to 2 for the second-order neighbor layer, representing the 16-neighborhood immediately adjacent to the 8-neighborhood around the center, and so on. However, since the effects of physical stress and contamination diffusion in chip manufacturing defects are greatly reduced beyond the distance of three chips, the calculation typically only considers the first three neighbor layers. The product of the distance attenuation factor of each neighboring layer and the sum of the influence coefficients of all defect clusters falling into that neighboring layer is calculated sequentially. This product is then summed over all neighboring layers to obtain the penalty score for the normal chip. The initial score is then subtracted from the penalty score to obtain the performance rating of the normal chip. The calculation formula is as follows: In the formula This indicates the performance score of a normal chip. This represents the preset base score. Indicates the maximum order of the neighboring layers. Index representing the defect cluster, , This represents the total number of defect clusters.

[0035] S5: Traverse all normal chips, classify all normal chips into grades based on performance scores, map the grades of all normal chips back to the digital model, and use different colors to mark the grades.

[0036] When classifying normal chips, a threshold interval method is used, with each chip grade corresponding to a performance score interval and a marking color.

[0037] In this embodiment, normal chips can be divided into four grades: automotive grade, industrial grade, consumer grade, and high-risk grade. The performance score ranges corresponding to these four grades decrease sequentially and have no overlap. Including defective chips, a total of five colors can be used for differentiation: green, blue, yellow, orange, and red. This method can transform abstract physical stress deductions into intuitive multi-color heatmaps, allowing process engineers to identify "dangerous edge areas," "transition buffer zones," and "absolutely safe core areas" on the wafer at a glance. This provides more intuitive feedback for improving front-end manufacturing processes (such as photolithography edge focusing and CMP polishing uniformity), significantly improving the quality control accuracy of the semiconductor packaging and testing process.

[0038] Please see Figure 2 The present invention also provides a wafer testing defect chip marking device for performing the above-described defect chip marking method, comprising: a data acquisition module, a data analysis module, a coefficient calculation module, a performance evaluation module, and a chip marking module.

[0039] The data acquisition module is used to perform quality inspection on the wafer, collect quality data of all chips on the wafer, establish a parameter matrix based on chip coordinates and quality data, and embed the parameter matrix into a two-dimensional digital model; The data analysis module is used to filter out all defective chips that fail the test based on the parameter matrix, perform connected component analysis on all defective chips in the digital model, and divide them into several defect clusters. The coefficient calculation module is used to generate the impact coefficient of each defect cluster based on the number, defect type and severity of all defective chips in each defect cluster; The performance evaluation module is used to divide several neighbor layers centered on any qualified normal chip, and to jointly calculate the performance score of the normal chip based on the number of defect clusters and the influence coefficient in the neighbor layers. The chip marking module is used to traverse all normal chips, classify all normal chips into grades based on performance scores, map the grades of all normal chips back to the digital model, and mark the grades with different colors.

[0040] The present invention also provides a storage medium for storing a computer program, which, when executed by a processor, implements the above-described defect chip marking method.

[0041] The above formulas are all dimensionless calculations. The formulas are derived from software simulations based on a large amount of collected data to obtain the most recent real-world results. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0042] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented in software, the above embodiments can be implemented, in whole or in part, as a computer program product. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution.

[0043] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0044] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for marking defective chips during wafer testing, characterized in that, The specific steps include: S1: Perform quality inspection on the wafer, collect quality data of all chips on the wafer, establish a parameter matrix based on chip coordinates and quality data, and embed the parameter matrix into a two-dimensional digital model, wherein the digital model is a uniform two-dimensional grid; S2: Based on the parameter matrix, all defective chips that fail the test are screened out. In the digital model, connected component analysis is performed on all defective chips, and they are divided into several defect clusters. S3: Based on the number, defect type and severity of all defective chips in each defect cluster, generate the impact coefficient of the defect cluster to quantify the degree of degradation of normal chips by the defect cluster; S4: Divide the normal chip into several neighboring layers with any qualified chip as the center, and calculate the performance score of the normal chip together based on the number of defect clusters and the influence coefficient in the neighboring layers. S5: Traverse all normal chips, classify all normal chips into grades based on performance scores, map the grades of all normal chips back to the digital model, and use different colors to mark the grades.

2. The wafer testing defect chip marking method according to claim 1, characterized in that: The quality inspection includes automatic optical inspection and probe station electrical inspection. The quality data includes chip inspection parameters, defect type, defect number and severity. The inspection parameters include chip size, defect area, leakage current and contact resistance. The defect types include no defects, surface defects, size defects and functional defects. Each defect type corresponds to a preset defect number and each defect type also corresponds to a preset severity.

3. The wafer testing defect chip marking method according to claim 2, characterized in that: Each grid in the two-dimensional grid corresponds to an element in the parameter matrix.

4. The wafer testing defect chip marking method according to claim 3, characterized in that: The logic for performing connected component analysis on defective chips is as follows: Chips with no defects are classified as normal chips, while chips with other defect types are classified as defective chips. Binary labels are used to distinguish between normal chips and defective chips, with normal chips having a value of 0 and defective chips having a value of 1. The two-dimensional mesh is also binarized. Based on binary labels, all defective chips and their corresponding grids in the two-dimensional grid are identified, and the connected component analysis of the defective chips is performed using the 8-neighborhood two-pass scanning method to obtain several defect clusters.

5. The wafer testing defect chip marking method according to claim 4, characterized in that: For any defect cluster, the logic for generating its influence coefficient is as follows: The detection parameters of all defective chips within the defect cluster are normalized. The product of the normalized detection parameters and the severity is defined as the defect feature value of the corresponding defective chip. The energy factor of the defective cluster is obtained by summing the defect feature values ​​of all defective chips in the defect cluster. Based on the number of defective chips within the defect cluster and the area of ​​a single chip, calculate the total area of ​​the defect cluster and simultaneously collect the perimeter of the defect cluster. Based on the total area and perimeter of the defect cluster, and combined with the thermodynamic interface energy theory, the shape factor of the defect cluster is calculated. Based on the total area of ​​the defect cluster, and combined with Saint-Venant's principle, the equivalent stress radius of the defect cluster is calculated, and the product of the energy factor, shape factor, and equivalent stress radius is used as the influence coefficient of the defect cluster.

6. The wafer testing defect chip marking method according to claim 5, characterized in that: The shape factor is expressed as a fraction, with the numerator being the outer perimeter and the denominator being the square root of the product of the total area and the constant π, multiplied by two.

7. The wafer testing defect chip marking method according to claim 5, characterized in that: The neighbor layer is a concentric square topology ring. For any normal chip, the logic for obtaining its performance score is as follows: An initial score is preset for a normal chip, and then the corresponding distance attenuation factor is calculated based on the order of the neighboring layers. The magnitude of the distance attenuation factor is negatively correlated with the order of the neighboring layers. Perform topological judgment on each neighbor layer and all defect clusters. If a neighbor layer and any defect cluster have an intersection in the digital model, then the defect cluster is considered to fall into that neighbor layer. The product of the distance attenuation factor of each neighboring layer and the sum of the influence coefficients of all defect clusters falling into that neighboring layer is calculated sequentially, and then summed over all neighboring layers to obtain the penalty score of the normal chip. Subtracting the penalty score from the initial score yields the performance rating of the normal chip.

8. The wafer testing defect chip marking method according to claim 1, characterized in that: When classifying normal chips, a threshold interval method is used, with each chip grade corresponding to a performance score interval and a marking color.

9. A wafer testing defect chip marking device, characterized in that: The defective chip marking device is used to perform the defective chip marking method as described in any one of claims 1-8, including: The data acquisition module is used to perform quality inspection on the wafer, collect quality data of all chips on the wafer, establish a parameter matrix based on chip coordinates and quality data, and embed the parameter matrix into a two-dimensional digital model. The data analysis module is used to filter out all defective chips that fail the test based on the parameter matrix, perform connected component analysis on all defective chips in the digital model, and divide them into several defect clusters. The coefficient calculation module is used to generate the influence coefficient of each defect cluster based on the number, defect type and severity of all defective chips in each defect cluster. The performance evaluation module is used to divide a normal chip that has passed the test into several neighboring layers, and to jointly calculate the performance score of the normal chip based on the number of defect clusters and the influence coefficient in the neighboring layers. The chip marking module is used to traverse all normal chips, classify all normal chips into grades based on performance scores, map the grades of all normal chips back to the digital model, and mark the grades with different colors.

10. A storage medium, characterized in that: The storage medium is used to store a computer program, which, when executed by a processor, implements the defect chip marking method as described in any one of claims 1-8.

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