A test structure of gate-source shared contact hole and a detection method of the test structure

Abstract

Embodiments of the present application provide a test structure of gate-source shared contact hole and a detection method of the test structure. The structure is constructed by building a stack structure containing an active region, a first gate, a second gate and an interlayer dielectric layer covering them in a test unit, and realizing the electrical connection between the active region and the gate by using the first gate-source shared contact hole and the second gate-source shared contact hole penetrating through the interlayer dielectric layer, so that the test structure directly simulates the actual structure of the polysilicon head shared contact hole in the SRAM bit cell in the physical layout and the material stacking. By designing a first test link and a second test link containing a plurality of test units connected in series, the process state of a single contact hole is converted into the electrical parameter change of the whole link. This design enables the test structure to accurately capture the metal bridging or resistance abnormality caused by large-size cavities, thereby effectively identifying and intercepting potential reliability risks caused by process deviation of the shared contact hole in the wafer test stage.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing and testing technology, specifically to a test structure for a gate-source shared contact hole and a method for detecting the test structure. Background Technology

[0002] As semiconductor process nodes continue to shrink, Static Random Access Memory (SRAM), as the core memory unit with the largest area in a chip, is facing increasing demands for compactness and process complexity. In advanced SRAM bit cell designs, to achieve the ultimate area reduction, a shared contact structure with polysilicon headers is typically used. This means that the source / drain of two inverters or the polysilicon gate are connected simultaneously through a single contact hole to reduce the area occupied by the contact hole.

[0003] However, at small-size process nodes, the dual demands for device performance and reliability lead to a significant increase in the thickness of the polysilicon protective layer. This increased thickness poses a significant challenge to the subsequent interlayer dielectric (ILD) deposition process, as it easily forms voids in trench structures with extremely high aspect ratios. Although in some advanced processes, due to the extremely narrow process variation window, completely avoiding the formation of micro-voids is physically almost impossible, and micro-voids usually do not have a substantial impact on yield; however, once large-sized voids are formed, tungsten metal is very likely to flow into these voids during subsequent shared contact via etching or tungsten (W) filling deposition. This abnormal metal filling can not only cause bridging failures between adjacent devices, resulting in short circuits, but also seriously affect the long-term electrical reliability of the device.

[0004] To monitor the process quality of contact holes and vias, existing wafer test key designs typically employ conventional structures such as via chains or Kelvin structures. However, these traditional test structures have significant limitations: (1) they cannot accurately reflect the complex actual topography of SRAM shared contact holes, and (2) they cannot reproduce the large-size voids unique to SRAM.

[0005] Therefore, the technical problem that needs to be solved is how to provide a test structure that can effectively monitor the resistance of shared contact holes and potential void defects in a real-world SRAM shared contact hole process environment while saving chip area. Summary of the Invention

[0006] This application provides a test structure for a gate-source shared contact hole, utilizing a real-world SRAM shared contact hole process environment. While saving chip area, it effectively monitors the resistance and potential void defects of the shared contact hole. This application also provides a detection method for the test structure, which can effectively monitor the resistance and potential void defects of the shared contact hole.

[0007] The specific plan is as follows: In a first aspect, embodiments of this application provide a test structure for a gate-source shared contact hole, comprising: a first test link and a second test link, wherein each test link includes multiple test units connected in series, and any two adjacent test units are electrically connected through a conductive layer; wherein each test unit includes: an active region, a first gate and a second gate; an interlayer dielectric layer covering the active region, the first gate and the second gate; and a conductive layer located above the interlayer dielectric layer; a first side of the active region is electrically connected to the first gate through a conductive material penetrating the interlayer dielectric layer in the first gate-source shared contact hole, and a second side of the active region is electrically connected through a conductive material penetrating the interlayer dielectric layer in the second gate-source shared contact hole. The material is electrically connected to the second gate; the conductive layer includes alternately distributed first conductive portions and second conductive portions; the first end of the first test link is the first conductive portion of the M1 test unit, and the last end of the first test link is the second conductive portion of the M1+n test unit; the first end of the second test link is the second side of the active region of the M2 test unit, and the last end of the second test link is the first side of the active region of the M2+n test unit; the test structure is used to obtain the parameter results of the electrical parameters of the first test link and the electrical parameters of the second test link when powered on, and the parameter results are used to reflect the fabrication quality results of the device structure formed synchronously with the test structure.

[0008] Optionally, in the first test link, the first conductive part of the M1th test unit is used as the first electrical signal start detection point, and the second conductive part of the M1+nth test unit is used as the first electrical signal end detection point. The electrical signal conduction direction in the first test link is as follows: within each test unit, the signal is vertically conducted through the first conductive part to the first side of the active region via the conductive material in the first gate-source shared contact hole, horizontally conducted from the first side of the active region to the second side of the active region, and vertically conducted from the second side of the active region to the second conductive part via the conductive material in the second gate-source shared contact hole; in the second test link, the signal is... The second side of the active region of the M2 test unit is the second electrical signal start detection point, and the first side of the active region of the M2+n test unit is the second electrical signal end detection point. The electrical signal conduction direction in the second test link is as follows: in the current test unit, the signal is vertically conducted to the second conductive part through the conductive material in the second gate-source shared contact hole via the second side of the active region, and horizontally conducted to the first conductive part of the next adjacent test unit via the second conductive part of the current test unit. In the next adjacent test unit, the signal is vertically conducted to the first side of the active region via the conductive material in the first gate-source shared contact hole.

[0009] Optionally, the test structure is disposed in the dicing channel of the wafer.

[0010] Optionally, the test structure uses the same manufacturing process as the device functional area of ​​the wafer.

[0011] Optionally, both the first gate and the second gate extend in a strip shape. The first end of the first gate is connected to the conductive material in the first gate-source shared contact hole in the first test link, and the first end of the second gate is connected to the conductive material in the second gate-source shared contact hole in the first test link. The second ends of the first gate and the second gate respectively extend above the active region in the second test link and to the first gate-source shared contact hole and the second gate-source shared contact hole that are not connected to the second test link.

[0012] Optionally, the fabrication quality results of the device structure are used to characterize whether there are any abnormal electrical parameters in at least one of the first gate-source shared contact hole and the second gate-source shared contact hole.

[0013] Secondly, embodiments of this application provide a method for detecting a test structure, wherein the test structure is the test structure described in the first aspect. The method includes: applying test signals to the beginning and end of a first test link of the test structure to obtain a first electrical parameter; applying test signals to the beginning and end of a second test link of the test structure to obtain a second electrical parameter; and determining a test result of the test structure based on the parameter result between the first electrical parameter and the second electrical parameter, which is used to reflect the fabrication quality result of a device structure formed synchronously with the test structure.

[0014] Optionally, the fabrication quality result is used to characterize whether at least one of the first gate-source shared contact hole and the second gate-source shared contact hole in the device structure formed synchronously with the test structure has abnormal electrical parameters; determining the test result of the test structure based on the parameter result between the first electrical parameter and the second electrical parameter includes: judging whether at least one of the first gate-source shared contact hole and the second gate-source shared contact hole has abnormal electrical parameters based on the degree of difference between the first electrical parameter and the second electrical parameter.

[0015] Optionally, the first electrical parameter includes a first resistance value, and the second electrical parameter includes a second resistance value. The step of determining whether at least one of the first gate-source shared contact hole and the second gate-source shared contact hole has an electrical parameter abnormality based on the degree of difference between the first electrical parameter and the second electrical parameter includes: obtaining a resistance difference value between the first resistance value and the second resistance value, wherein the resistance difference value is the absolute value of the difference between the first resistance value and the second resistance value, or the ratio of the first resistance value to the second resistance value; if the resistance difference value is greater than a preset difference threshold, and at least one of the first resistance value and the second resistance value is less than a preset short-circuit resistance threshold, then the electrical parameter abnormality is determined to be a short-circuit defect; if both the first resistance value and the second resistance value are greater than a preset open-circuit resistance threshold, then the electrical parameter abnormality is determined to be an open-circuit defect.

[0016] Compared with the prior art, this application has the following advantages: This application provides a test structure for a gate-source shared contact hole, including: a first test link and a second test link, wherein each test link includes multiple test units connected in series, and any two adjacent test units are electrically connected through a conductive layer; wherein each test unit includes: an active region, a first gate and a second gate; an interlayer dielectric layer covering the active region, the first gate and the second gate; and a conductive layer located above the interlayer dielectric layer; a first side of the active region is electrically connected to the first gate through a conductive material penetrating the interlayer dielectric layer in the first gate-source shared contact hole, and a second side of the active region is electrically connected through a conductive material penetrating the interlayer dielectric layer in the second gate-source shared contact hole. The conductive layer is electrically connected to the second gate; the conductive layer includes alternately distributed first conductive portions and second conductive portions; the first end of the first test link is the first conductive portion of the M1 test unit, and the last end of the first test link is the second conductive portion of the M1+n test unit; the first end of the second test link is the second side of the active region of the M2 test unit, and the last end of the second test link is the first side of the active region of the M2+n test unit; the test structure is used to obtain the parameter results of the electrical parameters of the first test link and the electrical parameters of the second test link when powered on, and the parameter results are used to reflect the fabrication quality results of the device structure formed synchronously with the test structure.

[0017] The gate-source shared contact hole test structure provided in this application constructs a stacked structure in the test unit containing an active region, a first gate, a second gate, and an interlayer dielectric layer covering them. The first and second gate-source shared contact holes penetrating the interlayer dielectric layer achieve electrical connection between the active region and the gate. This allows the test structure to directly simulate the actual structure of the polysilicon head shared contact hole in an SRAM bit cell in terms of physical layout and material stacking. This construction allows the test structure to undergo the same etching, deposition, and chemical mechanical polishing processes as the SRAM array during wafer fabrication, thus realistically replicating the void distribution characteristics of the interlayer dielectric layer caused by the high aspect ratio and thick protective layer inside the SRAM. Based on this, by designing a first test link and a second test link containing multiple test units connected in series, the process state of a single contact hole is transformed into changes in the electrical parameters of the entire link. When process fluctuations cause large voids in the interlayer dielectric layer, and abnormal inflow occurs during subsequent metal filling, the resistance or leakage current of the link will undergo measurable changes. This design eliminates the contradiction that conventional test structures cannot reflect the true internal topography of SRAM due to differences in pattern density and load effects. This allows the test structure to accurately capture metal bridging or resistance anomalies caused by large-sized voids, thereby effectively identifying and intercepting potential reliability risks caused by process deviations in shared contact holes during the wafer testing stage. Attached Figure Description

[0018] Figure 1 This is a top view schematic diagram of a semiconductor test structure provided in the first embodiment of this application.

[0019] Figure 2 This is a cross-sectional view of the test structure of the first test link provided in the first embodiment of this application.

[0020] Figure 3 This is a cross-sectional view of the test structure of the second test link provided in the first embodiment of this application.

[0021] Figure 4 This is a flowchart of a testing method for a test structure provided in the second embodiment of this application.

[0022] In the attached figures, the following labels are used: 01-Active region, 01-1-First side of the active region, 01-2-Second side of the active region; 02-Gate, 02-1-First gate, 02-11-First end of the first gate, 02-12-Second end of the first gate, 02-2-Second gate, 02-21-First end of the second gate, 02-22-Second end of the second gate; 03-Gate-source shared contact hole, 03-1-First gate-source shared contact hole, 03-2-Second gate-source shared contact hole; 04-Interlayer dielectric layer; 05-Conductive layer, 05-1-First conductive portion, 05-2 - Second conductive part; 06- First electrical signal start detection point, 07- First electrical signal end detection point, 08- Second electrical signal start detection point, 09- Second electrical signal end detection point; 10- First shallow trench isolation structure; 11- Second shallow trench isolation structure; 100- First test link, 101- M1 test unit, 102- Second M1-1 test unit, 103- M1+n test unit; 200- Second test link, 201- M2 test unit, 202- M2+1 test unit, 203- M2+n test unit. Detailed Implementation

[0023] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0024] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0025] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0026] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0027] As semiconductor process nodes continue to shrink, Static Random Access Memory (SRAM), as the core memory unit with the largest area in a chip, is facing increasing demands for compactness and process complexity. In advanced SRAM bit cell designs, to achieve the ultimate area reduction, a shared contact structure with polysilicon headers is typically used. This means that the source / drain of two inverters or the polysilicon gate are connected simultaneously through a single contact hole to reduce the area occupied by the contact hole.

[0028] However, at small-size process nodes, the dual demands for device performance and reliability lead to a significant increase in the thickness of the polysilicon protective layer. This increased thickness poses a significant challenge to the subsequent interlayer dielectric (ILD) deposition process, as it easily forms voids in trench structures with extremely high aspect ratios. Although in some advanced processes, due to the extremely narrow process variation window, completely avoiding the formation of micro-voids is physically almost impossible, and micro-voids usually do not have a substantial impact on yield; however, once large-sized voids are formed, tungsten metal is very likely to flow into these voids during subsequent shared contact via etching or tungsten (W) filling deposition. This abnormal metal filling can not only cause bridging failures between adjacent devices, resulting in short circuits, but also seriously affect the long-term electrical reliability of the device.

[0029] To monitor the process quality of contact holes and vias, existing wafer test key designs typically employ conventional structures such as via chains or Kelvin structures. However, these traditional test structures have significant limitations: (1) Significant differences in topography: Conventional via chains or Kelvin structures are usually located in scribe lines or specific test areas, and the pattern density, dielectric layer thickness, and etching load effects around them are significantly different from the highly dense actual environment inside the SRAM array. Therefore, they cannot truly reflect the complex actual topography at the shared contact holes of the SRAM.

[0030] (2) Inability to effectively capture specific defects: Due to the differences in terrain and process environment, conventional test structures may not be able to reproduce the large-size void problem unique to SRAM. Even if the conventional test key test passes, the shared contact holes inside the SRAM may still experience abnormal tungsten filling due to the unique local load effect, resulting in "missed test" phenomenon, which in turn leads to reliability risks after product shipment.

[0031] Therefore, the technical problem that needs to be solved is how to provide a test structure that can effectively monitor the resistance of shared contact holes and potential void defects in a real-world SRAM shared contact hole process environment while saving chip area.

[0032] To address the aforementioned technical problems, the first embodiment of this application provides a test structure for a gate-source shared contact hole. The following is combined with… Figures 1-3 The present invention will be further described in detail with specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form, using non-precise proportions, and are only used to facilitate and clarify the explanation of the embodiments.

[0033] The test structure provided in the first embodiment of this application is disposed in the dicing channel of a wafer. This test structure uses the same manufacturing process as the device functional area of ​​the wafer. This test structure directly simulates the physical layout and material stacking order of the shared contact holes in the polysilicon headers of SRAM bit cells. Therefore, during wafer manufacturing, this test structure undergoes the exact same etching, deposition, and chemical mechanical polishing processes as the SRAM array, which can realistically reflect the formation of interlayer dielectric voids caused by factors such as high aspect ratio and thick protective layers within the SRAM, especially the distribution characteristics of large-size voids. Since the shared contact holes in the test structure are fabricated synchronously with the actual SRAM device, when process fluctuations cause large-size voids in the interlayer dielectric layer, the subsequent tungsten metal filling process will also result in abnormal inflow into the contact holes of the test structure.

[0034] Please refer to Figure 1 This embodiment of a test structure for a gate-source shared contact hole includes: a first test link 100 and a second test link 200, wherein each test link contains multiple test units connected in series, and any two adjacent test units are electrically connected through a conductive layer 05. Figure 2 A cross-sectional view of the first test link 100 is shown, including the M1th test unit 101, the second M1-1th test unit 102, ..., the M1+nth test unit 103. The distribution of the test units across the layers in the depth direction and the current conduction in the first test link can be observed. Figure 3 A cross-sectional view of the M2 test unit 201, M2+1 test unit 202, ..., M2+n test unit 203 of the second test link 200 is shown. The distribution of the test units across layers in the depth direction and the current conduction in the second test link can be observed. The test unit includes the following components: active region 01 (e.g., ... Figure 2 In the middle, the first side of the active region 01-1, the second side of the active region 01-2), gate 02 (as shown) Figure 2 In the middle, the first gate 02-1, the second gate 02-2), and the gate-source shared contact hole 03 (such as... Figure 2 In the middle, the first gate-source shared contact hole 03-1, the second gate-source shared contact hole 03-2), interlayer dielectric layer 04 (such as Figure 2 As shown), conductive layer 05 (as shown) Figure 2 In the middle, the conductive layer includes a first conductive part 05-1 and a second conductive part 05-2.

[0035] The test unit specifically includes: an active region 01, a first gate 02-1 and a second gate 02-2; an interlayer dielectric layer 04 covering the active region 01, the first gate 02-1 and the second gate 02-2; a conductive layer 05 located above the interlayer dielectric layer 04; the first side 01-1 of the active region is electrically connected to the first gate 02-1 through a conductive material penetrating the first gate-source shared contact hole 03-1 of the interlayer dielectric layer 04, and the second side 01-2 of the active region is electrically connected to the second gate 02 through a conductive material penetrating the second gate-source shared contact hole 03-2 of the interlayer dielectric layer 04.

[0036] The conductive layer 05 includes alternating first conductive portions 05-1 and second conductive portions 05-2.

[0037] The first side 01-1 of the active region is electrically connected to the first gate 02-1 through a conductive material within the first gate-source shared contact hole 03-1 penetrating the interlayer dielectric layer 04. Specifically, the first side 01-1 of the active region and the first gate 02-1 are connected to the lower longitudinal portion of the conductive material within the first gate-source shared contact hole 03-1 penetrating the interlayer dielectric layer 04. Furthermore, a first conductive portion 05-1 is also connected to the upper longitudinal portion of the conductive material within the first gate-source shared contact hole 03-1.

[0038] like Figure 2 and Figure 3 It is known that the first gate-source shared contact hole 03-1 is vertically distributed in the interlayer dielectric layer 04. The lower part of the first gate-source shared contact hole 03-1 is connected to the first gate 02-1 at a first depth position through the conductive material it fills, and to the first side 01-1 of the active region at a second depth position. The first depth is less than the second depth. The top of the first gate-source shared contact hole 03-1 is connected to the first conductive part 05-1 of the conductive layer through the conductive material it fills. The first depth position can be the distance between the top surface of the first gate 02-1 and the top surface of the interlayer dielectric layer 04, or the distance between the top surface of the second gate 02-2 and the top surface of the interlayer dielectric layer 04. The second depth position can be the distance between the top surface of the active region and the top surface of the interlayer dielectric layer 04.

[0039] The second side 01-2 of the active region is electrically connected to the second gate 02-2 through a conductive material within the second gate-source shared contact hole 03-2 penetrating the interlayer dielectric layer 04. Specifically, the second side 01-2 of the active region and the second gate 02-2 are connected to the lower longitudinal portion of the conductive material within the second gate-source shared contact hole 03-2 penetrating the interlayer dielectric layer 04. Furthermore, a second conductive portion 05-2 is also connected to the upper longitudinal portion of the conductive material within the second gate-source shared contact hole 03-2.

[0040] Continue to refer to Figure 2 and Figure 3 The second gate-source shared contact hole 03-2 is vertically distributed in the interlayer dielectric layer 04. The lower part of the second gate-source shared contact hole 03-2 is connected to the second gate 02-2 at a first depth position through the conductive material it is filled with, and the second side 01-2 of the active region is connected at the second depth position. The top of the second gate-source shared contact hole 03-2 is connected to the second conductive part 05-2 of the conductive layer through the conductive material it is filled with.

[0041] like Figure 1 As shown, both the first gate 02-1 and the second gate 02-2 extend in a strip shape. The first end 02-11 of the first gate is connected to the conductive material in the first gate-source shared contact hole 03-1 in the first test link 100, and the first end 02-21 of the second gate is connected to the conductive material in the second gate-source shared contact hole 03-2 in the first test link 100. The second ends of the first gate 02-1 and the second gate 02-2 respectively (as shown) Figure 1 The second end 02-12 of the first gate and the second end 02-22 of the second gate both extend above the active region 01 in the second test link 200, and the first gate-source shared contact hole and the second gate-source shared contact hole are not connected to the second test link.

[0042] Continue to refer to Figure 2 A first shallow trench isolation structure 10 is provided at the bottom of the first gate-source shared contact hole 03-1 and adjacent to the first side 01-1 of the active region. A first gate 02-1 is also provided above the first shallow trench isolation structure 10. A second shallow trench isolation structure 11 is provided at the bottom of the second gate-source shared contact hole 03-2 and adjacent to the second side 01-2 of the active region. A second gate 02-2 is also provided above the second shallow trench isolation structure 11. In other embodiments of this application, the isolation structures at the bottom of the first gate-source shared contact hole 03-1 and the second gate-source shared contact hole 03-2 can also be other structures that can serve an isolation function.

[0043] The first end of the first test link 100 is the first conductive part 05-1 of the M1 test unit, and the last end of the first test link 100 is the second conductive part 05-2 of the M1+n test unit.

[0044] Specifically, such as Figure 2As shown, in the first test link 100, the first conductive part of the M1 test unit is taken as the first electrical signal start detection point 06, and the second conductive part of the M1+n test unit is taken as the first electrical signal end detection point 07. The electrical signal conduction direction in the first test link 100 is as follows: inside each test unit, the signal is vertically conducted through the conductive material in the first gate-source shared contact hole 03-1 via the first conductive part 05-1 to the first side 01-1 of the active region, horizontally conducted from the first side 01-1 of the active region to the second side 01-2 of the active region, and vertically conducted from the second side 01-2 of the active region via the conductive material in the second gate-source shared contact hole 03-2 to the second conductive part 05-2.

[0045] The first end of the second test link 200 is the second side 01-2 of the active region of the M2 test unit, and the last end of the second test link 200 is the first side 01-1 of the active region of the M2+n test unit.

[0046] Specifically, such as Figure 3 As shown, in the second test link 200, the second side 01-2 of the active region of the M2 test unit is the second electrical signal start detection point 08, and the first side 01-1 of the active region of the M2+n test unit is the second electrical signal end detection point 09. The electrical signal conduction direction in the second test link 200 is as follows: in the current test unit, the signal is vertically conducted to the second conductive part 05-2 via the conductive material in the second gate-source shared contact hole 03-2 through the second side 01-2 of the active region, and horizontally conducted to the first conductive part 05-1 of the next adjacent test unit through the second conductive part 05-2 of the current test unit. In the next adjacent test unit, the signal is vertically conducted to the first side 01-1 of the active region through the conductive material in the first gate-source shared contact hole 03-1 through the first conductive part 05-1.

[0047] By designing a long chain structure consisting of multiple test units connected in series (first test link and second test link), the impact of a single contact hole defect on the overall electrical parameters can be significantly amplified. Once a shared contact hole experiences a local short circuit or abnormal resistance due to tungsten filling into the void, the electrical parameters of the entire link (such as resistance value and leakage current) will undergo measurable changes, thereby enabling early warning of potential bridging failures and long-term reliability issues.

[0048] Traditional Via Chain primarily monitors the connectivity of the via itself, while Kelvin structures focus on accurately measuring the resistance of individual contacts. However, both are located in scribe lines or independent test areas, and their pattern density, load effects, and dielectric layer stress environment differ fundamentally from those of the SRAM core area. This application's embodiment integrates a dual-link, multi-cell shared contact via test structure within a limited area, avoiding excessive chip area usage while ensuring targeted monitoring of the SRAM-specific process window. Especially in small-size processes, when the process fluctuation window is narrow and micro-voids are unavoidable, this structure can effectively distinguish between harmless small voids and fatal large voids, improving the accuracy of yield assessment.

[0049] The first test link 100 extends from the first conductive part of unit M1 to the second conductive part of unit M1+n, connected in series along the conductive path; the second test link 200 connects from the second side of the active region of unit M2 to the first side of the active region of unit M2+n, connected in series along the active region path. This dual-link design provides two different current paths and electric field distributions, enabling the exposure of filling defects or interface problems of shared contact holes in different directions from different angles. This improves the sensitivity to latent defects in complex three-dimensional structures and avoids the risk of missed detection that may exist with a single test path.

[0050] The test structure provided in this application embodiment is used to acquire the electrical parameters of the first test link 100 and the second test link 200 when powered on. The parameter results are used to reflect the fabrication quality of the device structure formed synchronously with the test structure. The fabrication quality of the device structure is used to characterize whether at least one of the first gate-source shared contact hole 03-1 and the second gate-source shared contact hole 03-2 has abnormal electrical parameters.

[0051] Specifically, during test structure operation, after powering on the test structure, test signals are applied to the beginning and end of the first test link to obtain the first electrical parameters; test signals are then applied to the beginning and end of the second test link to obtain the second electrical parameters. By analyzing the degree of difference between the first and second electrical parameters, it is determined whether at least one of the first and second gate-source shared contact holes in at least one test unit of the test structure exhibits abnormal electrical parameters. This analysis determines whether a short-circuit defect or an open-circuit defect exists in the test structure, and based on the analysis results of the test structure, the defect detection results of the wafer device structure generated synchronously with the test structure are determined.

[0052] This allows for the rapid identification of systemic anomalies caused by shared contact hole process deviations during the wafer testing phase. This data can be used not only for the acceptance / acceptance determination of individual wafers but also fed back to the front-end process module for root cause analysis and parameter adjustments, forming a closed-loop quality control system. Particularly in the early stages of advanced process mass production or during process change verification, this testing structure can serve as a critical process health indicator, preventing batch reliability incidents caused by shared contact hole defects from reaching the customer.

[0053] Second Embodiment Based on the first embodiment, the second embodiment of this application provides a method for detecting a test structure, wherein the test structure is the test structure described in the first embodiment. Please refer to... Figure 4 The flowchart of the detection method for the test structure provided in the second embodiment of this application includes: steps S401 to S403.

[0054] Step S401: Apply test signals to the beginning and end of the first test link of the test structure to obtain the first electrical parameters; Step S402: Apply test signals to the beginning and end of the second test link of the test structure to obtain the second electrical parameters; Step S403: Determine the test result of the test structure based on the parameter result between the first electrical parameter and the second electrical parameter, so as to reflect the fabrication quality result of the device structure formed synchronously with the test structure.

[0055] The fabrication quality results are used to characterize whether at least one of the first gate-source shared contact hole and the second gate-source shared contact hole in the device structure formed synchronously with the test structure has abnormal electrical parameters.

[0056] Specifically, step S403 involves determining whether there is an abnormality in the electrical parameters of at least one of the first gate-source shared contact hole and the second gate-source shared contact hole, based on the degree of difference between the first electrical parameter and the second electrical parameter.

[0057] Based on the degree of difference between the electrical parameters of the first test link and the electrical parameters of the second test link, this application determines whether there is an electrical parameter abnormality in at least one of the first gate-source shared contact hole and the second gate-source shared contact hole, thereby determining whether there is an abnormality in the fabrication process of the test structure, and thus determining whether there is an abnormality in the fabrication process of the wafer device structure that grows synchronously with the test result.

[0058] The first electrical parameter includes a first resistance value, and the second electrical parameter includes a second resistance value. The step of determining whether at least one of the first gate-source shared contact hole and the second gate-source shared contact hole has an abnormal electrical parameter based on the degree of difference between the first electrical parameter and the second electrical parameter includes: obtaining the resistance difference value between the first resistance value and the second resistance value, wherein the resistance difference value is the absolute value of the difference between the first resistance value and the second resistance value, or the ratio of the first resistance value and the second resistance value. (1) Short circuit defect judgment: If the resistance difference value is greater than a preset difference threshold, and at least one of the first resistance value and the second resistance value is less than a preset short-circuit resistance threshold, then the abnormal electrical parameter is determined to be a short-circuit defect.

[0059] Short-circuit resistance threshold ( This threshold is used to characterize the upper limit of resistance when a metal bridge occurs in the contact hole. In a normal gate-source shared contact hole structure, the current flowing through the contact hole, active region, and polysilicon gate will exhibit a certain intrinsic resistance. When process fluctuations cause voids in the interlayer dielectric layer to be abnormally filled with metals such as tungsten (W), and the filled metal overflows and connects to adjacent conductive components (such as adjacent gates or active regions), a low-impedance bypass channel is formed. At this time, the overall resistance value of the test link will decrease significantly. When the measured resistance value is less than the short-circuit resistance threshold ( If the measured resistance value of the first test link is less than the short-circuit resistance threshold, it indicates the presence of an unexpected low-resistance path in the test link. For example, if the measured resistance value of the first test link is less than the short-circuit resistance threshold, it indicates the presence of an unexpected low-resistance path in the test link. If the measured resistance value of the second test link is less than the short-circuit resistance threshold, it indicates that an unexpected low-resistance path exists in the first test link. If the value is 0, it indicates that there is an unexpected low-resistance path in the second test link.

[0060] This application designs two parallel test paths: a first test path and a second test path. The only difference between the first and second test paths is the location where the electrical signal is applied during operation. The starting and ending signal detection points of the first test path are the first and second conductive parts of the conductive layer, respectively. The starting and ending signal detection points of the second test path are the second side and the first side of the active region, respectively.

[0061] Under ideal manufacturing conditions, two links should have similar structures and lengths, and their resistance values ​​should be essentially the same. However, short-circuit defects are often random and localized. For example, they may only occur at a specific shared contact point, causing one link to short-circuit while the other link remains normal; or the location and extent of the short circuits may differ between the two links.

[0062] When a short circuit occurs, the resistance of the affected link drops sharply, while the resistance of the unaffected link or the link affected to varying degrees remains relatively high, resulting in a difference in resistance between the two links. () significantly increased.

[0063] Therefore, this application determines that the test structure has a short-circuit defect by using a first judgment condition (the resistance difference value is greater than a preset difference threshold) and a second judgment condition (at least one of the first resistance value and the second resistance value is less than a preset short-circuit resistance threshold). The first judgment condition is to eliminate misjudgments caused by wafer-level uniform process deviations (for example, during wafer manufacturing, the deposition thickness of the metal layer on the entire wafer increases, or the overall doping concentration is low. This effect is uniform and will cause the resistance values ​​of all devices on the wafer to be either too high or too low).

[0064] The judgment result is as follows: if the resistance difference value is greater than the preset difference threshold, and at least one of the first resistance value and the second resistance value is less than the preset short-circuit resistance threshold, it indicates that the short-circuit defect in the test structure is caused by abnormal filling of the conductive material in the first gate-source shared contact hole, or the short-circuit defect in the test structure is caused by abnormal filling of the conductive material in the second gate-source shared contact hole.

[0065] This application combines the first and second judgment conditions to improve the accuracy of the test results analysis for defects caused by abnormal filling of conductive material in the gate-source shared contact hole.

[0066] (2) Determination of open circuit defects: If both the first resistance value and the second resistance value are greater than the preset circuit breaker resistance threshold, then the abnormal electrical parameter is determined to be a circuit breaker defect.

[0067] Disconnection resistance threshold ( This threshold is used to characterize the lower limit of resistance when the contact hole connection fails. Open circuit defects are usually caused by incomplete etching of the contact hole (residual dielectric layer), high-resistivity interface at the bottom of the contact hole (such as failure of silicide formation), or insufficient metal filling in the contact hole (the presence of voids leads to a reduction in the conductive cross-sectional area).

[0068] Open circuits or high-resistance defects typically manifest as disruption of the current path or a severe decrease in conductivity. When such defects occur in a test link, current cannot flow smoothly or is greatly impeded, causing the measured resistance value to tend towards infinity or far exceed the normal design value. This is because the total resistance of a normal contact chain (assuming dozens of holes in series) is typically between several hundred ohms and several thousand ohms. Once open-circuited, the resistance becomes at the level of an insulator. Therefore, the open-circuit resistance threshold ( The resistance must be set very high, much higher than the resistance of a normal chain, to ensure that there will be no misjudgment.

[0069] Because an open circuit defect interrupts the conductive path of the affected link, regardless of whether the defect occurs in the first test link, the second test link, or both links simultaneously, the result is an abnormally high resistance value. Therefore, if either (or both) the first or second resistance value exceeds the preset open circuit resistance threshold, the defect will be detected. This indicates that an open circuit or high-resistance failure has occurred.

[0070] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A test structure for a shared gate-source contact hole, characterized in that, include: The first test link and the second test link, wherein each test link contains multiple test units connected in series, and any two adjacent test units are electrically connected through a conductive layer. The test unit includes: an active region, a first gate, and a second gate; an interlayer dielectric layer covering the active region, the first gate, and the second gate; a conductive layer located above the interlayer dielectric layer; a first side of the active region is electrically connected to the first gate through a conductive material in a first gate-source shared contact hole penetrating the interlayer dielectric layer, and a second side of the active region is electrically connected to the second gate through a conductive material in a second gate-source shared contact hole penetrating the interlayer dielectric layer. The conductive layer includes alternating first and second conductive portions; The first end of the first test link is the first conductive part of the M1 test unit, and the last end of the first test link is the second conductive part of the M1+n test unit. The first end of the second test link is the second side of the active region of the M2 test unit, and the last end of the second test link is the first side of the active region of the M2+n test unit. The test structure is used to acquire the electrical parameters of the first test link and the electrical parameters of the second test link when powered on. The parameter results are used to reflect the fabrication quality of the device structure formed synchronously with the test structure.

2. The test structure according to claim 1, characterized in that, In the first test link, the first conductive part of the M1 test unit is used as the first electrical signal start detection point, and the second conductive part of the M1+n test unit is used as the first electrical signal end detection point. The electrical signal conduction direction in the first test link is as follows: inside each test unit, the signal is vertically conducted through the first conductive part to the first side of the active region via the conductive material in the first gate-source shared contact hole, horizontally conducted from the first side of the active region to the second side of the active region, and vertically conducted from the second side of the active region to the second conductive part via the conductive material in the second gate-source shared contact hole. In the second test link, the second side of the active region of the M2 test unit is taken as the second electrical signal start detection point, and the first side of the active region of the M2+n test unit is taken as the second electrical signal end detection point. The electrical signal conduction direction in the second test link is as follows: in the current test unit, the signal is vertically conducted to the second conductive part through the conductive material in the second gate-source shared contact hole via the second side of the active region, and horizontally conducted to the first conductive part of the next adjacent test unit via the second conductive part of the current test unit. In the next adjacent test unit, the signal is vertically conducted to the first side of the active region via the conductive material in the first gate-source shared contact hole.

3. The test structure according to claim 1, characterized in that, The test structure is set in the dicing channel of the wafer.

4. The test structure according to claim 1, characterized in that, The test structure uses the same manufacturing process as the device functional area of ​​the wafer.

5. The test structure according to claim 1, characterized in that, Both the first gate and the second gate extend in a strip shape. The first end of the first gate is connected to the conductive material in the first gate-source shared contact hole in the first test link. The first end of the second gate is connected to the conductive material in the second gate-source shared contact hole in the first test link. The second ends of the first gate and the second gate respectively extend above the active region in the second test link and are not connected to the first gate-source shared contact hole and the second gate-source shared contact hole of the second test link.

6. The test structure according to claim 1, characterized in that, The fabrication quality results of the device structure are used to characterize whether there are any abnormal electrical parameters in at least one of the first gate-source shared contact hole and the second gate-source shared contact hole.

7. A method for detecting a test structure, characterized in that, The test structure is the test structure according to any one of claims 1 to 6, and the method includes: Test signals are applied to the beginning and end of the first test link of the test structure to obtain the first electrical parameters; Test signals are applied to the beginning and end of the second test link of the test structure to obtain the second electrical parameters; Based on the parameter results between the first electrical parameter and the second electrical parameter, the test results of the test structure are determined, which are used to reflect the fabrication quality results of the device structure formed synchronously with the test structure.

8. The method according to claim 7, characterized in that, The fabrication quality results are used to characterize whether at least one of the first gate-source shared contact hole and the second gate-source shared contact hole in the device structure formed synchronously with the test structure has abnormal electrical parameters. Determining the test result of the test structure based on the parameter result between the first electrical parameter and the second electrical parameter includes: Based on the degree of difference between the first electrical parameter and the second electrical parameter, it is determined whether at least one of the first gate-source shared contact hole and the second gate-source shared contact hole has an abnormal electrical parameter.

9. The method according to claim 8, characterized in that, The first electrical parameter includes a first resistance value, and the second electrical parameter includes a second resistance value. The step of determining whether at least one of the first gate-source shared contact hole and the second gate-source shared contact hole has an abnormal electrical parameter based on the degree of difference between the first electrical parameter and the second electrical parameter includes: Obtain the resistance difference between the first resistance value and the second resistance value, wherein the resistance difference is the absolute value of the difference between the first resistance value and the second resistance value, or the ratio of the first resistance value to the second resistance value; If the resistance difference value is greater than a preset difference threshold, and at least one of the first resistance value and the second resistance value is less than a preset short-circuit resistance threshold, then the abnormal electrical parameter is determined to be a short-circuit defect. If both the first resistance value and the second resistance value are greater than the preset circuit breaker resistance threshold, then the abnormal electrical parameter is determined to be a circuit breaker defect.

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