Defect determination method and device, electronic equipment, storage medium and program product

Abstract

The disclosure provides a defect determination method, device, electronic equipment, storage medium and program product. The determination method comprises: after a preset process, obtaining a voltage contrast image corresponding to a wafer; determining an electrical parameter between a contact hole and a pad in a preset region of the wafer according to the voltage contrast image; and determining a defect in the preset region of the wafer according to the electrical parameter and a reference electrical parameter. The defect determination method provided by the disclosure compares the electrical parameter between the contact hole and the pad in the preset region of the wafer determined according to the voltage contrast image corresponding to the wafer with the corresponding reference electrical parameter in the reference voltage contrast image after the preset process, to determine whether there is a defect in the preset region, which can effectively improve the accuracy of defect determination and the efficiency of defect identification.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to methods, apparatus, electronic devices, storage media, and program products for determining defects. Background Technology

[0002] In semiconductor wafer manufacturing processes, short-circuit defects between contact holes (CTs) and pads (M0s) mainly originate from overlay (VOL shift) deviations and etch (ETCH) errors. However, in the contact hole etching process, due to limitations imposed by the pattern size and thickness of the pads, existing monitoring tools cannot directly measure the connection status between the contact holes and pads. Therefore, during wafer fabrication, there is a lack of effective means to detect the connection status between the formed contact holes and pads. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a method, apparatus, electronic device, storage medium, and program product for determining defects.

[0005] According to a first aspect of an exemplary embodiment of the present disclosure, a method for determining a defect is provided, the method comprising: After the preset process flow, obtain the voltage contrast map corresponding to the wafer; The electrical parameters between the contact holes and pads within a preset region of the wafer are determined based on the voltage contrast diagram; the electrical parameters characterize the conductivity between the contact holes and pads; the preset region characterizes the region where the probability of defect occurrence meets a preset condition; Based on the electrical parameters and reference electrical parameters, the defects in the preset area of ​​the wafer are determined; the reference electrical parameters include the electrical parameters between the contact holes and the pads in the preset area of ​​the reference voltage contrast diagram corresponding to the wafer.

[0006] In some exemplary embodiments, determining the defects within the preset region of the wafer based on the electrical parameters and reference electrical parameters includes: In response to the characteristic value of the electrical parameter being greater than the reference characteristic value of the reference electrical parameter, a short circuit defect is determined to have occurred between the contact hole and the pad within the preset area of ​​the wafer.

[0007] In some exemplary embodiments, the preset process includes an etching process for the contact hole and / or a photolithography process for the contact hole.

[0008] In some exemplary embodiments, the determination method further includes: In the voltage contrast diagram, the short-circuit defect is displayed in a preset manner; the preset manner characterizes the difference between the characterization value of the electrical parameter between the contact hole and the pad in the preset area of ​​the voltage contrast diagram and the reference characterization value of the reference electrical parameter corresponding to the reference voltage contrast diagram.

[0009] In some exemplary embodiments, the determination method further includes: The preset region is determined based on the wafer's graphic database system; and / or The preset region is determined based on the historical defect distribution of the wafer.

[0010] In some exemplary embodiments, determining the preset region based on the wafer's graphics database system includes: The spacing between the contact hole and the pad is determined based on the graphics database system; In response to the spacing being less than a spacing threshold, the area including the contact hole and the pad is determined as the preset area.

[0011] In some exemplary embodiments, determining the spacing between the contact hole and the pad according to the graphics database system includes: Based on the graphics database system, determine the minimum spacing between the edge of the contact hole and the edge of the pad; The minimum spacing is defined as the spacing between the contact hole and the pad.

[0012] In some exemplary embodiments, determining the preset region based on the historical defect distribution of the wafer includes: Determine the defect density of the historical defects of the first N batches of the wafers under the same process technology; where N is an integer greater than or equal to 2; The region whose defect density characterization value is greater than a preset threshold is defined as the preset region.

[0013] In some exemplary embodiments, determining the defect density of the historical defects in the first N batches of the wafers under the same process technology includes: Determine the defect density of the historical defects in a given region within the first N batches of the wafers under the same process technology.

[0014] In some exemplary embodiments, the given region includes one or more of the following regions: The graph database system includes graph density abrupt change areas, critical path traversal areas, and historical yield hotspot areas.

[0015] In some exemplary embodiments, when determining the preset region based on the wafer's graphical database system and the wafer's historical defect distribution status, the determination method further includes: The preset region is determined by weighting a first preset region determined by the graphics database system of the wafer and a second preset region determined by the historical defect distribution of the wafer; or The first region that overlaps with the first preset region and the second preset region, and the second region determined by weighting the remaining parts of the first preset region and the second preset region, are collectively used as the preset region.

[0016] According to a second aspect of an exemplary embodiment of the present disclosure, a defect determination apparatus is provided, comprising: The acquisition module is configured to acquire the voltage contrast map corresponding to the wafer after a preset process. The first determining module is configured to determine the electrical parameters between contact holes and pads within a preset region of the wafer based on the voltage contrast diagram; the electrical parameters characterize the conductivity between the contact holes and pads; the preset region characterizes the region where the probability of defect occurrence meets a preset condition; The second determining module is configured to determine defects in the preset region of the wafer based on the electrical parameters and reference electrical parameters; the reference electrical parameters include the electrical parameters between the contact holes and the pads in the preset region of the reference voltage contrast diagram corresponding to the wafer.

[0017] In some exemplary embodiments, the second determining module is further configured to determine, in response to a characterization value of the electrical parameter being greater than a reference characterization value of the reference electrical parameter, that a short-circuit defect has occurred between the contact hole and the pad within the preset area of ​​the wafer.

[0018] In some exemplary embodiments, the preset process includes an etching process for the contact hole and / or a photolithography process for the contact hole.

[0019] In some exemplary embodiments, the determining device further includes a display module, which is configured to: In the voltage contrast diagram, the short-circuit defect is displayed in a preset manner; the preset manner characterizes the difference between the characterization value of the electrical parameter between the contact hole and the pad in the preset area of ​​the voltage contrast diagram and the reference characterization value of the reference electrical parameter corresponding to the reference voltage contrast diagram.

[0020] In some exemplary embodiments, the determining device further includes a third determining module, which is configured to: The preset region is determined based on the wafer's graphic database system; and / or The preset region is determined based on the historical defect distribution of the wafer.

[0021] In some exemplary embodiments, the third determining module is further configured to determine the spacing between the contact hole and the pad based on the graphics database system; In response to the spacing being less than a spacing threshold, the area including the contact hole and the pad is determined as the preset area.

[0022] In some exemplary embodiments, the third determining module is further configured to: Based on the graphics database system, determine the minimum spacing between the edge of the contact hole and the edge of the pad; The minimum spacing is defined as the spacing between the contact hole and the pad.

[0023] In some exemplary embodiments, the third determining module is further configured to: Determine the defect density of the historical defects of the first N batches of the wafers under the same process technology; where N is an integer greater than or equal to 2; The region whose defect density characterization value is greater than a preset threshold is defined as the preset region.

[0024] In some exemplary embodiments, the third determining module is further configured to: Determine the defect density of the historical defects in a given region within the first N batches of the wafers under the same process technology.

[0025] In some exemplary embodiments, the given region includes one or more of the following regions: The graph database system includes graph density abrupt change areas, critical path traversal areas, and historical yield hotspot areas.

[0026] In some exemplary embodiments, when the preset region is determined based on the graphics database system of the wafer and the historical defect distribution status of the wafer, the third determining module is further configured to: The preset region is determined by weighting a first preset region determined by the graphics database system of the wafer and a second preset region determined by the historical defect distribution of the wafer; or The first region that overlaps with the first preset region and the second preset region, and the second region determined by weighting the remaining parts of the first preset region and the second preset region, are collectively used as the preset region.

[0027] According to a third aspect of an exemplary embodiment of this disclosure, an electronic device is provided, comprising: processor; Memory used to store processor-executable instructions; The processor is configured to execute the defect determination method in the above embodiments.

[0028] According to a fourth aspect of an exemplary embodiment of the present disclosure, a non-transitory computer-readable storage medium is provided, wherein instructions in the storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the defect determination method described in the above embodiments.

[0029] According to a fifth aspect of an exemplary embodiment of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the defect determination method as described in the above embodiments.

[0030] The defect determination method provided in this disclosure obtains a voltage contrast map corresponding to the wafer after a preset process. The electrical parameters between contact holes and pads within a preset area of ​​the wafer, determined based on the voltage contrast map, are compared with the corresponding reference electrical parameters in the reference voltage contrast map to determine potential defects within the preset area of ​​the wafer after the preset process. This improves the accuracy of defect determination while significantly reducing the data acquisition and processing volume caused by wafer scanning, effectively improving detection efficiency and reducing equipment operating costs.

[0031] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0033] Figure 1 This is a flowchart of a method for determining defects provided by an exemplary embodiment of this disclosure.

[0034] Figure 2This is a schematic diagram showing the results of determining defects within a preset area of ​​a wafer, provided by an exemplary embodiment of this disclosure.

[0035] Figure 3 This is a schematic diagram showing that, after the photolithography process of the contact holes in the wafer, there are no short-circuit defects in a preset area, as provided by an exemplary embodiment of this disclosure.

[0036] Figure 4 This is a schematic diagram illustrating a short-circuit defect in a predetermined area of ​​a wafer caused by overlay deviation of the photolithography machine during the photolithography process for contact holes in a wafer provided by an exemplary embodiment of this disclosure.

[0037] Figure 5 This is a schematic diagram illustrating a short-circuit defect in a predetermined area caused by etching process errors during the photolithography process of the contact holes of a wafer provided in an exemplary embodiment of this disclosure.

[0038] Figure 6 This is a cross-sectional schematic diagram of a short-circuit defect formed between a contact hole and a pad, as shown in a voltage contrast diagram, provided by an exemplary embodiment of this disclosure.

[0039] Figure 7 This is a top view schematic diagram showing a short-circuit defect formed between a contact hole and a pad, provided in an exemplary embodiment of this disclosure, in a voltage contrast diagram.

[0040] Figure 8 This is a schematic diagram of a process for determining a preset region based on a wafer graphics database system, provided by an exemplary embodiment of this disclosure. Figure 9 This is a schematic diagram of a process for determining a preset region based on a wafer graphics database system, provided by an exemplary embodiment of this disclosure. Figure 10 This is a flowchart illustrating the process of determining a preset region based on the historical defect distribution of a wafer, provided by an exemplary embodiment of this disclosure. Figure 11 This is a flowchart illustrating a specific example of a method for determining defects provided by an exemplary embodiment of this disclosure.

[0041] Figure 12 This is a defect determination apparatus provided by an exemplary embodiment of the present disclosure.

[0042] Figure 13 This is a block diagram illustrating an electronic device according to an exemplary embodiment of this disclosure.

[0043] Figure label: 10. Contact hole; 11. First row of contact holes; 12. Second row of contact holes; 13. Third row of contact holes; 14. Fourth row of contact holes; 15. Fifth row of contact holes; 17. First pad; 18. Second pad; 19. First contact hole; 20. First target pad; 21. Second contact hole; 22. Second target pad; 23. Adjacent pad to the second target pad; 24. Third contact hole; 25. Third target pad; 26. Adjacent pad to the third target pad; 1200. Determining device; 1201. Acquisition module; 1202. First determining module; 1204. Display module; 1203. Second determining module; 1205. Third determining module; 900. Computer equipment; 901. Processor; 902. Memory. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0045] In related technologies, during wafer fabrication, short-circuit defects can form between contact holes and pads due to overlay misalignment or etching / photolithography process errors in the contact holes. High-voltage scanning electron microscopy (HV-SEM) utilizes the differences in the absorption capabilities of different materials used in wafer fabrication for secondary electrons (SE) and backscattered electrons (BSE) to create image contrast, i.e., a voltage contrast map, to identify defects caused by overlay misalignment or etching errors between contact holes and pads during wafer fabrication. However, in the contact hole etching process, limited by the pattern size and film thickness of the pads (M0), HV-SEM cannot directly measure the connection state between the contact holes and pads, and therefore cannot accurately identify related defects.

[0046] Based on this, this disclosure provides a method for determining defects. In this method, after a preset process step, a voltage contrast map corresponding to the wafer is obtained. The electrical parameters between contact holes and pads within a preset region of the wafer are determined based on the voltage contrast map. These electrical parameters characterize the conductivity between the contact holes and pads. Defects within the preset region of the wafer are determined based on the electrical parameters and reference electrical parameters. The reference electrical parameters include the electrical parameters between contact holes and pads within the preset region of the reference voltage contrast map corresponding to the wafer. The preset region characterizes the area where the probability of defect occurrence meets preset conditions. The reference voltage contrast map characterizes the voltage contrast map corresponding to the defect-free condition after wafer fabrication. The defect determination method provided by this disclosure, after a preset process step, compares the electrical parameters between contact holes and pads within the preset region of the wafer determined based on the voltage contrast map with the corresponding reference electrical parameters in the reference voltage contrast map to determine whether defects exist within the preset region. This effectively improves the accuracy of defect determination and the efficiency of defect identification.

[0047] Exemplary embodiments of this disclosure provide a method for determining defects, such as... Figure 1 As shown, Figure 1 This is a flowchart of a method for determining defects provided in an exemplary embodiment of this disclosure. The method includes: S100. After the preset process, obtain the voltage contrast map corresponding to the wafer.

[0048] S200. Determine the electrical parameters between contact holes and pads within a preset region of the wafer based on the voltage contrast diagram; the electrical parameters characterize the conductivity between the contact holes and pads; the preset region characterizes the area where the defect occurrence probability meets the preset conditions. S300. Determine the defects in a preset area of ​​the wafer based on the electrical parameters and reference electrical parameters; the reference electrical parameters include the electrical parameters between contact holes and pads in the preset area of ​​the reference voltage contrast diagram corresponding to the wafer.

[0049] In step S100, a voltage contrast map corresponding to the wafer is obtained after a preset process step. The preset process step may include processes prone to defects, such as the process step for contact holes, or any process step in the wafer fabrication process. In practical applications, it can be determined according to needs. In practical applications, processes prone to defects can be selected, such as etching processes and / or photolithography processes for contact holes. This ensures both the efficiency of wafer fabrication and the effective identification of defects in the wafer fabrication process, thereby improving wafer fabrication yield.

[0050] In step S200, one of the major defects generated during wafer fabrication is commonly found between contact holes and pads, such as short-circuit defects between a contact hole and at least two adjacent pads. Short-circuit defects between contact holes and at least two adjacent pads are typically caused by overlay misalignment between the contact hole and the pad, or by etching / photolithography process errors or etching process errors in the contact hole. Therefore, determining the electrical parameters between the contact hole and the pad, i.e., determining the conductivity between the contact hole and the pad, can help identify potential defects that may occur during wafer fabrication.

[0051] When detecting defects generated during wafer fabrication, the detection can be performed on the entire wafer or on a predetermined area. A predetermined area represents a region where the probability of defect occurrence meets a predetermined condition. For example, this might include the area of ​​contact holes and corresponding pads within the wafer. Targeting a predetermined area within the wafer for defect detection significantly improves the accuracy of defect identification and location while drastically reducing the data acquisition and processing volume associated with wafer scanning, effectively increasing detection efficiency and reducing equipment operating costs. In this embodiment, the predetermined condition can be a condition where the probability of defect occurrence is greater than or equal to a predetermined probability value. The predetermined probability value can be set according to the needs of the actual wafer fabrication process and can be any value between 50% and 90%. For example, a predetermined probability value of 60% means that when the probability of defect occurrence in a region is greater than or equal to 60%, the probability of defect occurrence in that region meets the predetermined condition, and that region belongs to the predetermined area.

[0052] In step S300, the electrical parameters between the contact hole and the pad determined according to the voltage contrast diagram are compared with the corresponding reference electrical parameters to determine the defects that may exist after the preset process, so as to improve the accuracy of defect determination.

[0053] In this embodiment, the voltage contrast image is an image acquired using the voltage contrast (VC) imaging mode of a scanning electron microscope (SEM) to characterize the potential distribution state on the wafer surface. The reference voltage contrast image is used to characterize the voltage contrast image corresponding to a defect-free wafer after fabrication. The reference voltage contrast image can be a voltage contrast image generated through simulation based on the wafer's corresponding Graphic Data System (GDS) data under an ideal defect-free state. The simulation process of the reference voltage contrast image includes: extracting the connection relationships of each connection structure in a predetermined region on the wafer based on GDS data, and predicting the corresponding characterization value in the voltage contrast imaging, such as grayscale signal value or brightness value, based on the expected electrical state of each connection node (grounded, connected to power, or floating), thereby forming the reference voltage contrast image. The reference voltage contrast image is used to compare with the voltage contrast image acquired during actual wafer inspection to determine whether defects exist between contact holes and at least two adjacent pads within the predetermined region of the wafer.

[0054] In the exemplary embodiments of this disclosure, grayscale signal values ​​are used as examples to characterize the potential level. For instance, the conductivity between contact holes and pads within a preset area in a voltage contrast diagram refers to the grayscale signal values ​​in the voltage contrast diagram used to characterize the potential level of the preset area. Similarly, the conductivity between contact holes and pads within a corresponding area of ​​a reference voltage contrast diagram is a set of preset standard signal values, which are grayscale signal values ​​used to characterize the potential level of the preset area under an ideal defect-free state, serving as a benchmark for comparison with the actual voltage contrast diagram.

[0055] Short-circuit defects between contact holes and at least two adjacent pads are among the major defects in wafer fabrication. Therefore, during wafer fabrication, a voltage contrast map of the wafer after a predetermined process can be obtained. Based on this voltage contrast map, the electrical parameters between contact holes and pads within a predetermined region can be determined, i.e., the conductivity between contact holes and pads within that region. The electrical parameters between contact holes and pads are compared with the reference electrical parameters corresponding to a reference voltage contrast map. The difference in conductivity between contact holes and pads within the predetermined region is used to determine short-circuit defects. Since the voltage contrast map can sensitively reflect changes in conductivity between contact holes and pads within a predetermined region of the wafer, the difference in conductivity between contact holes and pads within the predetermined region, based on the voltage contrast map of the wafer after the predetermined process and the reference voltage contrast map, can accurately identify the presence of short-circuit defects between contact holes and pads within the predetermined region. This significantly reduces the data acquisition and processing volume associated with wafer scanning during wafer inspection, improves inspection efficiency, and provides a precise basis for subsequent process adjustments.

[0056] In exemplary embodiments of this disclosure, the preset process may include a contact hole fabrication process in a wafer, such as an etching process for the contact hole and / or a photolithography process for the contact hole.

[0057] In the wafer fabrication process, the overlay process between contact holes and pads, as well as the etching process and / or photolithography process of contact holes, are key steps in forming the contact hole structure. At this stage, the contact holes have not yet been covered by the subsequent metal filling layer, and their surface morphology and conductivity directly reflect the execution quality of the overlay, etching, or photolithography process. Moreover, problems such as overlay deviation, etching deviation, photoresist deviation, or over-etching generated at this stage can easily lead to abnormal connections between the contact holes and pads in the subsequent process. Therefore, obtaining a voltage contrast map and performing defect detection after this process can enable early detection and timely intervention before defects are buried or covered, effectively preventing defects from being transmitted to subsequent process chains.

[0058] The defect determination method provided by the exemplary embodiments of this disclosure is applicable to wafers after separate etching or photolithography processes, or it can cover both processes simultaneously for comprehensive inspection. It has flexible process adaptability and can meet the differentiated needs of different production lines for defect monitoring nodes, thereby maximizing the integrity and conductivity reliability of the contact hole structure and providing timely and accurate process feedback for improving the overall wafer yield.

[0059] In this embodiment, after the preset process, the voltage contrast map corresponding to the wafer is obtained, and the electrical parameters between contact holes and pads within a preset area of ​​the wafer are determined based on the voltage contrast map. These electrical parameters are then compared with the corresponding reference electrical parameters in the reference contrast map to identify potential defects. This defect determination can be performed according to the needs of the wafer fabrication process, ensuring both wafer fabrication efficiency and effective defect identification, thereby improving wafer yield. Furthermore, defect determination within a preset area improves the accuracy of defect identification and positioning while reducing the data acquisition and processing volume associated with wafer scanning, effectively increasing detection efficiency and reducing equipment operating costs.

[0060] Figure 2 This is a schematic diagram showing the display results of determining defects within a preset area of ​​a wafer according to an exemplary embodiment of this disclosure. It should be noted that... Figure 2 In the wafer fabrication process, by comparing the electrical parameters between contact holes and pads in the wafer determined by the voltage contrast map of the wafer after the preset process with the electrical parameters corresponding to the reference voltage contrast map, possible short-circuit defects in the preset area are identified based on the difference in conductivity between the two in the preset area, and the results of the identified short-circuit defects are displayed in a preset manner.

[0061] like Figure 2 As shown, the elliptical hole is used to characterize contact hole 10, and the strip-shaped structure and rounded rectangle are used to characterize the pad. (Refer to...) Figure 2 The contact holes 10 are arranged in an array on the wafer surface, from left to right: the first row of contact holes 11, the second row of contact holes 12, the third row of contact holes 13, the fourth row of contact holes 14, and the fifth row of contact holes 15. Each row contains multiple contact holes 10, and each contact hole 10 should be located in the corresponding area of ​​the pad to ensure electrical connection with the pad. After the actual process of manufacturing the contact holes 10, such as the overlay process between the contact holes 10 and the corresponding pad, and after the etching process and / or photolithography process, due to overlay deviations, etching deviations, photoresist deviations, or over-etching issues during the process, the contact position of the contact hole 10 in contact with the corresponding pad may deviate. If the deviation is too large, causing the contact hole 10 to contact two adjacent pads simultaneously, a short circuit defect will occur. Figure 2 As shown, in the third row of contact holes 13, the contact hole 10 corresponding to the first pad 17 should make contact with the first pad 17, and the end of the contact hole 10 corresponding to the first pad 17 should be completely located within the area of ​​the first pad 17. However, due to process deviations, it made contact with two adjacent pads, namely the first pad 17 and the second pad 18, at the same time, resulting in an unexpected electrical connection and thus a short circuit defect.

[0062] A short-circuit defect can occur during wafer fabrication, where any two pads short-circuit due to errors in the manufacturing process after any step. Before providing an exemplary description of short-circuit defects, this disclosure provides a comparative illustration of an example where there are no short-circuit defects in a predetermined area of ​​the wafer. Figure 3 This is a schematic diagram illustrating, as provided by an exemplary embodiment of this disclosure, that there are no short-circuit defects in a predetermined area after the photolithography process of the contact holes on a wafer, as shown below. Figure 3 As shown, after the corresponding process of the wafer, the first contact hole 19 is aligned with the predefined first target pad 20 below, and only makes electrical contact with the first target pad 20, without any abnormal lateral offset or dimensional abnormality, to ensure the uniqueness of the structural interconnection and the integrity of electrical isolation.

[0063] Figure 4 This is a schematic diagram illustrating a short-circuit defect in a predetermined area of ​​the wafer caused by overlay deviation of the photolithography machine during the photolithography process for contact holes in a wafer, as provided in an exemplary embodiment of this disclosure. Figure 4As shown, in the photolithography process for contact holes on a wafer, the photolithography machine etches to form a second contact hole 21 according to the overlay requirements. This second contact hole 21 must be aligned with a predefined second target pad 22 below. When the overlay accuracy of the photolithography machine deviates (e.g., along the overlay), Figure 4 As shown in the diagram, the X-direction is offset by 20nm, exceeding the predetermined process range. This causes the opening of the second contact hole 21 to deviate from the second target pad 22 and move towards the adjacent pad 23 of the second target pad. If the offset is too large, the opening of the second contact hole 21 will contact the two adjacent pads (the second target pad 22 and the adjacent pad 23 of the second target pad). In subsequent process steps, a conductive connection structure is formed within the second contact hole 21, which will cause the conductive connection structure within the second contact hole 21 to form a short circuit connection with the two adjacent pads (the second target pad 22 and the adjacent pad 23 of the second target pad).

[0064] Figure 5 This is a schematic diagram illustrating a short-circuit defect in a predetermined area caused by etching process errors during the photolithography process of a wafer contact hole provided in an exemplary embodiment of this disclosure. Figure 5 As shown, in the photolithography process for the contact holes on a wafer, the photolithography machine etches a third contact hole 24 according to the overlay requirements. This third contact hole 24 must be aligned with a pre-defined third target pad 25 below. During the etching process of the third contact hole 24, deviations in process parameters cause deviations in the etching trajectory, resulting in deformation of the formation path of the third contact hole 24. This deformation causes the third contact hole 24 to extend laterally and contact the adjacent pad 26 of the third target pad. In subsequent process steps, a conductive connection structure is formed within the third contact hole 24. This will cause the conductive connection structure within the third contact hole 24 to form a short-circuit connection with the two adjacent pads (the third target pad 25 and the adjacent pad 26 of the third target pad).

[0065] In the defect determination method provided by the exemplary embodiments of this disclosure, after a preset process step, a voltage contrast map corresponding to the wafer is obtained. Based on the voltage contrast map and a reference voltage contrast map corresponding to the wafer, defects within a preset area of ​​the wafer can be determined promptly. This allows for the timely detection of defects caused by equipment issues during wafer fabrication (such as…). Figure 4 (as shown) or due to parameter reasons (such as) Figure 5 (As shown) or other reasons that may cause short circuit defects, timely adjustment of the preparation parameters in the wafer preparation process improves the yield of wafer preparation.

[0066] Exemplary embodiments of this disclosure provide a method for determining defects, in which defects between contact holes and pads within a preset area of ​​a wafer are determined based on electrical parameters and reference electrical parameters, including: In response to a characteristic value of an electrical parameter being greater than a reference characteristic value of a reference electrical parameter, a short-circuit defect is determined to occur between the contact hole and the pad within a preset area of ​​the wafer.

[0067] In this embodiment, the preset region can be any region where the probability of any defect occurring meets a preset condition. For example, a region in a wafer including contact holes and corresponding pads. After a preset process, such as after the etching process and / or photolithography process of the contact hole, if a short-circuit defect occurs between the contact hole and at least two adjacent pads, that is, the contact hole is in contact with at least two adjacent pads simultaneously, this forms a conductive path between the contact hole and at least two adjacent pads. Theoretically, in the absence of defects, the contact hole should only contact its corresponding pad, while other adjacent pads should be in a non-conductive, unconnected, or insulated state. In this case, the corresponding position in the voltage contrast diagram will have different characterization values ​​than the corresponding position in the reference voltage contrast diagram. For example, the corresponding position in the voltage contrast diagram will have different grayscale information values ​​than the corresponding position in the reference voltage contrast diagram.

[0068] In the reference voltage contrast diagram, the grayscale value of the preset region, such as the area including the contact hole and its corresponding pad, is 150. That is, in an ideal, defect-free state, where the contact hole only contacts its corresponding pad, the baseline grayscale value is 150. However, in the actual wafer fabrication process, the grayscale value of the corresponding preset region in the corresponding voltage contrast diagram increases to 220. This increase from 150 to 220 indicates that because the contact hole simultaneously contacts at least two adjacent pads, a conductive path is formed between the contact hole and at least two adjacent pads, significantly increasing the charge accumulation within the preset region. In other words, the conductivity of the preset region is increased compared to the conductivity in the ideal, defect-free state. Therefore, if the characteristic value of the electrical parameters between the contact hole and the pad in the preset region of the voltage contrast diagram is greater than the characteristic value of the corresponding electrical parameters in the reference voltage contrast diagram, it can be determined that a short-circuit defect has occurred within the preset region of the wafer.

[0069] After the contact hole etching process, a voltage contrast image of the wafer is acquired using the voltage contrast imaging mode of a scanning electron microscope. A corresponding reference voltage contrast image is also acquired, which characterizes the baseline conductivity of each region of the wafer in a defect-free state. The voltage contrast image and the reference voltage contrast image are compared to extract the grayscale signal value of a preset region. If the grayscale signal value of the preset region in the voltage contrast image is greater than the grayscale signal value of the preset region in the reference voltage contrast image, a short-circuit defect is determined to have occurred within the preset region of the wafer.

[0070] In the exemplary embodiments of this disclosure, the existence of a short-circuit defect is determined based on the conductivity of the short-circuit defect that occurs in the actual process. That is, when the conductivity between the contact hole and the pad in the preset area of ​​the voltage contrast diagram is greater than the conductivity between the contact hole and the pad in the corresponding area of ​​the reference voltage contrast diagram, it is determined that a short-circuit defect occurs in the preset area. This can simply and accurately determine the possibility of the existence of a defect.

[0071] In exemplary embodiments of this disclosure, the preset region includes the area between the contact hole and the pad in the wafer. For example, the preset region may include the area between the contact hole and the peripheral pad.

[0072] This disclosure provides an exemplary embodiment of a method for determining a defect, wherein, in response to a characteristic value of an electrical parameter being greater than a reference characteristic value of a reference electrical parameter, a short-circuit defect is determined to exist between a contact hole and a pad within a preset area of ​​a wafer, including: In response to a characteristic value of an electrical parameter being greater than a characteristic value of a reference electrical parameter, it is determined that a contact hole in a predetermined area of ​​the wafer is connected to at least two of the pads, forming a short-circuit defect.

[0073] The area between the contact hole and the surrounding pads is a critical interface between the conductive link structure and the interconnect layer. During the manufacturing process, short-circuit defects can easily occur due to equipment issues, parameter issues, or other reasons, such as metal residue, incomplete etching, or bridging. Furthermore, if a short-circuit defect occurs between a contact hole and at least two adjacent pads in the wafer, the charge accumulation in that area will significantly increase, leading to increased conductivity. This is reflected in the voltage contrast diagram, where the corresponding grayscale value will also increase. Therefore, the conductivity change between the contact hole and the pads within a preset area has a clear signal response characteristic on the voltage contrast diagram, enabling precise location of short-circuit defects in the wafer. In addition, since grayscale value recognition can be performed within the preset area, the low detection efficiency caused by indiscriminate scanning of the entire wafer can be effectively avoided.

[0074] like Figure 4 and Figure 5 As shown, when the conductivity between the contact hole and the pad in the preset area of ​​the voltage contrast diagram is greater than the conductivity of the corresponding area in the reference voltage contrast diagram, it can be determined that a short circuit defect has occurred in the preset area of ​​the wafer.

[0075] In the exemplary embodiments of this disclosure, the voltage contrast map of a wafer in an ideal defect-free state is used as a reference voltage contrast map. During wafer fabrication, after a preset process, an actual voltage contrast map is obtained. The characterization values ​​corresponding to the conductivity within a preset region of the wafer, such as grayscale values, are compared. If the grayscale value corresponding to the preset region of the wafer in the voltage contrast map is greater than the grayscale value corresponding to the reference voltage contrast map, it can be determined that a short-circuit defect has occurred in the preset region. This method can accurately identify short-circuit defects, significantly improve detection efficiency, effectively reduce the risk of missed detections, and improve product yield.

[0076] In an exemplary embodiment of this disclosure, the determination method further includes: displaying a short-circuit defect in a voltage contrast diagram in a preset manner; the preset manner characterizes the difference between the characterization value of the electrical parameter between the contact hole and the pad in the preset area of ​​the voltage contrast diagram and the reference characterization value of the corresponding reference electrical parameter in the reference voltage contrast diagram.

[0077] The preset method in the exemplary embodiments of this disclosure refers to a pre-set display rule used to present short-circuit defects on a voltage contrast map with a specific visual effect that distinguishes them from normal areas. This effect can directly reflect the degree of difference between the conductivity of the defect area and the conductivity of the corresponding area in the reference voltage contrast map.

[0078] The exemplary embodiments of this disclosure display short-circuit defects in a voltage contrast diagram in a preset manner. This preset manner is used to characterize the difference between the conductivity of the preset area in the voltage contrast diagram and the conductivity of the corresponding area in the reference voltage contrast diagram. This can transform the originally abstract and difficult-to-observe conductivity differences into visual and intuitive graphical symbols, enabling inspection personnel or automatic identification systems to intuitively know the location and degree of conductivity abnormalities in the preset area, thereby significantly improving the convenience of defect identification and the user-friendliness of human-computer interaction.

[0079] Meanwhile, since this display method directly corresponds to the degree of conductivity difference, it can quickly pinpoint the precise location and relative severity of short-circuit defects without additional data comparison or result interpretation, effectively shortening the time cycle for defect judgment and feedback, and further improving detection efficiency.

[0080] The degree of difference between the conductivity of the defect region and the conductivity of the corresponding region in the reference voltage contrast map can be reflected by one or more of the following methods: The intensity of brightness indicates the location of the short-circuit defect; The magnitude of the flicker frequency at the location of the short-circuit defect; The color of the display showing the location of the short-circuit defect changes; The location of short-circuit defects is marked with different shapes.

[0081] In this embodiment, the preset display mode can be flexibly set according to different needs, making the detection results both intuitive and information-rich, providing a clearer and more direct visual basis for rapid diagnosis and timely adjustment of process anomalies, and helping to further improve the timeliness and accuracy of wafer yield control.

[0082] In the exemplary embodiments of this disclosure, Figure 6 This is a cross-sectional schematic diagram of a short-circuit defect formed between a contact hole and a pad, provided in an exemplary embodiment of this disclosure, shown in a voltage contrast diagram. Figure 7 This is a top view schematic diagram showing a short-circuit defect formed between a contact hole and a pad, provided in an exemplary embodiment of this disclosure, displayed in a voltage contrast diagram. (See diagram below.) Figure 6 As shown, during the fabrication of contact hole 10 on the wafer, due to a process abnormality, contact hole 10 came into contact with two adjacent pads, the first pad and the second pad, forming a short-circuit defect. This short-circuit defect is displayed in a high-brightness, flickering manner in the voltage contrast diagram. Figure 7 As shown. Figure 7 In the image, the area containing the contact hole 10 is displayed in a high-brightness, flashing manner.

[0083] In an exemplary embodiment of this disclosure, a method for determining defects is provided, the method further comprising: Based on the wafer's graphic database system, determine the preset area; and / or The preset area is determined based on the historical defect distribution of the wafer.

[0084] In this embodiment, a preset area requiring defect detection can be determined using a graphical database system corresponding to the wafer. The wafer's graphical database system can clearly describe the various structures within the wafer and the relationships between nodes, thereby effectively determining the preset area.

[0085] The exemplary embodiments of this disclosure determine a preset region based on a graphical database system corresponding to the wafer. This ensures that the definition of the preset region does not rely on a fixed template or manual experience, but is adaptively defined based on the structural features and electrical properties of the wafer itself as reflected by the graphical database system. Since the graphical database system can accurately represent the various structures in each region of the wafer under defect-free conditions and the correlation between nodes of each structure, the preset region determined accordingly can more accurately match the actual morphology and process conditions of the current wafer. This effectively avoids the problem of the preset region not matching the actual situation due to process fluctuations or positional offsets between different wafers, and significantly improves the accuracy of the preset region setting.

[0086] In exemplary embodiments of this disclosure, a method for determining defects is provided, such as... Figure 8 As shown, Figure 8This is a schematic flowchart illustrating the process of determining a preset region based on a wafer graphics database system, provided by an exemplary embodiment of this disclosure, including: S400 determines the spacing between contact holes and pads based on a graphical database system; S500, in response to a spacing less than a spacing threshold, determines the area including contact holes and pads as a preset area.

[0087] Exemplary embodiments of this disclosure determine the spacing between contact holes and pads based on a graphics database system corresponding to the wafer. The graphics database system precisely describes the shape, hierarchy, and location of all structures on the wafer; that is, it can accurately and clearly describe the shape, hierarchy, and location of contact holes and pads. Therefore, the spacing between contact holes and pads can be accurately determined based on their shape and location.

[0088] The spacing threshold can be determined according to the fabrication requirements, ideally to accurately assess the likelihood of short circuits. For example, the spacing threshold characterizes the maximum spacing between contact holes and pads that may exhibit defects after a predetermined process. Determining the spacing threshold based on the minimum spacing between contact holes and pads can effectively assess areas prone to defects, thereby effectively defining the predetermined area. For instance, the minimum spacing between contact holes and pads can be weighted and used as the spacing threshold. Alternatively, 0.7 to 0.9 times the minimum spacing between contact holes and pads can be used as the spacing threshold.

[0089] The minimum spacing between the contact hole and the pad can be the minimum spacing between the edge of the contact hole and the edge of the pad, or the minimum spacing between the center point of the contact hole and the center point of the pad. For regularly shaped contact holes and pads, either the minimum spacing between the edge of the contact hole and the edge of the pad, or the minimum spacing between the center point of the contact hole and the center point of the pad, can be selected as the minimum spacing between the contact hole and the pad. For irregularly shaped contact holes and pads, the minimum spacing between the edge of the contact hole and the edge of the pad can be selected as the minimum spacing between the contact hole and the pad. This setting method can accurately describe the relationship between the spacing between the contact hole and the pad, so as to accurately determine the preset area.

[0090] In exemplary embodiments of this disclosure, a method for determining defects is provided, such as... Figure 9 As shown, Figure 9 This is a schematic flowchart illustrating the process of determining a preset region based on a wafer graphics database system, provided by an exemplary embodiment of this disclosure, including: S401, based on the graphics database system, determine the minimum spacing between the edge of the contact hole and the edge of the pad; S402 defines the minimum spacing as the distance between the contact hole and the pad.

[0091] In the exemplary embodiments of this disclosure, considering the characteristics of different contact holes and pads, such as the regularity of their shapes, the minimum distance between the edge of the contact hole and the edge of the pad is used as the distance between the contact hole and the pad. This allows the minimum distance between the edge of the contact hole and the edge of the pad to be used as the distance between the contact hole and the pad, regardless of whether the shape of the contact hole and the pad is regular or not, to accurately assess the possibility of defects in the contact hole and the pad after a preset process, and thus accurately determine the preset area.

[0092] The method for determining the preset area in the exemplary embodiments of this disclosure does not require separate settings for different batches or different product types. The preset area can be automatically determined based on the graphical database system, which improves the automation and versatility of the detection process and further ensures the reliability and consistency of subsequent short-circuit defect judgment based on the preset area, providing a more solid foundation for the overall improvement of defect detection accuracy.

[0093] In the exemplary embodiments of this disclosure, a preset region can be determined based on the historical defect distribution of the wafer. For example, the preset region can be determined based on the historical defect distribution of the first N batches of wafers under the same process technology. Determining the preset region based on the historical defect distribution allows for a more accurate determination of the preset region in conjunction with the actual production status.

[0094] In exemplary embodiments of this disclosure, a method for determining defects is provided, such as... Figure 10 As shown, Figure 10 This is a flowchart illustrating a process for determining a preset region based on the historical defect distribution of a wafer, provided by an exemplary embodiment of this disclosure. The process includes: S600, determine the defect density of historical defects in the first N batches of wafers under the same process technology; where N is greater than or equal to 2; S700 defines the region where the defect density characterization value is greater than a preset threshold as the preset region.

[0095] In exemplary embodiments of this disclosure, to ensure that the determination of the preset region better reflects the actual production status, the preset region can be determined based on the distribution of historical defects in the wafer regions of the first N batches of wafers under the same process technology. For example, in a voltage contrast diagram, a defect distribution heatmap can be formed from the historical defects of the first N batches of wafers under the same process technology, and the defect density in the relevant wafer region can be determined based on the defect distribution heatmap. The defect density characterizes the number or frequency of occurrences of historical defects from the first N batches under the same process technology in the relevant wafer region. To more accurately describe the number or frequency of occurrences of historical defects from the first N batches under the same process technology in the relevant wafer region, the variance or standard deviation of the corresponding number or frequency can be used as the characterization value of the defect density.

[0096] The preset threshold can be determined according to the manufacturing needs, ideally to accurately assess the likelihood of short circuits. For example, the preset threshold characterizes the value of defects that may occur after a preset process. By assessing whether the defect density is greater than the preset threshold, the likelihood of defects occurring in contact holes and pads after a preset process can be determined more accurately in conjunction with actual production conditions.

[0097] In an exemplary embodiment of this disclosure, determining the defect density of historical defects in the first N batches of wafers under the same process technology includes: determining the defect density of historical defects in a given region within the first N batches of wafers under the same process technology.

[0098] During wafer fabrication, short-circuit defects can occur between contact holes and pads due to overlay deviations or etching / photolithography process errors. Therefore, when determining the preset area, the focus can be on a given region within the wafer based on the shape characteristics of the contact holes and pads. For example, the given region may include areas of abrupt changes in pattern density in a graphics database system, areas traversed by the critical path, and historical yield hotspots.

[0099] The graph database system precisely describes the shape, hierarchy, and location of all structures on the wafer, including contact holes and pads. Pattern density abrupt change regions include areas on the wafer where the pattern density of related structures, such as contact holes or pads, changes abruptly. Critical path traversal regions include areas on the wafer traversed by the critical path corresponding to related structures, such as contact holes or pads. Historical yield hotspot regions include areas within the first M batches of wafers under the same process technology where defects occur most frequently. For example, high-frequency regions may include regions exceeding a preset number of defects occurring in other regions, or regions where the number of defects occurring in other regions is T times the number of defects occurring in other regions. Here, M is an integer greater than or equal to 2, and T is greater than 1.

[0100] The exemplary embodiments of this disclosure, by determining a preset area based on the historical defect distribution in a given region within the wafer, can more accurately determine the preset area in conjunction with the actual production status, thereby significantly improving detection efficiency, effectively reducing the risk of missed detections, and increasing product yield.

[0101] In exemplary embodiments of this disclosure, a preset region can be determined simultaneously based on a wafer's graphic database system and the wafer's historical defect distribution. For example, a first preset region determined by the wafer's graphic database system and a second preset region determined based on the wafer's historical defect distribution can be used together as the preset region. Alternatively, the first preset region determined by the wafer's graphic database system and the second preset region determined based on the wafer's historical defect distribution can be weighted and then determined as the preset region.

[0102] A wafer involves numerous structures, including a large number of contact holes and pads. Therefore, after each process step, defect inspection of these numerous areas, including contact holes and pads, is required. The wafer fabrication process is also highly complex, necessitating multiple inspections for potential defects during each batch of wafers. To ensure inspection efficiency while effectively reducing the risk of missed defects, a weighted average of a first preset region determined by a wafer's graphical database system and a second preset region determined by the wafer's historical defect distribution can be used to define a preset region.

[0103] In one exemplary embodiment, a first preset region determined by a wafer's graphical database system can be used as the primary measurement component, while a second preset region determined based on the wafer's historical defect distribution can be used as a reference measurement component. The preset region is then determined by weighting these components. In this embodiment, the first and second preset regions have a high degree of overlap, and the preset region can be determined relatively accurately based on the first preset region. In this case, the first preset region can be used as the primary measurement component, and the second preset region as the reference measurement component to determine the preset region.

[0104] In one exemplary embodiment, a second preset region determined based on the historical defect distribution of the wafer can be used as the primary measurement component, while a first preset region determined based on the wafer's graphical database system can be used as a reference measurement component. The preset region is then determined by weighting these components. In this embodiment, the first and second preset regions have low overlap, and the preset region cannot be accurately determined based solely on the first preset region. In such cases, the second preset region can be used as the primary measurement component, and the first preset region as the reference measurement component to determine the preset region.

[0105] In an exemplary embodiment, a first region that overlaps with the second preset region, and a second region determined by weighting the remaining portions of the first and second preset regions, can be collectively used as a preset region. The first region, which is the region with a high probability of defect occurrence during wafer fabrication, is the overlapping region between the first preset region determined by the wafer's graphical database system and the second preset region determined by the wafer's historical defect distribution. Therefore, it can be used as a preset region. The remaining portions of the first and second preset regions can be used as a primary or reference measurement to determine the second region, and this region can also be used as a preset region.

[0106] In the exemplary embodiments of this application, considering both the characteristics of wafer design and the characteristics of the process in wafer fabrication, the first preset region determined by the wafer's graphic database system and the second preset region determined by the wafer's historical defect distribution are used as the basis for determining the preset region. This can ensure detection efficiency while effectively reducing the risk of missed detections.

[0107] In exemplary embodiments of this disclosure, a method for determining defects is provided, such as... Figure 11 As shown, Figure 11 This is a flowchart illustrating a specific example of a method for determining defects provided in an exemplary embodiment of this disclosure. The method includes: S101, determine the preset area based on the wafer's graphic database system and the wafer's historical defect distribution status; S102, Determine the reference voltage contrast diagram, which is a voltage contrast diagram generated based on the corresponding GDS data of the wafer under an ideal defect-free state.

[0108] S103, after the etching process of the contact holes on the wafer, obtain the voltage contrast map corresponding to the wafer.

[0109] In this embodiment, for ease of description, steps S102 and S103 are used to describe the acquisition order of the reference voltage contrast map and the voltage contrast map. However, this does not constitute a limitation of this disclosure. In actual application, the acquisition order of the reference voltage contrast map and the voltage contrast map can be determined as needed. For example, the voltage contrast map corresponding to the wafer can be acquired first after the etching process of the contact holes of the wafer, and then the reference voltage contrast map can be determined.

[0110] S104, determine the electrical parameters between contact holes and pads in a preset area of ​​the voltage contrast diagram and the electrical parameters between contact holes and pads in the corresponding preset area of ​​the reference voltage contrast diagram; the preset area includes the contact holes of the wafer and the area between at least two adjacent pads thereon.

[0111] S105, in response to the fact that the characterization value of the electrical parameter between the contact hole and the pad in the preset area of ​​the voltage contrast diagram is greater than the characterization value of the electrical parameter between the contact hole and the pad in the corresponding preset area of ​​the reference voltage contrast diagram, it is determined that the contact hole in the preset area of ​​the wafer is connected to at least two pads, forming a short circuit defect.

[0112] S106, in the voltage contrast diagram, the short-circuit defect is displayed in a flashing manner.

[0113] In this embodiment, after the etching process of the contact holes on the wafer, the electrical parameters between the contact holes and pads in the preset area of ​​the obtained voltage contrast diagram of the wafer are compared with the electrical parameters between the contact holes and pads in the preset area of ​​the reference contrast diagram to determine whether there is a short circuit defect between the contact hole and at least two pads. This can directly and effectively determine whether there is a short circuit defect in the preset area, so as to adjust the preparation parameters in the wafer preparation process in a timely manner, improve the wafer preparation yield, and reduce costs.

[0114] Exemplary embodiments of this disclosure, such as Figure 12 As shown, Figure 12 This disclosure provides an exemplary embodiment of a defect determination device 1200, which includes: an acquisition module 1201, a first determination module 1202, a second determination device 1203, a display module 1204, and a third determination module 1205.

[0115] The acquisition module 1201 is configured to acquire the voltage contrast map corresponding to the wafer after a preset process.

[0116] The first determining module 1202 is configured to determine the electrical parameters between contact holes and pads within a preset region of the wafer based on the voltage contrast diagram; the electrical parameters characterize the conductivity between the contact holes and pads; the preset region characterizes the region where the probability of defect occurrence meets a preset condition; The second determining module 1203 is configured to determine defects in the preset area of ​​the wafer based on the electrical parameters and reference electrical parameters; the reference electrical parameters include the electrical parameters between the contact holes and the pads in the preset area of ​​the reference voltage contrast diagram corresponding to the wafer.

[0117] In some exemplary embodiments, the second determining module 1203 is further configured to determine, in response to a characterization value of the electrical parameter being greater than a reference characterization value of the reference electrical parameter, that a short-circuit defect has occurred between the contact hole and the pad within the preset area of ​​the wafer.

[0118] In some exemplary embodiments, the preset process includes an etching process for the contact hole and / or a photolithography process for the contact hole.

[0119] In some exemplary embodiments, the determining device further includes a display module 1204, which is configured to: In the voltage contrast diagram, the short-circuit defect is displayed in a preset manner; the preset manner characterizes the difference between the characterization value of the electrical parameter between the contact hole and the pad in the preset area of ​​the voltage contrast diagram and the reference characterization value of the reference electrical parameter corresponding to the reference voltage contrast diagram.

[0120] In some exemplary embodiments, the determining device further includes a third determining module 1205, which is configured to: The preset region is determined based on the wafer's graphic database system; and / or The preset region is determined based on the historical defect distribution of the wafer.

[0121] In some exemplary embodiments, the third determining module 1205 is further configured to: The spacing between the contact hole and the pad is determined based on the graphics database system; In response to the spacing being less than a spacing threshold, the area including the contact hole and the pad is determined as the preset area.

[0122] In some exemplary embodiments, the third determining module 1205 is further configured to: Based on the graphics database system, determine the minimum spacing between the edge of the contact hole and the edge of the pad; The minimum spacing is defined as the spacing between the contact hole and the pad.

[0123] In some exemplary embodiments, the third determining module 1205 is further configured to: Determine the defect density of the historical defects of the first N batches of the wafers under the same process technology; where N is an integer greater than or equal to 2; The region whose defect density characterization value is greater than a preset threshold is defined as the preset region.

[0124] In some exemplary embodiments, the third determining module 1205 is further configured to: Determine the defect density of the historical defects in a given region within the first N batches of the wafers under the same process technology.

[0125] In some exemplary embodiments, the given region includes one or more of the following regions: The graph database system includes graph density abrupt change areas, critical path traversal areas, and historical yield hotspot areas.

[0126] In some exemplary embodiments, when the preset region is determined based on the graphics database system of the wafer and the historical defect distribution status of the wafer, the third determining module 1205 is further configured to: The preset region is determined by weighting a first preset region determined by the graphics database system of the wafer and a second preset region determined by the historical defect distribution of the wafer; or The first region that overlaps with the first preset region and the second preset region, and the second region determined by weighting the remaining parts of the first preset region and the second preset region, are collectively used as the preset region.

[0127] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0128] Figure 13 This is a block diagram illustrating an electronic device according to an exemplary embodiment of this disclosure. The electronic device may be an online inspection device, such as a high-voltage scanning electron microscope (HV-SEM) device. An HV-SEM is an electron beam inspection device used in semiconductor manufacturing for wafer defect detection, and can be used for voltage contrast (VC) inspection. It may also be a computer device 900. For example, the computer device 900 may be provided as a terminal device. See reference... Figure 13 The computer device 900 includes a processor 901, the number of which can be set to one or more as needed. The computer device 900 also includes a memory 902 for storing instructions executable by the processor 901, such as application programs. The number of memories can be set to one or more as needed. The stored application programs can be one or more. The processor 901 is configured to execute instructions to perform the defect determination method provided in the above embodiments.

[0129] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, apparatus (devices), or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. Computer storage media include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data), including but not limited to RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and can include any information delivery medium.

[0130] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is provided, such as a memory 902 including instructions, which can be executed by a processor 901 of a computer device 900 to complete the aforementioned method for determining defects. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0131] In exemplary embodiments of this disclosure, a non-transitory computer-readable storage medium is provided, which, when the instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform the defect determination method provided by the exemplary embodiments of this disclosure.

[0132] In an exemplary embodiment of this disclosure, a computer program product is provided, including a computer program and a method for determining the aforementioned defects when the computer program is executed by a processor.

[0133] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0134] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0135] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0136] In this disclosure, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase “comprising…” does not exclude the presence of additional identical elements in the article or device that includes said element.

[0137] Although preferred embodiments of the present disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0138] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, the intent of this disclosure also includes these modifications and variations.

Claims

1. A method for determining defects, characterized in that, The determination method includes: After the preset process flow, obtain the voltage contrast map corresponding to the wafer; The electrical parameters between the contact holes and pads within a preset region of the wafer are determined based on the voltage contrast diagram; the electrical parameters characterize the conductivity between the contact holes and pads; the preset region characterizes the region where the probability of defect occurrence meets a preset condition; Based on the electrical parameters and reference electrical parameters, the defects in the preset area of ​​the wafer are determined; the reference electrical parameters include the electrical parameters between the contact holes and the pads in the preset area of ​​the reference voltage contrast diagram corresponding to the wafer.

2. The method for determining defects according to claim 1, characterized in that, Determining the defects within the preset region of the wafer based on the electrical parameters and reference electrical parameters includes: In response to the characteristic value of the electrical parameter being greater than the reference characteristic value of the reference electrical parameter, a short circuit defect is determined to have occurred between the contact hole and the pad within the preset area of ​​the wafer.

3. The method for determining defects according to claim 1, characterized in that, The preset process includes the etching process of the contact hole and / or the photolithography process of the contact hole.

4. The method for determining defects according to claim 2, characterized in that, The determination method further includes: In the voltage contrast diagram, the short-circuit defect is displayed in a preset manner; the preset manner characterizes the difference between the characterization value of the electrical parameter between the contact hole and the pad in the preset area of ​​the voltage contrast diagram and the reference characterization value of the reference electrical parameter corresponding to the reference voltage contrast diagram.

5. The method for determining defects according to any one of claims 1-4, characterized in that, The determination method further includes: The preset region is determined based on the wafer's graphic database system; and / or The preset region is determined based on the historical defect distribution of the wafer.

6. The method for determining defects according to claim 5, characterized in that, Determining the preset region based on the wafer's graphic database system includes: The spacing between the contact hole and the pad is determined based on the graphics database system; In response to the spacing being less than a spacing threshold, the area including the contact hole and the pad is determined as the preset area.

7. The method for determining defects according to claim 6, characterized in that, Determining the spacing between the contact hole and the pad according to the graphics database system includes: Based on the graphics database system, determine the minimum spacing between the edge of the contact hole and the edge of the pad; The minimum spacing is defined as the spacing between the contact hole and the pad.

8. The method for determining defects according to claim 5, characterized in that, Determining the preset region based on the historical defect distribution of the wafer includes: Determine the defect density of the historical defects of the first N batches of the wafers under the same process technology; where N is an integer greater than or equal to 2; The region whose defect density characterization value is greater than a preset threshold is defined as the preset region.

9. The method for determining defects according to claim 8, characterized in that, Determining the defect density of the historical defects in the first N batches of the wafers under the same process technology includes: Determine the defect density of the historical defects in a given region within the first N batches of the wafers under the same process technology.

10. The method for determining defects according to claim 9, characterized in that, The given region includes one or more of the following regions: The graph database system includes graph density abrupt change areas, critical path traversal areas, and historical yield hotspot areas.

11. The method for determining defects according to claim 5, characterized in that, When determining the preset region based on the wafer's graphical database system and the wafer's historical defect distribution status, the determination method further includes: The preset region is determined by weighting a first preset region determined by the graphics database system of the wafer and a second preset region determined by the historical defect distribution of the wafer; or The first region that overlaps with the first preset region and the second preset region, and the second region determined by weighting the remaining parts of the first preset region and the second preset region, are collectively used as the preset region.

12. A defect determination device, characterized in that, include: The acquisition module is configured to acquire the voltage contrast map corresponding to the wafer after a preset process. The first determining module is configured to determine the electrical parameters between contact holes and pads within a preset area of ​​the wafer based on the voltage contrast diagram; The electrical parameters characterize the conductivity between the contact hole and the pad. The preset region represents the region where the probability of defect occurrence meets the preset conditions. The second determining module is configured to determine defects in the preset region of the wafer based on the electrical parameters and reference electrical parameters; The reference electrical parameters include the electrical parameters between the contact holes and the pads within the preset area of ​​the reference voltage contrast diagram corresponding to the wafer.

13. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to perform the defect determination method as described in any one of claims 1-11.

14. A non-transitory computer-readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the defect determination method as described in any one of claims 1-11.

15. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the method for determining defects as described in any one of claims 1-11.

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