A vertical annealing furnace ultra-thin wafer stack flat annealing process

Abstract

The application provides a vertical annealing furnace ultra-thin wafer stack horizontal annealing process, comprising the following steps: taking out a quartz boat of the vertical annealing furnace, and performing nitrogen blowing on a furnace cavity; adhering and stacking a back surface of a piece of pretreated qualified ultra-thin wafer and a front surface of a piece of test wafer in a same clamping groove of a wafer box, and arranging the flat edges of the ultra-thin wafer and the test wafer to be staggered, to form a wafer stack; horizontally placing the wafer stack on the quartz boat, so that the test wafer supports the ultra-thin wafer; annealing by using a segmented step heating mode, and cooling to room temperature after heat preservation by using a segmented temperature control mode. By the whole matching design of nitrogen atmosphere protection, uniform heating and cooling, regular wafer stack loading, and slow cooling and shaping, the problems of wafer stack deformation, adhesion, warping and high-temperature oxidation of the ultra-thin wafer stack are solved, the process stability is high, the batch consistency is good, the process is suitable for large-scale production operation of the vertical annealing furnace, the process is replicable and can be implemented, and the process meets the semiconductor precision heat treatment production standard.

Description

Technical Field

[0001] This invention relates to the field of semiconductor wafer thermal processing technology, specifically to a vertical annealing furnace for the flat-laying annealing process of ultrathin wafer stacks. Background Technology

[0002] Ultra-thin wafers are widely used in power devices, MEMS, chip packaging and other fields. Due to their thin thickness, poor rigidity, and extremely low bending strength, they are very easy to break and deform during the heat treatment process.

[0003] Currently, commonly used vertical annealing furnaces uniformly adopt a single-wafer flat-laying loading process, horizontally inserting the wafer into the quartz boat slot for independent heat treatment of each wafer. This existing solution has four major drawbacks: 1. When ultra-thin wafers are placed horizontally, they rely on the force of the edge for support. The weight of the wafer itself, the scouring of the circulating air in the furnace, and the uneven thermal stress generated by heating and cooling can easily cause the wafer edge to crack or the whole wafer to break, resulting in huge material loss and cost. 2. When a single wafer is suspended without planar support, stress release is unrestrained at high temperatures, resulting in arc-shaped warping, uneven surfaces, and excessive wafer flatness. Subsequent photolithography, coating, and polishing processes cannot be processed normally, leading to low batch yield. 3. Manually inserting and removing individual wafers can easily scratch or break ultrathin wafers, requiring a high level of operator skill. The loading time per furnace is long, the number of wafers that can be loaded per furnace is small, and the equipment utilization rate is limited. 4. When a single wafer is placed horizontally, there are temperature differences between the front and back sides, and between the center and the edge. This results in uneven release of internal stress and poor consistency of electrical parameters among wafers in the same batch.

[0004] In general, high-temperature heat treatment of double-layer wafer stacking can cause silicon wafer interface bonding and adhesion, making the two wafers firmly bonded together and unable to be separated, resulting in direct scrapping. Therefore, all annealing and oxidation equipment prohibits wafer stacking contact. There is currently no mature process for stacking and annealing ultra-thin wafers, and the industry pain points of high breakage and low capacity in ultra-thin wafer annealing have not been effectively solved for a long time.

[0005] Therefore, this invention proposes a vertical annealing furnace for the flat-laying annealing process of ultrathin wafer stacks. Summary of the Invention

[0006] The purpose of this invention is to overcome the above-mentioned shortcomings and provide a vertical annealing furnace for the flat-laying annealing process of ultrathin wafer stacking.

[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: a vertical annealing furnace for annealing ultrathin wafers stacked in a flat manner, comprising the following steps: S1. Remove the quartz boat from the vertical annealing furnace and purge the furnace cavity with nitrogen to establish a pure nitrogen inert atmosphere. S2. Place a pre-processed qualified ultrathin wafer with its back side against a test wafer with its front side in the same slot of the wafer cassette, with the flat edges of the ultrathin wafer and the test wafer staggered to form a stack; place the stack horizontally on a quartz boat so that the test wafer supports the ultrathin wafer. S3. Send the quartz boat into the furnace chamber, close the furnace cover and continuously introduce nitrogen for a period of time to expel oxygen and water vapor from the furnace. S4. Annealing is carried out using a segmented, stepped heating method, followed by temperature control and cooling to room temperature in stages after heat preservation.

[0008] Furthermore, in S2, the angle between the flat edges of the ultrathin wafer and the test wafer is 8°~15°.

[0009] Furthermore, the angle at which the flat edges are offset is 10°.

[0010] Furthermore, in S2, the thickness of the ultrathin wafer is 50~200μm, and the test wafer is a bare silicon wafer of the same material and size as the ultrathin wafer but with a greater thickness, and there is no bonding adhesive layer between the two.

[0011] Furthermore, in step S2, the pretreatment includes cleaning and drying the back side of the ultrathin wafer to remove particles and organic residues.

[0012] Furthermore, in step S3, the gas inside the furnace is first replaced with a large flow of nitrogen for 5-10 minutes, and then a small flow is used to maintain a slight positive pressure inside the furnace.

[0013] Furthermore, in S4, the segmented step heating includes: heating to a first temperature at a first rate and holding at that temperature for a first duration, then heating to a second temperature at a second rate and holding at that temperature for a second duration. The segmented temperature control cooling includes: cooling to a first cooling temperature at a first cooling rate, and then naturally cooling to room temperature along with the furnace.

[0014] Furthermore, the first temperature is 250℃~350℃, the second temperature is 400℃~900℃; the first rate is 5℃ / min~10℃ / min, the second rate is 5℃ / min~10℃ / min; the first duration is 10min~20min, and the second duration is 20min~60min.

[0015] Furthermore, the first cooling rate is 5℃ / min to 10℃ / min, and the first cooling temperature is 250℃ to 350℃.

[0016] Furthermore, it also includes S5: after annealing, the quartz boat is taken out of the furnace, the stacked group is slicing, the ultrathin wafer is separated from the test wafer, and the ultrathin wafer is tested.

[0017] Compared with the prior art, the present invention has the following beneficial effects: This invention significantly solves the problems of deformation, adhesion, warping, and high-temperature oxidation of ultra-thin wafer stacks through a complete matching design including nitrogen atmosphere protection throughout the process, uniform heating and cooling, orderly stacking and furnace loading, and slow cooling and shaping. It has high process stability, good batch consistency, is suitable for mass production in vertical annealing furnaces, and the process is replicable and can be implemented locally, meeting the standards for semiconductor precision heat treatment production. Attached Figure Description

[0018] The accompanying drawings, which form part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the structure in which the ultrathin wafer and the test wafer are placed in a quartz boat in this invention.

[0019] Figure 2 This is a schematic diagram of the structure in this invention where the ultrathin wafer and the test wafer are placed at an 8° offset.

[0020] Figure 3 This is a schematic diagram of the structure in this invention where the ultrathin wafer and the test wafer are placed at a 10° offset.

[0021] Figure 4 This is a schematic diagram of the structure in this invention where the ultrathin wafer and the test wafer are placed at a 15° offset.

[0022] In the image: 1. Quartz boat; 2. Ultra-thin wafer; 3. Test wafer. Detailed Implementation

[0023] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Example 1: like Figure 1 As shown: This invention addresses the vertical annealing process for 6-inch ultrathin silicon wafers. Based on a nitrogen-sealed protective atmosphere, it employs a quartz boat stacking method to complete the low-temperature isothermal annealing treatment, effectively improving the problems of warpage, thermal deformation, and fragmentation of ultrathin wafers. The specific process steps and parameters are as follows: S1. Wafer pretreatment and preheating heat treatment: A 50μm ultrathin polished wafer was selected and pre-cleaned and dried to ensure that the wafer surface was free of water stains, particles, and organic residues. The wafer to be processed was then placed in a clean, room-temperature wafer box for pre-treatment before annealing to ensure consistency in subsequent heat treatment.

[0025] S2. Quartz boat is removed from the furnace, and a basic nitrogen atmosphere is established inside the furnace: After the equipment has completed standby preheating, the furnace door of the vertical annealing furnace is opened, and the furnace cavity nitrogen purging system is started simultaneously to continuously introduce high-purity nitrogen to replace the residual air and water vapor in the furnace cavity, maintain a slightly positive pressure nitrogen inert atmosphere in the furnace, and prevent high-temperature oxidation and surface blooming defects of the wafer.

[0026] S3. Wafer alignment and precision furnace loading: In a nitrogen-protected dust-free environment, a qualified ultrathin wafer 2 (back side) and a test wafer 3 (front side) are stacked in the same slot of the wafer cassette, with the flat edges of the wafers slightly offset by 8°, forming a stacked assembly. Figure 2 As shown, the complete wafer stack is placed horizontally on the high-purity quartz boat 1 for the vertical furnace, and the bottom surface of the ultra-thin wafer 2 is tested to ensure that the plane of wafer 3 supports the entire wafer. Throughout the wafer loading process, the wafers are handled with care to prevent micro-deformation, chipping, and scratches caused by human force. After loading, the flatness and positional consistency of the wafers are checked.

[0027] S4. The quartz boat carrying the wafers is placed into the furnace and cured in a sealed nitrogen atmosphere: The quartz boat, fully loaded with wafers, is smoothly placed into the isothermal process zone of the vertical furnace tube, and the furnace door is closed to achieve a sealed furnace cavity. High-purity nitrogen is continuously introduced to maintain a stable inert atmosphere inside the furnace, keep the furnace cavity pressure constant, remove residual impurities, and ensure that the entire batch of wafers is in a uniform, clean, and oxygen-free heat treatment environment.

[0028] S5. Uniform heating and isothermal annealing: A segmented, stable heating rate mode is adopted, with the heating rate controlled at 5℃ / min to avoid thermal shock deformation of the ultra-thin wafer caused by rapid heating. The temperature is gradually increased to the set annealing isothermal range and held for 10 minutes. This long-term isothermal release of lattice stress inside the wafer improves wafer warpage and residual stress unevenness, thereby enhancing the overall flatness and electrical stability.

[0029] Specifically: Slow, step-by-step heating is used to avoid concentrated thermal stress caused by instantaneous temperature differences. (1) Low temperature preheating section: The furnace temperature is raised to 250℃ at a rate of 5℃ / min and kept at a constant temperature for 10min to release the residual mechanical stress of the wafer at room temperature. (2) Heating to the process temperature range: heating from 250℃ to 400℃ annealing temperature, heating rate 5℃ / min; (3) Constant temperature annealing section: The target temperature is kept constant for 20 minutes to complete the lattice repair and uniform release of internal stress.

[0030] High-purity nitrogen is continuously introduced throughout the process to stabilize the airflow inside the furnace.

[0031] S6. Slow cooling process: After isothermal annealing, a slow in-furnace cooling process is adopted, with the cooling rate strictly controlled at 5℃ / min. Rapid cooling by opening the furnace door or direct cold air blowing is strictly prohibited. Slow cooling avoids secondary stress, wafer bending, and cracking caused by excessive temperature differences in the ultra-thin wafers, ensuring stable solidification of the wafer's lattice structure. The wafer can only be removed from the furnace after the furnace temperature has dropped to room temperature.

[0032] Specifically: Slow cooling process to avoid secondary deformation; rapid cooling is prohibited after annealing; two-stage temperature-controlled cooling: (1) Temperature control and cooling section: The furnace body is cooled from the highest annealing temperature to 250℃ at a cooling rate of 5℃ / min; (2) Natural slow cooling section: Turn off heating below 250℃ and let the furnace cool naturally to room temperature to avoid secondary warping and cracking caused by rapid cooling.

[0033] S7. Inspection of pieces after baking and batch quality verification: Once the furnace temperature reaches the target level, open the furnace door and manually remove the stacked wafers from the quartz boat. Place them in the same slot in the wafer cassette. Use tweezers to separate the wafers, offset by 8°, and remove them one by one. Perform a full inspection of the batch of wafers for appearance, flatness, warpage, and surface cleanliness, checking for defects such as wafer adhesion, micro-deformation, surface oxidation, and color differences. Record the batch yield and process parameters to complete the closed loop of the entire annealing process.

[0034] Example 2: like Figure 1 As shown: This invention addresses the vertical annealing process for 6-inch ultrathin silicon wafers. Based on a nitrogen-sealed protective atmosphere, it employs a quartz boat stacking method to complete the low-temperature isothermal annealing treatment, effectively improving the problems of warpage, thermal deformation, and fragmentation of ultrathin wafers. The specific process steps and parameters are as follows: S1. Wafer pretreatment and preheating heat treatment: A 100μm ultrathin polished wafer was selected and pre-cleaned and dried to ensure that the wafer surface was free of water stains, particles, and organic residues. The wafer to be processed was then placed in a clean, room-temperature wafer box for pre-treatment before annealing to ensure consistency in subsequent heat treatment.

[0035] S2. Quartz boat is removed from the furnace, and a basic nitrogen atmosphere is established inside the furnace: After the equipment has completed standby preheating, the furnace door of the vertical annealing furnace is opened, and the furnace cavity nitrogen purging system is started simultaneously to continuously introduce high-purity nitrogen to replace the residual air and water vapor in the furnace cavity, maintain a slightly positive pressure nitrogen inert atmosphere in the furnace, and prevent high-temperature oxidation and surface blooming defects of the wafer.

[0036] S3. Wafer alignment and precision furnace loading: In a nitrogen-protected dust-free environment, a qualified ultrathin wafer 2 (back side) and a test wafer 3 (front side) are stacked in the same slot of the wafer cassette, with the flat edges of the wafers slightly offset by 10°, forming a stacked assembly. Figure 3 As shown, the complete wafer stack is placed horizontally on the high-purity quartz boat 1 for the vertical furnace, and the bottom surface of the ultra-thin wafer 2 is tested to ensure that the plane of wafer 3 supports the entire wafer. Throughout the wafer loading process, the wafers are handled with care to prevent micro-deformation, chipping, and scratches caused by human force. After loading, the flatness and positional consistency of the wafers are checked.

[0037] S4. The quartz boat carrying the wafers is placed into the furnace and cured in a sealed nitrogen atmosphere: The quartz boat, fully loaded with wafers, is smoothly placed into the isothermal process zone of the vertical furnace tube, and the furnace door is closed to achieve a sealed furnace cavity. High-purity nitrogen is continuously introduced to maintain a stable inert atmosphere inside the furnace, keep the furnace cavity pressure constant, remove residual impurities, and ensure that the entire batch of wafers is in a uniform, clean, and oxygen-free heat treatment environment.

[0038] S5. Uniform heating and isothermal annealing: A segmented, stable-rate heating mode is adopted, with the heating rate controlled at 8℃ / min to avoid thermal shock deformation of the ultra-thin wafer caused by rapid heating. The temperature is gradually increased to the set annealing isothermal range and held for 15 minutes. This long-term isothermal release of lattice stress inside the wafer improves wafer warpage and residual stress unevenness, thereby enhancing the overall flatness and electrical stability.

[0039] Specifically: Slow, step-by-step heating is used to avoid concentrated thermal stress caused by instantaneous temperature differences. (1) Low temperature preheating section: The furnace temperature is raised to 300℃ at a rate of 8℃ / min and kept at a constant temperature for 15min to release the residual mechanical stress of the wafer at room temperature. (2) Heating to the process temperature range: heating from 300℃ to 600℃ annealing temperature, heating rate 8℃ / min; (3) Constant temperature annealing section: The target temperature is kept constant for 40 minutes to complete lattice repair and uniform release of internal stress.

[0040] High-purity nitrogen is continuously introduced throughout the process to stabilize the airflow inside the furnace.

[0041] S6. Slow cooling process: After isothermal annealing, a slow in-furnace cooling process is adopted, with the cooling rate strictly controlled at 8℃ / min. Rapid cooling by opening the furnace door or direct cold air blowing is strictly prohibited. Slow cooling avoids secondary stress, wafer bending, and cracking caused by excessive temperature differences in the ultra-thin wafers, ensuring stable solidification of the wafer's lattice structure. The wafer can only be removed from the furnace after the furnace temperature has dropped to room temperature.

[0042] Specifically: Slow cooling process to avoid secondary deformation; rapid cooling is prohibited after annealing; two-stage temperature-controlled cooling: (1) Temperature control and cooling section: The furnace body is cooled from the highest annealing temperature to 300℃ at a cooling rate of 8℃ / min; (2) Natural slow cooling section: heating is turned off below 300℃, and the furnace is naturally cooled to room temperature to avoid secondary warping and cracking caused by rapid cooling.

[0043] S7. Inspection of pieces after baking and batch quality verification: Once the furnace temperature reaches the target level, open the furnace door and manually remove the stacked wafers from the quartz boat. Place them in the same slot in the wafer cassette. Use tweezers to separate the wafers, staggering them by 10°, and remove them one by one. Perform a full inspection of the batch of wafers for appearance, flatness, warpage, and surface cleanliness, checking for defects such as wafer adhesion, micro-deformation, surface oxidation, and color differences. Record the batch yield and process parameters to complete the closed loop of the entire annealing process.

[0044] Example 3: like Figure 1 As shown: This invention addresses the vertical annealing process for 6-inch ultrathin silicon wafers. Based on a nitrogen-sealed protective atmosphere, it employs a quartz boat stacking method to complete the low-temperature isothermal annealing treatment, effectively improving the problems of warpage, thermal deformation, and fragmentation of ultrathin wafers. The specific process steps and parameters are as follows: S1. Wafer pretreatment and preheating heat treatment: A 200μm thick ultrathin polished wafer was selected and pre-cleaned and dried to ensure that the wafer surface was free of water stains, particles, and organic residues. The wafer to be processed was then placed in a clean, room-temperature wafer box for pre-treatment before annealing to ensure consistency in subsequent heat treatment.

[0045] S2. Quartz boat is removed from the furnace, and a basic nitrogen atmosphere is established inside the furnace: After the equipment has completed standby preheating, the furnace door of the vertical annealing furnace is opened, and the furnace cavity nitrogen purging system is started simultaneously to continuously introduce high-purity nitrogen to replace the residual air and water vapor in the furnace cavity, maintain a slightly positive pressure nitrogen inert atmosphere in the furnace, and prevent high-temperature oxidation and surface blooming defects of the wafer.

[0046] S3. Wafer alignment and precision furnace loading: In a nitrogen-protected dust-free environment, a qualified ultrathin wafer 2 (back side) and a test wafer 3 (front side) are stacked in the same slot of the wafer cassette, with the flat edges of the wafers slightly offset by 15°, forming a stacked assembly. Figure 4 As shown, the complete wafer stack is placed horizontally on the high-purity quartz boat 1 for the vertical furnace, and the bottom surface of the ultra-thin wafer 2 is tested to ensure that the plane of wafer 3 supports the entire wafer. Throughout the wafer loading process, the wafers are handled with care to prevent micro-deformation, chipping, and scratches caused by human force. After loading, the flatness and positional consistency of the wafers are checked.

[0047] S4. The quartz boat carrying the wafers is placed into the furnace and cured in a sealed nitrogen atmosphere: The quartz boat, fully loaded with wafers, is smoothly placed into the isothermal process zone of the vertical furnace tube, and the furnace door is closed to achieve a sealed furnace cavity. High-purity nitrogen is continuously introduced to maintain a stable inert atmosphere inside the furnace, keep the furnace cavity pressure constant, remove residual impurities, and ensure that the entire batch of wafers is in a uniform, clean, and oxygen-free heat treatment environment.

[0048] S5. Uniform heating and isothermal annealing: A segmented, stable-rate heating mode is adopted, with the heating rate controlled at 10℃ / min to avoid thermal shock deformation of the ultra-thin wafer caused by rapid heating. The temperature is gradually increased to the set annealing isothermal range and held for 20 minutes. This long-term isothermal release of lattice stress inside the wafer improves wafer warpage and residual stress unevenness, thereby enhancing the overall flatness and electrical stability.

[0049] Specifically: Slow, step-by-step heating is used to avoid concentrated thermal stress caused by instantaneous temperature differences. (1) Low temperature preheating section: The furnace temperature is raised to 350℃ at a rate of 10℃ / min and kept at a constant temperature for 20min to release the residual mechanical stress of the wafer at room temperature; (2) Heating to the process temperature range: heating from 350℃ to 900℃ annealing temperature, heating rate 10℃ / min; (3) Constant temperature annealing section: The target temperature is kept constant for 60 minutes to complete lattice repair and uniform release of internal stress.

[0050] High-purity nitrogen is continuously introduced throughout the process to stabilize the airflow inside the furnace.

[0051] S6. Slow cooling process: After isothermal annealing, a slow in-furnace cooling process is adopted, with the cooling rate strictly controlled at 10℃ / min. Rapid cooling by opening the furnace door or direct cold air blowing is strictly prohibited. Slow cooling avoids secondary stress, wafer bending, and cracking caused by excessive temperature differences in the ultra-thin wafers, ensuring stable solidification of the wafer's lattice structure. The wafer can only be removed from the furnace after the furnace temperature has dropped to room temperature.

[0052] Specifically: Slow cooling process to avoid secondary deformation; rapid cooling is prohibited after annealing; two-stage temperature-controlled cooling: (1) Temperature control and cooling section: The furnace body is cooled from the highest annealing temperature to 350℃ at a rate of 10℃ / min; (2) Natural slow cooling section: Turn off heating below 350℃ and let the furnace cool naturally to room temperature to avoid secondary warping and cracking caused by rapid cooling.

[0053] S7. Inspection of pieces after baking and batch quality verification: Once the furnace temperature reaches the target level, open the furnace door and manually remove the stacked wafers from the quartz boat. Place them in the same slot in the wafer cassette. Use tweezers to separate the wafers, staggering them by 15°, and remove them one by one. Perform a full inspection of the batch of wafers for appearance, flatness, warpage, and surface cleanliness, checking for defects such as wafer adhesion, micro-deformation, surface oxidation, and color differences. Record the batch yield and process parameters to complete the closed loop of the entire annealing process.

[0054] This process significantly solves the problems of deformation, adhesion, warping, and high-temperature oxidation of ultra-thin wafers through a complete set of matching designs, including nitrogen atmosphere protection throughout the process, uniform heating and cooling, orderly stacking and furnace loading, and slow cooling and shaping. The process has high stability and good batch consistency, is suitable for mass production in vertical annealing furnaces, and is replicable and feasible, meeting the standards for semiconductor precision heat treatment production.

[0055] Example 4: Based on Example 1, this embodiment designs a multi-level temperature single-variable control experiment for 6-inch ultrathin polished silicon wafers with a thickness of 150μm. It precisely explores the influence of isothermal annealing temperature on the adhesion rate, fragmentation rate and warpage of ultrathin silicon wafers. With all other process parameters fixed, only the isothermal annealing temperature is changed. The wafer quality differences of four sets of process conditions (600℃, 700℃, 800℃, and 900℃) are compared to screen the optimal annealing temperature window suitable for mass production of 150μm ultrathin wafers.

[0056] This experiment used 6-inch ultra-thin polished silicon wafers of the same batch with a thickness of 150μm, ensuring consistent initial surface cleanliness, flatness, and residual stress. All experimental groups fully replicated the entire process system of Example 1: a nitrogen-sealed protective atmosphere, equidistant stacking of wafers in high-purity quartz boats, standardized pre-cleaning and drying, and uniform furnace cavity nitrogen purging and replacement procedures, wafer spacing, and manual loading procedures. The experiment maintained a fixed heating rate of 5℃ / min, a constant-temperature annealing time of 20min, and a cooling rate of 5℃ / min. Slow cooling within the furnace throughout the process was implemented to prevent secondary stress damage caused by rapid cooling upon opening the furnace door or direct cold air blowing.

[0057] The experiment was conducted with four temperature gradients, with 10 samples per test in each group. Each group was repeated twice for mass production verification, resulting in a total of 20 valid samples per group. The isothermal annealing temperature was set at 600℃ for group A, 700℃ for group B, 800℃ for group C, and 900℃ for group D. All groups were operated strictly according to the complete process flow (S1-S7) in Example 1.

[0058] After cooling to room temperature after being removed from the furnace, wafers are uniformly inspected and their performance tested. The quantitative judgment criteria are as follows: wafer adhesion defects are defined as two or more wafers that are bonded together and adhered. Manual separation is prone to causing surface scratches and lattice damage. Fragmentation defects include wafer edge chipping, corner missing, hidden cracks and complete breakage defects. Warp is measured using a semiconductor wafer stress tester. The average warp, adhesion occurrence rate and fragmentation rate of each group of wafers are uniformly statistically analyzed.

[0059] Batch test data for 150μm ultrathin silicon wafers show that: Under the low-temperature annealing condition of 600℃, the residual stress in the internal lattice of the wafer is not fully released, the stress elimination effect is limited, the overall flatness of the wafer is poor, and the average warpage of the batch is about 40μm. At this temperature, the atomic thermal migration activity is low, the risk of stacking adhesion and thermal stress cracking is extremely low, and the adhesion rate and fragmentation rate are close to zero.

[0060] Under the medium-temperature annealing condition of 700℃, the residual stress inside the wafer is effectively released, the lattice structure tends to be stable, the average warpage of the batch is reduced to 30μm, and the flatness is greatly improved; at the same time, there are no obvious high-temperature adhesion or hot cracking defects, and the adhesion rate and fragmentation rate are maintained at an extremely low and controllable level in mass production.

[0061] Under the optimal annealing range of 800℃, the lattice stress of the 150μm ultrathin silicon wafer is completely released, the structure is stabilized, the average warpage of the batch is optimal, reaching 26μm, and the uniformity and electrical stability of the whole wafer are the best; only a very few slight adhesion phenomena exist, and there are no batch adhesion or fragment defects.

[0062] Under the high-temperature annealing conditions of 900℃, the ultra-high furnace temperature leads to a significant increase in the thermal migration rate of atoms on the surface of silicon wafers. At the same time, the ultra-large temperature difference generates additional thermal stress, and the average warpage of the batch rises to 31μm. The flatness is somewhat deteriorated compared to 800℃. However, there are still no batch adhesions or fragment defects at the wafer stacking interface, and the overall quality still meets the requirements for mass production.

[0063] Based on the three core quality indicators of 150μm ultrathin silicon wafers—adhesion rate, fragmentation rate, and warpage—600~900℃ is the suitable constant temperature annealing temperature window for this process, with 800℃ being the optimal temperature point. This temperature range can effectively release residual stress inside the ultrathin silicon wafer, ensuring that the wafer flatness meets mass production requirements, while avoiding high-temperature adhesion and thermal stress cracking defects.

[0064] This embodiment targets highly sensitive ultrathin silicon wafers with a thickness of only 150μm. Through a four-gradient constant temperature single-variable controllable comparative experiment, it accurately quantifies for the first time the differential influence of different annealing temperatures on three core quality parameters of ultrathin wafers: adhesion defects, fragmentation defects, and warpage deformation. This solves the industry's technical pain points in the existing vertical annealing process for ultrathin silicon wafers.

[0065] Comparative Example: 600℃, single-piece flat laying process comparison: This comparative example uses the same annealing temperature, temperature change parameters, furnace atmosphere, heating and cooling rates, annealing time, and wafer specifications as Group A in Example 4. The only difference is that the original stacked flat placement method is changed to a single flat placement method for the process. All other experimental variables are kept the same, and the number of experimental samples and batch verification methods are completely consistent with Group A.

[0066] Experimental data:

[0067] Experimental results show that under the same 600℃ low-temperature annealing conditions, the single-wafer flat-lay method eliminates the risks of inter-wafer bonding and extrusion, as well as wafer adhesion. However, because the heating method of a single-wafer suspended flat-lay method is completely different from that of the stacked flat-lay method, the wafer lacks lateral support constraints, allowing for unrestricted free thermal deformation and preventing the release of residual lattice stress. This results in significantly aggravated overall warpage and fragmentation. Compared to the stacked vertical process in Group A, the comparative single-wafer flat-lay process eliminates the risk of adhesion, but the fragmentation rate is as high as 65%, with an average warpage of 65μm. The wafer flatness consistency is significantly deteriorated, resulting in a large number of warpage defects and fragmentation. However, the flatness index cannot meet the requirements of subsequent precision processes such as photolithography, coating, and bonding.

[0068] This proves that under the low temperature condition of 600℃, the stacked flat method can use the micro-constraint between wafers to suppress free thermal deformation and reduce the warpage. It is a key structural condition for low temperature annealing to make up for insufficient stress release and control wafer deformation. Although the traditional single-wafer flat method completely eliminates the adhesion problem, it will lead to uncontrolled wafer deformation and flatness failure of ultrathin wafers, and is accompanied by the risk of fragmentation. It is not suitable for mass production of precision annealing of ultrathin silicon wafers.

[0069] Meanwhile, by adding a comparative test between the stacked flat structure and the single flat structure at 600℃, the structural advantages of the stacked flat structure under the same annealing conditions were verified: under the condition of insufficient low-temperature stress release, the free thermal deformation of the wafer can be restricted by the uniform micro-constraint between wafers, which can significantly reduce the risk of warpage and make up for the performance shortcomings of the low-temperature process.

[0070] The quantitative process parameter system developed in this comparative experiment specifically addresses the process challenges of 150μm ultrathin silicon wafers, such as thinness, stress sensitivity, easy deformation, easy adhesion, and easy cracking. The process is replicable, feasible, and can be mass-produced, effectively improving the stability, reliability, and mass production economy of the precision thermal processing technology for semiconductor ultrathin silicon wafers.

[0071] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.

Claims

1. A vertical annealing furnace process for annealing ultrathin wafers stacked in a flat configuration, characterized in that, Includes the following steps: S1. Remove the quartz boat from the vertical annealing furnace and purge the furnace cavity with nitrogen to establish a pure nitrogen inert atmosphere. S2. Place a pre-processed qualified ultrathin wafer with its back side against a test wafer with its front side in the same slot of the wafer cassette, with the flat edges of the ultrathin wafer and the test wafer staggered to form a stack; place the stack horizontally on a quartz boat so that the test wafer supports the ultrathin wafer. S3. Send the quartz boat into the furnace chamber, close the furnace cover and continuously introduce nitrogen for a period of time to expel oxygen and water vapor from the furnace. S4. Annealing is carried out using a segmented, stepped heating method, followed by temperature control and cooling to room temperature in stages after heat preservation.

2. The vertical annealing furnace for ultrathin wafer stacking and annealing according to claim 1, characterized in that, In step S2, the angle between the flat edges of the ultrathin wafer and the test wafer is 8°~15°.

3. The vertical annealing furnace for ultrathin wafer stacking and annealing according to claim 2, characterized in that, The angle between the flat edges is 10°.

4. The vertical annealing furnace for ultrathin wafer stacking and annealing according to claim 1, characterized in that, In step S2, the thickness of the ultrathin wafer is 50~200μm, and the test wafer is a bare silicon wafer of the same material and size as the ultrathin wafer but with a greater thickness. There is no bonding adhesive layer between the two.

5. The vertical annealing furnace for ultrathin wafer stacking and annealing according to claim 1, characterized in that, In step S2, the pretreatment includes cleaning and drying the back side of the ultrathin wafer to remove particles and organic residues.

6. The vertical annealing furnace for ultrathin wafer stacking and annealing according to claim 1, characterized in that, In step S3, the gas inside the furnace is first replaced with a large flow of nitrogen for 5 to 10 minutes, and then a small flow is used to maintain a slight positive pressure inside the furnace.

7. The vertical annealing furnace for ultrathin wafer stacking and annealing according to claim 1, characterized in that, In S4, the segmented step heating includes: heating to a first temperature at a first rate and holding at that temperature for a first duration, and then heating to a second temperature at a second rate and holding at that temperature for a second duration. The segmented temperature control cooling includes: cooling to a first cooling temperature at a first cooling rate, and then naturally cooling to room temperature along with the furnace.

8. The vertical annealing furnace for ultrathin wafer stacking and annealing according to claim 7, characterized in that, The first temperature is 250℃~350℃, and the second temperature is 400℃~900℃; the first rate is 5℃ / min~10℃ / min, and the second rate is 5℃ / min~10℃ / min; the first duration is 10min~20min, and the second duration is 20min~60min.

9. The vertical annealing furnace for ultrathin wafer stacking and annealing according to claim 7, characterized in that, The first cooling rate is 5℃ / min to 10℃ / min, and the first cooling temperature is 250℃ to 350℃.

10. The vertical annealing furnace process for annealing ultrathin wafers stacked in a flat manner according to claim 1, characterized in that, It also includes S5: After annealing, the quartz boat is taken out of the furnace, the stacked group is split into wafers, the ultrathin wafer is separated from the test wafer, and the ultrathin wafer is tested.

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