STI medium for optimizing inverse narrow channel effect and preparation method thereof

Abstract

The application discloses an STI medium for optimizing reverse narrow channel effect and a preparation method thereof. The medium is formed through a laminating process and is used for filling a shallow isolation groove between two active regions on a surface of a semiconductor substrate. From outside to inside and from bottom to top, the medium comprises a liner oxide layer, a buffer layer and a cover layer in sequence. The liner oxide layer is made of SiO2 film, the buffer layer is made of fluorine-doped SiO2 (FSG), and the cover layer is made of dense SiO2. The laminated structure of the liner oxide layer, the buffer layer and the cover layer effectively neutralizes and weakens the local compressive stress at the edge of the STI through the differential matching of the stress of different medium layers, especially the compressive stress, directly inhibits the inducing factor of the reverse narrow channel effect. The cover layer is deposited on the buffer layer, so that the low stress / low k characteristics of the buffer layer are utilized, and the mechanical strength, the compactness and the pressure resistance of the entire STI filling area are ensured, and the perfect balance between the performance and the reliability is achieved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology and relates to the optimization of shallow trench isolation (STI) process, specifically to an optimized STI dielectric and preparation method for anti-narrow channel effect. Background Technology

[0002] As semiconductor process nodes continue to evolve and device sizes continue to shrink, shallow trench isolation (STI) technology plays a crucial role in isolating active regions and preventing leakage current from adjacent devices. However, in advanced processes, especially at 90nm and below nodes, the threshold voltage decreases as the channel width decreases; this phenomenon is known as the inverse narrow channel effect (INWE).

[0003] Existing research has found that the anti-narrow channel effect is mainly related to the filling material and the changes in the electric field distribution at the edges of the shallow trench isolation (STI) process. When the channel width decreases, the electric field distribution at the edges of the STI isolation structure changes, making the channel edge region easier to turn on, thereby reducing the overall threshold voltage.

[0004] Currently, the mainstream STI (Short Channel Ingress) filling scheme in the industry is mainly based on a single dielectric material such as pure SiO2. However, this scheme has significant shortcomings in dealing with the reverse narrow channel effect, including:

[0005] (1) Stress concentration problem: Pure SiO2 filling medium will generate large local compressive stress on the sidewalls of STI, especially at the top corners. Stress concentration leads to changes in carrier mobility, which in turn aggravates the drift of threshold voltage.

[0006] (2) High dielectric constant: The k value of ordinary SiO2 is about 4.0~4.2. Under narrow channel conditions, the high parasitic capacitance will further affect the RC delay and switching speed of the device.

[0007] (3) Limitation of gap filling capacity: As the trench depth-to-width ratio increases, pure SiO2 is prone to pores or gaps during deposition, which leads to a decrease in isolation reliability.

[0008] Since lowering the threshold voltage makes transistors easier to turn on, it can lead to increased leakage current, reduced noise margin, and inconsistent performance, which negatively impacts the reliability of digital logic circuits and the gain and frequency response of analog circuits. Therefore, it is essential to suppress the anti-narrow channel effect. Summary of the Invention

[0009] To address the shortcomings of existing technologies, this invention proposes an optimized STI dielectric and its preparation method that incorporates anti-narrow channel effect. By employing a dielectric stacking process and utilizing differentiated matching of stresses in different dielectrics, the edge field stress of the STI is optimized, thus solving the problems of significant anti-narrow channel effect, local stress concentration, and large parasitic capacitance in existing technologies.

[0010] An optimized anti-narrow channel effect STI dielectric is formed by dielectric stacking process and is used to fill shallow isolation trenches between two active regions on the surface of a semiconductor substrate. From the outside to the inside and from the bottom to the top, it consists of a pad oxide layer, a buffer layer and a capping layer.

[0011] The elastic modulus, thermal stress, and dielectric constant of the buffer layer material are lower than those of the cover layer.

[0012] Preferably, the material of the liner oxide layer is a SiO2 thin film, the material of the buffer layer is fluorine-doped SiO2 (FSG), and the material of the cover layer is dense SiO2.

[0013] Preferably, the pad oxide layer is obtained by growing a SiO2 thin film on the surface of a silicon substrate through a rapid thermal processing process.

[0014] Preferably, the buffer layer is obtained by plasma-enhanced chemical vapor deposition of SiH4, SiF4 and O2 on the pad oxide layer.

[0015] Preferably, the capping layer is obtained by high-density plasma chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition of dense SiO2 material above the buffer layer.

[0016] Preferably, the height of the buffer layer is 30% to 50% of the STI height, and the height of the cover layer is 50% to 70% of the STI height.

[0017] A method for preparing STI dielectric with optimized anti-narrow channel effect, the specific steps of which are as follows:

[0018] Step 1: In the STI trench formed by etching, a SiO2 thin film is grown on the surface of the silicon substrate as a liner oxide layer by a rapid thermal processing process.

[0019] Step 2: Using plasma-enhanced chemical vapor deposition, a layer of fluorine-doped SiO2 (FSG) is deposited on the liner oxide layer as a buffer layer. The reaction gases are SiH4, SiF4 and O2.

[0020] Step 3: Deposit a dense SiO2 material as a capping layer on the buffer layer using high-density plasma chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition.

[0021] Preferably, the process also includes removing excess deposited material through chemical mechanical polishing to make the STI region flush with the surface of the active region, exposing the active region and preparing it for subsequent gate processes.

[0022] Preferably, the deposition thickness of the buffer layer and the capping layer is adjusted according to the process node and device type.

[0023] As a preferred option, for high-frequency devices, increasing the thickness of the buffer layer can further reduce parasitic capacitance.

[0024] As a preferred option, for high-voltage devices, the thickness of the cover layer is increased to enhance the isolation withstand voltage capability.

[0025] The present invention has the following beneficial effects:

[0026] 1. Stress optimization using STI dielectric stacking process: Abandoning the traditional single SiO2 filling, a stacked structure of pad oxide layer, buffer layer and capping layer is adopted. Through the differentiated matching of stress of different dielectric layers, the local compressive stress at the edge of STI is effectively neutralized and weakened. In particular, the compressive stress directly suppresses the inducing factors of the anti-narrow channel effect.

[0027] 2. Introducing Fluorine-Doped SiO2 (FSG) as a buffer layer: FSG has a low elastic modulus and low thermal stress, which can significantly reduce thermal stress concentration at the sidewalls and top corners of STI trenches. Simultaneously, FSG has a lower dielectric constant than ordinary SiO2, effectively reducing parasitic capacitance and improving the performance of high-frequency or advanced logic devices. Furthermore, FSG has excellent gap-filling capabilities, perfectly filling high aspect ratio, narrow-pitch STI trenches, significantly improving the process window and reliability of the isolation structure.

[0028] 3. Cover layer design that balances density: Depositing a dense material as a cover layer on top of the buffer layer utilizes the low stress / low k characteristics of the buffer layer while ensuring the mechanical strength, density, and pressure resistance of the entire STI filling area, achieving a perfect balance between performance and reliability.

[0029] 4. High feasibility for mass production: It adopts the industry's mature and low-cost combination of FSG and SiO2, with good process compatibility. There is no need to introduce expensive or new deposition equipment, and mass production is highly feasible. Attached Figure Description

[0030] Figures 1-4 This is a schematic diagram showing the structure of each step in a method for preparing an optimized anti-narrow channel effect STI dielectric provided for an embodiment.

[0031] The components are: 1. Semiconductor substrate; 2. Oxide layer; 3. Silicon nitride layer; 4. STI trench; 5. Pad oxide layer; 6. Buffer layer; 7. Cover layer. Detailed Implementation

[0032] The present invention will be further explained below with reference to the accompanying drawings;

[0033] As mentioned in the background section, existing shallow trench isolation typically uses pure SiO2 as the filling medium. In advanced processes, it suffers from stress concentration, high dielectric constant, and insufficient isolation reliability. It cannot effectively address the reverse narrow channel effect, leading to a decrease in threshold voltage, resulting in increased leakage current, reduced noise margin, and inconsistent performance. This negatively impacts the reliability of digital logic circuits and the gain, frequency response, and other performance characteristics of analog circuits.

[0034] To address the shortcomings of the existing technology, this invention proposes an optimized STI dielectric and its preparation method to mitigate the narrow-channel effect. It employs an STI filling structure with dielectric stacks and optimizes the STI edge field stress through differentiated matching of stresses in different dielectrics, thereby effectively alleviating the narrow-channel effect. The invention will be further explained below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the invention. Those skilled in the art can obtain other drawings and other implementation methods based on these drawings without creative effort. Furthermore, the scope of protection of this invention is defined by the claims, and other improvements made using conventional techniques by those skilled in the art are also within the scope of protection of this invention. In addition, details omitted in specific embodiments fall within the knowledge scope of those skilled in the art.

[0035] It should be noted that the accompanying drawings only schematically illustrate the parts related to the present invention, and all are in a very simplified form and use non-precise proportions. They are only used to facilitate and clarify the illustration of the embodiments of the present invention, and do not represent the actual structure of the product.

[0036] When referring to spatially related terms in this invention, such as "height," "thickness," "upper," "lower," "vertical," "horizontal," "top," "bottom," "inner," "outer," and similar terms, the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings. This is solely for the purpose of facilitating and simplifying the description of the invention, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and should not be construed as a limitation of the invention. In addition to the orientation shown in the figures, these spatially related terms are also used to describe the possible orientation of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotation of 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0037] An optimized anti-narrow channel effect STI dielectric is formed by dielectric stacking process and is used to fill the shallow isolation trench between two active regions on the surface of a semiconductor substrate. From the outside to the inside and from the bottom to the top, it consists of a pad oxide layer 5, a buffer layer 6 and a capping layer 7.

[0038] The material of the liner oxide layer 5 is a SiO2 thin film, the material of the buffer layer 6 is fluorine-doped SiO2 (FSG), and the material of the cover layer 7 is dense SiO2.

[0039] Compared to the traditional single SiO2 filling scheme, the differentiated matching of stresses in different dielectric layers in the pad oxide layer 5, buffer layer 6 and capping layer 7 effectively neutralizes and weakens the local compressive stress at the edge of STI, directly suppressing the inducing factors of the anti-narrow channel effect.

[0040] The buffer layer 6 material, FSG, has a low elastic modulus and low thermal stress, which can significantly reduce thermal stress concentration at the sidewalls and top corners of the STI trench. Simultaneously, its dielectric constant is 3.5~3.8, lower than that of ordinary SiO2 materials, effectively reducing parasitic capacitance, making it highly suitable for high-frequency and advanced logic chips. Furthermore, FSG's high fluidity allows it to perfectly fill high aspect ratio, narrow-pitch STI trenches, avoiding voids or gaps that may occur in traditional CVD processes, and significantly improving the process window and reliability of STI.

[0041] A dense SiO2 layer 7 is formed by filling the buffer layer 6 above the buffer layer. This layer is waterproof and oxygen-proof, which not only utilizes the low stress and low dielectric constant of FSG, but also ensures the mechanical strength, density and pressure resistance of the entire STI filling area, thus guaranteeing long-term reliability and achieving a perfect balance between performance and reliability.

[0042] Furthermore, the thickness ratio of the buffer layer 6 and the cover layer 7 can be flexibly adjusted according to the specific process node and device type requirements. For example, for high-frequency devices, the thickness of the FSG layer can be appropriately increased to further reduce parasitic capacitance; for high-voltage devices, the thickness of dense SiO2 can be appropriately increased to enhance isolation withstand voltage capability.

[0043] A method for preparing STI dielectric with optimized anti-narrow channel effect, the specific steps of which are as follows:

[0044] Step 1, as follows Figure 1 As shown, in the STI trench formed by etching, a SiO2 thin film is first grown on the surface of the silicon substrate as a liner oxide layer 5 through a rapid thermal processing process to remove defects and damage on the surface of the semiconductor substrate 1 caused by STI etching and to release the lattice stress generated during the etching process.

[0045] Step 2, as follows Figure 2As shown, a plasma-enhanced chemical vapor deposition (PECVD) process was used, with SiH4, SiF4, and O2 as the reactant gases, to deposit a layer of fluorine-doped SiO2 (FSG) as a buffer layer 6 on the pad oxide layer 5. FSG has advantages such as low elastic modulus, low thermal stress, low dielectric constant, and high fluidity, providing a basis for performance optimization in subsequent filling processes. For high-frequency devices, the thickness of the FSG layer can be appropriately increased to further reduce parasitic capacitance.

[0046] Step 3, as follows Figure 3 As shown, a dense SiO2 material is deposited on the buffer layer as a capping layer 7 via high-density plasma chemical vapor deposition (HDPD) or sub-atmospheric pressure chemical vapor deposition (SAPD). The dense SiO2 material provides good compactness and mechanical strength for the STI filling, avoids the adverse effects of water and oxygen on the underlying buffer layer 6 material, and ensures the long-term reliability of the isolation structure. For high-voltage devices, the thickness of the dense SiO2 can be appropriately increased to enhance the isolation withstand voltage capability.

[0047] Step 4, as follows Figure 4 As shown, the excess high-density insulating dielectric layer on the surface of silicon nitride 3 is removed by chemical mechanical polishing, so that the STI trench 4 is flush with the surface of the active region, exposing the active region and preparing for the subsequent gate process.

[0048] To illustrate the beneficial effects of this application, taking a logic chip at a 90nm process node as an example, firstly, an oxide layer 2 and a silicon nitride layer (SIN) 3 are sequentially formed on a semiconductor substrate 1 (Sub Si), and then an STI trench 4 is formed through photolithography and etching processes. Using pure SiO2 to fill the STI, the threshold voltage (Vt) of the narrow-channel NMOS device is measured as a function of the channel width (W).

[0049] Simultaneously, the optimized anti-narrow channel effect STI dielectric described in this application is used for filling. Specifically: First, a SiO2 film of approximately 10 nm thick is grown in the STI trench 4 and thermally annealed at 900 °C to form a padding oxide layer 5. Then, a FSG of approximately 200 nm thick is deposited using plasma-enhanced chemical vapor deposition (PECVD) to ensure uniform FSG coverage without voids, forming a buffer layer 6. Finally, a dense SiO2 layer of 300 nm thick is deposited using high-density plasma-enhanced chemical vapor deposition (PECVD) to form a capping layer 7, ensuring complete filling.

[0050] Tests revealed that the narrow-channel device filled with STI dielectric using the optimized anti-narrow-channel effect described in this application exhibited a reduction in threshold voltage fluctuation as the channel width decreased from 15% to less than 5%, essentially eliminating the anti-narrow-channel effect. Simultaneously, due to the introduction of the FSG buffer layer, the device's parasitic capacitance was reduced by approximately 8%, and the overall chip leakage current met specifications.

Claims

1. An optimized STI dielectric for anti-narrow channel effect, used to fill a shallow isolation trench between two active regions on the surface of a semiconductor substrate, characterized in that: Formed through a dielectric lamination process, including a padding oxide layer, a buffer layer, and a capping layer.

2. The STI dielectric with optimized anti-narrow channel effect as described in claim 1, characterized in that: The pad oxide layer is in direct contact with the semiconductor substrate, and the buffer layer is located between the pad oxide layer and the cover layer.

3. The STI dielectric with optimized anti-narrow channel effect as described in claim 1, characterized in that: The elastic modulus, thermal stress, and dielectric constant of the buffer layer material are lower than those of the cover layer.

4. An STI dielectric optimized for anti-narrow channel effect as described in claim 1 or 3, characterized in that: The material of the liner oxide layer is a SiO2 thin film, the material of the buffer layer is fluorine-doped SiO2, and the material of the cover layer is dense SiO2.

5. The STI dielectric with optimized anti-narrow channel effect as described in claim 4, characterized in that: The pad oxide layer is obtained by growing a SiO2 thin film on the surface of a silicon substrate through a rapid thermal processing process.

6. The STI dielectric with optimized anti-narrow channel effect as described in claim 4, characterized in that: The buffer layer was obtained by plasma-enhanced chemical vapor deposition of SiH4, SiF4 and O2 on the pad oxide layer.

7. The STI dielectric with optimized anti-narrow channel effect as described in claim 4, characterized in that: The capping layer is obtained by high-density plasma chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition of dense SiO2 material above the buffer layer.

8. The STI dielectric with optimized anti-narrow channel effect as described in claim 1, characterized in that: The height of the buffer layer is 30% to 50% of the STI height, and the height of the cover layer is 50% to 70% of the STI height.

9. An STI dielectric optimized for anti-narrow channel effect as described in claim 1 or 8, characterized in that: The deposition thickness of the buffer layer and the capping layer is adjusted according to the process node and device type. For high-frequency devices, the thickness of the buffer layer is increased to further reduce parasitic capacitance; for high-voltage devices, the thickness of the capping layer is increased to enhance isolation withstand voltage capability.

10. A method for preparing an STI dielectric with optimized anti-narrow channel effect, characterized in that: The specific steps are as follows: Step 1: In the STI trench formed by etching, a SiO2 thin film is grown on the surface of the silicon substrate as a pad oxide layer by a rapid thermal processing process. Step 2: A fluorine-doped SiO2 (FSG) layer is deposited on the liner oxide layer as a buffer layer using plasma-enhanced chemical vapor deposition (PECVD). The reaction gases are SiH4, SiF4, and O2. Step 3: Deposit a dense SiO2 material as a capping layer on the buffer layer using high-density plasma chemical vapor deposition or sub-atmospheric pressure chemical vapor deposition.

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