Packaging architecture and method of manufacturing the same

Abstract

A package architecture and a method of manufacturing the same are disclosed. The package architecture includes a first substrate, a first chip, at least a first thermal conductive element, a first mold encapsulation material, and a heat dissipation member. The first chip is disposed on the first substrate. The first thermal conductive element is disposed on the first substrate and adjacent to the first chip. The first mold encapsulation material is disposed on the first substrate and covers side surfaces of the first chip and side surfaces of the first thermal conductive element. The heat dissipation member is disposed on the first substrate, the first chip, the first thermal conductive element, and the first mold encapsulation material.

Description

Technical Field

[0001] This invention relates to a packaging architecture and its manufacturing method, and particularly to a packaging architecture that improves the heat dissipation performance of a chip. Background Technology

[0002] As the semiconductor industry advances, chips are operating faster and faster, generating more and more heat. However, as the temperature rises, the chip's performance deteriorates.

[0003] Therefore, the semiconductor industry needs packaging architectures that improve chip heat dissipation efficiency. Such packaging architectures can quickly dissipate the heat generated by the chip to maintain its operation. Summary of the Invention

[0004] One objective of this invention is to propose a packaging architecture that can improve chip heat dissipation efficiency.

[0005] One embodiment of the present invention provides a packaging architecture comprising a first substrate, a first chip, at least one first thermally conductive element (heat spreader), a first molding compound, and a heat sink. The first chip is disposed on the first substrate. The first thermally conductive element is disposed on the first substrate and adjacent to the first chip. The first molding compound is disposed on the first substrate and covers the side surfaces of the first chip and the first thermally conductive element. The heat sink is disposed on the first substrate, the first chip, the first thermally conductive element, and the first molding compound.

[0006] Another embodiment of the present invention provides a method for manufacturing a packaging architecture, comprising preparing a first package and disposing of a heat sink on the first package. Preparing the first package includes the following steps: disposing of a first chip on a first substrate; disposing of at least one first thermally conductive element on the first substrate, the at least one first thermally conductive element being disposed adjacent to the first chip; and disposing of a first molding compound on the first substrate, the first molding compound covering the side surface of the first chip and the side surface of the at least one first thermally conductive element.

[0007] According to a packaging architecture of an embodiment of the present invention, the heat generated by the first chip can be conducted to the first substrate via the first thermally conductive element, and further conducted to the heat sink via the first thermally conductive element. The first substrate and the heat sink can further dissipate the heat into the atmosphere, thereby rapidly removing the heat generated by the first chip to maintain the operation of the first chip.

[0008] The above description of the content of this invention and the following description of the embodiments are intended to demonstrate and explain the spirit and principles of this invention, and to provide a further explanation of the scope of this patent application. Attached Figure Description

[0009] Figure 1This is a side cross-sectional view of a packaging architecture according to an embodiment of the present invention;

[0010] Figure 2 yes Figure 1 A top-view cross-sectional diagram of the packaging architecture in the diagram;

[0011] Figure 3 and Figure 4 yes Figure 1 A side cross-sectional view of the manufacturing process of the packaging architecture, wherein... Figures 3A to 3C This is a schematic diagram of a process of setting multiple first heat-conducting elements and multiple coaxial conductive vias on a first substrate.

[0012] Figure 5 This is a side cross-sectional view of a packaging architecture according to another embodiment of the present invention;

[0013] Figure 6 yes Figure 5 A top-view cross-sectional diagram of the packaging architecture in the diagram;

[0014] Figures 6A to 6C This is a schematic diagram of a process of setting multiple first heat-conducting elements and multiple coaxial conductive vias on a first substrate.

[0015] Figure 7 This is a side cross-sectional view of a packaging architecture according to another embodiment of the present invention;

[0016] Figure 8 yes Figure 7 A top-view cross-sectional diagram of the packaging architecture in the diagram;

[0017] Figure 9 yes Figure 7 A side cross-sectional view of the manufacturing process of the packaging architecture;

[0018] Figures 9A to 9C This is a schematic diagram of a process in which multiple third heat-conducting elements are disposed on the upper surface of a second substrate;

[0019] Figure 10 This is a side cross-sectional view of a packaging architecture according to another embodiment of the present invention;

[0020] Figure 11 yes Figure 10 A top-view cross-sectional diagram of the packaging architecture in the diagram;

[0021] Figures 11A to 11C This is a schematic diagram of a process of setting multiple third heat-conducting elements on a second substrate;

[0022] Figure 12 This is a side cross-sectional view of a packaging architecture according to another embodiment of the present invention;

[0023] Figures 13 to 16 yes Figure 12 A side cross-sectional view of the manufacturing process of the packaging architecture, wherein... Figures 13A to 13C This is a schematic diagram of a process in which multiple third heat-conducting elements are disposed on a second substrate;

[0024] Figure 17 This is a side cross-sectional view of a packaging architecture according to another embodiment of the present invention;

[0025] Figure 18 This is a side cross-sectional view of a packaging architecture according to another embodiment of the present invention.

[0026] Symbol Explanation

[0027] 1: Packaging Architecture

[0028] 1a: First package

[0029] 11: First substrate

[0030] 12: First Chip

[0031] 120: Side surface

[0032] 13: First heat-conducting element

[0033] 131: Signal Conductive Through Hole

[0034] 132: Grounding component

[0035] 14: First mold sealing material

[0036] 15: Second heat-conducting element

[0037] 16: Thermal paste

[0038] 17: Heat sink

[0039] 18: Circuit board

[0040] 19: Coaxial conductive via

[0041] 2: Packaging Architecture

[0042] 23: First heat-conducting element

[0043] 24: First mold sealing material

[0044] 25: Second heat-conducting element

[0045] 26: Thermal paste

[0046] 3: Packaging Architecture

[0047] 3a: Second package

[0048] 31: Second substrate

[0049] 310: Conductive via

[0050] 311: Lower surface

[0051] 312: Upper surface

[0052] 32: Second chip

[0053] 320: Side surface

[0054] 33: Third heat-conducting element

[0055] 331: Signal Conductive Through Hole

[0056] 332: Grounding component

[0057] 34: Second mold sealing material

[0058] 35: Fourth heat-conducting element

[0059] 36: Thermal paste

[0060] 37: Heat sink

[0061] 4: Packaging Architecture

[0062] 41: Second substrate

[0063] 410: Conductive via

[0064] 43: Third heat-conducting element

[0065] 44: Second mold sealing material

[0066] 45: Fourth heat-conducting element

[0067] 46: Thermal paste

[0068] 47: Heat sink

[0069] 5: Packaging Architecture

[0070] 5a: Second package

[0071] 51: Second substrate

[0072] 510: Conductive via

[0073] 511: Lower surface

[0074] 512: Upper surface

[0075] 52: Second chip

[0076] 53: Third heat-conducting element

[0077] 54: Second mold sealing material

[0078] 55: Fourth heat-conducting element

[0079] 56: Thermal paste

[0080] 57: Heat sink

[0081] 58: Second heat-conducting element

[0082] 59: Metal sintered epoxy resin layer

[0083] 6: Packaging Architecture

[0084] 6a: First package

[0085] 61: First substrate

[0086] 62: First Chip

[0087] 620: Side surface

[0088] 63: First heat-conducting element

[0089] 64: First mold sealing material

[0090] 661, 662: Thermal paste

[0091] 67: Heat sink

[0092] 68: Circuit board

[0093] 69: Antenna layer

[0094] 7: Packaging Architecture

[0095] 7a: First Package

[0096] 73: First heat-conducting element

[0097] 74: First mold sealing material

[0098] 90: Mold

[0099] 91: Release film

[0100] C: Capacitor

[0101] R: Resistor Detailed Implementation

[0102] The following embodiments describe in detail the features and advantages of the present invention, the content of which is sufficient to enable any person skilled in the art to understand the technical content of the embodiments of the present invention and to implement them accordingly. Based on the disclosure, claims, and drawings in this specification, any person skilled in the art can easily understand the related objects and advantages of the present invention. The following embodiments further illustrate the content of the present invention in detail, but are not intended to limit the scope of the present invention in any way.

[0103] In the so-called schematic diagrams of this specification, dimensions, proportions, and angles may be exaggerated for illustrative purposes, but are not intended to limit the invention. Various modifications are possible without departing from the spirit of the invention. The up, down, front, and back orientations mentioned in the description of the embodiments and drawings are for illustrative purposes and are not intended to limit the invention.

[0104] Please refer to Figure 1 and Figure 2 . Figure 1 A side cross-sectional view of a packaging architecture according to an embodiment of the present invention is shown. Figure 2 Draw Figure 1 A top-view cross-sectional diagram of the packaging architecture. Figure 1 It is along Figure 2 A side view of the B-B line section. Figure 2 It is along Figure 1 A top-view cross-sectional view of the A-A line. The packaging architecture 1 includes a first substrate 11, a first chip 12, multiple first thermally conductive elements 13, a first molding compound 14, a second thermally conductive element 15, thermal paste 16, a heat sink 17, and a circuit board 18. The packaging architecture 1 may also include multiple coaxial conductive vias 19.

[0105] like Figure 1 and Figure 2 As shown, a first chip 12 is disposed on a first substrate 11. The first chip 12 can be electrically connected and fixed to the first substrate 11 via a flip-chip method. The first substrate 11 can be a fan-out circuit board. A first thermally conductive element 13 is disposed on the first substrate 11, surrounding and adjacent to the first chip 12. The first thermally conductive element 13 is a coaxial conductive via, including a signal conductive via 131 and a grounding element 132. The signal conductive via 131 is a columnar conductive material, and the grounding element 132 is a tubular conductive material. The signal conductive via 131 and the grounding element 132 are coaxially arranged, and the grounding element 132 surrounds the signal conductive via 131. Multiple first thermally conductive elements 13 are arranged to surround and be adjacent to the first chip 12, and are in thermal contact with the first chip 12. Thermal contact means that heat energy can be transferred between the two; they can be in direct contact or separated by a very small distance without direct contact. The first thermally conductive element 13 can be separated from the first chip 12 by a very small distance without direct contact. Alternatively, the packaging architecture 1 may also include an optional plurality of coaxial conductive vias 19 disposed on the first substrate 11 surrounding and adjacent to the first thermally conductive element 13, but is not limited thereto. In other embodiments, the coaxial conductive vias 19 may be omitted. In other embodiments, the first thermally conductive element 13 may also be in direct contact with the first chip 12 without affecting the operation of the first chip 12.

[0106] like Figure 1 As shown, in this embodiment, a first molding compound 14 is disposed on a first substrate 11 and covers the side surface of the first chip 12, the side surface of the first thermally conductive element 13, and the side surface of the coaxial conductive via 19. The first thermally conductive element 13 and the coaxial conductive via 19 respectively penetrate the first molding compound 14. A second thermally conductive element 15 is disposed on the first chip 12, the first thermally conductive element 13, and the first molding compound 14. The first chip 12 is located between the second thermally conductive element 15 and the first substrate 11. The second thermally conductive element 15 is in thermal contact with the first chip 12 and also in thermal contact with the first thermally conductive element 13. In this embodiment, the second thermally conductive element 15 is in direct contact with the first chip 12, the second thermally conductive element 15 is directly connected to the grounding member 132 of the first thermally conductive element 13, and the second thermally conductive element 15 may not be connected to the coaxial conductive via 19.

[0107] Thermal paste 16 is disposed on the first thermally conductive element 13, the first molding material 14, the second thermally conductive element 15, and the coaxial conductive via 19. A heat sink 17 is disposed on the thermal paste 16. Thus, the heat sink 17 is located on the first substrate 11, the first chip 12, the first thermally conductive element 13, the first molding material 14, and the second thermally conductive element 15. The second thermally conductive element 15 is located between the heat sink 17 and the first chip 12. The thermal paste 16 is located between the heat sink 17 and the first molding material 14, and between the heat sink 17 and the second thermally conductive element 15. A circuit board 18 is disposed on and electrically connected to the first substrate 11. The first substrate 11 is located between the first chip 12 and the circuit board 18.

[0108] Therefore, the heat generated by the first chip 12 can be conducted to the first substrate 11 and then to the circuit board 18 via the first thermal conductive element 13, and can also be conducted to the thermal paste 16 and then to the heat sink 17 via the first thermal conductive element 13 and the second thermal conductive element 15. The circuit board 18 and the heat sink 17 further dissipate the heat into the atmosphere, thereby quickly removing the heat generated by the first chip 12 to maintain the operation of the first chip 12.

[0109] The following is for reference Figure 3 , Figure 4 and Figure 1 ,illustrate Figure 1 The manufacturing process of the packaging architecture 1 shown is described. Figure 3 and Figure 4 Draw Figure 1 A side cross-sectional view of the manufacturing process of the packaging architecture.

[0110] like Figure 3 and Figure 4 As shown, prepare a first package 1a. (As indicated) Figure 3As shown, a first chip 12 is disposed on a first substrate 11, and a plurality of first thermally conductive elements 13 and a plurality of coaxial conductive vias 19 are disposed on the first substrate 11, the order of which is not fixed. The first thermally conductive elements 13 are disposed around and adjacent to the first chip 12. The plurality of coaxial conductive vias 19 are disposed around and adjacent to the first thermally conductive elements 13. In this embodiment, the first chip 12 can be electrically connected and fixed on the first substrate 11 by flip-chip bonding, and the first thermally conductive elements 13 and coaxial conductive vias 19 can be formed on the first substrate 11 by printing.

[0111] In another embodiment, Figures 3A to 3C The process of depicting a plurality of first thermally conductive elements 13 and a plurality of coaxial conductive vias 19 disposed on a first substrate 11 may include the following steps. For example... Figure 3A As shown, a release film 91 is formed on a mold 90, and a plurality of first heat-conducting elements 13 and a plurality of coaxial conductive vias 19, arranged in an upside-down manner, are formed on the release film 91. A first chip 12 is also formed on a first substrate 11. Figure 3B As shown, the mold 90 is flipped up and down to attach the first heat-conducting element 13 and the coaxial conductive through-hole 19 onto the first substrate 11 (transfer printing). Figure 3C As shown, the release film 91 is decomposed to detach the first thermally conductive element 13 and the coaxial conductive through hole 19 from the mold 90. The material of the release film 91 may be formed of hydrolyzed adhesive, but is not limited to this, and may also be replaced by a method that can temporarily fix the first thermally conductive element 13 and the coaxial conductive through hole 19 to the mold 90.

[0112] like Figure 4 As shown, a first molding compound 14 is disposed on a first substrate 11, and the first molding compound 14 covers the side surface of the first chip 12, the side surface of the first thermally conductive element 13, and the side surface of the coaxial conductive via 19. The first thermally conductive element 13 and the coaxial conductive via 19 respectively penetrate the first molding compound 14. Thus, the preparation of the first package 1a is completed.

[0113] In this embodiment, the first thermally conductive element 13 and the coaxial conductive via 19 can be formed first, followed by the formation of the first molding compound 14, but this is not a limitation. In other embodiments, the first molding compound 14 covering the side surface of the first chip 12 can be formed first, followed by the formation of multiple through holes in the first molding compound 14, and then the formation of the first thermally conductive element 13 and the coaxial conductive via 19 within the multiple through holes. However, the process of this embodiment is simpler than that of other embodiments.

[0114] like Figure 1As shown, a second thermally conductive element 15 is disposed on the first package 1a to thermally contact the first chip 12 and the first thermally conductive element 13. The first chip 12 is located between the second thermally conductive element 15 and the first substrate 11. Thermal paste 16 is disposed on the first molding material 14 and the second thermally conductive element 15 of the first package 1a. A heat sink 17 is disposed on the first package 1a and the thermal paste 16. The thermal paste 16 is located between the heat sink 17 and the first molding material 14 and between the heat sink 17 and the second thermally conductive element 15. The first package 1a is disposed on a circuit board 18, and the first substrate 11 is located between the first chip 12 and the circuit board 18. Thus, the manufacturing of the package architecture 1 is completed.

[0115] Please refer to Figure 5 and Figure 6 . Figure 5 A side cross-sectional view of a packaging architecture according to another embodiment of the present invention is shown. Figure 6 Draw Figure 5 A top-view cross-sectional diagram of the packaging architecture. Figure 5 It is along Figure 6 A side view of the D-D line section. Figure 6 It is along Figure 5 A top-view cross-sectional view of the C-C line. The package architecture 2 includes a first substrate 11, a first chip 12, a plurality of first thermally conductive elements 13, a plurality of first thermally conductive elements 23, a first molding compound 24, a second thermally conductive element 25, a thermal paste 26, a heat sink 17, and a circuit board 18. The package architecture 2 may also include a plurality of coaxial conductive vias 19.

[0116] like Figure 5 and Figure 6 As shown, a first chip 12 is disposed on a first substrate 11. First thermally conductive elements 13 and 23 are disposed on the first substrate 11, surrounding and adjacent to the first chip 12. The first substrate 11 may be a fan-out circuit board. The first thermally conductive element 13 is a coaxial conductive via. A plurality of first thermally conductive elements 13 are arranged to surround and be adjacent to the first chip 12, and are in thermal contact with the first chip 12. The first thermally conductive element 23 is a wall (which can be used to supply power voltage). A plurality of first thermally conductive elements 23 are arranged to surround and be adjacent to the first chip 12, and are in thermal contact with the first chip 12. Each first thermally conductive element 23 extends in a direction substantially perpendicular to the side surface 120 of the first chip 12. Figure 6 As shown, the side surface 120 includes a portion parallel to the XZ plane and a portion parallel to the YX plane. A plurality of first heat-conducting elements 23, near the portion parallel to the XZ plane, extend along the YZ plane. A plurality of first heat-conducting elements 23, near the portion parallel to the YZ plane, extend along the XZ plane. Figure 5 and Figure 6As shown, the first thermally conductive element 13 and the first thermally conductive element 23 may be spaced a very small distance from the first chip 12 without directly contacting the first chip 12, but this is not a limitation. In other embodiments, the first thermally conductive element 13 and / or the first thermally conductive element 23 may also directly contact the first chip 12 without affecting its operation.

[0117] In this embodiment, a first molding compound 24 is disposed on a first substrate 11 and covers the side surface 120 of the first chip 12, the side surface of the first thermally conductive element 13, the side surface of the first thermally conductive element 23, and the side surface of the coaxial conductive via 19. The first thermally conductive element 13, the first thermally conductive element 23, and the coaxial conductive via 19 respectively penetrate the first molding compound 24. A second thermally conductive element 25 is disposed on the first chip 12, the first thermally conductive element 13, the first thermally conductive element 23, and the first molding compound 24. The first chip 12 is located between the second thermally conductive element 25 and the first substrate 11. The second thermally conductive element 25 is in thermal contact with the first chip 12, and also in thermal contact with the first thermally conductive elements 13 and 23. In this embodiment, the second thermally conductive element 15 is in direct contact with the first chip 12, and is directly connected to the first thermally conductive elements 13 and 23, and may not be connected to the coaxial conductive via 19.

[0118] Thermal paste 26 is disposed on the first thermally conductive element 13, the first thermally conductive element 23, the first molding material 24, the second thermally conductive element 15, and the coaxial conductive via 19. A heat sink 17 is disposed on the thermal paste 26. Thus, the heat sink 17 is located on the first substrate 11, the first chip 12, the first thermally conductive element 13, the first thermally conductive element 23, the first molding material 24, and the second thermally conductive element 25. The second thermally conductive element 25 is located between the heat sink 17 and the first chip 12. The thermal paste 26 is located between the heat sink 17 and the first molding material 24, and between the heat sink 17 and the second thermally conductive element 25. A circuit board 18 is disposed on and electrically connected to the first substrate 11. The first substrate 11 is located between the first chip 12 and the circuit board 18.

[0119] Therefore, the heat generated by the first chip 12 can be conducted to the first substrate 11 and then to the circuit board 18 via the first thermal conductive element 13 and the first thermal conductive element 23, and can also be conducted to the thermal paste 26 and then to the heat sink 17 via the first thermal conductive element 13, the first thermal conductive element 23 and the second thermal conductive element 25. The circuit board 18 and the heat sink 17 further dissipate the heat into the atmosphere, thereby quickly removing the heat generated by the first chip 12 to maintain the operation of the first chip 12.

[0120] The manufacturing process of package architecture 2 is similar to that of package architecture 1, except that the first thermal conductive element 23 is formed simultaneously with the formation of the first thermal conductive element 13 and the coaxial conductive via 19. The first thermal conductive element 23 can also be formed on the first substrate 11 by printing.

[0121] In another embodiment, Figures 6A to 6C The process of configuring a plurality of first thermally conductive elements 13, a plurality of first thermally conductive elements 23, and a plurality of coaxial conductive vias 19 on a first substrate 11 may include the following steps. For example... Figure 6A As shown, a release film 91 is formed on a mold 90, and a plurality of first thermally conductive elements 13, a plurality of first thermally conductive elements 23, and a plurality of coaxial conductive vias 19, arranged in an upside-down manner, are formed on the release film 91. A first chip 12 is also formed on a first substrate 11. Figure 6B As shown, the mold 90 is flipped up and down, and the first heat-conducting element 13, the first heat-conducting element 23, and the coaxial conductive through-hole 19 are attached to the first substrate 11 (transfer). Figure 6C As shown, the release film 91 is decomposed to detach the first thermally conductive element 13, the first thermally conductive element 23, and the coaxial conductive through hole 19 from the mold 90. The material of the release film 91 may be formed of hydrolyzed adhesive, but is not limited thereto, and may also be replaced by a method that can temporarily fix the first thermally conductive element 13, the first thermally conductive element 23, and the coaxial conductive through hole 19 to the mold 90.

[0122] Alternatively, the packaging architecture 2 may also include an optional plurality of coaxial conductive vias 19 disposed on the first substrate 11 surrounding and adjacent to the first thermally conductive element 13, but is not limited thereto. In other embodiments, the coaxial conductive vias 19 may be omitted.

[0123] Please refer to Figure 7 and Figure 8 . Figure 7 A side cross-sectional view of a packaging architecture according to another embodiment of the present invention is shown. Figure 8 Draw Figure 1 A top-view cross-sectional diagram of the packaging architecture. Figure 7 It is along Figure 8 A side view of the J-J line section. Figure 8 It is along Figure 7 A top view of the cross-section along line E-E. Additionally, along... Figure 7 A top view of the F-F line section, and... Figure 2 Similar and for reference Figure 2In this embodiment, the packaging architecture 3 includes a first substrate 11, a first chip 12, multiple first thermally conductive elements 13, a first molding compound 14, a second thermally conductive element 15, a second substrate 31, a second chip 32, multiple third thermally conductive elements 33, a second molding compound 34, a fourth thermally conductive element 35, a thermal paste 36, a heat sink 37, and a circuit board 18. The packaging architecture 3 may also include multiple coaxial conductive vias 19.

[0124] like Figure 7 and Figure 8 As shown, a first chip 12 is disposed on a first substrate 11. The first substrate 11 may be a fan-out circuit board. A first thermally conductive element 13 is disposed on the first substrate 11. A plurality of first thermally conductive elements 13 are arranged to surround and be adjacent to the first chip 12, and are in thermal contact with the first chip 12. The first thermally conductive elements 13 may be spaced a very small distance from the first chip 12 without directly contacting the first chip 12. In addition, the package architecture 3 may also include an optional plurality of coaxial conductive vias 19 disposed on the first substrate 11 surrounding and adjacent to the first thermally conductive elements 13, but is not limited thereto. In other embodiments, the coaxial conductive vias 19 may be omitted. In other embodiments, the first thermally conductive elements 13 may also be in direct contact with the first chip 12 without affecting the operation of the first chip 12.

[0125] like Figure 7 As shown, in this embodiment, a first molding compound 14 is disposed on a first substrate 11 and covers the side surface of the first chip 12, the side surface of the first thermally conductive element 13, and the side surface of the coaxial conductive via 19. The first thermally conductive element 13 and the coaxial conductive via 19 respectively penetrate the first molding compound 14. A second thermally conductive element 15 is disposed on the first chip 12, the first thermally conductive element 13, and the first molding compound 14. The first chip 12 is located between the second thermally conductive element 15 and the first substrate 11. The second thermally conductive element 15 is in thermal contact with the first chip 12 and with the first thermally conductive element 13. In this embodiment, the second thermally conductive element 15 is in direct contact with the first chip 12, the second thermally conductive element 15 is directly connected to the grounding member 132 of the first thermally conductive element 13, and the second thermally conductive element 15 may not be connected to the coaxial conductive via 19.

[0126] A second substrate 31 is disposed on the first thermally conductive element 13, the first molding material 14, the second thermally conductive element 15, and the coaxial conductive via 19. A second chip 32 is disposed on the second substrate 31. The second substrate 31 may be a fan-out circuit board. The second chip 32 can be electrically connected and fixed to the second substrate 31 by flip-chip method. The second substrate 31 may be a fan-out circuit board. A third thermally conductive element 33 is disposed on the second substrate 31, surrounding and adjacent to the second chip 32. The second substrate 31 includes a conductive via 310. The conductive via 310 connects the first thermally conductive element 13 and the third thermally conductive element 33. The first thermally conductive element 13 and the third thermally conductive element 33 are substantially aligned in the vertical direction (Z direction). The third thermally conductive element 33 is a coaxial conductive via, including a signal conductive via 331 and a grounding element 332. The signal conductive via 331 is a columnar conductive material, and the grounding element 332 is a tubular conductive material. The signal conductive via 331 and the grounding element 332 are coaxially arranged, with the grounding element 332 surrounding the signal conductive via 331. Multiple third thermally conductive elements 33 are arranged around and adjacent to the second chip 32, and are in thermal contact with the second chip 32. The third thermally conductive elements 33 may be spaced a very small distance from the second chip 32 without direct contact, but this is not a limitation. In other embodiments, the third thermally conductive elements 33 may also be in direct contact with the second chip 32 without affecting its operation.

[0127] In this embodiment, the second molding material 34 is disposed on the second substrate 31 and covers the side surface of the second chip 32 and the side surface of the third thermally conductive element 33. The third thermally conductive element 33 penetrates the second molding material 34. The fourth thermally conductive element 35 is disposed on the second chip 32, the third thermally conductive element 33, and the second molding material 34. The second chip 32 is located between the fourth thermally conductive element 35 and the second substrate 31. The fourth thermally conductive element 35 is in thermal contact with the second chip 32 and also in thermal contact with the third thermally conductive element 33. In this embodiment, the fourth thermally conductive element 35 is in direct contact with the second chip 32, and the fourth thermally conductive element 35 is directly connected to the grounding member 332 of the third thermally conductive element 33.

[0128] Thermal paste 36 is disposed on the third thermally conductive element 33, the second molding material 34, and the fourth thermally conductive element 35. A heat sink 37 is disposed on the thermal paste 36. Thus, the heat sink 37 is located on the second substrate 31, the second chip 32, the third thermally conductive element 33, the second molding material 34, and the fourth thermally conductive element 35. The fourth thermally conductive element 35 is located between the heat sink 37 and the second chip 32. The thermal paste 36 is located between the heat sink 37 and the second molding material 34, and between the heat sink 37 and the fourth thermally conductive element 35. The second chip 32 and the second molding material 34 are located between the second substrate 31 and the heat sink 37. A circuit board 18 is disposed on and electrically connected to the first substrate 11. The first substrate 11 is located between the first chip 12 and the circuit board 18.

[0129] Therefore, the heat generated by the first chip 12 can be conducted through the first thermally conductive element 13 to the first substrate 11 and then to the circuit board 18. It can also be conducted through the first thermally conductive element 13 and the second thermally conductive element 15 to the conductive vias 310 of the second substrate 31, and then to the third thermally conductive element 33, the fourth thermally conductive element 35, the thermal paste 36, and the heat sink 37. The heat generated by the second chip 32 can be conducted through the third thermally conductive element 33 and the fourth thermally conductive element 35 to the thermal paste 36 and then to the heat sink 37. It can also be conducted through the third thermally conductive element 33 to the conductive vias 310 of the second substrate 31, and then to the first thermally conductive element 13, the first substrate 11, and the circuit board 18. According to the second law of thermodynamics, heat is transferred from high temperature to low temperature. The circuit board 18 and the heat sink 37 further dissipate the heat into the atmosphere, thereby rapidly removing the heat generated by the first chip 12 and the second chip 32 to maintain their operation.

[0130] The following is for reference Figure 3 , Figure 4 , Figure 9 and Figure 7 ,illustrate Figure 7 The manufacturing process of the packaging architecture 3 shown is described. Figure 9 Draw Figure 7 A side cross-sectional view of the manufacturing process of the packaging architecture.

[0131] like Figure 3 and Figure 4 As shown, prepare a first package 1a. (As indicated) Figure 3As shown, a first chip 12 is disposed on a first substrate 11, and a plurality of first thermally conductive elements 13 and a plurality of coaxial conductive vias 19 are disposed on the first substrate 11, the order of which is not fixed. The first thermally conductive elements 13 are disposed around and adjacent to the first chip 12. The plurality of coaxial conductive vias 19 are disposed around and adjacent to the first thermally conductive elements 13. In this embodiment, the first chip 12 can be electrically connected and fixed on the first substrate 11 by flip-chip bonding, and the first thermally conductive elements 13 and coaxial conductive vias 19 can be formed on the first substrate 11 by printing.

[0132] In another embodiment, Figures 3A to 3C The process of depicting a plurality of first thermally conductive elements 13 and a plurality of coaxial conductive vias 19 disposed on a first substrate 11 may include the following steps. For example... Figure 3A As shown, a release film 91 is formed on a mold 90, and a plurality of first heat-conducting elements 13 and a plurality of coaxial conductive vias 19, arranged in an upside-down manner, are formed on the release film 91. A first chip 12 is also formed on a first substrate 11. Figure 3B As shown, the mold 90 is flipped up and down to attach the first heat-conducting element 13 and the coaxial conductive through-hole 19 onto the first substrate 11 (transfer printing). Figure 3C As shown, the release film 91 is decomposed to detach the first thermally conductive element 13 and the coaxial conductive through hole 19 from the mold 90. The material of the release film 91 may be formed of hydrolyzed adhesive, but is not limited to this, and may also be replaced by a method that can temporarily fix the first thermally conductive element 13 and the coaxial conductive through hole 19 to the mold 90.

[0133] like Figure 4 As shown, a first molding compound 14 is disposed on a first substrate 11, and the first molding compound 14 covers the side surface of the first chip 12, the side surface of the first thermally conductive element 13, and the side surface of the coaxial conductive via 19. The first thermally conductive element 13 and the coaxial conductive via 19 respectively penetrate the first molding compound 14. Thus, the preparation of the first package 1a is completed.

[0134] like Figure 9As shown, a second package 3a is prepared and disposed on a first package 1a. Specifically, a second thermally conductive element 15 is disposed on the first package 1a to thermally contact the first chip 12 and the first thermally conductive element 13. The first chip 12 is located between the second thermally conductive element 15 and the first substrate 11. A second substrate 31 is disposed on the first molding material 14 of the first package 1a and the second thermally conductive element 15. Thus, the second thermally conductive element 15 is disposed on a lower surface 311 of the second substrate 31. A second chip 32 is disposed on an upper surface 312 of the second substrate 31. A plurality of third thermally conductive elements 33 are disposed on the upper surface 312 of the second substrate 31. The third thermally conductive elements 33 are arranged to surround and be adjacent to the second chip 32. In this embodiment, the second chip 32 can be electrically connected and fixed to the upper surface 312 of the second substrate 31 by flip-chip bonding, and the third thermally conductive elements 33 can be formed on the upper surface 312 of the second substrate 31 by printing.

[0135] In another embodiment, Figures 9A to 9C The process of depicting a plurality of third heat-conducting elements 33 disposed on a second substrate 31 may include the following steps. For example... Figure 9A As shown, a release film 91 is formed on a mold 90, and a plurality of third heat-conducting elements 33, arranged in an upside-down manner, are formed on the release film 91. A second chip 32 is formed on a second substrate 31. Figure 9B As shown, the mold 90 is flipped up and down to attach the third heat-conducting element 33 onto the second substrate 31 (transfer). Figure 9C As shown, the release film 91 is decomposed to detach the third heat-conducting element 33 from the mold 90. The material of the release film 91 may be formed of hydrolyzed adhesive, but is not limited to this, and may also be replaced by a method that can temporarily fix the third heat-conducting element 33 to the mold 90.

[0136] A second molding compound 34 is disposed on the upper surface 312 of the second substrate 31. The second molding compound 34 covers the side surface of the second chip 32 and the side surface of the third thermally conductive element 33. The third thermally conductive element 33 penetrates the second molding compound 34. The third thermally conductive element 33 is in thermal contact with the second substrate 31 and the second chip 32. The second package 3a includes the second thermally conductive element 15, the second substrate 31, the second chip 32, the third thermally conductive element 33, and the second molding compound 34. Thus, the preparation of the second package 3a is completed, and the second package 3a is simultaneously disposed on the first package 1a.

[0137] like Figure 7As shown, a fourth thermally conductive element 35 is disposed on the second chip 32, the third thermally conductive element 33, and the second molding material 34 of the second package 3a, to provide thermal contact with the second chip 32 and the third thermally conductive element 33. The second chip 32 is located between the fourth thermally conductive element 35 and the second substrate 31. Thermal paste 36 is disposed on the third thermally conductive element 33 and the second molding material 34, and on the fourth thermally conductive element 35 of the second package 3a. A heat sink 37 is disposed on the second package 3a and the thermal paste 36. The second package 3a is located between the first package 1a and the heat sink 37. The thermal paste 36 is located between the heat sink 37 and the second molding material 34, and between the heat sink 37 and the fourth thermally conductive element 35. The first package 1a is disposed on the circuit board 18, and the first substrate 11 is located between the first chip 12 and the circuit board 18. Thus, the manufacturing of the package architecture 3 is completed.

[0138] Please refer to Figure 10 and Figure 11 . Figure 10 A side cross-sectional view of a packaging architecture according to another embodiment of the present invention is shown. Figure 11 Draw Figure 10 A top-view cross-sectional diagram of the packaging architecture. Figure 10 It is along Figure 11 A side view of the P-P line section. Figure 11 It is along Figure 10 A top-view cross-section diagram of the K-K line. Additionally, along... Figure 10 A top view of the M-M line profile, and... Figure 6 Similar and for reference Figure 6 .

[0139] In this embodiment, the packaging architecture 4 includes a first substrate 11, a first chip 12, a plurality of first thermally conductive elements 13, a plurality of first thermally conductive elements 23, a first molding compound 24, a second thermally conductive element 25, a second substrate 41, a second chip 32, a plurality of third thermally conductive elements 33, a plurality of third thermally conductive elements 43, a second molding compound 44, a fourth thermally conductive element 45, a thermal paste 46, a heat sink 47, and a circuit board 18. The packaging architecture 4 may further include a plurality of coaxial conductive vias 19.

[0140] like Figure 10 and Figure 11As shown, a first chip 12 is disposed on a first substrate 11. The first substrate 11 may be a fan-out circuit board. First thermally conductive elements 13 and 23 are disposed on the first substrate 11, surrounding and adjacent to the first chip 12. The first thermally conductive element 13 is a coaxial conductive via. A plurality of first thermally conductive elements 13 are arranged to surround and be adjacent to the first chip 12, and are in thermal contact with the first chip 12. The first thermally conductive element 23 is a wall (which can be used to supply power voltage). A plurality of first thermally conductive elements 23 are arranged to surround and be adjacent to the first chip 12, and are in thermal contact with the first chip 12. Each first thermally conductive element 23 extends in a direction substantially perpendicular to the side surface 120 of the first chip 12 (see reference). Figure 6 ).

[0141] A first molding compound 24 is disposed on a first substrate 11 and covers the side surface 120 of the first chip 12, the side surface of the first thermally conductive element 13, the side surface of the first thermally conductive element 23, and the side surface of the coaxial conductive via 19. The first thermally conductive element 13, the first thermally conductive element 23, and the coaxial conductive via 19 respectively penetrate the first molding compound 24. A second thermally conductive element 25 is disposed on the first chip 12, the first thermally conductive element 13, the first thermally conductive element 23, and the first molding compound 24. The first chip 12 is located between the second thermally conductive element 25 and the first substrate 11. The second thermally conductive element 25 is in thermal contact with the first chip 12, and also in thermal contact with the first thermally conductive elements 13 and 23. In this embodiment, the second thermally conductive element 15 is in direct contact with the first chip 12, directly connected to the first thermally conductive elements 13 and 23, and may not be connected to the coaxial conductive via 19.

[0142] A second substrate 41 is disposed on the first thermally conductive element 13, the first thermally conductive element 23, the first molding material 14, the second thermally conductive element 15, and the coaxial conductive via 19. A second chip 32 is disposed on the second substrate 41. The second substrate 41 may be a fan-out circuit board. The second chip 32 can be electrically connected and fixed to the second substrate 41 by flip-chip bonding. A third thermally conductive element 33 and a third thermally conductive element 43 are disposed on the second substrate 41, surrounding and adjacent to the second chip 32. The second substrate 41 includes a conductive via 410. The conductive via 410 connects the first thermally conductive element 13 and the third thermally conductive element 33, and also connects the first thermally conductive element 13 and the third thermally conductive element 43. The first thermally conductive element 13 and the third thermally conductive element 33 are substantially aligned in the vertical direction (Z direction). The third thermally conductive element 33 is a coaxial conductive via. A plurality of first thermally conductive elements 33 are arranged to surround and be adjacent to the second chip 32, and are in thermal contact with the second chip 32. The third thermally conductive element 43 is a wall (which can be used to supply power voltage). A plurality of third thermally conductive elements 43 are arranged to surround and be adjacent to the second chip 32 and to be in thermal contact with the second chip 32. Each third thermally conductive element 43 extends in a direction substantially perpendicular to the side surface 320 of the second chip 32.

[0143] like Figure 11 As shown, the side surface 320 includes a portion parallel to the XZ plane and a portion parallel to the YX plane. A plurality of third heat-conducting elements 43, near the portion parallel to the XZ plane, extend along the YZ plane. A plurality of third heat-conducting elements 43, near the portion parallel to the YZ plane, extend along the XZ plane. Figure 10 and Figure 11 As shown, the third thermally conductive element 33 and the third thermally conductive element 43 respectively penetrate the second molding material 44. The third thermally conductive element 33 and the third thermally conductive element 43 may be spaced a very small distance from the second chip 32 without directly contacting the second chip 32, but this is not a limitation. In other embodiments, the third thermally conductive element 33 and / or the third thermally conductive element 43 may also directly contact the second chip 32 without affecting the operation of the second chip 32.

[0144] In this embodiment, the second molding compound 44 is disposed on the second substrate 41 and covers the side surface 320 of the second chip 32, the side surface of the third thermally conductive element 33, and the side surface of the third thermally conductive element 43. The third thermally conductive element 33 and the third thermally conductive element 43 respectively penetrate the second molding compound 44. The fourth thermally conductive element 45 is disposed on the second chip 32, the third thermally conductive element 33, the third thermally conductive element 43, and the second molding compound 44. The second chip 32 is located between the fourth thermally conductive element 45 and the second substrate 41. The fourth thermally conductive element 45 is in thermal contact with the second chip 32, and is also in thermal contact with the third thermally conductive elements 33 and 43. In this embodiment, the fourth thermally conductive element 45 is in direct contact with the second chip 32, and is directly connected to the third thermally conductive elements 33 and 43.

[0145] Thermal paste 46 is disposed on the third thermally conductive element 33, the third thermally conductive element 43, the second molding material 44, and the fourth thermally conductive element 45. A heat sink 47 is disposed on the thermal paste 46. Thus, the heat sink 47 is located on the second substrate 41, the second chip 32, the third thermally conductive element 33, the third thermally conductive element 43, the second molding material 44, and the fourth thermally conductive element 45. The fourth thermally conductive element 45 is located between the heat sink 47 and the second chip 32. The thermal paste 46 is located between the heat sink 47 and the second molding material 44, and between the heat sink 47 and the fourth thermally conductive element 45. A circuit board 18 is disposed on and electrically connected to the first substrate 11. The first substrate 11 is located between the first chip 12 and the circuit board 18.

[0146] Therefore, the heat generated by the first chip 12 can be conducted to the first substrate 11 and then to the circuit board 18 via the first thermal conductive element 13 and the first thermal conductive element 23. It can also be conducted to the second substrate 41 via the first thermal conductive element 13, the first thermal conductive element 23, and the second thermal conductive element 25, and then to the third thermal conductive element 33, the third thermal conductive element 43, the fourth thermal conductive element 45, the thermal paste 46, and the heat sink 47. The heat generated by the second chip 32 can be conducted to the thermal paste 46 via the third thermal conductive element 33, the third thermal conductive element 43, and the fourth thermal conductive element 45, and then to the heat sink 47. It can also be conducted to the second substrate 41 via the third thermal conductive element 33 and the third thermal conductive element 43, and then to the first thermal conductive element 13, the first thermal conductive element 23, the first substrate 11, and the circuit board 18. According to the second law of thermodynamics, heat is transferred from high temperature to low temperature. The circuit board 18 and heat sink 37 further dissipate heat into the atmosphere, thereby quickly removing the heat generated by the first chip 12 and the second chip 32 to maintain the operation of the first chip 12 and the second chip 32.

[0147] The manufacturing process of package architecture 4 is similar to that of package architecture 3, except that the first thermally conductive element 23 is formed simultaneously when forming the first thermally conductive element 13 and the coaxial conductive via 19, and the third thermally conductive element 43 is formed simultaneously when forming the third thermally conductive element 33. The first thermally conductive element 23 can also be formed on the first substrate 11 by printing. The third thermally conductive element 43 can also be formed on the second substrate 41 by printing.

[0148] In another embodiment, Figures 6A to 6C The process of configuring a plurality of first thermally conductive elements 13, a plurality of first thermally conductive elements 23, and a plurality of coaxial conductive vias 19 on a first substrate 11 may include the following steps. For example... Figure 6A As shown, a release film 91 is formed on a mold 90, and a plurality of first thermally conductive elements 13, a plurality of first thermally conductive elements 23, and a plurality of coaxial conductive vias 19, arranged in an upside-down manner, are formed on the release film 91. A first chip 12 is also formed on a first substrate 11. Figure 6B As shown, the mold 90 is flipped up and down, and the first heat-conducting element 13, the first heat-conducting element 23, and the coaxial conductive through-hole 19 are attached to the first substrate 11 (transfer printing). Figure 6C As shown, the release film 91 is decomposed to detach the first thermally conductive element 13, the first thermally conductive element 23, and the coaxial conductive through hole 19 from the mold 90. The material of the release film 91 may be formed of hydrolyzed adhesive, but is not limited thereto, and may also be replaced by a method that can temporarily fix the first thermally conductive element 13, the first thermally conductive element 23, and the coaxial conductive through hole 19 to the mold 90.

[0149] Furthermore, Figures 11A to 11C The process of disposing of a plurality of third heat-conducting elements 33 and a plurality of third heat-conducting elements 43 on a second substrate 41 may include the following steps. For example... Figure 11A As shown, a release film 91 is formed on a mold 90, and a plurality of third heat-conducting elements 33 and a plurality of third heat-conducting elements 43, arranged in an upside-down manner, are formed on the release film 91. A second chip 32 is further formed on a second substrate 41. Figure 11B As shown, the mold 90 is flipped up and down, and the third heat-conducting element 33 and the third heat-conducting element 43 are attached to the second substrate 41 (transfer). Figure 11C As shown, the release film 91 is decomposed to detach the third thermally conductive element 33 and the third thermally conductive element 43 from the mold 90. The material of the release film 91 may be formed of hydrolyzed adhesive, but is not limited to this, and may also be replaced by a method that can temporarily fix the third thermally conductive element 33 and the third thermally conductive element 43 to the mold 90.

[0150] Alternatively, the packaging architecture 4 may also include an optional plurality of coaxial conductive vias 19 disposed on the first substrate 11 surrounding and adjacent to the first thermally conductive element 13, but is not limited thereto. In other embodiments, the coaxial conductive vias 19 may be omitted.

[0151] Please refer to Figure 12 . Figure 12 A side cross-sectional view of a packaging architecture according to another embodiment of the present invention is illustrated. In this embodiment, the packaging architecture 5 includes a first package 1a, a second package 5a, a fourth thermally conductive element 55, a metal-sintered epoxy resin layer 59, a thermal paste 56, a heat sink 57, and a circuit board 18.

[0152] like Figure 12 As shown, the first package 1a includes a first substrate 11, a first chip 12, a plurality of first thermally conductive elements 13, and a first molding compound 14. The first chip 12 is disposed on the first substrate 11. The first substrate 11 may be a fan-out circuit board. The first thermally conductive elements 13 are disposed on the first substrate 11. The plurality of first thermally conductive elements 13 are arranged to surround and be adjacent to the first chip 12, and are in thermal contact with the first chip 12. The first thermally conductive elements 13 may be spaced a very small distance from the first chip 12 without directly contacting the first chip 12. In addition, the first package 1a of the packaging architecture 5 may also include an optional plurality of coaxial conductive vias 19 disposed on the first substrate 11 surrounding and adjacent to the first thermally conductive elements 13, but this is not a limitation. In other embodiments, the coaxial conductive vias 19 may be omitted. In other embodiments, the first thermally conductive elements 13 may also be in direct contact with the first chip 12 without affecting the operation of the first chip 12.

[0153] In another embodiment, Figures 3A to 3C The process of depicting a plurality of first thermally conductive elements 13 and a plurality of coaxial conductive vias 19 disposed on a first substrate 11 may include the following steps. For example... Figure 3A As shown, a release film 91 is formed on a mold 90, and a plurality of first heat-conducting elements 13 and a plurality of coaxial conductive vias 19, arranged in an upside-down manner, are formed on the release film 91. A first chip 12 is also formed on a first substrate 11. Figure 3B As shown, the mold 90 is flipped up and down to attach the first heat-conducting element 13 and the coaxial conductive through-hole 19 onto the first substrate 11 (transfer printing). Figure 3C As shown, the release film 91 is decomposed to detach the first thermally conductive element 13 and the coaxial conductive through hole 19 from the mold 90. The material of the release film 91 may be formed of hydrolyzed adhesive, but is not limited to this, and may also be replaced by a method that can temporarily fix the first thermally conductive element 13 and the coaxial conductive through hole 19 to the mold 90.

[0154] In this embodiment, a first molding compound 14 is disposed on a first substrate 11 and covers the side surfaces of the first chip 12, the first thermally conductive element 13, and the coaxial conductive via 19. The first thermally conductive element 13 and the coaxial conductive via 19 respectively penetrate the first molding compound 14. Additionally, a metal-bonded epoxy resin layer 59 is disposed on the first chip 12, the first thermally conductive element 13, and the coaxial conductive via 19. The metal-bonded epoxy resin layer 59 can be formed and coated on the first chip 12, the first thermally conductive element 13, and the coaxial conductive via 19 by printing.

[0155] The second package 5a includes a second thermally conductive element 58, a second substrate 51, a second chip 52, a plurality of third thermally conductive elements 53, and a second molding compound 54. The second thermally conductive element 58 is disposed on a lower surface 511 of the second substrate 51. The second chip 52 is disposed on an upper surface 512 of the second substrate 51. The second substrate 51 may be a fan-out circuit board. A plurality of third thermally conductive elements 53 are disposed on the upper surface 512 of the second substrate 51. The third thermally conductive elements 53 are arranged to surround and be adjacent to the second chip 52, and are in thermal contact with the second chip 52. The third thermally conductive elements 53 may be coaxial conductive vias. The third thermally conductive elements 53 may be spaced a very small distance from the second chip 52 without direct contact with the second chip 52, but this is not a limitation. In other embodiments, the third thermally conductive elements 53 may also be in direct contact with the second chip 52 without affecting its operation.

[0156] In another embodiment, Figures 13A to 13C The process of depicting a plurality of third heat-conducting elements 53 disposed on a second substrate 51 may include the following steps. For example... Figure 13A As shown, a release film 91 is formed on a mold 90, and a plurality of third heat-conducting elements 53, arranged in an upside-down manner, are formed on the release film 91. A second chip 52 is also formed on a second substrate 51. Figure 13B As shown, the mold 90 is flipped up and down to attach the third heat-conducting element 53 onto the second substrate 51 (transfer). Figure 13C As shown, the release film 91 is decomposed to detach the third heat-conducting element 53 from the mold 90. The material of the release film 91 may be formed of hydrolyzed adhesive, but is not limited to this, and may also be replaced by a method that can temporarily fix the third heat-conducting element 53 to the mold 90.

[0157] In this embodiment, the second molding compound 54 is disposed on the upper surface 512 of the second substrate 51 and covers the side surface of the second chip 52 and the side surface of the third thermally conductive element 53. The third thermally conductive element 53 penetrates the second molding compound 54. A fourth thermally conductive element 55 is disposed on the second chip 52, the third thermally conductive element 53, and the second molding compound 54 of the second package 5a. The second chip 52 is located between the fourth thermally conductive element 55 and the second substrate 51. The fourth thermally conductive element 55 is in thermal contact with the second chip 52 and also in thermal contact with the third thermally conductive element 53. In this embodiment, the fourth thermally conductive element 55 is in direct contact with the second chip 52 and is directly connected to the third thermally conductive element 53.

[0158] The second thermally conductive element 58 and the second substrate 51 of the second package 5a are disposed on a metal-bonded epoxy resin layer 59. The metal-bonded epoxy resin layer 59 is located between the second thermally conductive element 58 and the first chip 12, between the second thermally conductive element 58 and the first thermally conductive element 13, and between the second substrate 51 and the first thermally conductive element 13. Thus, the first chip 12 is located between the second thermally conductive element 58 and the first substrate 11. The second thermally conductive element 58 is in thermal contact with the first chip 12 and the first thermally conductive element 13 via the metal-bonded epoxy resin layer 59. In this embodiment, the second thermally conductive element 58 and the first chip 12 are indirectly connected via the metal-bonded epoxy resin layer 59, and the second thermally conductive element 58 and the first thermally conductive element 13 are indirectly connected via the metal-bonded epoxy resin layer 59. The second thermally conductive element 58 may not be connected to the coaxial conductive via 19. Moreover, the second substrate 51 includes a conductive via 510. The conductive via 510 connects the third thermally conductive element 53 and the metal-bonded epoxy resin layer 59. A metal-sintered epoxy resin layer 59 connects a conductive via 510 and a first thermally conductive element 13. The first thermally conductive element 13 and the third thermally conductive element 53 are substantially aligned in the vertical direction.

[0159] Thermal paste 56 is disposed on the third thermally conductive element 53, the second molding material 54, and the fourth thermally conductive element 55. A heat sink 57 is disposed on the thermal paste 56. Thus, the heat sink 57 is located on the second substrate 51, the second chip 52, the third thermally conductive element 53, the second molding material 54, and the fourth thermally conductive element 55. The fourth thermally conductive element 55 is located between the heat sink 57 and the second chip 52. The thermal paste 56 is located between the heat sink 57 and the second molding material 54, and between the heat sink 57 and the fourth thermally conductive element 55. The second chip 58 and the second molding material 54 are located between the second substrate 51 and the heat sink 57. The second package 5a is located between the first package 1a and the heat sink 57. A circuit board 18 is disposed on and electrically connected to the first substrate 11. The first substrate 11 is located between the first chip 12 and the circuit board 18.

[0160] Therefore, the heat generated by the first chip 12 can be conducted through the first thermally conductive element 13 to the first substrate 11 and then to the circuit board 18. It can also be conducted through the first thermally conductive element 13, the metal-bonded epoxy resin layer 59, and the second thermally conductive element 58 to the second substrate 51, and then to the third thermally conductive element 53, the fourth thermally conductive element 55, the thermal paste 56, and the heat sink 57. The heat generated by the second chip 52 can be conducted through the third thermally conductive element 53 and the fourth thermally conductive element 55 to the thermal paste 56 and then to the heat sink 57. It can also be conducted through the third thermally conductive element 53 to the second substrate 51, and then to the metal-bonded epoxy resin layer 59, the first thermally conductive element 13, the first substrate 11, and the circuit board 18. According to the second law of thermodynamics, heat is transferred from high temperature to low temperature. The circuit board 18 and the heat sink 57 further dissipate the heat into the atmosphere, thereby rapidly removing the heat generated by the first chip 12 and the second chip 52 to maintain their operation.

[0161] The following is for reference Figure 3 , Figure 4 , Figures 13 to 16 and Figure 12 ,illustrate Figure 12 The manufacturing process of the packaging architecture 5 shown is described. Figures 13 to 16 Draw Figure 12 A side cross-sectional view of the manufacturing process of the packaging architecture.

[0162] like Figure 3 and Figure 4 As shown, prepare the first package 1a. (As indicated) Figure 3 As shown, a first chip 12 is disposed on a first substrate 11, and a plurality of first thermally conductive elements 13 and a plurality of coaxial conductive vias 19 are disposed on the first substrate 11, the order of which is not fixed. The first thermally conductive elements 13 are disposed around and adjacent to the first chip 12. The plurality of coaxial conductive vias 19 are disposed around and adjacent to the first thermally conductive elements 13. In this embodiment, the first chip 12 can be electrically connected and fixed on the first substrate 11 by flip-chip bonding, and the first thermally conductive elements 13 and coaxial conductive vias 19 can be formed on the first substrate 11 by printing.

[0163] like Figure 4 As shown, a first molding compound 14 is disposed on a first substrate 11, and the first molding compound 14 covers the side surface of the first chip 12, the side surface of the first thermally conductive element 13, and the side surface of the coaxial conductive via 19. The first thermally conductive element 13 and the coaxial conductive via 19 respectively penetrate the first molding compound 14. Thus, the preparation of the first package 1a is completed.

[0164] like Figure 13 and Figure 14 As shown, prepare the second package 5a. (As indicated) Figure 13As shown, a second chip 52 is disposed on the upper surface 512 of the second substrate 51, and a plurality of third thermal conductive elements 53 are disposed on the upper surface 512 of the second substrate 51, in any order. The third thermal conductive elements 53 are arranged to surround and be adjacent to the second chip 52. In this embodiment, the second chip 52 can be electrically connected and fixed to the second substrate 51 by flip-chip bonding, and the third thermal conductive elements 53 can be formed on the second substrate 51 by printing.

[0165] like Figure 14 As shown, a second molding compound 54 is disposed on the upper surface 512 of the second substrate 51, and the second molding compound 54 covers the side surface of the second chip 52 and the side surface of the third thermal conductive element 53. The third thermal conductive element 53 penetrates the second molding compound 54. Thus, the preparation of the second package 5a is completed. Figure 4 Preparation of the first package 1a shown Figure 14 The preparation of the second package 5a shown can be done in any order, or simultaneously.

[0166] like Figure 15 As shown, a fourth thermally conductive element 55 is disposed on the second chip 52, the third thermally conductive element 53, and the second molding material 54 of the second package 5a to make thermal contact with the second chip 52 and the third thermally conductive element 53. The second chip 52 is located between the fourth thermally conductive element 55 and the second substrate 51. Figure 4 Preparation of the first package 1a shown Figure 15 The preparation of the combination of the second package 5a and the fourth thermal conductive element 55 shown can be done in any order, or simultaneously.

[0167] like Figure 16 As shown, a metal-sintered epoxy resin layer 59 is disposed on the first chip 12, the first thermally conductive element 13, and the coaxial conductive via 19 of the first package 1a. The metal-sintered epoxy resin layer 59 can be formed on the first chip 12, the first thermally conductive element 13, and the coaxial conductive via 19 by printing. Figure 16 Preparation of the combination of the first package 1a and the metal sintered epoxy resin layer 59 shown Figure 14 The preparation of the second package 5a shown can be done in any order, or simultaneously. Figure 16 Preparation of the combination of the first package 1a and the metal sintered epoxy resin layer 59 shown Figure 16 The preparation of the combination of the second package 5a and the fourth thermal conductive element 55 shown can be done in any order, or simultaneously.

[0168] like Figure 16 and Figure 12As shown, the second package 5a is disposed on the first package 1a via a metal-bonded epoxy resin layer 59. The metal-bonded epoxy resin layer 59 connects the second thermally conductive element 58 and the first chip 12, connects the second thermally conductive element 58 and the first thermally conductive element 13, and connects the conductive via 510 of the second substrate 51 and the first thermally conductive element 13. Thus, the first chip 12 is located between the second thermally conductive element 58 and the first substrate 11.

[0169] like Figure 12 As shown, thermal paste 56 is applied on the third thermally conductive element 53 and the second molding material 54, and on the fourth thermally conductive element 55 of the second package 5a. A heat sink 57 is applied on the second package 5a and the thermal paste 56. The second package 5a is located between the first package 1a and the heat sink 57. The thermal paste 56 is located between the heat sink 57 and the second molding material 54, and between the heat sink 57 and the fourth thermally conductive element 55. The first package 1a is placed on the circuit board 18, and the first substrate 11 is located between the first chip 12 and the circuit board 18. Thus, the manufacturing of the package architecture 5 is completed.

[0170] Please refer to Figure 17 The diagram illustrates a side cross-sectional view of a packaging architecture according to another embodiment of the present invention. The packaging architecture 6 includes a first substrate 61, a first chip 62, a plurality of first thermal conductive elements 63, a first molding material 64, a thermal paste 661, a thermal paste 662, a heat sink 67, a circuit board 68, and an antenna layer 69.

[0171] like Figure 17 As shown, a first chip 62 is disposed on a first substrate 61. The first substrate 61 may contain an insulating material. A first thermally conductive element 63 is disposed on the first substrate 61, surrounding and adjacent to the first chip 62. The first thermally conductive element 63 is a columnar conductive material. A plurality of first thermally conductive elements 63 are arranged to surround and be adjacent to the first chip 62, and are in thermal contact with the first chip 62. The first thermally conductive elements 63 may be spaced a very small distance from the first chip 62 without directly contacting it. Passive components such as resistors R and capacitors C may also be disposed on the first substrate 61. A first molding material 64 is disposed on the first substrate 61 and covers the side surfaces of the first chip 62 and the side surfaces of the first thermally conductive elements 63. The first thermally conductive elements 63 may penetrate the first molding material 64. An antenna layer 69 is disposed on the first substrate 61. The first substrate 61 is located between the antenna layer 69 and the first chip 62. In other embodiments, the first thermally conductive element 63 may also be in direct contact with the first chip 62 without affecting the operation of the first chip 62.

[0172] In this embodiment, a circuit board 68 is disposed on and electrically connected to the first thermally conductive element 63 and the first molding material 64. Thermal paste 661 is disposed between the first molding material 64 and the circuit board 68, and between the first chip 62 and the circuit board 68. The first chip 62 is located between the first substrate 61 and the circuit board 68. Thermal paste 662 is disposed on the circuit board 68, and a heat sink 67 is disposed on the thermal paste 662. Thermal paste 662 is located between the circuit board 68 and the heat sink 67. The circuit board 68 is located between the first chip 62 and the heat sink 67. The first chip 62 is located between the first substrate 61 and the heat sink 67.

[0173] Therefore, the heat generated by the first chip 62 can be conducted to the circuit board 68 via the first thermally conductive element 63 and the thermal paste 661, and then to the heat sink 67 via the thermal paste 662. The heat sink 67 further dissipates the heat into the atmosphere, thereby quickly removing the heat generated by the first chip 62 to maintain its operation. Moreover, the first substrate 61 can mitigate the impact of the heat generated by the first chip 62 on the performance of the antenna layer 69.

[0174] The following explanation Figure 17 The manufacturing process of the package architecture 6 shown is as follows: A first package 6a is prepared. A first chip 62 is disposed on a first substrate 61, and a plurality of first thermally conductive elements 63 are disposed on the first substrate 61 in any order. Passive components such as resistors R and capacitors C may also be disposed on the first substrate 61. The first thermally conductive elements 63 are arranged to surround and be adjacent to the first chip 62. In this embodiment, the first chip 62 can be electrically connected and fixed to the first substrate 61 via flip-chip bonding, and the first thermally conductive elements 63 can be formed on the first substrate 61 via printing.

[0175] A first molding compound 64 is disposed on a first substrate 61, covering the side surface of the first chip 62 and the side surface of the first thermally conductive element 63. The first thermally conductive element 63 penetrates the first molding compound 64. Thus, the preparation of the first package 6a is completed.

[0176] In this embodiment, the first thermally conductive element 63 can be formed first, followed by the formation of the first molding compound 64, but this is not a limitation. In other embodiments, the first molding compound 64 covering the side surface of the first chip 62 can be formed first, followed by the formation of multiple through holes in the first molding compound 64, and then the formation of the first thermally conductive element 63 within the multiple through holes. However, the process of this embodiment is simpler than that of other embodiments.

[0177] An antenna layer 69 is disposed on a first substrate 61 of the first package 6a. The first substrate 61 is located between the antenna layer 69 and the first chip 62. A circuit board 68 is disposed on a first thermally conductive element 63 and a first molding compound 64. The circuit board 68 is electrically connected to the first thermally conductive element 63. Thermal paste 661 is filled between the first molding compound 64 and the circuit board 68, and between the first chip 62 and the circuit board 68. The first chip 62 is located between the first substrate 61 and the circuit board 68. Thus, the first package 6a is disposed on the circuit board 68. The first chip 62 is located between the first substrate 61 and the circuit board 68.

[0178] Thermal paste 662 is applied onto circuit board 68. A heat sink 67 is applied onto thermal paste 662. Thus, thermal paste 662 is applied between heat sink 67 and circuit board 68, and heat sink 67 is applied onto first package 6a. Thermal paste 662 is located between circuit board 68 and heat sink 67. Circuit board 68 is located between first chip 62 and heat sink 67. First chip 62 is located between first substrate 61 and heat sink 67. Thus, the manufacturing of package architecture 6 is completed.

[0179] Please refer to Figure 18 The diagram illustrates a side cross-sectional view of a packaging architecture according to another embodiment of the present invention. The packaging architecture 7 includes a first substrate 61, a first chip 62, a plurality of first thermal conductive elements 63, a plurality of first thermal conductive elements 73, a first molding material 74, a thermal paste 661, a thermal paste 662, a heat sink 67, a circuit board 68, and an antenna layer 69. Figure 18 The packaging architecture 7 and Figure 17 The encapsulation architecture is similar to that of 6, and the following mainly focuses on the differences.

[0180] like Figure 18 As shown, a first thermally conductive element 63 and a second thermally conductive element 73 are disposed on a first substrate 61, surrounding and adjacent to a first chip 62. The first thermally conductive element 73 serves as a wall (used to supply power voltage). A plurality of first thermally conductive elements 73 are arranged to surround and be adjacent to the first chip 62, and are in thermal contact with the first chip 62. Each first thermally conductive element 73 extends in a direction substantially perpendicular to the side surface 620 of the first chip 62. A first molding compound 74 is disposed on the first substrate 61 and covers the side surface 620 of the first chip 62, the side surface of the first thermally conductive element 63, and the side surface of the first thermally conductive element 73. The first thermally conductive elements 63 and 73 respectively penetrate the first molding compound 74.

[0181] Therefore, the heat generated by the first chip 62 can be conducted to the circuit board 68 via the first thermal conductive element 63, the first thermal conductive element 73, and the thermal paste 661, and then to the heat sink 67 via the thermal paste 662. The heat sink 67 further dissipates the heat into the atmosphere, thereby quickly removing the heat generated by the first chip 62 to maintain its operation. Moreover, the first substrate 61 can mitigate the impact of the heat generated by the first chip 62 on the performance of the antenna layer 69.

[0182] Figure 18 The manufacturing process of the packaging architecture 7 and Figure 17 The manufacturing process of the packaging architecture 6 is similar, except that when preparing the first package 7a, the first thermal conductive element 63 and the first thermal conductive element 73 can be formed simultaneously. The first thermal conductive element 73 can also be formed on the first substrate 61 by printing.

[0183] In summary, in the packaging architecture of one embodiment of the present invention, the heat generated by the first chip can be conducted to the first substrate and then to the circuit board via the first thermally conductive element, and can also be conducted to the thermal paste and then to the heat sink via the first and second thermally conductive elements. The circuit board and the heat sink further dissipate the heat into the atmosphere, thereby rapidly removing the heat generated by the first chip to maintain the operation of the first chip.

[0184] In another embodiment of the packaging architecture of the present invention, the heat generated by the first chip can be conducted to the first substrate and then to the circuit board via the first thermally conductive element, and further conducted to the second substrate and then to the third thermally conductive element, the fourth thermally conductive element, thermal paste, and the heat sink via the first and second thermally conductive elements. The heat generated by the second chip can be conducted to the thermal paste and then to the heat sink via the third and fourth thermally conductive elements, and further conducted to the second substrate and then to the first thermally conductive element, the first substrate, and the circuit board via the third thermally conductive element. According to the second law of thermodynamics, heat is transferred from high temperature to low temperature. The circuit board and the heat sink further dissipate the heat into the atmosphere, thereby rapidly removing the heat generated by the first and second chips to maintain their operation.

[0185] In another embodiment of the packaging architecture of the present invention, the heat generated by the first chip can be conducted to the first substrate and then to the circuit board via the first thermally conductive element, and further conducted to the second substrate and then to the third thermally conductive element, the fourth thermally conductive element, thermal paste, and the heat sink via the first thermally conductive element, the metal-bonded epoxy resin layer, and the second thermally conductive element. The heat generated by the second chip can be conducted to the thermal paste and then to the heat sink via the third and fourth thermally conductive elements, and further conducted to the second substrate and then to the metal-bonded epoxy resin layer, the first thermally conductive element, the first substrate, and the circuit board via the third thermally conductive element. According to the second law of thermodynamics, heat is transferred from high temperature to low temperature. The circuit board and the heat sink further dissipate the heat into the atmosphere, thereby rapidly removing the heat generated by the first and second chips to maintain their operation.

[0186] In another embodiment of the packaging architecture of the present invention, the heat generated by the first chip can be conducted to the circuit board via the first thermally conductive element and thermal paste, and then to the heat sink via the thermal paste. The heat sink further dissipates the heat into the atmosphere, thereby quickly removing the heat generated by the first chip to maintain the operation of the first chip. Moreover, the first substrate can mitigate the impact of the heat generated by the first chip on the performance of the antenna layer.

Claims

1. A packaging architecture, comprising: First substrate; The first chip is disposed on the first substrate; At least one first thermally conductive element is disposed on the first substrate and adjacent to the first chip; A first molding material is disposed on the first substrate and covers the side surface of the first chip and the side surface of the at least one first thermally conductive element; as well as A heat sink is disposed on the first substrate, the first chip, the at least one first thermally conductive element, and the first molding material.

2. The packaging architecture as claimed in claim 1, wherein the number of the at least one first thermal conductive element is multiple, the first thermal conductive elements are multiple coaxial conductive vias, the coaxial conductive vias are arranged adjacent to the first chip and respectively penetrate the first molding material.

3. The packaging architecture of claim 1, wherein the number of the at least one first thermal conductive element is multiple, the first thermal conductive elements are multiple walls, the walls are arranged adjacent to the first chip and respectively penetrate the first molding material, and each wall extends in a direction substantially perpendicular to the side surface of the first chip.

4. The packaging architecture as claimed in claim 1, further comprising a circuit board disposed on and electrically connected to the first substrate, the first substrate being located between the first chip and the circuit board.

5. The packaging architecture of claim 1, further comprising a second thermally conductive element disposed on the first chip and the first molding material and located between the heat sink and the first chip, wherein the second thermally conductive element is in thermal contact with the first thermally conductive element, and the first chip is located between the second thermally conductive element and the first substrate.

6. The packaging architecture of claim 5, further comprising thermal paste disposed between the heat sink and the first molding material and between the heat sink and the second thermally conductive element.

7. The packaging architecture as described in claim 5, further comprising: The second substrate is disposed on the second thermally conductive element; The second chip is disposed on the second substrate; At least one third thermal conductive element is disposed on the second substrate and adjacent to the second chip, the at least one third thermal conductive element is in thermal contact with the second substrate and the second substrate is in thermal contact with the at least one first thermal conductive element; The second molding material is disposed on the second substrate and covers the side surface of the second chip and the side surface of the at least one third thermal conductive element; as well as A fourth thermally conductive element is disposed on the second chip and the second molding material and located between the heat sink and the second chip. The second chip is located between the fourth thermally conductive element and the second substrate. The fourth thermally conductive element is in thermal contact with the second chip and the at least one third thermally conductive element. in The second chip and the second molding material are located between the second substrate and the heat sink.

8. The packaging architecture of claim 7, wherein the number of the at least one third thermal conductive element is multiple, the third thermal conductive elements are multiple coaxial conductive vias, the coaxial conductive vias are arranged adjacent to the second chip and respectively penetrate the second molding material.

9. The packaging architecture of claim 7, wherein the number of the at least one third thermally conductive element is multiple, the third thermally conductive elements are multiple walls arranged adjacent to the second chip and respectively penetrating the second molding material, each of the walls extending in a direction substantially perpendicular to the side surface of the second chip.

10. The packaging architecture of claim 7, further comprising thermal paste disposed between the heat sink and the second molding material and between the heat sink and the fourth thermally conductive element.

11. The packaging architecture of claim 7, further comprising a circuit board disposed on and electrically connected to the first substrate, the first substrate being located between the first chip and the circuit board.

12. The packaging architecture of claim 7, further comprising a metal sintered epoxy resin layer disposed between the second substrate and the at least one first thermally conductive element and between the second thermally conductive element and the first chip.

13. The packaging architecture of claim 1, further comprising an antenna layer disposed on the first substrate, the first substrate being located between the antenna layer and the first chip, and the first chip being located between the first substrate and the heat sink.

14. The packaging architecture of claim 13, further comprising a circuit board disposed between the first chip and the heat sink and connected to the at least one first thermally conductive element.

15. The packaging architecture of claim 14, further comprising thermal paste disposed between the first molding material and the circuit board and between the circuit board and the heat sink.

16. A method for manufacturing a packaging architecture, comprising: Prepare the first package, which includes: A first chip is disposed on a first substrate; At least one first thermally conductive element is disposed on the first substrate, the at least one first thermally conductive element being disposed adjacent to the first chip; and A first molding compound is disposed on the first substrate, the first molding compound covering the side surface of the first chip and the side surface of the at least one first thermally conductive element; and A heat sink is disposed on the first package.

17. The method of manufacturing the packaging architecture as claimed in claim 16, wherein the step of disposing of the at least one first thermally conductive element on the first substrate includes: A release film is formed on the mold; The at least one first thermally conductive element is formed on the release film; The mold is flipped over and the at least one first thermally conductive element is attached to the first substrate; as well as Decomposing the release film causes the at least one first thermally conductive element to detach from the mold.

18. The method of manufacturing the packaging architecture as described in claim 16, further comprising: A second package is prepared before the heat sink is mounted on the first package, comprising: A second heat-conducting element is disposed on the lower surface of the second substrate; A second chip is disposed on the upper surface of the second substrate; At least one third thermally conductive element is disposed on the upper surface of the second substrate, the at least one third thermally conductive element being adjacent to the second chip and in thermal contact with the second substrate; and A second molding material is disposed on the upper surface of the second substrate, and the second molding material covers the side surface of the second chip and the side surface of the at least one third thermal conductive element; A fourth thermally conductive element is disposed on the second chip and the second molding material, the second chip being located between the fourth thermally conductive element and the second substrate, and the fourth thermally conductive element being in thermal contact with the second chip and the at least one third thermally conductive element; and The second package is disposed on top of the first package; wherein After the heat sink is disposed on the first package, the second package is located between the first package and the heat sink.

19. The method of manufacturing the packaging architecture as claimed in claim 18, wherein the step of disposing of the at least one third thermally conductive element on the upper surface of the second substrate comprises: A release film is formed on the mold; The at least one third thermally conductive element is formed on the release film; The mold is flipped over and the at least one third thermally conductive element is attached to the upper surface of the second substrate; as well as Decomposing the release film causes the at least one third thermally conductive element to detach from the mold.

20. The method of manufacturing the packaging architecture as described in claim 18, further comprising: A metal-sintered epoxy resin layer is coated on the first chip and the at least one first thermally conductive element in the first package. as well as The second package is disposed on the first package via the metal sintered epoxy resin layer.

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