Chip package heat dissipation structure, heat dissipation type chip package structure and preparation method thereof

Abstract

The application provides a chip packaging heat dissipation structure, a heat dissipation type chip packaging structure and a preparation method thereof. The chip packaging heat dissipation structure comprises a silicon interlayer and a closed bottom sheet. The silicon interlayer provides a first surface and a second surface opposite to each other. The first surface is used for loading a core particle. The silicon interlayer is provided with a bottom heat dissipation cavity on the second surface. The bottom heat dissipation cavity is filled with a phase change material. The closed bottom sheet is bonded on the second surface of the silicon interlayer and seals the opening of the bottom heat dissipation cavity on the second surface. The application can efficiently dissipate heat of the core particle.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a chip packaging heat dissipation structure, a heat dissipation type chip packaging structure, and a method for preparing the same. Background Technology

[0002] In the field of advanced semiconductor packaging, especially in COWOS (Chip-on-Wafer-on-Substrate) technology, high-density 3D stacked structures, such as the integrated structure of logic chips and HBM, will experience a sharp increase in heat flux density during operation. If heat dissipation is not carried out in a timely and effective manner, it will affect the stability of the integrated structure.

[0003] Traditional heat dissipation methods involve using conventional thermal interface materials (TIMs) combined with external heat sinks. Conventional TIMs widely employ thermal grease or liquid metal for heat dissipation, relying on passive conduction and convection. Furthermore, in the process of using thermal grease or liquid metal to fill the gap between the chip and the external heat sink for heat dissipation, it is also necessary to coordinate with an air-cooling or liquid-cooling system.

[0004] While traditional heat dissipation methods can effectively cool chips, they suffer from high thermal resistance. Additionally, external heat sinks can accumulate heat due to micro-gaps in contact with traditional thermal interface materials. This results in poor transient response, making them unable to handle sudden power consumption surges, such as AI inference peaks, and potentially causing a rapid rise in local chip temperature, leading to thermal failure. Summary of the Invention

[0005] To address the aforementioned issues, the present invention provides a chip packaging heat dissipation structure, a heat dissipation-type chip packaging structure, and a method for preparing the same, which can efficiently dissipate heat from the chip by filling a silicon interlayer with a phase change material.

[0006] In a first aspect, the present invention provides a chip packaging heat dissipation structure, the chip packaging heat dissipation structure comprising: a silicon interposer and a closed substrate;

[0007] The silicon interposer has a first surface and a second surface opposite to each other. The first surface is used to load the chip, and the silicon interposer has a bottom heat dissipation chamber on the second surface. The bottom heat dissipation chamber is filled with a phase change material. The closed substrate is bonded to the second surface of the silicon interposer and the opening of the bottom heat dissipation chamber on the second surface is sealed.

[0008] Optionally, the closed film is adapted to the second surface.

[0009] Optionally, the chip package heat dissipation structure may also include a through-silicon via (TSV) structure; The through-silicon via (TSV) structure penetrates the silicon interposer and the closed substrate, and is separated from the bottom heat dissipation chamber.

[0010] Optionally, the chip package heat dissipation structure may also include: a redistribution layer; A redistribution layer is bonded to the first surface, and a silicon interposer is used to load the die through the redistribution layer.

[0011] Optionally, the phase change material includes: SnBi phase change alloy or GaInSn phase change alloy; The materials used for closed substrates include silicon.

[0012] In a second aspect, the present invention provides a method for fabricating a chip package heat dissipation structure, the method comprising: Provides silicon interposer and closed substrate; A bottom heat dissipation chamber is etched out on one surface of a silicon interlayer; The bottom heat dissipation chamber is filled with phase change material; A closed substrate is bonded to a silicon interposer to seal the opening of the bottom heat dissipation chamber.

[0013] Optionally, after the step of bonding the closed substrate to the silicon interposer to seal the opening of the bottom heat dissipation chamber, the fabrication method further includes: Silicon via etching is performed on a closed substrate and a silicon interposer to form a silicon via structure that penetrates the closed substrate and the silicon interposer.

[0014] Optionally, prior to the step of bonding the closed substrate to the silicon interposer to seal the opening of the bottom heat dissipation chamber, the fabrication method further includes: A redistribution layer is formed on the surface of the silicon interposer away from the closed substrate.

[0015] Thirdly, the present invention provides a heat-dissipating chip packaging structure, the heat-dissipating chip packaging structure comprising: a chip and a chip packaging heat dissipation structure as described in any of the first aspects; The core particles are bonded to the first surface.

[0016] Optionally, the heat-dissipating chip package structure further includes: a substrate; The closed film is soldered to the substrate.

[0017] Optionally, the heat-dissipating chip package structure also includes: a closed top plate; A top heat dissipation chamber is formed on the surface of the core particle away from the first surface, and the top heat dissipation chamber is filled with phase change material; The closed top plate is bonded to the surface of the core away from the first surface and closes the opening of the top heat dissipation chamber on the core.

[0018] Fourthly, the present invention provides a method for fabricating a heat-dissipating chip package structure, the method comprising: A chip package heat dissipation structure is obtained by using any of the preparation methods in the second aspect; Core particles are bonded to the first surface of the silicon interlayer.

[0019] The chip packaging heat dissipation structure, heat dissipation chip packaging structure and its preparation method provided in this invention fill a silicon interposer with a phase change material, so that the phase change material and the chip are separated by only a micrometer-level gap, shortening the distance between the phase change material and the chip. This allows the heat generated by the chip to be quickly absorbed when the temperature of the chip rises sharply, thereby efficiently dissipating heat from the chip. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figures 1a to 1c These are schematic cross-sectional views of different stages in the fabrication process of a chip packaging heat dissipation structure according to an embodiment of this application; Figures 2a to 2c These are schematic cross-sectional views of different stages in the fabrication process of a heat-dissipating chip packaging structure according to an embodiment of this application; Figure 3 This is a schematic cross-sectional view of a heat-dissipating chip package structure according to an embodiment of this application.

[0022] Figure label: 1. Silicon interposer; 11. Bottom heat dissipation chamber; 2. Closed substrate; 3. Chip; 31. Top heat dissipation chamber; 4. Closed top substrate; 5. Substrate; 6. Reinforcing rib; 71. Redistribution layer; 72. Molded enclosure; 73. Through-silicon via structure; 74. Microbumps; 75. C4 bumps; 76. Solder balls. Detailed Implementation

[0023] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0025] Spatial relation terms such as "below," "under," "below," "below," "above," and "above" are used here to describe the relationship between one element or feature shown in the figure and other elements or features. Similarly, "directly above" can be used here to describe an element or feature shown in the figure that coincides in a vertical straight line direction, which may be partial or complete, depending on the actual situation or the content of the illustration. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as "below," "below," or "below" of other elements will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0026] It should be noted that when an element is referred to as "fixedly connected" to another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. Conversely, when an element is referred to as being "directly on" another element, there is no intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0027] It should also be understood that the terms “including / comprise” or “have” specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0028] In a first aspect, one embodiment of the present invention provides a chip packaging heat dissipation structure, combined with Figure 1c The chip packaging heat dissipation structure includes: a silicon interposer 1 and a closed substrate 2.

[0029] The silicon interposer 1 has a first surface and a second surface opposite to each other. The first surface is used to load the core 3. A bottom heat dissipation chamber 11 is formed on the second surface of the silicon interposer 1. The bottom heat dissipation chamber 11 is filled with a phase change material (PCM). The closed substrate 2 is bonded to the second surface of the silicon interposer 1 and closes the opening of the bottom heat dissipation chamber 11 on the second surface.

[0030] The thickness of the silicon interposer 1 ranges from 100μm to 300μm, such as 120μm, 150μm, 180μm, 200μm, 250μm, and 280μm. The specific position of the bottom heat dissipation chamber 11 relative to the silicon interposer 1 can be arranged according to the subsequent through-silicon via (TSV) arrangements. This divides the second surface into four equal parts. Taking a grid of 4 as an example, if each grid needs to have through-silicon vias, the bottom heat dissipation chamber 11 can be distributed in each grid or part of the grid; if only the four central grids or one or more at the edge need to have through-silicon vias, the bottom heat dissipation chamber 11 can be distributed in other grids, but is not limited to this; the bottom heat dissipation chamber 11 in the grid can be a large groove occupying most of the corresponding grid area, and the grooves in adjacent grids can be connected or not connected. The bottom heat dissipation chamber 11 in the grid can also be micro-holes distributed on the corresponding grid.

[0031] In this embodiment, the first surface is the upper surface of the silicon interposer 1, and the second surface is the lower surface of the silicon interposer 1; the bottom heat dissipation chamber 11 is an array of micro-holes distributed on the corresponding grid, the diameter of the bottom heat dissipation chamber 11 is in the range of 10μm to 50μm, such as 20μm, 30μm, etc.; the depth of the bottom heat dissipation chamber 11 is in the range of 50μm to 150μm, such as 60μm, 80μm, 100μm, 120μm, etc.; the spacing between adjacent bottom heat dissipation chambers 11 is 1.2 to 2 times the diameter of the bottom heat dissipation chamber 11, such as 1.5 times, 1.6 times, 1.8 times, etc.

[0032] The chip packaging heat dissipation structure provided in this embodiment fills the silicon interposer 1 with phase change material, so that there is only a micrometer-level gap between the phase change material and the core 3, which shortens the distance between the phase change material and the core 3. Thus, when the temperature of the core 3 rises sharply, it can quickly absorb the heat generated by the core 3, thereby efficiently dissipating heat from the core 3.

[0033] It should be noted that the size of the closed bottom plate 2 relative to the second surface can be the same, i.e., completely cover it, or it can be slightly larger or smaller than the second surface depending on the actual application scenario, or it can cover a local area of ​​the second surface depending on the distribution of the bottom heat dissipation chamber 11 on the second surface.

[0034] In a further optional embodiment of this example, the closed substrate 2 is adapted to the second surface, that is, the closed substrate 2 and the second surface have the same dimensions. By providing the closed substrate 2, it is possible to prevent phase change material with high latent heat from being sputtered out of the bottom heat dissipation chamber 11.

[0035] In a further optional embodiment of this invention, the chip package heat dissipation structure also includes a through-silicon via (TSV) structure 73, also known as a TSV channel. The TSV structure 73 penetrates the silicon interposer 1 and the closed substrate 2, and is spaced apart from the bottom heat dissipation chamber 11. The minimum distance between the TSV structure 73 and the adjacent bottom heat dissipation chamber 11 is not less than 20 μm; this embodiment does not impose a specific limitation on this.

[0036] It is understood that the through-silicon via structure 73 is achieved by creating through-silicon vias on the silicon interposer 1 and the closed substrate 2 and filling them with appropriate materials to achieve electrical connection with the core 3 mounted on the silicon interposer 1. The specific manufacturing process of the through-silicon via structure 73 will not be described in detail in this embodiment.

[0037] In a further optional embodiment of this embodiment, the chip package heat dissipation structure further includes: a redistribution layer (RDL) 71.

[0038] A redistribution layer 71 is attached to the first surface, and a silicon interposer 1 is used to load the die 3 through the redistribution layer 71. The circuitry in the redistribution layer 71 is electrically connected to the corresponding through-silicon via (TSV) structure 73.

[0039] In a further optional embodiment of this embodiment, the phase change material includes, but is not limited to, Sn-Bi phase change alloy or Ga-In-Sn phase change alloy; the material of the closed substrate 2 includes, but is not limited to, silicon.

[0040] The chip packaging heat dissipation structure provided in this embodiment makes full use of the empty space on the silicon interposer 1 by opening a bottom heat dissipation chamber 11 in the non-TSV region of the silicon interposer 1. This not only improves the space utilization of the subsequent chip packaging structure, but also enhances the heat dissipation efficiency of the chip 3, which can effectively reduce the thermal failure problem caused by local temperature runaway of the chip 3.

[0041] In a second aspect, an embodiment of the present invention provides a method for preparing a chip package heat dissipation structure as described in the first aspect, the method comprising steps S101 to S104.

[0042] Step S101: Provide a silicon interposer 1 and a closed substrate 2.

[0043] Step S102: Etch the bottom heat dissipation chamber 11 on the second surface of the silicon interposer 1.

[0044] Step S103: Fill the bottom heat dissipation chamber 11 with phase change material, combined with Figure 1a .

[0045] Step S104: Bond the closed substrate 2 to the second surface of the silicon interposer 1 to seal the opening of the bottom heat dissipation chamber 11, and combine. Figure 1b .

[0046] In a further optional embodiment of this embodiment, after the step of bonding the closed substrate 2 to the silicon interposer 1 to seal the opening of the bottom heat dissipation chamber 11, the fabrication method further includes: etching silicon vias on the closed substrate 2 and the silicon interposer 1 to form a silicon via structure 73 penetrating the closed substrate 2 and the silicon interposer 1, combined with... Figure 1c .

[0047] In a further optional embodiment of this embodiment, before the step of bonding the closed substrate 2 to the silicon interposer 1 to close the opening of the bottom heat dissipation chamber 11, the preparation method further includes: forming a redistribution layer 71 on the surface of the silicon interposer 1 away from the closed substrate 2.

[0048] Thirdly, one embodiment of the present invention provides a heat-dissipating chip packaging structure, combined with Figure 2a and Figure 2b The heat-dissipating chip package structure includes: a chip 3 and a chip package heat dissipation structure as described in the first aspect. The chip 3 is bonded to the first surface.

[0049] In this embodiment, the chip 3 is bonded to the first surface via a redistribution layer 71 to be electrically connected to the through-silicon via structure 73 via circuitry on the redistribution layer 71.

[0050] In a further optional embodiment of this embodiment, combined with Figure 2c The heat-dissipating chip packaging structure also includes a substrate 5. The substrate 5 is located on the side of the closed substrate 2 away from the chip 3 and is soldered to the closed substrate 2. The through-silicon via structure 73 is also electrically connected to the circuitry on the substrate 5; solder balls 76 are fixed to the bottom surface of the substrate 5.

[0051] In a further optional embodiment of this embodiment, combined with Figure 2c The chip packaging heat dissipation structure also includes a molding compound 72. The molding compound 72 fills the periphery of the chip 3 to encapsulate the chip 3 on the silicon interposer 1.

[0052] In a further optional embodiment of this embodiment, combined with Figure 2c The chip package heat dissipation structure also includes a reinforcing rib 6. The reinforcing rib 6 is fixed to the surface of the substrate 5 facing the chip package heat dissipation structure to suppress warping of the substrate 5.

[0053] In this embodiment, the reinforcing rib 6 is a ring structure and surrounds the periphery of the chip package heat dissipation structure.

[0054] In a further optional embodiment of this embodiment, combined with Figure 3 The heat-dissipating chip package structure also includes a closed top plate 4. A top heat dissipation chamber 31 is formed on the upper surface of the chip 3, and the top heat dissipation chamber 31 is filled with a phase change material. The closed top plate 4 is bonded to the upper surface of the chip 3 and closes the opening of the top heat dissipation chamber 31 on the chip 3.

[0055] The top heat dissipation chamber 31 can be a large groove or a micro-hole. In this embodiment, the top heat dissipation chamber 31 is an array of micro-holes distributed on the top of the core 3. The diameter of the top heat dissipation chamber 31 can be referenced to the bottom heat dissipation chamber 11, but this embodiment does not limit it. The depth and spacing of the top heat dissipation chamber 31 need to be adjusted according to the different core 3, but this embodiment does not limit them.

[0056] When a single chip 3 is bonded to the same chip package heat dissipation structure, the size of the closed top plate 4 relative to the upper surface of the chip 3 can be the same, i.e., completely covering it, or it can be slightly larger or smaller than the upper surface of the chip 3 depending on the actual application scenario. It can also cover a local area of ​​the second surface depending on the distribution of the top heat dissipation chamber 31 on the second surface. When multiple chips 3 are bonded to the same chip package heat dissipation structure, the closed top plate 4 can bond the corresponding chip 3 individually or bond multiple chips 3 simultaneously.

[0057] Fourthly, an embodiment of the present invention provides a method for fabricating a heat-dissipating chip package structure as described in the third aspect, the method comprising steps S201 to S203.

[0058] Step S201: Provide substrate 5, core 3, and chip package heat dissipation structure prepared by the method in the second aspect.

[0059] Step S202: Mount the chip 3 onto the first surface of the chip package heat dissipation structure, and combine... Figure 2a .

[0060] In this embodiment, the core 3 is bonded to the redistribution layer 71 by bottom filling. The core 3 is electrically connected to the redistribution layer 71 via microbumps 74.

[0061] Step S203: Solder the substrate 5 to the closed substrate 2 in the chip packaging heat dissipation structure, and combine them. Figure 2c .

[0062] Step S203 includes planting C4 bumps 75 (Controlled Collapse Chip Connection bumps) on the bottom surface of the closed substrate 2; and electrically connecting the substrate 5 to the chip package heat dissipation structure through the C4 bumps 75.

[0063] In a further optional embodiment of this embodiment, the step of electrically connecting the substrate 5 to the chip package heat dissipation structure via C4 bumps 75 includes: bottom filling the bottom of the closed substrate 2 to fix the closed substrate 2 to the upper surface of the substrate 5, the C4 bumps 75 abutting against the substrate 5, and the through silicon via structure 73 being electrically connected to the circuit on the substrate 5 via the C4 bumps 75.

[0064] In a further optional embodiment of this example, prior to the step of electrically connecting the substrate 5 to the chip package heat dissipation structure via C4 bumps 75, the fabrication method further includes: filling the first surface with EMC (Epoxy Molding Compound) to form a molding compound 72, combined with... Figure 2b .

[0065] In a further optional embodiment of this example, after step S203, the preparation method further includes: attaching reinforcing ribs 6 to the upper surface of the substrate 5, and soldering balls 76 to the back surface of the substrate 5, in combination with... Figure 2c .

[0066] In a further optional embodiment of this example, the preparation method further includes: steps S204 to S206, combined with... Figure 3 .

[0067] Step S204: Etch the top heat dissipation chamber 31 on the upper surface of the core 3.

[0068] Step S205: Fill the top heat dissipation chamber 31 with phase change material.

[0069] Step S206: Bond the closed top plate 4 to the upper surface of the core 3 to seal the opening of the top heat dissipation chamber 31.

[0070] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0071] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0072] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A chip packaging heat dissipation structure, characterized in that, The chip packaging heat dissipation structure includes: a silicon interposer and a closed substrate; The silicon interposer provides a first surface and a second surface opposite to each other. The first surface is used to load the chip. The silicon interposer has a bottom heat dissipation chamber formed on the second surface. The bottom heat dissipation chamber is filled with a phase change material. The closed substrate is bonded to the second surface of the silicon interposer and seals the opening of the bottom heat dissipation chamber on the second surface.

2. The chip packaging heat dissipation structure according to claim 1, characterized in that, The closed substrate is adapted to the second surface.

3. The chip packaging heat dissipation structure according to claim 2, characterized in that, The chip packaging heat dissipation structure also includes a through-silicon via structure; The through-silicon via structure penetrates the silicon interposer and the closed substrate, and is spaced apart from the bottom heat dissipation chamber.

4. The chip packaging heat dissipation structure according to claim 1, characterized in that, The chip package heat dissipation structure also includes: a redistribution layer; The redistribution layer is bonded to the first surface, and the silicon interposer is used to load the chip through the redistribution layer.

5. The chip package heat dissipation structure according to any one of claims 1 to 4, characterized in that, The phase change material includes: SnBi phase change alloy or GaInSn phase change alloy; The material of the closed substrate includes silicon.

6. A method for fabricating a chip package heat dissipation structure, characterized in that, The preparation method includes: Provides silicon interposer and closed substrate; A bottom heat dissipation chamber is etched out on one surface of the silicon interposer; A phase change material is filled into the bottom heat dissipation chamber; The closed substrate is bonded to the silicon interposer to seal the opening of the bottom heat dissipation chamber.

7. The preparation method according to claim 6, characterized in that, After the step of bonding the closed substrate to the silicon interposer to seal the opening of the bottom heat dissipation chamber, the fabrication method further includes: Silicon via etching is performed on the closed substrate and the silicon interposer to form a silicon via structure that penetrates the closed substrate and the silicon interposer.

8. The preparation method according to claim 6, characterized in that, Prior to the step of bonding the closed substrate to the silicon interposer to seal the opening of the bottom heat dissipation chamber, the fabrication method further includes: A redistribution layer is formed on the surface of the silicon interposer away from the closed substrate.

9. A heat-dissipating chip packaging structure, characterized in that, The heat-dissipating chip package structure includes: a chip and a chip package heat dissipation structure as described in any one of claims 1 to 5; The core is bonded to the first surface.

10. The heat-dissipating chip packaging structure according to claim 9, characterized in that, The heat-dissipating chip packaging structure also includes: a substrate; The closed substrate is welded to the base plate.

11. The heat-dissipating chip packaging structure according to claim 9, characterized in that, The heat-dissipating chip packaging structure further includes: a closed top plate; A top heat dissipation chamber is formed on the surface of the core particle away from the first surface, and the top heat dissipation chamber is filled with a phase change material; The closed top plate is bonded to the surface of the core away from the first surface and closes the opening of the top heat dissipation chamber on the core.

12. A method for fabricating a heat-dissipating chip packaging structure, characterized in that, The preparation method includes: The chip package heat dissipation structure is obtained by the preparation method according to any one of claims 6 to 8; Core particles are bonded to the first surface of the silicon interposer.

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