Shielding die for protecting integrated circuit dies in a multi-die package

Abstract

Embodiments of the present disclosure include a multi-die package that includes a shield die that covers a package die and inter-die connectivity signals. The shield die is conductively coupled to the package die, and in response to the shield die being tampered with or removed, certain functionality of the package die will be disabled, thereby preventing access to confidential or otherwise sensitive information by a potential attacker.

Description

Background Technology

[0001] New trends in integrated circuit manufacturing and packaging have led to the relocation of internal die signals to die boundaries and the upper metal layer, making these signals more vulnerable to physical probing attacks. Furthermore, die decomposition has shifted signals originally located within the die to semi-external buses, such as bridging circuit dies (e.g., Intel® Embedded Multi-Die Interconnect Bridge (EMIB)), further increasing their vulnerability. Existing solutions (e.g., cryptographic methods and internal interposer wiring) offer limited protection and fail to meet the comprehensive security requirements of signals routed in the upper metal layer, especially in multi-die configurations. Attached Figure Description

[0002] Figure 1 A side view of an example integrated circuit package including a shielded die, according to embodiments of this document, is shown.

[0003] Figure 2 It shows Figure 1 An exploded perspective view of an integrated circuit package.

[0004] Figure 3 A side view of another example integrated circuit package including a shielded die, according to embodiments of this document, is shown.

[0005] Figure 4 A side view of yet another example integrated circuit package including a shielded die, according to embodiments of this document, is shown.

[0006] Figure 5 It is a top view of a wafer having a die that may be included in any of the embodiments disclosed herein.

[0007] Figure 6 It can be a cross-sectional view of an integrated circuit device that can be included in any of the embodiments disclosed herein.

[0008] Figure 7 It can be a cross-sectional view of an integrated circuit device assembly that may be included in the embodiments disclosed herein.

[0009] Figure 8 It can be a block diagram of an example electrical device that may include any embodiment disclosed herein. Detailed Implementation

[0010] Advances in integrated circuit manufacturing and packaging have led to shifts in the layout of signals within the die. These signals are increasingly routed to die boundaries and overlying metal layers, making them more vulnerable to physical probing attacks. The trend of die decomposition further exacerbates this vulnerability, diverting signals that were originally located inside the die to semi-external buses, such as die-to-die bridging circuits (e.g., Intel® Embedded Multi-Die Interconnect Bridge (EMIB)), thereby increasing the risk of these signals being subjected to potential physical attack threats such as electromagnetic (EM) and photonic fault insertion, as well as contact and non-contact signal probing.

[0011] Existing solutions for protecting die-to-die signals include routing critical signals through internal interposers, which are more challenging to probe, or introducing cryptographic techniques such as authentication encryption. However, these approaches are limited in scope and do not provide a comprehensive solution for signals routed in the upper metal layer of the die, particularly those associated with technologies that provide back-side power transfer to the die (e.g., Intel® PowerVia technology). Current practice relies on specific methodologies and design-phase guidelines to mitigate the risk of physical attacks on these signals. Furthermore, active shielding techniques that utilize upper metal wiring to shield lower metal layer signal traces are limited to single-die protection and cannot be extended to multi-die packages (e.g., die-to-die signal protection). While shielding solutions exist implemented at the printed circuit board (PCB) level, these solutions do not provide protection at the package level. Back-side power transfer compatible dies typically employ passive “carrier wafers” for mechanical support, but these can be easily removed, exposing the underlying die.

[0012] This disclosure addresses these or other weaknesses by implementing a shielded die located above multiple integrated circuit dies in a multi-die package and providing comprehensive protection for the package dies and their inter-die connectivity. The shielded die can cover all package dies and inter-die connectivity signals, thereby providing a robust physical and technical barrier against probing attacks. The shielded die can be electrically connected to the package dies via a lower interposer underneath and / or can be directly connected to the dies (e.g., in a back-side power transfer embodiment).

[0013] Shielded dies and accompanying packages can be designed to prevent access to any confidential information or components within the package when the shielded die is removed or tampered with in some way, thus protecting sensitive information while still allowing secure debugging. For example, the packaged die can initiate a "block-on-debug" configuration to eliminate the use of secret values, delete secret values ​​or information (e.g., authentication information), keys or authentication certificates, or disable processing or other functions of one or more dies. This approach not only enhances the platform's security by reinforcing package components against physical attacks (e.g., side-channel and EM or laser fault insertion) but also maintains compatibility with existing packaging technologies, providing a cost-effective solution to pressing industry challenges.

[0014] Furthermore, the embodiments described herein allow for secure debugging of the package without exposing confidential aspects of the integrated circuit die or other components of the package when the shielded die is removed. Package-level debugging may require the removal of the shielded die to gain access to the packaged components. Therefore, in embodiments where "debug blocking" is activated by removing the shielded die, enhanced protection can be provided for the die or components during debugging operations.

[0015] Referring now to the accompanying drawings, which are not necessarily drawn to scale, similar or identical numerals may be used to label the same or similar parts in different drawings. The use of similar or identical numerals in different drawings does not imply that all drawings including similar or identical numerals constitute a single or identical embodiment. Identical numerals with different letter suffixes may represent different instances of similar parts. The accompanying drawings generally illustrate the various embodiments discussed in this document by way of example and not limitation.

[0016] It should be understood that the accompanying drawings show an idealized version of the structural cross-section. In an actual cross-section, the lines, layers, and other elements shown in the drawings may have shapes different from those shown. For example, a surface shown as a plane may have undulating, raised, or recessed features; sidewalls may taper towards the surface; 90-degree angles may be rounded; and lines, layers, and features may overlap more or less with those shown.

[0017] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding thereof. However, it will be apparent, however, that novel embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form for ease of description. All modifications, equivalents, and alternatives are intended to be covered within the scope of the claims.

[0018] Figure 1 A side view of an example integrated circuit package 100 including a shielded die, according to embodiments of this document, is shown. Figure 2 It shows Figure 1 An exploded perspective view of package 100. In some cases, package 100 may be referred to as a packaged integrated circuit component. Example package 100 includes a package substrate 102, wherein integrated circuit dies 106A-C are attached to the package substrate 102 via an interposer 104. Dies 106A-C may be packaged or unpackaged integrated circuit products, which include one or more integrated circuit dies (e.g., Figure 5 502 core, Figure 6 The integrated circuit structure 600 and / or one or more other suitable components. The die 106A-C may include one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processing unit (GPU), accelerator, chipset processor), I / O controller, memory, or network interface controller.

[0019] In some embodiments, die 106A-C may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. In addition to including one or more processor units, die 106A-C may also include additional components such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die including the processor unit.

[0020] The example package 100 also includes a shielding die 112 above each of the dies 106A-C, such that it covers the entire top side / upper surface of the die. While the example shielding die 112 covers the entire die beneath it, other embodiments may cover another portion of the entire package, for example, only a specific die (or portion of the die) of the package. As shown, the shielding die 112 may also cover additional areas of the package 100 beyond the outer edges of the dies 106A-C. As shown, one or more material layers 114 may be disposed between the dies 106A-C and the shielding die 112. In some embodiments, layer 114 may be a metal film that provides an additional passive barrier to reinforce the protection of the covered area from optical or electromagnetic detection threats (e.g., laser fault injection, laser detection, emission microscopy, EM fault insertion, etc.).

[0021] The shielded die 112 includes conductive (e.g., metallic) traces 113 that connect to vias in one or more of the dies 106A-C (e.g., via 107 in die 106C), vias within one or more interposers of the package (e.g., via 109 in interposer 108A), or vias within other structures of the package (e.g., via 111 in package wall structure 110). Interposer 104 includes traces providing electrical connections between respective dies, between one of the dies 106A-C and one of the interposers 108A-C, or between respective interposers in interposers 108A-C. In some embodiments, for example... Figure 1 In the illustrated embodiment, at least certain traces of trace 113 may substantially traverse the length of shielded die 112. As used herein, "substantially traverse" can mean that trace 113 extends across a large portion of the length of shielded die; for example, some traces of trace 113 may extend across more than 70% of the length of shielded die 112. This provides further security by minimizing areas of shielded die 112 that may be vulnerable to potential attacks. In certain embodiments, shielded die 112 includes only passive traces 113 and does not include circuit components such as resistors, capacitors, or any active components.

[0022] In some embodiments, example package 100 may be designed to be coupled to a circuit board (e.g., Figure 7 The circuit board 702 can be implemented as a motherboard or mainboard of a computer system. For example, the main circuit board can provide the die and other components of the computer system (e.g., memory, storage devices, network interfaces, peripherals, power supplies, etc.). Figure 8 Electrical connections between one or more of the components shown and described below. The main circuit board may include one or more traces and circuit components to provide interconnection between such computer system components.

[0023] like Figure 1 As shown, the shielded die 112 is electrically coupled to the package substrate 102 and the dies 106A-C via traces 113, and connections between traces 113 and dies 106A-C can be formed directly or indirectly. For example, some conductive connections can be indirectly formed between the shielded die 112 and one of the dies 106A-C by one or more of the following: traces in the package substrate 102, traces in the interposer 104, vias in the interposers 108A, 108B or 108C, and / or package wall structures 110 (which surround such as...) Figure 2 Each of the dies 106A-C in the package 100 shown, and which itself can be considered as a type of interposer, has a via. Furthermore, in some cases, the traces of the shielded die 112 can pass through the die (e.g., as shown in the diagram). Figure 1 The upper surface of the die 106C shown in the diagram is directly connected to the die. In embodiments implementing back-side power transfer technology, power can be transferred through traces 113 in the shielded die 112 to one or more of the dies (e.g., one of the traces 113 connected to the die 106C may be a power transfer signal).

[0024] The encapsulation wall structure 110 and the shielding die 112 provide a physical barrier for the dies 106A-C, thereby helping to prevent probing attacks to some extent. Additionally, the trace 113 of the shielding die 112 and / or the via 111 of the encapsulation wall structure 110 can be used to provide further protection for the dies 106A-C. Specifically, the dies 106A-C can be configured such that the signal provided through the trace 113 is necessary for proper operation. For example, in a particular embodiment, if the shielding die 112 is removed or the trace 113 of the shielding die 112 is destroyed (resulting in an open circuit in the circuitry including the trace 113), certain functions of the dies 106A-C can be partially or completely disabled. For example, in this case, confidential or other sensitive data processing functions of the die can be disabled, while other essential functions can be retained. This bifurcation of protection allows for the protection of sensitive data processed by the die or otherwise present in the die, while also allowing for safe commissioning of the die (e.g., when shielded die 112 is not attached to package 100).

[0025] As an example, shielded die 112 may provide traces for passing or otherwise transmitting specific signals between package dies, which would disable a specific function if the die detects the absence of said signal (indicating the removal, tampering, or destruction of shielded die 112). Shielded die 112 may, for example, pass static values ​​(e.g., binary (1 / 0) values ​​or other types of values) to the die to indicate the presence of shielded die 112 on the package. As another example, shielded die 112 may pass dynamic values ​​between package dies to indicate the presence of shielded die 112, such as passing an incrementing counter value expected to continuously increase during operation.

[0026] In some embodiments, shielded die 112 may contain information necessary for platform functionality (e.g., a package-specific identifier), and the die may need to obtain such information to provide full functionality. For example, shielded die 112 may include a unique value stored, for example, in a metal trace 113 (e.g., produced by laser cutting), which would enable shielded die 112 to be cryptographically paired with other dies in package 100. For example, the key may be split into two parts, one stored in a one-time programmable (OTP) memory inside the die, and the other on shielded die 112. Therefore, the key cannot be obtained or otherwise recovered if shielded die 112 is not present and connected. In some cases, the part of the key stored on shielded die 112 may not require confidentiality.

[0027] In some embodiments, die 106A-C may include logic for detecting changes in the electrical characteristics (e.g., resistance, capacitance, or inductance) of the circuitry in which the shielded die 112 is implemented. Tampering with the shielded die 112 (including minor alterations to the traces by an attacker without removing electrical connectivity) will result in a change in electrical characteristics (e.g., capacitance). When such a change is detected, the die can then disable a specific function in response to the detected capacitance change. This reduces the likelihood of an attacker thinning the upper portion of the shielded die 112 (while maintaining the connectivity of the trace 113) to be closer to the packaged die 106A-C.

[0028] The shielded die 112 and the package wall structure 110 can mitigate some physical attacks that require access to the packaged components during functional operation. This is due to the mechanical presence of the shielded die 112 (covering, for example, die-to-die connectivity), and because if the shielded die 112 connectivity is disrupted, malfunctions, or is removed, the function of the packaged die or other components is prevented or disabled. Furthermore, the mere presence of the shielding provided by the package wall structure 110 and the shielded die 112 forces attackers to place antennas or other attack tools at a greater distance from the packaged die, thus also hindering attacks that require access to the die but do not require full electrical connection (e.g., various electromagnetic (EM) radiation-based attacks).

[0029] Figure 3A side view of another example integrated circuit package 300 including shielded dies according to embodiments herein is shown. Package 300 is identical to package 100 described above, except that package 300 includes bridging circuit dies 105A, 105B in an interposer 104 to provide die-to-die connections. Specifically, bridging circuit die 105A interconnects dies 106A and 106B, while bridging circuit die 105B interconnects dies 106B and 106C. In a particular embodiment, bridging circuit dies 105A, 105B may be implemented as an Intel® Embedded Multi-Die Interconnect Bridge (EMIB). Shielded die 112 may provide protection against attacks to traces / circuit within bridging circuit dies 105A, 105B in the same manner as the protection provided to dies 106A-C.

[0030] Figure 4 A side view of yet another example integrated circuit package 400 including shielded dies according to embodiments herein is shown. Package 400 includes components similar to those of packages 100, 300, but does not include the interposer layer 104. For example, package 400 includes bridge circuit dies 105A, 105B within a package substrate 102, instead of... Figure 3 Bridge circuit chips 105A and 105B are shown in the intermediate layer 104.

[0031] Figure 5 This is a top view of a wafer 500 having a die 502 that may be included in any of the embodiments disclosed herein. The wafer 500 may be composed of semiconductor material and dies 502 having integrated circuit structures formed on the surface of the wafer 500. Each die 502 may be a repeating unit of an integrated circuit product including any suitable integrated circuit. After the semiconductor product is manufactured, the wafer 500 may undergo a singlet process in which the dies 502 are separated from each other to provide discrete “chips” of the integrated circuit product. The die 502 may be any of the dies 106A-C disclosed herein. The die 502 may include one or more transistors (e.g., discussed below). Figure 6The wafer 500 or die 502 may include a transistor 640, supporting circuitry for routing electrical signals to the transistor, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components that can be fabricated on the wafer. In some embodiments, the wafer 500 or die 502 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM), magnetic RAM (MRAM), resistive RAM (RRAM), conductive bridged RAM (CBRAM), etc.), logic gates (e.g., AND, OR, NAND, and NOR gates), or any other suitable circuit elements. Multiple devices and components may be combined on a single die. For example, a memory array formed by multiple memory devices may be formed on the same die as a processor unit or other logic configured to store information in the memory devices or execute instructions stored in the memory array.

[0032] Figure 6 This is a cross-sectional view of an integrated circuit structure 600 that can be included in any of the embodiments disclosed herein (e.g., in any of dies 106A-C). Multiple instances of the integrated circuit structure 600 can be included in die 502 ( Figure 5 The integrated circuit structure 600 can be formed on a die substrate 602. The die substrate 602 can be a semiconductor substrate made of semiconductor materials including, for example, n-type or p-type materials (or a combination of both). The die substrate 602 can include, for example, a crystalline substrate formed using bulk silicon or silicon-on-insulator (SOI) substructures. In some embodiments, the die substrate 602 can include a silicon layer on top of an SOI layer, wherein the bulk silicon is located below the SOI layer. In some embodiments, the die substrate 602 can be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, Group III-V, or Group IV can also be used to form the die substrate 602. Although some examples of materials that can form the die substrate 602 are described herein, any material that can be used as the basis for the integrated circuit structure 600 can be used. The die substrate 602 can be a monolithized die (e.g., Figure 5 502 die) or wafer (e.g., Figure 5 The portion of the 500 wafer.

[0033] The integrated circuit structure 600 may include a device layer 604 disposed on a die substrate 602. The device layer 604 may include features of a transistor 640 (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)) formed on the die substrate 602. The transistor 640 may include, for example, source and drain regions (S / D regions 620), a gate 622 for controlling current flow between the S / D regions 620, and S / D contacts 624 for routing electrical signals to and from the S / D regions 620. The transistor 640 may include additional features not shown for clarity, such as device isolation regions, gate contacts, etc. The transistor 640 is not limited to... Figure 6 The types and configurations shown can include a wide variety of other types and configurations, such as non-planar transistors or combinations of planar and non-planar transistors. Non-planar transistors can include FinFET transistors (e.g., dual-gate transistors or tri-gate transistors) and gate-around or fully-around transistors (e.g., nanoribbon, nanosheet, or nanowire transistors).

[0034] Transistor 640 may include a gate 622 formed of at least two layers (gate dielectric and gate electrode). The gate dielectric may include one or more layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material.

[0035] High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when using high-k materials, an annealing process may be performed on the gate dielectric to improve its quality.

[0036] The gate electrode can be formed on the gate dielectric and may include at least one p-type or n-type work function metal, depending on whether the transistor is a p-type metal-oxide-semiconductor (PMOS) transistor or an n-type metal-oxide-semiconductor (NMOS) transistor. In some embodiments, the gate electrode may consist of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a fill metal layer. Other metal layers, such as barrier layers, may be included for other purposes.

[0037] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metal discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metal discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0038] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of a gate stack (including a gate dielectric and a gate electrode) to be positioned on either side of the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming the sidewall spacers are well known in the art and typically include deposition and etching steps. In some embodiments, multiple pairs of sidewall spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0039] The S / D region 620 can be formed within a die substrate 602 adjacent to the gate 622 of the transistor 640. For example, the S / D region 620 can be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic can be implanted into the die substrate 602 to form the S / D region 620. An annealing process to activate the dopant and further diffuse it into the die substrate 602 can be performed after the ion implantation process. In the latter process, the die substrate 602 can be etched first to form a trench at the location of the S / D region 620. An epitaxial deposition process can then be performed to fill the trench with the material used to fabricate the S / D region 620. In some embodiments, a silicon alloy such as silicon-germanium or silicon carbide can be used to fabricate the S / D region 620. In some embodiments, the epitaxially deposited silicon alloy can be in-situ doped with dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials (e.g., germanium or group III-V materials or alloys) can be used to form the S / D region 620. In other embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D region 620.

[0040] One or more interconnect layers can be disposed on device layer 604 (in Figure 6The interconnect layers (shown as interconnect layers 606-610) route electrical signals, such as power and / or information-carrying signals (e.g., input / output (I / O) signals), to and from devices (e.g., transistor 640) in the device layer 604. For example, conductive components of the device layer 604 (e.g., gate 622 and S / D contact 624) may be electrically coupled to the interconnect structure 628 of the interconnect layers 606-610. One or more interconnect layers 606-610 may form a metallized stack 619 of the integrated circuit structure 600 (which may also be referred to as an "ILD stack" (interlayer dielectric stack)).

[0041] Interconnect structure 628 can be arranged within interconnect layers 606-610 to route electrical signals according to a variety of designs; specifically, the arrangement is not limited to... Figure 6 The specific configuration of the interconnect structure 628 shown. Although in Figure 6 A specific number of interconnect layers 606-610 are shown, but embodiments of this disclosure include integrated circuit structures having more or fewer interconnect layers than those shown.

[0042] In some embodiments, the interconnect structure 628 may include traces or lines 628a and / or vias 628b filled with a conductive material such as a metal. Line 628a may be arranged to route electrical signals in a direction substantially parallel to a plane on the die substrate 602 on which the device layer 604 is formed. For example, from Figure 6 From this perspective, line 628a can route electrical signals in the direction of entering and exiting the page and / or in the direction of passing through the page. Via 628b can be arranged to route electrical signals in a direction substantially perpendicular to the plane of the die substrate 602 on which the device layer 604 is formed. In some embodiments, lines 628a of different interconnect layers 606-610 are electrically coupled through via 628b.

[0043] Interconnect layers 606-610 may include a dielectric material 626, and interconnect structures 628 are disposed within the dielectric material 626, such as... Figure 6 As shown. In some embodiments, the dielectric material 626 in different interconnect layers 606-610 may have different compositions; in other embodiments, the composition of the dielectric material 626 in different interconnect layers 606-610 may be the same. Device layer 604 may include dielectric material 626, transistor 640 disposed within the dielectric material 626, and the bottom layer of the metallized stack located on the dielectric material 626. The dielectric material 626 as part of device layer 604 may have a different composition than the dielectric material 626 included in interconnect layers 606-610; in other embodiments, the composition of the dielectric material 626 in device layer 604 may be the same as the dielectric material 626 included in any of interconnect layers 606-610.

[0044] A first interconnect layer 606 (which may be referred to as metal 1 or “M1” layer) may be formed directly on device layer 604. In some embodiments, as shown, the first interconnect layer 606 may include a line 628a and / or a via 628b. The line 628a of the first interconnect layer 606 may be coupled to a contact (e.g., an S / D contact 624) of device layer 604. The via 628b of the first interconnect layer 606 may be coupled to a line 628a of the second interconnect layer 608.

[0045] The second interconnect layer 608 (which may be referred to as metal 2 or “M2” layer) may be formed directly on the first interconnect layer 606. In some embodiments, the second interconnect layer 608 may include vias 628b to couple lines 628a of the second interconnect layer 608 to lines 628a of the third interconnect layer 610. Although lines 628a and vias 628b are structurally distinguished by lines within the respective interconnect layers for clarity, in some embodiments, lines 628a and vias 628b may be structurally and / or materially continuous (e.g., simultaneously filled during a dual damascene process).

[0046] Based on similar techniques and configurations described in conjunction with the second interconnect layer 608 or the first interconnect layer 606, a third interconnect layer 610 (which may be referred to as metal 3 or “M3” layer) (and additional interconnect layers as needed) may be sequentially formed on the second interconnect layer 608. In some embodiments, the “higher” (i.e., farther from device layer 604) interconnect layers in the metallization stack 619 of the integrated circuit structure 600 may be thicker than the lower interconnect layers in the metallization stack 619, wherein lines 628a and vias 628b in the higher interconnect layers are thicker than lines 628a and vias 628b in the lower interconnect layers.

[0047] The integrated circuit structure 600 may include a solder resist material 634 (e.g., polyimide or a similar material) and conductive contacts 636 formed on a stack of interconnect layers 606-610. Figure 6 In this diagram, conductive contact 636 is shown in the form of a bonding pad. Conductive contact 636 may be electrically coupled to the topmost interconnect structure 628 of the metallized stack 619 and configured to route electrical signals between transistor 640 and components outside the integrated circuit structure 600. For example, solder joints may be formed on conductive contact 636 to mechanically and / or electrically couple integrated circuit components including integrated circuit structure 600 to another component (e.g., a printed circuit board). Integrated circuit structure 600 may include additional or alternative structures for routing electrical signals from interconnect layers 606-610; for example, conductive contact 636 may include other similar features (e.g., pillars) that can route electrical signals between transistor 640 and external components.

[0048] In some embodiments where the integrated circuit structure 600 is a dual-sided die portion, the integrated circuit structure 600 may include a second metallization stack (not shown) located on the side of the die substrate 602 opposite to the device layer 604. This second metallization stack may include multiple interconnect layers as discussed above with reference to interconnect layers 606-610. Through-silicon vias (TSVs) extending through the die substrate 602 may provide a conductive path from the transistor 640 to the second metallization stack, and the second metallization stack may electrically couple the TSVs to additional conductive contacts (not shown) located on the side of the integrated circuit structure 600 opposite to the conductive contact 636.

[0049] In some embodiments, the TSV extending through the die substrate 602 can be used to route power and ground signals from conductive contacts located on the side of the integrated circuit structure 600 opposite to conductive contacts 636 to transistor 640 and any other components integrated into the integrated circuit structure 600, and the metallization stack 619 can be used to route information-carrying signals from conductive contacts 636 to transistor 640 and any other components integrated into the integrated circuit structure 600. In other words, routing power and ground signals to transistor 640 (via the back-side or bottom-side metallization stack and TSV) can be separate from routing information-carrying signals to transistors. Power and ground signals are provided by the back-side or bottom-side metallization stack and TSV, and information-carrying signals are provided by the top-side metallization stack (e.g., metallization stack 619).

[0050] Several integrated circuit dies can be stacked with one or more TSVs in a stack of dies, thereby providing connectivity between one die and any of the other dies in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a substrate integrated circuit die, and the TSVs in the HBM dies can provide connectivity between the individual HBM dies and the substrate integrated circuit dies. Conductive contacts can provide additional connectivity between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).

[0051] Figure 7 This is a cross-sectional view of an integrated circuit device assembly 700. The integrated circuit device assembly 700 includes multiple components disposed on a circuit board 702 (which may be a motherboard, system board, mainboard, etc.). The integrated circuit device assembly 700 includes components disposed on a first surface 740 and a second surface 742 of the circuit board 702, with the second surface 742 opposite to the first surface 740. Typically, the components can be disposed on either or both of the first surface 740 and the second surface 742 of the circuit board 702.

[0052] In some embodiments, circuit board 702 may be a printed circuit board (PCB) comprising multiple metal (or interconnect) layers separated from each other by dielectric material layers and interconnected by conductive vias. Each metal layer includes conductive traces. The metal layers may be patterned to route electrical signals between components electrically coupled to circuit board 702. In other embodiments, circuit board 702 may be a non-PCB substrate. In some embodiments, circuit board 702 may be, for example, a package substrate 102 or a circuit board (e.g., a motherboard or motherboard) to which package substrate 102 is attached.

[0053] Figure 7 The illustrated integrated circuit device assembly 700 includes an on-intermediate package structure 736 coupled to a first side 740 of a circuit board 702 via a coupling member 716. The coupling member 716 electrically and mechanically couples the on-intermediate package structure 736 to the circuit board 702 and may include solder balls (e.g.,...). Figure 7 This includes pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a disk grid array (LGA), male and female parts of the socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure. (Therefore, the coupling component may include conductive contacts.)

[0054] The interposer-on-intercept (IPI) structure 736 may include an integrated circuit component 720 coupled to an interposer 704. The interposer 704 may provide an intermediate substrate for bridging the circuit board 702 and the integrated circuit component 720. The integrated circuit component 720 is coupled to the interposer 704 via a coupling member 718. The coupling member 718 may take any suitable form, such as the form discussed above with reference to coupling member 716. Although Figure 7 Only one integrated circuit component attached to the interposer is shown, but multiple integrated circuit components can be coupled to interposer 704. Additional interposers can be coupled to interposer 704.

[0055] Integrated circuit component 720 may be a packaged or unpackaged integrated circuit product, comprising one or more integrated circuit dies (e.g., Figure 5 The 502 die, including Figure 6The integrated circuit component 720 includes an integrated circuit structure 600 die and / or one or more other suitable components. The packaged integrated circuit component includes one or more integrated circuit dies mounted on a package substrate, wherein the integrated circuit die and the package substrate are encapsulated in a housing material such as metal, plastic, glass, or ceramic. In a non-packaged example of integrated circuit component 720, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to the interposer 704. Integrated circuit component 720 may include one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SoC), processor core, graphics processing unit (GPU), accelerator, chipset processor), I / O controller, memory, or network interface controller. In some embodiments, integrated circuit component 720 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0056] In embodiments where integrated circuit component 720 includes multiple integrated circuit dies, the dies may be of the same type (homogeneous multi-die integrated circuit component) or of two or more different types (heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0057] In addition to including one or more processor units, the integrated circuit component 720 may also include additional components such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separate from the integrated circuit die including the processor unit. These separate integrated circuit dies may be referred to as “die.” In embodiments where the integrated circuit component includes multiple integrated circuit dies, interconnections between the dies may be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (e.g., Intel® Embedded Multi-Die Interconnect Bridge (EMIB)), or combinations thereof.

[0058] Typically, interposer 704 can extend connections to wider or narrower pitches or reroute connections to different connections. For example, interposer 704 can couple a coupling component 718 with a first pitch to a coupling component 716 with a pitch wider than the first pitch. Figure 7In the illustrated embodiment, integrated circuit component 720 and circuit board 702 are attached to opposite sides of interposer 704. In other embodiments, integrated circuit component 720 and circuit board 702 may be attached to the same side of interposer 704. In some embodiments, three or more components may be interconnected via interposer 704.

[0059] In some embodiments, the interposer 704 may be formed as a PCB, comprising a plurality of metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 704 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some embodiments, the interposer 704 may be formed of alternative rigid or flexible materials, which may include the same materials described above for semiconductor substrates (e.g., silicon, germanium, and other Group III-V and IV materials). The interposer 704 may include metal interconnects 708 and vias, including but not limited to vias 710-1 (which extend from a first side 750 of the interposer 704 to a second side 754 of the interposer 704), blind vias 710-2 (which extend from a first side 750 or a second side 754 of the interposer 704 to an inner metal layer), and buried vias 710-3 (which connect to an inner metal layer).

[0060] In some embodiments, interposer 704 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer can connect connections on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, interposer 704 including the silicon interposer may further include one or more wiring layers to route connections on the first side of interposer 704 to an opposite second side of interposer 704.

[0061] In some embodiments, the interposer 704 and the circuit board 702 may comprise an amorphous solid layer of glass (which may be referred to as a glass core or glass substrate). In some embodiments, the glass layer may comprise silica (including silicon dioxide (SiO2)), fused silica, aluminosilicates (including alumina (Al2O3) and silicon dioxide), borosilicates (including silicon dioxide and boron trioxide (B2O3)), or aluminoborosilicates (including alumina, silicon dioxide, and boron trioxide). In some embodiments, the glass layer may comprise one or more of the following additives: alumina, boron trioxide, magnesium oxide (MgO), calcium oxide (CaO), strontium oxide (SrO), barium oxide (BaO), tin oxide (IV) (SnO2), nitrous oxide (N2O), potassium oxide (K2O), phosphorus trioxide (P2O3), zirconium dioxide (ZrO2), lithium oxide (Li2O), titanium, and zinc. In some embodiments, the glass layer may include silicon and oxygen, and one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass layer comprises at least 23% silicon by weight, at least 26% oxygen by weight, and at least 5% aluminum by weight. In some embodiments, the glass layer does not include organic binders or organic materials. For example, the glass layer is not a substrate or board comprising glass fibers and epoxy resin binders, such as a printed circuit board (PCB) comprising multiple metal (or interconnect) layers separated from each other by dielectric material layers (e.g., FR-4 or other glass fiber reinforced epoxy resin laminates) and interconnected by conductive vias.

[0062] In some embodiments, the glass layer has a thickness ranging from about 50 micrometers to about 1.4 millimeters. In some embodiments, the glass layer is a multilayer glass substrate (coreless substrate) or a portion of a multilayer glass substrate (coreless substrate). Individual glass layers in a multilayer glass substrate may have a thickness ranging from about 25 micrometers to about 50 micrometers. In some embodiments, the glass layer may have a length on one side ranging from about 10 millimeters to about 250 millimeters (e.g., it may have an area ranging from about 10 mm x 10 mm to about 250 mm x 250 mm). In some embodiments, the glass layer comprises a rectangular prism volume in which segments or portions (e.g., through-glass vias) are removed and filled with other metals (e.g., metallic).

[0063] In some embodiments, the redistribution layer (RDL) may be located on either side or both sides of the glass layer to provide a conductive path from the top and / or bottom surface of the interposer 704 or the circuit board 702 to the glass layer. The glass layer may include through-glass vias (TGVs) that extend through the glass layer to provide a conductive path through the glass core, glass substrate, or glass layer.

[0064] Intermediate layer 704 may also include embedded devices 714, including passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on intermediate layer 704. The on-intermediate package structure 736 may take the form of any on-intermediate package structure known in the art.

[0065] The integrated circuit device assembly 700 may include an integrated circuit component 724 coupled to a first surface 740 of the circuit board 702 via a coupling member 722. The coupling member 722 may take the form of any of the embodiments discussed above with reference to the coupling member 716, and the integrated circuit component 724 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 720.

[0066] Figure 7 The illustrated integrated circuit device assembly 700 also includes a stacked package structure 734 coupled to a second side 742 of a circuit board 702 via a coupling member 728. The stacked package structure 734 may include integrated circuit components 726 and 732 coupled together via a coupling member 730, such that integrated circuit component 726 is disposed between the circuit board 702 and integrated circuit component 732. The coupling members 728 and 730 may take the form of any embodiment of the coupling member 716 discussed above, and integrated circuit components 726 and 732 may take the form of any embodiment of the integrated circuit component 720 discussed above. The stacked package structure 734 can be configured according to any stacked package structure known in the art.

[0067] Figure 8 This is a block diagram of an example electrical device 800 that may include any microelectronic components disclosed herein. For example, any suitable component of the electrical device 800 may include embodiments of this disclosure, including one or more of packages 100, 300, 400, integrated circuit device assembly 700, integrated circuit component 720, integrated circuit structure 600, integrated circuit die 502, or other aspects disclosed herein. Multiple components in... Figure 8 The components are shown as included in electrical device 800, but any one or more of these components may be omitted or duplicated, depending on the application. In some embodiments, some or all of the components included in electrical device 800 may be attached to one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are manufactured onto a single system-on-a-chip (SoC) die.

[0068] Additionally, in various embodiments, electrical equipment 800 may not include... Figure 8 The electrical device 800 may include one or more components, but may also include interface circuitry for coupling to one or more components. For example, the electrical device 800 may not include display device 806, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 806 may be coupled. In another set of examples, the electrical device 800 may not include audio input device 824 or audio output device 808, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which audio input device 824 or audio output device 808 may be coupled.

[0069] Electrical device 800 may include one or more processor units 802. As used herein, the terms “processor unit,” “processing unit,” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. One or more processor units 802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processing units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor unit. Thus, a processor unit may be referred to as an XPU (or xPU).

[0070] Electrical device 800 may include memory 804, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memory), solid-state memory, and / or hard disk drive. In some embodiments, memory 804 may include memory located on the same integrated circuit die as one or more processor units 802. The memory may be used as cache memory (e.g., L1 cache, L2 cache, L3 cache, L4 cache, last level cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0071] In some embodiments of the electrical device 800, a first processor unit in one or more processor units 802 may be heterogeneous or asymmetric with a second processor unit in one or more processor units 802 in the electrical device 800. There may be various differences between the one or more processor units 802 in the system in a range of performance metrics, including architecture, microarchitecture, thermal, power consumption characteristics, etc. These differences can effectively manifest themselves as asymmetry and heterogeneity between the one or more processor units 802 in the electrical device 800.

[0072] In some embodiments, electrical device 800 may include a communication component 812. For example, communication component 812 may manage wireless communication for transmitting data to and from electrical device 800. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation via a non-solid medium. The term "wireless" does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires.

[0073] Communication component 812 can implement any of a variety of wireless standards or protocols, including but not limited to IEEE standards (including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments)), Long Term Evolution (LTE) projects, and any amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as “3GPP2”), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks; the acronym stands for Global Microwave Access Interoperability, a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. Communication component 812 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. Communication component 812 may operate according to GSM Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication component 812 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, as well as any other wireless protocol designated as 3G, 4G, 5G, and above. In other embodiments, communication component 812 may operate according to other wireless protocols. Electrical device 800 may include antenna 822 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0074] In some embodiments, communication component 812 can manage wired communication, such as electrical, optical, or any other suitable communication protocol (e.g., the IEEE 802.3 Ethernet standard). In some embodiments, electrical device 800 includes multiple communication components. For example, a first communication component may be dedicated to short-range wireless communication, such as Wi-Fi or Bluetooth, and a second communication component may be dedicated to long-range wireless communication, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication component may be dedicated to wireless communication, and the second communication component may be dedicated to wired communication.

[0075] Electrical device 800 may include battery / power circuit 814. Battery / power circuit 814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of electrical device 800 to an energy source (e.g., AC mains power) separate from electrical device 800.

[0076] Electrical device 800 may include display device 806 (or corresponding interface circuitry, as discussed above). Display device 806 may include one or more embedded or wired or wirelessly connected external visual indicators, such as head-up displays, computer monitors, projectors, touch screen displays, liquid crystal displays (LCDs), light-emitting diode displays, or flat panel displays.

[0077] Electrical device 800 may include audio output device 808 (or corresponding interface circuitry, as discussed above). Audio output device 808 may include any embedded or wired or wirelessly connected external device that generates audible indicators, such as a speaker, headphones, or earbuds.

[0078] Electrical device 800 may include audio input device 824 (or corresponding interface circuitry, as discussed above). Audio input device 824 may include any embedded or wired or wirelessly connected device that generates signals representing sound, such as a microphone, microphone array, or digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output). Electrical device 800 may include Global Navigation Satellite System (GNSS) equipment (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. GNSS device 818 may communicate with satellite-based systems and may determine the geographical location of electrical device 800 based on information received from one or more GNSS satellites, as is known in the art.

[0079] Electrical device 800 may include other output devices 810 (or corresponding interface circuitry, as discussed above). Examples of other output devices 810 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0080] Electrical device 800 may include other input devices 820 (or corresponding interface circuitry, as discussed above). Examples of other input devices 820 may include accelerometers, gyroscopes, compasses, image capture devices (e.g., monocular or stereo cameras), trackballs, touchpads, keyboards, cursor control devices such as mice, styluses, touchscreens, proximity sensors, microphones, barcode readers, quick-response (QR) code readers, electrocardiogram (ECG) sensors, PPG (photoplethysmography) sensors, skin conductance sensors, any other sensors, or radio frequency identification (RFID) readers.

[0081] Electrical device 800 can have any form factor, such as handheld or mobile electrical devices (e.g., cellular phones, smartphones, mobile internet devices, music players, tablet computers, laptop computers, 2-in-1 convertible computers, portable all-in-one computers, netbook computers, ultrabook computers, personal digital assistants (PDAs), ultra-mobile personal computers, portable game consoles), desktop electrical devices, servers, rack-mounted computing solutions (e.g., blade, tray, or skid-mounted computing systems), workstations or other networked computing components, printers, scanners, monitors, set-top boxes, entertainment control units, stationary game consoles, smart TVs, vehicle control units, digital cameras, digital video recorders, wearable electrical devices, or embedded computing systems (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or device, or manufacturing equipment). In some embodiments, electrical device 800 can be any other electronic device that processes data. In some embodiments, electrical device 800 can include multiple discrete physical components. Given that electrical device 800 can be categorized as a range of devices in various embodiments, in some embodiments, electrical device 800 can be referred to as a computing device or computing system.

[0082] As used herein, “connection” can indicate that elements are in direct physical or electrical contact with each other, and “coupling” can indicate that elements cooperate or interact with each other, but the elements may be in direct physical or electrical contact or may not be in direct physical or electrical contact. Furthermore, the terms “comprising,” “including,” “having,” etc., as used with respect to embodiments of this disclosure are synonymous. Terms modified by the word “substantially” include arrangements, orientations, spacing, or positions that differ slightly in meaning from the unmodified terms. For example, a layer, surface, or feature referred to as substantially parallel can refer to a layer, surface, or feature that is parallel to each other by a few degrees, and a layer, surface, or feature referred to as substantially perpendicular to each other can refer to a feature that is perpendicular to each other by + / -15 degrees.

[0083] As used herein, the phrase “located” in the context of a first layer or component being located on a second layer or component means that the first layer or component is directly and physically attached to the second layer or component (with no layer or component between the first layer or component and the second layer or component) or is physically attached to the second layer or component through one or more intermediate layers or components. As used herein, the term “adjacent” means layers or components arranged immediately next to each other (e.g., side by side, vertically).

[0084] Certain terms may also be used herein for reference only and are therefore not intended to be restrictive. For example, terms such as “upper,” “lower,” “above,” “below,” “bottom,” and “top” refer to directions of reference in the accompanying drawings. Terms such as “front,” “back,” “back,” and “side” describe the orientation and / or position of layers, components, parts of components, etc., within a consistent but arbitrary frame of reference, as becomes clear from the text describing the layers, components, parts of components, etc., discussed and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words with similar meanings. Furthermore, “first,” “second,” “third,” etc., describe common objects and indicate different instances of the same object referred to. Such adjectives do not imply that the objects so described must be in a given sequence in time or space, in order, or in any other way.

[0085] As used herein, the term "integrated circuit component" refers to a packaged or unpackaged integrated circuit product. A packaged integrated circuit component includes one or more integrated circuit dies mounted on a package substrate, wherein the integrated circuit die and the package substrate are encapsulated in a housing material such as metal, plastic, glass, or ceramic. In one example, a packaged integrated circuit component includes one or more processor units mounted on a substrate, wherein the outer surface of the substrate includes a ball grid array (BGA). In one example of an unpackaged integrated circuit component, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to a printed circuit board. An integrated circuit component may include one or more of any computing system components or any other computing system components described or referenced herein, such as processor units (e.g., system-on-a-chip (SoC), processor core, graphics processing unit (GPU), accelerator, chipset processor), I / O controllers, memory, or network interface controllers.

[0086] As used herein, the phrase "conductive coupling" refers to one or more conductive paths existing between components described as conductively coupled. For example, see reference... Figure 1 Due to the presence of conductive paths through the packaging substrate 102 and the interposer 104 (e.g., through vias 111, 109 and 107), the shield die 112 is electrically coupled to the dies 106A-C.

[0087] As used in this application and claims, a list of items connected by the term "and / or" can represent any combination of the listed items. For example, the phrase "A, B and / or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C. Similarly, as used in this application and claims, a list of items connected by the term "at least one" can represent any combination of the listed items. For example, the phrase "at least one of A, B, or C" can mean A; B; C; A and B; A and C; B and C; or A, B and C. Furthermore, as used in this application and claims, a list of items connected by the term "one or more" can represent any combination of the listed items. For example, the phrase "one or more of A, B, and C" can mean A; B; C; A and B; A and C; B and C; or A, B and C.

[0088] The disclosed methods, apparatuses, and systems should not be construed as limiting in any way. Rather, this disclosure relates to all novel and non-obvious features and aspects, individually and in various combinations and sub-combinations of the disclosed embodiments. The disclosed methods, apparatuses, and systems are not limited to any particular aspect or feature or combination thereof, nor are the disclosed embodiments required to provide any one or more particular advantages or to solve any one or more particular problems.

[0089] This document is provided with reference to the operational, scientific, or other theoretical descriptions of the apparatuses or methods presented in this disclosure for the purpose of better understanding and is not intended to be limiting. The apparatuses and methods in the appended claims are not limited to those that operate in a manner described by such operational theories.

[0090] Although the operations of some of the disclosed methods are described in a specific sequential order for ease of illustration, it should be understood that this description includes rearrangement unless the specific language used herein requires a particular order. For example, in some cases, the sequentially described operations may be rearranged or performed concurrently. Furthermore, for the sake of simplicity, the accompanying figures may not show the various ways in which the disclosed methods can be used in conjunction with other methods.

[0091] Specific details have been set forth in the foregoing description, but embodiments of the described techniques may be practiced without each of these specific details. Well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the understanding of this specification. Phrases such as “embodiment,” “various embodiments,” “some embodiments,” etc., may include features, structures, or characteristics, but not every embodiment necessarily includes a particular feature, structure, or characteristic. Embodiments of this disclosure may have some, all, or none of the features described in the examples described herein.

[0092] The following examples relate to additional embodiments of the techniques disclosed herein.

[0093] Example 1 is an apparatus comprising: a packaging substrate; a first integrated circuit die coupled to the packaging substrate; a second integrated circuit die coupled to the packaging substrate; and a die coupled to and covering the first and second integrated circuit dies; wherein the function of the first or second integrated circuit die is based on the conductive coupling of the first and second integrated circuit dies to the die (e.g., the first and second integrated circuit dies are conductively coupled through at least one metal trace in the die covering the first and second integrated circuit dies).

[0094] Example 2 includes the apparatus according to Example 1, wherein a first integrated circuit die or a second integrated circuit die is used to modify (e.g., disable) a function based on the detection that a circuit including at least one metal trace is open.

[0095] Example 3 includes the apparatus according to Example 1 or 2, wherein a first integrated circuit die or a second integrated circuit die is used to delete specific data based on the detection that a circuit including at least one metal trace is open.

[0096] Example 4 includes an apparatus according to any one of Examples 1-3, wherein a first integrated circuit die is used to transmit a signal to a second integrated circuit die via at least one metal trace, and the function of the second integrated circuit die is based on receiving a signal from the first integrated circuit die.

[0097] Example 5 includes the apparatus according to Example 4, wherein the signal includes a static value.

[0098] Example 6 includes the apparatus according to Example 4, wherein the signal includes an incrementing counter value.

[0099] Example 7 includes an apparatus according to any one of Examples 1-3, wherein a first integrated circuit die or a second integrated circuit die is used to obtain a value based on information stored in at least one metal trace, and the function of the first integrated circuit die or the function of the second integrated circuit die is based on obtaining a value from at least one metal trace.

[0100] Example 8 includes the apparatus according to Example 7, wherein the value stored in at least one metal trace includes a package identifier.

[0101] Example 9 includes the apparatus according to Example 7, wherein the value stored in at least one metal trace includes at least a portion of a key or a cryptographic key share.

[0102] Example 10 includes an apparatus according to any one of Examples 1-3, wherein a first integrated circuit die or a second integrated circuit die is used to detect changes in one or more electrical characteristics of a circuit including at least one metal trace, and the function of the first integrated circuit die or the function of the second integrated circuit die is modified based on the detection of one or more changes in electrical characteristics.

[0103] Example 11 includes an apparatus according to any one of Examples 1-10, wherein a first integrated circuit die and a second integrated circuit die are used to maintain a specific function based on the detection that a circuit including at least one metal trace is open.

[0104] Example 12 includes an apparatus according to any one of Examples 1-11, wherein the die extends beyond the outer edges of the first integrated circuit die and the second integrated circuit die.

[0105] Example 13 includes an apparatus according to any one of Examples 1-12, wherein at least one metal trace substantially traverses the length of the die.

[0106] Example 14 includes an apparatus according to any one of Examples 1-13, wherein at least one metal trace is electrically coupled to the first integrated circuit die or the second integrated circuit die via a die-opposite side of the first integrated circuit die or a die-opposite side of the second integrated circuit die.

[0107] Example 15 includes the apparatus according to Example 14, wherein at least one metal trace is electrically coupled to a first integrated circuit die or a second integrated circuit die via a metal trace in a package substrate.

[0108] Example 16 includes the apparatus according to Example 14, wherein at least one metal trace is electrically coupled to a first integrated circuit die or a second integrated circuit die through a metal trace in an interlayer between a package substrate and an integrated circuit die.

[0109] Example 17 includes the apparatus according to any one of Examples 1-16, and further includes a metal layer between the first integrated circuit dies or between the second integrated circuit dies.

[0110] Example 18 includes the apparatus according to any one of Examples 1-17, and further includes an interposer surrounding an integrated circuit die, the interposer including a via electrically coupling at least one metal trace to a first integrated circuit die or a second integrated circuit die.

[0111] Example 19 includes the apparatus according to any one of Examples 1-18, wherein the die does not include active circuit components.

[0112] Example 20 includes the apparatus according to any one of Examples 1-19, and further includes a circuit board, to which a package substrate is coupled.

[0113] Example 21 is a system including an integrated circuit package, the integrated circuit package comprising: a package substrate; a plurality of integrated circuit dies coupled to the package substrate; and a die covering the plurality of integrated circuit dies, the die including metal traces conductively coupled to the plurality of integrated circuit dies; wherein the function of at least one of the plurality of integrated circuit dies is based on conductive coupling with the metal traces of the die above the plurality of integrated circuit dies.

[0114] Example 22 includes the system according to Example 21, wherein the function of at least one integrated circuit die is modified based on the detection that the circuit including at least one metal trace of the die is open.

[0115] Example 23 includes a system according to Example 21 or 22, wherein at least one integrated circuit die is used to delete specific data based on the detection that a circuit including at least one metal trace of the die is open.

[0116] Example 24 includes a system according to any one of Examples 21-23, wherein a first integrated circuit die is used to transmit a signal to a second integrated circuit die via at least one metal trace on the die, and the function of the second integrated circuit die is based on receiving a signal from the first integrated circuit die.

[0117] Example 25 includes the system according to Example 24, wherein the signal includes a static value.

[0118] Example 26 includes the system according to Example 24, wherein the signal includes an incrementing counter value.

[0119] Example 27 includes a system according to any one of Examples 21-23, wherein at least one integrated circuit die is used to obtain a value based on information stored in a metal trace of the die, and the function of at least one integrated circuit die is based on obtaining the value.

[0120] Example 28 includes the system according to Example 27, wherein the value stored in the metal traces of the die includes a package identifier.

[0121] Example 29 includes the system according to Example 27, wherein the value stored in the metal traces of the die includes at least a portion or share of the key.

[0122] Example 30 includes a system according to any one of Examples 21-23, wherein at least one integrated circuit die is used to detect changes in one or more electrical characteristics of a circuit including a metal trace of the die, and the function of at least one integrated circuit die is modified based on the detection of one or more changes in electrical characteristics.

[0123] Example 31 includes a system according to any one of Examples 21-30, wherein at least one integrated circuit die is used to maintain a specific function based on the detection that a circuit including a metal trace of the die is open.

[0124] Example 32 includes a system according to any one of Examples 21-31, wherein the die extends beyond the outer edge of each of the plurality of integrated circuit dies.

[0125] Example 33 includes a system according to any one of Examples 21-32, wherein the metal traces of the die substantially traverse the length of the die.

[0126] Example 34 includes a system according to any one of Examples 21-33, wherein the metal traces of the die are electrically coupled to the integrated circuit die on the side opposite to the die.

[0127] Example 35 includes the system according to Example 34, wherein the metal traces of the die are electrically coupled to the integrated circuit die through the packaging substrate.

[0128] Example 36 includes the system according to Example 34, wherein the metal traces of the die are electrically coupled to the integrated circuit die through an interlayer between the packaging substrate and the integrated circuit die.

[0129] Example 37 includes a system according to any one of Examples 21-36, wherein the integrated circuit package further includes a metal layer between the die and at least one integrated circuit die.

[0130] Example 38 includes a system according to any one of Examples 21-37, wherein the integrated circuit package further includes an interposer layer surrounding a plurality of integrated circuit dies, the interposer layer including vias that electrically couple at least one metal trace of the die to the integrated circuit dies in the plurality of integrated circuit dies.

[0131] Example 39 includes a system according to any one of Examples 21-38, wherein the die does not include active circuit components.

[0132] Example 40 includes the system described in any of Examples 21-32, and also includes a circuit board to which an integrated circuit package is coupled.

[0133] Example 41 includes the system according to Example 40, and further includes a power delivery circuit coupled to a circuit board, the power delivery circuit being coupled to at least one integrated circuit die via one or more metal traces of the die.

[0134] Example 42 is an integrated circuit device assembly comprising: a circuit board; an interposer coupled to the circuit board; a plurality of integrated circuit components coupled to the interposer; and a die coupled to and physically shielding the plurality of integrated circuit components, the die covering each of the plurality of integrated circuit components and including metal traces interconnecting a first integrated circuit component of the plurality of integrated circuit components with a second integrated circuit component of the plurality of integrated circuit components.

[0135] Example 43 includes an integrated circuit device assembly according to Example 42, wherein the function of a first integrated circuit component or a second integrated circuit component is based on conductive coupling between the first integrated circuit component and the second integrated circuit component via metal traces.

[0136] Example 44 includes an integrated circuit device assembly according to Example 42 or 43, wherein a first integrated circuit component or a second integrated circuit component is used to delete data based on the detection that a circuit including a metal trace of a die is open.

[0137] Example 45 includes an integrated circuit device assembly according to any one of Examples 42-44, wherein a first integrated circuit component is used to transmit signals to a second integrated circuit component via metal traces, and the function of the second integrated circuit component is based on receiving signals from the first integrated circuit component.

[0138] Example 46 includes an integrated circuit device assembly according to Example 45, wherein the signal includes a static value.

[0139] Example 47 includes an integrated circuit device assembly according to Example 45, wherein the signal includes an incrementing counter value.

[0140] Example 48 includes an integrated circuit device assembly according to any one of Examples 42-44, wherein a first integrated circuit component or a second integrated circuit component is used to obtain a value based on information stored in a metal trace of the die, and the function of the first integrated circuit component or the function of the second integrated circuit component is based on the value obtained from the metal trace.

[0141] Example 49 includes an integrated circuit device assembly according to Example 48, wherein the values ​​stored in the metal traces include a package identifier.

[0142] Example 50 includes an integrated circuit device assembly according to Example 48, wherein the value stored in the metal trace includes at least a portion or share of a key.

[0143] Example 51 includes an integrated circuit device assembly according to any one of Examples 42-44, wherein a first integrated circuit component or a second integrated circuit component is used to detect changes in one or more electrical characteristics of a circuit including metal traces, and the function of the first integrated circuit component or the second integrated circuit component is modified based on the detection of one or more changes in electrical characteristics.

[0144] Example 52 includes an integrated circuit device assembly according to any one of Examples 42-51, wherein a first integrated circuit component and a second integrated circuit component are used to maintain a specific function based on the detection that a circuit including a metal trace is open.

[0145] Example 53 is a system comprising: a circuit board; and an integrated circuit package coupled to the circuit board, the integrated circuit package comprising: a packaging substrate; a plurality of integrated circuit dies coupled to the packaging substrate; and a die covering the plurality of integrated circuit dies, the die including metal traces conductively coupled to the plurality of integrated circuit dies; wherein at least one of the plurality of integrated circuit dies is conductively coupled to the metal traces of the die above the plurality of integrated circuit dies.

[0146] Example 54 includes the system according to Example 53, wherein the function of at least one integrated circuit die is modified based on the detection that the circuit including at least one metal trace of the die is open.

[0147] Example 55 includes a system according to Example 53 or 54, wherein at least one integrated circuit die is used to delete specific data based on the detection that a circuit including at least one metal trace of the die is open.

[0148] Example 56 includes a system according to any one of Examples 53-55, wherein a first integrated circuit die is used to transmit a signal to a second integrated circuit die via at least one metal trace on the die, and the function of the second integrated circuit die is based on receiving a signal from the first integrated circuit die.

[0149] Example 57 includes a system according to any one of Examples 53-55, wherein at least one integrated circuit die is used to obtain a value based on information stored in a metal trace of the die, and the function of at least one integrated circuit die is based on obtaining the value.

Claims

1. An apparatus comprising: Packaging substrate; A first integrated circuit die is coupled to the packaging substrate; A second integrated circuit die is coupled to the packaging substrate; as well as A die, coupled to and covering the first integrated circuit die and the second integrated circuit die; The function of the first integrated circuit die or the function of the second integrated circuit die is based on the conductive coupling between the first integrated circuit die and the second integrated circuit die and the die.

2. The apparatus according to claim 1, wherein, The first integrated circuit die and the second integrated circuit die are electrically coupled through metal traces in the die covering the first integrated circuit die and the second integrated circuit die.

3. The apparatus according to claim 1, wherein, The first integrated circuit die or the second integrated circuit die is used to modify the function based on the detection that the circuit including the metal trace of the die is open.

4. The apparatus according to claim 1, wherein, The first integrated circuit die or the second integrated circuit die is used to delete specific data based on the detection that a circuit including the metal trace of the die is open.

5. The apparatus according to claim 1, wherein, The first integrated circuit die is used to transmit a signal to the second integrated circuit die through at least one metal trace of the die, and the function of the second integrated circuit die is based on receiving the signal from the first integrated circuit die.

6. The apparatus according to claim 5, wherein, The signal includes a static value or an incrementing counter value.

7. The apparatus according to claim 1, wherein, The first integrated circuit die or the second integrated circuit die is used to obtain a value based on information stored in the die, and the function of the first integrated circuit die or the function of the second integrated circuit die is based on obtaining the value from the die.

8. The apparatus according to claim 7, wherein, The values ​​stored in the die include a package identifier, at least a portion of a key, or a share of a key.

9. The apparatus according to claim 1, wherein, The first integrated circuit die or the second integrated circuit die is used to detect changes in one or more electrical characteristics of a circuit including the metal traces of the die, and the function of the first integrated circuit die or the function of the second integrated circuit die will be modified based on the detection of the changes in the one or more electrical characteristics.

10. The apparatus according to claim 1, wherein, The first integrated circuit die and the second integrated circuit die are used to maintain a specific function based on the detection that the circuit including the metal trace of the die is open.

11. The apparatus according to claim 1, wherein, The die extends beyond the outer edges of the first integrated circuit die and the second integrated circuit die.

12. The apparatus according to claim 1, wherein, The at least one metal trace substantially traverses the length of the die.

13. The apparatus according to claim 1, wherein, The at least one metal trace is electrically coupled to the first integrated circuit die or the second integrated circuit die via the side of the first integrated circuit die opposite to the die or the side of the second integrated circuit die opposite to the die.

14. The apparatus according to claim 13, wherein, The at least one metal trace is electrically coupled to the first integrated circuit die or the second integrated circuit die through the metal trace in the packaging substrate.

15. The apparatus according to claim 1, wherein, The at least one metal trace is electrically coupled to the first integrated circuit die or the second integrated circuit die through a metal trace in the interlayer between the packaging substrate and the integrated circuit die.

16. The apparatus according to any one of claims 1-15, further comprising a metal layer between the first integrated circuit die and the die or between the second integrated circuit die and the die.

17. The apparatus of any one of claims 1-15, further comprising an interposer layer surrounding the first integrated circuit die and the second integrated circuit die, the interposer layer comprising vias conductively coupling the metal traces of the die to the first integrated circuit die or the second integrated circuit die.

18. A system comprising: Circuit board; as well as An integrated circuit package, coupled to the circuit board, the integrated circuit package comprising: Packaging substrate; Multiple integrated circuit dies are coupled to the packaging substrate; and A die, covering the plurality of integrated circuit dies, the die including metal traces conductively coupled to the plurality of integrated circuit dies; Wherein, at least one of the plurality of integrated circuit dies is electrically coupled to the metal trace of the die above the plurality of integrated circuit dies.

19. The system according to claim 18, wherein, The functionality of the at least one integrated circuit die will be modified based on the detection that the circuit including at least one metal trace of the die is open.

20. The system according to claim 18, wherein, The at least one integrated circuit die is used to delete specific data based on the detection that a circuit including at least one metal trace of the die is open.

21. The system according to any one of claims 18-20, wherein, The first integrated circuit die is used to transmit signals to the second integrated circuit die through at least one metal trace on the die, and the function of the second integrated circuit die is based on receiving the signals from the first integrated circuit die.

22. The system according to any one of claims 18-20, wherein, The at least one integrated circuit die is used to obtain a value based on information stored in the metal traces of the die, and the function of the at least one integrated circuit die is based on obtaining the value.

23. An integrated circuit device assembly, comprising: Circuit board; Intermediate layer, coupled to the circuit board; Multiple integrated circuit components are coupled to the intermediary layer; A die coupled to and physically shielding the plurality of integrated circuit components, the die covering each of the plurality of integrated circuit components and including metal traces interconnecting a first integrated circuit component and a second integrated circuit component among the plurality of integrated circuit components.

24. The integrated circuit device assembly of claim 23, wherein, The function of the first integrated circuit component or the function of the second integrated circuit component is based on the conductive coupling between the first integrated circuit component and the second integrated circuit component via the metal trace.

25. The integrated circuit device assembly according to claim 23 or 24, wherein, The first integrated circuit component or the second integrated circuit component deletes data based on the detection that the circuit including the metal trace of the die is open.

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