Semiconductor device including encapsulated pair interconnect structure and method of manufacture

Abstract

Semiconductor devices including encapsulated pair interconnect structures and methods of manufacture are disclosed. The semiconductor device has a plurality of encapsulated pair interconnect structures. The encapsulated pair interconnect structures each have a first conductive pillar and a second conductive pillar. An encapsulant is deposited over the first and second conductive pillars. The first and second encapsulated pair interconnect structures are disposed on opposite sides of a semiconductor die. A second encapsulant is deposited over the semiconductor die, the first encapsulated pair interconnect structure, and the second encapsulated pair interconnect structure to form a panel. A built interconnect structure is formed over the panel. The panel is singulated through the first and second encapsulated pair interconnect structures between the respective first and second conductive pillars of each encapsulated pair interconnect structure.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods of manufacturing including encapsulated mating interconnect structures. Background Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and creating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Vertical interconnect structures (such as conductive pillars) are typically pre-molded and then embedded in a semiconductor package after separate molding. The pre-molded interconnect structures are formed as strips or blocks of multiple pillars to improve efficiency. However, current methods have several drawbacks. One problem is that current pick-and-place methods limit the usable length and width aspect ratios. Narrow, long packages may experience cracking issues during the pick-and-place of longer blocks of vertical interconnect structures. Therefore, there is a need for new semiconductor devices and fabrication methods that include encapsulating mating interconnect structures. Attached Figure Description

[0004] Figures 1a-1c The illustration shows a semiconductor wafer with multiple semiconductor dies separated by saw tracks; Figure 2a-2o The diagram illustrates the formation of an encapsulated mating interconnect structure; Figures 3a-3h The illustration shows a semiconductor package with an encapsulated mating interconnect structure. Figure 4a and 4b The illustration shows the back-side polishing option for encapsulating mating interconnect structures; Figures 5a-5h The diagram illustrates optional configurations for encapsulating mating interconnect structures; and Figure 6a and 6b The illustration shows an electronic device with a semiconductor package. Detailed Implementation

[0005] The invention is described with reference to the figures in one or more embodiments described below, where similar numbers in the figures denote the same or similar elements. While the invention has been described with respect to the best mode for achieving the objectives of the invention, those skilled in the art will appreciate that it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims, as well as their equivalents supported by the following disclosure and figures. Features shown in the figures are not necessarily drawn to scale. Elements assigned the same reference numerals in the figures have similar functions and descriptions to each other. The term “semiconductor die” as used herein refers to both the singular and plural forms of the term, and therefore can refer to both a single semiconductor device and multiple semiconductor devices.

[0006] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create the voltage and current relationships necessary for the circuit to function.

[0007] Back-end manufacturing refers to the process of dicing or isomerizing a finished wafer into individual semiconductor dies and packaging those dies for structural support, electrical interconnection, and environmental isolation. To isomerize a semiconductor die, the wafer is scribed along non-functional areas known as scribes, causing it to break apart. Laser cutting tools or saw blades are used for wafer isomerization. After isomerization, the individual semiconductor dies are deployed on a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed on top of the semiconductor die are then connected to contact pads within the package. Electrical connections can be made by bonding conductive layers, bumps, pillar bumps, conductive paste, or wiring. Encapsulation or other molding materials are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, making the functionality of the semiconductor device available to other system components.

[0008] Figure 1a A semiconductor wafer 100 is shown having a substrate material 102 for structural support, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials. Multiple semiconductor dies or electrical components 104 are formed on the wafer 100, separated by non-active inter-die wafer regions or saw tracks 106. The saw tracks 106 provide dicing areas to individualize the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100 to 450 millimeters (mm).

[0009] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a backside or non-active surface 108 and an active surface 110. The active surface 110 contains analog or digital circuitry, including active devices, passive devices, conductive layers, and dielectric layers, implemented as formed on or within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memories, power devices, or other signal processing circuitry. The semiconductor die 104 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0010] A conductive layer 112 is formed over the active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer 112 may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as a contact pad for electrical connection to circuitry on the active surface 110.

[0011] exist Figure 1c In this process, a saw blade or laser cutting tool 118 is used to monomerize the semiconductor wafer 100 into individual semiconductor dies 104 through the saw groove 106. The individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies (KGD) or known good cells (KGU) after monomerization.

[0012] Figure 2a-2o The illustration shows the formation of an encapsulation mating interconnect structure for including semiconductor die 104 in a semiconductor package. Figure 2a A carrier 120 is shown, having an optional interface layer, release adhesive layer, or double-sided adhesive 122 formed or deployed on the carrier 120 as a temporary adhesive bonding film, etch stop layer, heat release layer, or UV release layer. The carrier 120 contains a sacrificial substrate material for structural support, such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost, rigid materials. The term carrier may refer to carrier 120 alone or a combination of carrier 120 and adhesive layer 122. In some embodiments, carrier 120 is an 8-inch diameter silicon wafer.

[0013] A mask or photoresist layer 130 is formed on the carrier 120. The photoresist layer 130 can be formed using spin coating, spraying, lamination, film-assisted molding, or any other suitable method. Materials used for the photoresist layer 130 include photosensitive polyimide (PSPI), epoxy-based photoresist, acrylic-based photoresist, or any other suitable material. The thickness of the photoresist layer 130 can vary depending on the desired conductive pillar size and subsequent processing requirements.

[0014] By forming a complete passage Figure 2b An opening 132 in the photoresist layer is used to expose the carrier 120 or adhesive layer 122 (if used), with the photoresist layer 130 serving as a mask. The opening 132 is formed by laser ablation using a laser 134. In other embodiments, the opening 132 is formed using photolithography by applying a patterned mask to the photoresist layer 130, exposing selected areas to light, and developing the exposed or unexposed areas to form the opening. Any other suitable method can be used to form the opening 132. The size and placement of the opening 132 are determined based on the specific application and desired electrical properties. The opening 132 is formed to completely penetrate the photoresist layer 130, but it can also be formed to only partially extend into the photoresist layer.

[0015] exist Figure 2c In this process, conductive pillars 140 are formed by filling openings 132 with a conductive material. The conductive pillars 140 can be formed from any material described above for conductive layer 112 and are deposited using any of the methods mentioned above. Typically, conductive material is deposited to fill openings 132, as shown, wherein portions 142 of the conductive material physically connect each pillar 140 and cover the top surface of the photoresist layer 130. Alternatively, openings 132 can be filled only to the top of the photoresist layer 130 or shorter than its top to reduce the need for a back-side polishing step.

[0016] Figure 2d The polishing machine 144 is used for back-side polishing to remove portion 142 and to physically and electrically isolate the conductive pillars 140 from each other. The top surface of the pillars 140 is made coplanar with the photoresist layer 130.

[0017] exist Figure 2eThe photoresist layer 130 is removed, leaving conductive posts 140 on the carrier 120. The photoresist layer 130 can be removed by wet stripping, plasma ashing, thermal decomposition, or any other suitable method. Upon removal, the conductive posts 140 remain on the carrier 120 in a desired pattern. In one embodiment, the carrier 120 is completely covered by posts 140 spaced at uniform intervals across the entire berth of the carrier, with optional allowances remaining around the perimeter of the carrier. In other embodiments, additional gaps are left between some of the posts 140 as serrations, as explained below and... Figures 5a-5h As illustrated in the diagram. In some embodiments, in addition to the above... Figures 2a-2d In addition to the method illustrated in the figure, columns 140 may be deployed or formed on carrier 120 by other methods, such as by separately forming columns and then picking them up and placing them on carrier.

[0018] exist Figure 2f A molding compound or encapsulant 150 is deposited on a carrier 120 and conductive pillars 140 to form a panel or wafer 151. The encapsulant 150 is deposited using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable coaters. The encapsulant 150 can be a liquid or particulate polymer composite material, such as epoxy resin, epoxy acrylate, or other suitable polymer with or without fillers. The encapsulant 150 is non-conductive, provides structural support, and protects the semiconductor device from external components and contaminants in the environment.

[0019] Encapsulation 150 is deposited to completely cover the top surface of conductive pillar 140. In other embodiments, film-assisted molding or other techniques are used to deposit encapsulation 150, wherein conductive pillar 140 remains exposed from the encapsulation. Figure 2g In this process, a grinder 144 or other suitable mechanism is used to remove a portion of the encapsulation 150 above the conductive post 140 while the conductive post remains covered by the encapsulation. In some embodiments, after back-side grinding, the encapsulation 150 remains on top of the conductive post 140 for up to 20 micrometers (μm).

[0020] exist Figure 2hIn this process, a back-side abrasive tape 152 is mounted onto the surfaces of the encapsulation 150 and conductive posts 140 that have just been abraded. The panel 151 is flipped so that the back-side abrasive tape 152 faces downwards, and the carrier 120 is oriented upwards and available for abrasion using a grinder 144. In some embodiments, the grinder 144 is a different grinder, or has different abrasive heads or other components with different grit ratings more suitable for removing the carrier 120. The grinder 144 begins abrading the carrier 120 at the top and continues abrading until the carrier is completely removed. The adhesive layer 122 is removed by abrasion or by using separation cleaning, stripping, etching, or other removal processes. In some embodiments, the carrier 120 is removed by UV release, thermal release, or other suitable means instead of abrasion.

[0021] Figure 2i The back-side abrasive tape 152 supports the encapsulation 150, with conductive posts 140 exposed where the carrier 120 is removed. Figure 2j In this process, the second back-side abrasive belt 154 is mounted onto the encapsulant 150, opposite to the first back-side abrasive belt 152. Figure 2k Remove the back-side grinding belt 152. Figure 2l The back-side grinding belt 152 is shown mounted in a metal frame 156. The metal frame 156 provides a mechanism for holding the panel 151 during monomerization. The back-side grinding belt 156 can be mounted onto the frame 156 before or after the panel 151 is mounted onto the back-side grinding belt.

[0022] Figure 2l and 2m The diagram illustrates a serration 160 for isolating panel 151 into multiple encapsulated mating interconnect structures 162. Figure 2l A cross-sectional view is shown, while Figure 2m A plan view is shown. The encapsulated mating interconnect structure 162 is referred to as encapsulated because the interconnect structure (i.e., the conductive post 140) is encapsulated within the encapsulation 150. The term "mating" in the term "encapsulated mating interconnect structure" 162 refers to the manner in which the conductive posts 140 are distributed symmetrically within the occupancy area of ​​each cell, wherein each individual post 140 has a second individual post 140 symmetrically positioned within the same encapsulated mating interconnect structure as a mating pair.

[0023] Panel 151 can be monomerized into an encapsulated mating interconnect structure of any desired size and shape. The encapsulated mating interconnect structure 162 is formed with a length of six conductive posts 140 and a width of two posts 140. Figure 2n An alternative configuration is illustrated, in which the saw 164 defines the cuts to form a plurality of encapsulated mating interconnect structures 166, each of size 4 by 6 conductive pillars 140. Figure 2oThe option of having a cell length in the vertical direction is shown, where the saw 170 defines an area for encapsulated mating interconnect structures 172, each consisting of 2x4 conductive posts 140 in size. Any suitable length and width can be used. Each of the sawn encapsulated mating interconnect structures 162 can also be referred to as an e-bar or PCB cell. The rows and columns of posts 140 in panel 151 are sufficiently separated to allow a saw kerf to be defined between any two adjacent rows or columns to fabricate encapsulated mating interconnect structures of any desired size.

[0024] Figures 3a-3h The illustration shows the formation of a semiconductor package having a semiconductor die 104 and an encapsulated mating interconnect structure 162. Figure 3a In this embodiment, a semiconductor die 104 and an encapsulated mating interconnect structure 162 are deployed on a carrier 180. The carrier 180 can be any of the options described above for carrier 120 and may optionally include adhesive or other interface layers described above for adhesive layer 122. The semiconductor die 104 is picked up and placed onto the carrier 180, with the active surface 110 oriented toward the carrier. In the illustrated embodiment, a single semiconductor die 104 is used for each final cell being manufactured, separated by serrations 182. Although only two complete cells are shown, the carrier 180 is typically large enough to form together hundreds of cells, each separated from each other by serrations 182. Any other desired electrical components (e.g., additional semiconductor dies, semiconductor packages, chiplets, or discrete active or passive components) can be deployed on the carrier 180 along with the semiconductor die 104 to be included in the package being formed.

[0025] Encapsulated mating interconnect structures 162 are deployed on or within serrations 182 between or around semiconductor dies 104, with the exposed ends of conductive posts 140 oriented toward the carrier 180. Semiconductor dies 104 are typically square or rectangular, with the encapsulated mating interconnect structures 162 deployed adjacent to two opposing sides of each semiconductor die or adjacent to all four sides of each semiconductor die. Serrations 182 travel downwards from the center or middle of each encapsulated mating interconnect structure 162 such that, upon subsequent monomerization, each of the mated conductive posts 140 is split, with one of the mated posts being encapsulated along with each of two adjacent semiconductor dies 104. In the illustrated embodiment, one row of conductive posts 140 of each encapsulated mating interconnect structure 162 accompanies each adjacent semiconductor die 104. In other embodiments, wider encapsulated mating interconnect structures are used, with multiple rows held together on each side of the serration 182. For example, if the encapsulated mating interconnect structure 166 is used, after monolithization, two rows of conductive pillars 140 will remain on each side of the semiconductor die 104 in each package.

[0026] exist Figure 3b In this process, encapsulation 190 is deposited on semiconductor die 104 and encapsulated mating interconnect structure 162 using the methods and materials described above for encapsulation 150. Encapsulation 190 completely covers the entire footprint of carrier 180, including semiconductor die 104 and encapsulated mating interconnect structure 162, forming reconstructed wafer 192. Reconstructed wafer 192 is so named because semiconductor die 104 is repositioned from wafer 100 and reassembled into a new structure. The term "reconstructed" reflects that the original wafer 100 has been disassembled and then reorganized into a new wafer. After encapsulation and planarization, the surface of reconstructed wafer 192 resembles that of a standard semiconductor wafer. This allows for further processing, such as redistribution layer (RDL) formation, similar to conventional wafer-level processing. Reconstructed wafer 192 operates like a conventional wafer, but consists of multiple individual dies that have been encapsulated.

[0027] exist Figure 3c In this process, carrier 180 is removed as described above with respect to carrier 120, and the constructed interconnect structure 200 is formed on the reconstructed wafer 192. The constructed interconnect structure 200 is formed by constructing interleaved conductive layers 202 and insulating layers 204. The first layer formed on the reconstructed wafer 192 can be either a conductive layer 202 or an insulating layer 204. Each successive conductive layer 202 causes an insulating layer 204 to be formed between it and the previous conductive layer.

[0028] Conductive layer 202 is formed using any of the treatments and materials mentioned above for conductive layer 112. Insulating layer 204 comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide (PI), photosensitive polyimide (PSPI), benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials having similar insulating and structural properties. Insulating layer 204 can be formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering, thermal oxidation, or other suitable means. Any insulating layer, passivation layer, dielectric layer, or encapsulation mentioned above or below can be formed using any of the materials or methods described for insulating layer 204.

[0029] Openings are formed through each insulating layer 204 to expose the contacts or contact pads of the underlying conductive layer 202, or, in the case of the first insulating layer 204, to expose the ends of the conductive pillars 140 and the contact pads of the conductive layer 112. The openings can be formed by chemical etching, photolithography, mechanical drilling, laser drilling, or any other suitable means. The conductive layer 202 is formed to extend through the openings in the insulating layer 204 to be physically and electrically coupled to the underlying conductive layer, or physically and electrically coupled to the contact pads of the conductive pillars 140 and the conductive layer 112. The conductive layer 202 of the constructed interconnect structure 200 physically and electrically contacts the conductive layer 112 of the semiconductor die 104. The conductive layer 202 includes conductive traces for fan-out or fan-in from the semiconductor die 104, and optionally includes contact pads at both ends of the traces for connection to the underlying contacts and for subsequent formation of the upper conductive structure.

[0030] Additional conductive layers 202 and insulating layers 204 are interleaved on the reconstructed wafer 192 as needed to achieve desired electrical signal routing. The interconnect structure 192, referred to as the constructed interconnect structure, is formed in such a manner that insulating and conductive layers are successively constructed on the reconstructed wafer 192 until the desired signal routing is achieved. Contact pads or under-bump metallization (UBM) pads are formed as part of or on top of the top conductive layer 202. The UBM pads may optionally be formed from multiple conductive layers including a wetting layer, a barrier layer, and an adhesive layer. Additional passivation or solder mask layers may optionally be formed on the UBM pads. The UBM pads may have a flat top surface as illustrated, or may be conformally formed in openings in the insulating layer 204.

[0031] Conductive bump material is deposited on the contact pads or UBM pads of the top conductive layer 202 using evaporation, electroplating, electroless plating, droplet coating, or screen printing. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 202 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed to form balls or bumps 206 by heating the material above its melting point. The bumps 206 can also be compression bonded or thermocompressed bonded to the conductive layer 202. The bumps 206 represent a type of interconnect structure that can be formed. The interconnect structure can also use bonded wiring, conductive paste, column bumps, microbumps, or other electrical interconnects. The term "constructed interconnect structure" 200 may include the bumps 206, or may only include the underlying insulating layer 204 and conductive layer 202.

[0032] exist Figure 3dIn the process, the reconstructed wafer 192 is mounted onto the back-side polishing belt 210 and flipped. Figure 3e In this process, a polishing machine 212 or other suitable mechanism is used to reduce the thickness of the reconstructed wafer 192. The encapsulation 190 is back-side polished to remove the top portion of the encapsulation until the conductive pillars 140 are exposed at the new top surface of the reconstructed wafer 192. In embodiments where an encapsulation mating interconnect structure 162 is formed (where the encapsulation 150 remains above the top of the conductive pillars 140), back-side polishing also removes a portion of the encapsulation 150 to expose the conductive pillars. In some embodiments, a portion of the semiconductor die 104 is also removed. After back-side polishing, the back surfaces of the semiconductor die 104, conductive pillars 140, encapsulation 150, and encapsulation 190 are all coplanar with each other.

[0033] exist Figure 3f In the middle, a rear RDL layer is formed. An insulating layer 214 is first formed as described above for insulating layer 204. A conductive layer 216 is formed on top of insulating layer 214 as described above for conductive layer 216. Conductive layer 216 includes contact pads for external interconnects and optionally includes conductive traces for fan-in or fan-out electrical connections from conductive pillars 140. Solder bumps 218 are formed on the contact pads or UBMs of conductive layer 216 as described above for solder bumps 206. In some embodiments, an interconnect structure similar to the constructed interconnect structure 200 is formed on the rear side of the reconstructed wafer 192, including a plurality of insulating and conductive layers interleaved on each other.

[0034] Figure 3g The reconstructed wafer 192 is shown after processing and before monomerization. Figure 3h This illustrates a semiconductor package 220 produced by isotopizing a reconstructed wafer 192 via sawing 182. Each package mating interconnect structure 162 is halved by isotopization, producing two halves 162a and 162b. Each cell includes one half of each adjacent package mating interconnect structure 162. Figure 3h The package 220 includes half 162a of the encapsulated mating interconnect structure 162 from the right and half 162b of the encapsulated mating interconnect structure from the left. Each conductive post 140 has a paired conductive post in the same encapsulated mating interconnect structure 162 that has been separated into another semiconductor package 220.

[0035] Package 220 is a semiconductor package that uses encapsulated mating interconnect structure 162 for vertical interconnects. Using encapsulated mating interconnect structure 162 during the manufacturing process increases the aspect ratio of the pre-formed vertical interconnects that the package can use, because each package doubles the width of its vertical interconnect block by combining with adjacent semiconductor packages to form encapsulated mating interconnect structure 162.

[0036] Instead of each package 220 forming its own interconnect structure with a single row of conductive posts 140, pick-and-place occurs with double rows of conductive posts, effectively doubling the width of each interconnect unit that must be picked and placed without changing the total number of vertical conductive posts 140 in use. Doubling the width of each pick-and-place interconnect block (e.g., encapsulated mating interconnect structure 162) increases the maximum usable length while remaining within the allowable aspect ratio for the pick-and-place process in use.

[0037] For example, if a specific processing aspect ratio requirement specifies a maximum length of four conductive posts 140 (a maximum aspect ratio of 4:1) when using the width of one conductive post, then pairing the posts into interconnect structure 162 allows for a maximum length of eight conductive posts instead of four. Therefore, by doubling the conductive posts to encapsulate the paired interconnect structure 162, the package 220 forms an effective maximum 1x8 block of conductive posts 140. In this example, the maximum size of the conductive post block would have been 1x4 without doubling (i.e., without the paired conductive posts). In practice, the encapsulated block of conductive posts 140 is typically significantly larger, but the same effect of pairing to increase width to increase the maximum length holds true for any size.

[0038] Increasing the width of each individual module that must be picked up and placed increases structural rigidity, thereby increasing pick-and-place throughput performance. Package 220 leverages existing capabilities of embedded wafer-level ball grid array manufacturing technology to enable dual-sided RDLs by utilizing molded e-bars as vertical interconnects.

[0039] Figure 4a and Figure 4b An alternative embodiment of forming the encapsulated mating interconnect structure 162 is illustrated. Figure 4a From the above Figure 2g Continue. The grinder 144 continues grinding over the encapsulation 150 until sufficient encapsulation is removed to expose the top of the conductive post 140. In some embodiments, the top portion of the conductive post 140 is also removed. Figure 4b The panel 151 is shown after backside grinding. Each conductive post 140 has a top end and a bottom end that are coplanar with the surface of the encapsulation 150. The encapsulation mating interconnect structure 162 is manufactured as follows: Figure 2h-2o The process continues as shown, but results in an encapsulated mating interconnect structure in which the conductive posts 140 are exposed at both ends. During the fabrication phase of the encapsulated mating interconnect structure, any of the above or below embodiments may be ground to expose both ends of the conductive posts 140.

[0040] Figures 5a-5h The illustration shows additional, alternative, or optional configuration options for encapsulating mating interconnect structures. Figure 5aIn the final package to which each post will terminate, the conductive posts 140 are grouped into groups 230. Groups 230 can be formed by moving each conductive post 140 closer together within a group; increasing the size of the gap between posts across the serration; or a combination of both. Grouping the conductive posts 140 into groups 230 increases the margin for unitization by having serrations wider than the gap between conductive posts within a group. Each group 230 is paired with another group 230 such that each individual post 140 is paired with another individual post 140 in the adjacent group 230 to form an encapsulation mating interconnect structure 232.

[0041] Figure 5b Panel 240 with group 230 is shown after the deposition of encapsulation 150. Figure 5b Equivalent to Figure 2l The steps in this process involve panels 240 having groups 230 instead of each pillar 140 being equally separated across the entire panel footprint. Sawtooth 242 indicates where monomerization occurs at this stage to form the encapsulated mating interconnect structure 232. Sawtooth 244 remains between each pair of groups 230 for later monomerization, along with the final semiconductor package being formed. The gaps between the conductive pillars 240 can be the same width or different for sawtooth 242 compared to sawtooth 244.

[0042] Figure 5c Another embodiment is illustrated, in which panel 250 has thinner conductive pillars 251 formed closer together within group 252. With pillars 251 that are narrower and closer together than pillars 140, four rows of pillars are possible in the same group size used for two rows above. Pillars 251 are formed using the same processing and materials described above for pillars 140. Group 252 is cut in pairs at slits 253 to form an encapsulated mating interconnect structure. Slits 254 are areas reserved for later monomerization along with the final semiconductor package.

[0043] The gap 256 between the groups of columns can be as follows Figure 5d As shown, the gap 256 increases or decreases as the panel 260 increases. In one embodiment, the gap 256 is between 250 μm and 500 μm. In other embodiments, any suitable gap size is used.

[0044] Figure 5e-5h The illustration shows... Figures 3a-3h The diagram shows a plan view of the panel that forms the device. Figure 5e It is an embodiment similar to semiconductor package 220. Figure 5eEach encapsulated mating interconnect structure 262 has groups 264 of pillars 140, with each encapsulated mating interconnect structure having two rows. A sawtooth 182, which separates the illustrated cells from adjacent cells, extends directly between the groups 264 of each encapsulated mating interconnect structure 262. After monolithization, the closer groups 264 from each encapsulated mating interconnect structure 262 within the boundaries of the sawtooth 182 will remain encapsulated with the semiconductor die 104.

[0045] Figure 5f An embodiment in which the encapsulated mating interconnect structure 270 has groups 272 of pillars 140 is illustrated. Each group 272 has two rows of pillars 140. When the device is singled out via sipe 274, the two rows of pillars 140 from each encapsulated mating interconnect structure 270 within the sipe boundary will remain within the package on each side of the semiconductor die 104. The encapsulated mating interconnect structure can be fabricated with any desired number and length of rows of pillars in each group.

[0046] Figure 5g An encapsulated mating interconnect structure 276 with pillars 251 is shown. The pillars 251 are thinner than pillars 140, as seen in the plan view, and thus four rows of pillars 251 can be used for each group 278. In addition to being thinner, more rows are possible, with the group 278 having pillars 251 offset from each other in each row. Each successive row removed from the semiconductor die 104 has pillars 251 deployed between the pillars of the previous row rather than being directly aligned. After being singled out via sawtooth 279, one group 278 is retained on each side of the semiconductor die 104 in the semiconductor package.

[0047] Figure 5h An embodiment is shown in which two opposite sides of the semiconductor die 104 have longer encapsulated mating interconnect structures 280. Group 282 of posts 251 is similar to group 278, but extends a greater length as part of the longer encapsulated mating interconnect structure 280. The encapsulated mating interconnect structure 280 extends all the way to or nearly to the sawtooth 284 perpendicular to the travel of the encapsulated mating interconnect structure. Using a longer encapsulated mating interconnect structure 280 that extends to one or two vertical sawtooths allows more of the footprint area to be filled using posts 251 or 140. In one embodiment, each of the four encapsulated mating interconnect structures extends to an adjacent vertical sawtooth while extending only to the edge of the semiconductor die 104 in the opposite direction.

[0048] Figures 5a-5h Any encapsulated mating interconnect structures and group embodiments, and variations thereof, shown herein can be used in any of the other embodiments described above. Group configurations can be mixed and matched on different sides of semiconductor die 104. Some embodiments do not include encapsulated mating interconnect structures on all four sides of semiconductor die 104.

[0049] Figure 6a and Figure 6b The illustration shows the integration of the semiconductor package (e.g., semiconductor package 220) described above into a larger electronic device 300. Figure 6a The illustration shows a partial cross-section of a semiconductor package 220 mounted as part of an electronic device 300 onto a printed circuit board (PCB) or other substrate 302. Solder bumps 206 flow back to the conductive layer 304 of the PCB 302 to physically attach and electrically connect the semiconductor package 220 to the PCB. In other embodiments, thermocompression or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between the semiconductor package 220 and the PCB 302. A semiconductor die 104 is electrically coupled to the conductive layer 304 via bumps 206 and a constructed interconnect structure 200. Contact pads or UBMs of the conductive layer 216 and optional solder bumps 218 may be used to form a stacked package.

[0050] Figure 6b The illustration shows an electronic device 300 having a chip carrier substrate or PCB 302, the chip carrier substrate or PCB 302 having multiple semiconductor packages, including semiconductor package 220, disposed on the surface of the PCB 302. Depending on the application, the electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages.

[0051] Electronic device 300 may be a standalone system using semiconductor packaging to perform one or more electrical functions. Alternatively, electronic device 300 may be a sub-component of a larger system. For example, electronic device 300 may be a part of a tablet, cellular phone, digital camera, communication system, or other electronic device. Alternatively, electronic device 300 may be a graphics card, network interface card, or other signal processing card that can be plugged into a computer. Semiconductor packages may include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor dies or electrical components. Miniaturization and weight reduction are crucial for product market acceptance. The distance between semiconductor devices can be reduced to achieve higher density. PCB 302 may have more irregular shapes to facilitate fitting into more ergonomic and smaller device housings.

[0052] exist Figure 6bIn this PCB 302, a general-purpose substrate is provided for the structural support and electrical interconnection of semiconductor packages deployed on the PCB. Conductive signal traces 304 are formed on or within the surface of the PCB 302 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 304 provide electrical communication between each of the semiconductor package, mounted components, and other external system components. Trace 304 also provides power and ground connections to each of the semiconductor packages.

[0053] In some embodiments, the semiconductor device has two packaging levels. The first-level package is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second-level package involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only a first-level package, where the die is directly and mechanically deployed on the PCB.

[0054] For illustrative purposes, several types of first-level packages, including bonded wiring packages 346 and flip chips 348, are shown on PCB 302. Additionally, several types of second-level packages, including ball grid arrays (BGAs) 350, bumped chip carriers (BCCs) 352, planar grid arrays (LGAs) 356, multi-chip modules (MCMs) or SIP modules 358, quad flat no-lead packages (QFNs) 360, quad flat packages 362, and embedded wafer-level ball grid arrays (eWLBs) 364, are shown deployed on PCB 302. In one embodiment, eWLB 364 is a fan-out wafer-level package (Fo-WLP) or a fan-in wafer-level package (Fi-WLP).

[0055] Depending on system requirements, any combination of semiconductor packages configured with any combination of first-level and second-level package styles, along with other electrical components, can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less prone to failure and less expensive to manufacture, reducing costs along the supply chain.

[0056] While one or more embodiments of the invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations to these embodiments can be made without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Multiple encapsulated pair interconnect structures are formed as follows: Provide a carrier, For each encapsulated mating interconnect structure, a first conductive post and a second conductive post are deployed on the carrier, and The first encapsulation is deposited on the first and second conductive pillars; Provide semiconductor dies; The first and second encapsulated pairing interconnect structures from the plurality of encapsulated pairing interconnect structures are deployed adjacent to two opposite sides of the semiconductor die; A second encapsulation is deposited on a semiconductor die, a first encapsulation mating interconnect structure, and a second encapsulation mating interconnect structure to form a panel; An interconnected structure is formed on top of the panel; as well as A panel is monolithized between the corresponding first conductive post and second conductive post of each encapsulated pair interconnect structure via the first encapsulated pair interconnect structure and the second encapsulated pair interconnect structure.

2. The method of claim 1, further comprising: The plurality of encapsulated pairing interconnection structures are formed, each including a first row of conductive pillars and a second row of conductive pillars, wherein the first row of conductive pillars includes a first pillar and the second row of conductive pillars includes a second conductive pillar.

3. The method of claim 1, further comprising: As part of the process of forming the plurality of encapsulated mating interconnect structures, the back side of the first encapsulation is ground to expose the first conductive post and the second conductive post.

4. The method of claim 1, further comprising: Before deploying the first encapsulated mating interconnect structure and the second encapsulated mating interconnect structure adjacent to the semiconductor die, the carrier is removed by backside grinding.

5. The method of claim 1, wherein each of the first conductive pillars is configured in a corresponding first group of conductive pillars, and each of the second conductive pillars is configured in a corresponding second group of conductive pillars.

6. The method of claim 5, wherein each of the first group and the second group comprises a plurality of offset conductive column rows.

7. A method for manufacturing a semiconductor device, comprising: Provide semiconductor dies; Deploy the encapsulated mating interconnect structure adjacent to the semiconductor die; Encapsulation is deposited on a semiconductor die and encapsulated mating interconnect structure to form a panel; An interconnect structure is formed on top of the encapsulation, semiconductor die, and encapsulated mating interconnect structure; as well as The panel is monolithically assembled by encapsulating the paired interconnect structure.

8. The method of claim 7, further comprising: An encapsulated pair interconnect structure is formed, comprising a first row of conductive pillars and a second row of conductive pillars.

9. The method of claim 7, wherein the encapsulated mating interconnect structure comprises a plurality of conductive pillars, and each of the conductive pillars is exposed at both ends of the respective conductive pillar.

10. The method of claim 7, further comprising: Encapsulated pairing interconnect structures are formed on the carrier; as well as The carrier is removed by backside grinding before the encapsulated mating interconnect structure is deployed adjacent to the semiconductor die.

11. A semiconductor device, comprising: Semiconductor die; An encapsulated mating interconnect structure is deployed adjacent to the semiconductor die; Encapsulation material is deposited on the semiconductor die and the encapsulated mating interconnect structure; and The constructed interconnect structure is formed on the encapsulation, semiconductor die, and encapsulated mating interconnect structure.

12. The semiconductor device of claim 11, wherein the encapsulated mating interconnect structure includes a first row of conductive pillars and a second row of conductive pillars.

13. The semiconductor device of claim 11, further comprising: A conductive layer is formed on the semiconductor die, the encapsulated mating interconnect structure, and the encapsulation opposite the constructed interconnect structure.

14. The semiconductor device of claim 11, wherein the encapsulated mating interconnect structure comprises a first group of conductive pillars and a second group of conductive pillars.

15. The semiconductor device of claim 14, wherein both the first group and the second group comprise a plurality of offset rows of conductive pillars.

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