A multi-layer redistribution method by using a meta-level bonding

Abstract

The present application relates to a kind of multi-layer redistribution of meta-order bonding method, fill temporary filling material to the package substrate of bearing chip, with double-order slope gradient slope shallow cavity, and flatten, make the top surface of filling material and the top surface of substrate flush to form temporary continuous plane, prepare redistribution layer cavity outer section on temporary continuous plane and implement whole surface polishing;According to the etching parameter of filling material physical property matching, based on the difference of etching rate, the filling material in cavity is completely removed, while the substrate matrix and the formed metal circuit are protected;Again, prepare cavity inner section on slope and chip surface, make two segments of wiring butt joint and conduct at cavity mouth edge, only to the wiring area above chip do localized polishing and remove redundant metal layer, complete single-layer redistribution preparation, to realize three-dimensional substrate under multi-layer redistribution stable processing, reduce circuit forming defect, improve the overall reliability of package interconnection.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a method for multilayer redistribution using epoch-level bonding. Background Technology

[0002] With the continuous iteration of high-density advanced packaging technologies, embedded chip bonding and packaging solutions have gradually become the mainstream direction for improving chip integration density. The redistribution layer plays a core role in fanning out interconnects from chip pads, and the quality of redistribution directly affects the conductivity and long-term reliability of packaged devices. Conventional redistribution processes are only suitable for flat substrates without three-dimensional steps. When the substrate has a three-dimensional structure to accommodate the chip, the slope formed by the height difference will directly interfere with multiple processes such as thin film deposition, metal plating, and surface polishing. During the plating stage, current concentration is prone to occur at the transition points of the slope, resulting in excessive differences in the thickness of the metal layer. The overall uniform polishing operation will cause excessive grinding of the metal at the transition points, leading to defects such as circuit defects and open circuits. The existing processing flow lacks targeted processing logic for layering and partitioning. When removing temporary process auxiliary materials, it is difficult to distinguish the etching rates of different materials, which can easily damage the pre-formed metal lines. It is difficult to complete multi-layer redistribution stacking processing, resulting in low overall process yield and failing to meet the high-density wiring production requirements of new embedded bonding and packaging. Summary of the Invention

[0003] The main objective of this invention is to provide a method for multilayer rewiring using a first-order bonding technique. This method involves temporarily filling and leveling to create a unified processing benchmark, preparing internal and external wiring in segments, and combining this with selective etching and localized polishing. The goal is to achieve stable fabrication of multilayer rewiring under a three-dimensional substrate structure, reduce circuit defects, and improve the reliability of packaged interconnects.

[0004] To achieve the above objectives, the present invention provides a method for meta-level bonding multilayer redistribution, comprising the following steps:

[0005] A temporary filling material is filled into the shallow cavity of a packaging substrate with a double-gradient slope cavity wall and a chip supported at the bottom of the cavity. The surface of the temporary filling material is then leveled until the upper surface of the temporary filling material is flush with the top surface of the packaging substrate, forming a temporary continuous plane.

[0006] An extracavity section of the redistribution layer is prepared on the temporary continuous plane, and the extracavity section of the redistribution layer is subjected to full-surface polishing.

[0007] According to the material properties of the temporary filling material, the corresponding etching parameters are matched to completely remove the temporary filling material in the shallow cavity. The etching parameters are set to have a higher etching rate for the temporary filling material than for the packaging substrate material and the redistribution layer metal material.

[0008] An intracavity section of a redistribution layer is prepared on the surface of the double-gradient slope and the chip. The top end of the intracavity section is physically connected and electrically interconnected with the outer cavity section at the opening edge of the shallow cavity.

[0009] Localized polishing is performed on the area above the chip surface in the cavity section of the redistribution layer to remove the metal deposition layer in the area that exceeds the target thickness, thus completing the fabrication of the single-layer redistribution structure.

[0010] Further, the step of filling a shallow cavity of a packaging substrate with a cavity wall having a double-gradient slope and a chip supported at the cavity bottom with a temporary filling material, and performing a surface leveling treatment on the temporary filling material, includes:

[0011] Inject liquid temporary filling material into the shallow cavity;

[0012] Maintain a vacuum negative pressure state in the process environment until the temporary filling material completely wets the double-step variable slope and fills the shallow cavity;

[0013] The temporary filling material that has been filled is subjected to a stepped temperature pre-curing treatment;

[0014] The surface of the pre-cured temporary filler material is ground until the upper surface of the temporary filler material is flush with the top surface of the encapsulation substrate.

[0015] Further, the step of fabricating the extracavity segment of the redistribution layer on the temporary continuous plane includes:

[0016] An insulating dielectric layer is deposited on a temporary continuous planar surface and then cured.

[0017] A metal seed layer is sputtered and deposited, coated with photoresist and patterned to define the external wiring pattern;

[0018] A metal layer is deposited in the wiring pattern area using an electroplating process;

[0019] Remove the photoresist and etch away the seed layer in the area not covered by the metal layer to form the cavity segment of the redistribution layer.

[0020] Further, the step of performing a full-surface polishing process on the external cavity section of the redistribution layer includes:

[0021] The surface of the external cavity section and the temporary filling material was simultaneously ground using a coarse polishing pad.

[0022] When the remaining thickness of the metal layer in the outer cavity section reaches a preset threshold after rough polishing, the process switches to fine polishing pad to perform precision planarization grinding on the ground surface.

[0023] The thickness of the metal layer in the external cavity section is detected in real time, and polishing is terminated when the metal layer thickness reaches the preset value.

[0024] Further, the step of completely removing the temporary filling material within the shallow cavity includes:

[0025] The packaging substrate is pre-treated with surface cleaning to remove polishing residue from the surface of the external cavity section.

[0026] The etching parameters are matched according to the material properties of the temporary filler material, and the main etching process is performed.

[0027] During the etching process, passivation gas is continuously introduced to form a passivation protective film on the redistribution layer metal and the substrate surface.

[0028] An etching process was performed to remove the remaining temporary filling material in the shallow cavity area after the main etching.

[0029] Further, the step of removing the remaining temporary filler material within the shallow cavity area after the main etching includes:

[0030] The etched packaging substrate is wet-cleaned to remove etching byproducts adhering to the surface.

[0031] Plasma activation treatment was applied to the double-gradient inclined plane and the chip surface.

[0032] The activated surface is dried with nitrogen to remove the cleaning solution adhering to the surface.

[0033] Further, the step of fabricating an intracavity section of the redistribution layer on the surface of the double-gradient slope and the chip includes:

[0034] An insulating dielectric layer is deposited on a double-gradient slope and the chip surface and then cured.

[0035] The insulating dielectric layer is etched to the surface of the chip pad through photolithography and etching processes to form interconnect vias;

[0036] Metal seed layers are sputtered and deposited on the surface of the insulating dielectric layer and the inner wall of the interconnect vias;

[0037] Photoresist is applied and the cavity wiring pattern is defined. A metal layer is deposited using an electroplating process to form the cavity section of the redistribution layer.

[0038] Furthermore, the step of depositing a metal layer using an electroplating process includes:

[0039] The packaging substrate is placed in the electroplating tank, and an external auxiliary cathode structure is arranged at the station corresponding to the slope turning position of the double-step variable slope in the electroplating tank.

[0040] When the electroplating power supply is turned on, the concentrated current at the bend of the slope is diverted through the auxiliary cathode structure.

[0041] Adjust the electroplating current density and electroplating time until the metal deposition thickness at different locations on the slope is consistent.

[0042] Further, the step of performing localized polishing on the region located above the chip surface in the cavity section of the redistribution layer includes:

[0043] A photoresist protective layer is coated on the surface of the double-gradient slope and the external cavity section. After photolithography and development, only the area above the chip surface in the cavity section of the redistribution layer is exposed.

[0044] Based on the chip surface size, a small polishing head of the corresponding specification is determined to perform targeted grinding on the exposed area;

[0045] The thickness of the metal layer is monitored in real time. Polishing is stopped once the target thickness is reached, and the photoresist protective layer is removed.

[0046] Furthermore, the multilayer stacking fabrication steps of the single-layer redistribution structure include:

[0047] An interlayer dielectric layer is deposited on the single-layer redistribution structure, and the entire surface of the interlayer dielectric layer is polished.

[0048] Conductive vias are fabricated within the interlayer dielectric layer using photolithography and etching processes.

[0049] Repeat all the fabrication steps of the aforementioned single-layer rewiring structure to fabricate the next single-layer rewiring structure on the interlayer dielectric layer.

[0050] The meta-level bonding multilayer redistribution method provided by this invention has the following beneficial effects:

[0051] This invention transforms the three-dimensional morphology of a substrate into a flat processing plane using temporary filler material. It prioritizes the formation of outer wiring and full-surface polishing. The etching method is selected based on the properties of the filler material, and a protective effect is achieved based on the difference in etching rates between different materials. This removes the temporary filler material while preventing corrosion damage to the substrate and the formed metal lines. By separately forming the inner and outer wiring sections to adapt to the three-dimensional slope of the substrate, and using electroplating as an auxiliary cathode to improve the uneven metal thickness caused by current accumulation on the slope, the invention achieves thickness adjustment only for the wiring above the chip, avoiding damage to the slope metal lines during the polishing process. The entire process can be directly adapted to existing conventional equipment in semiconductor packaging production lines. Through layered and zoned processing logic, it reduces various forming defects generated during the three-dimensional wiring process from the source. The uniformity of line thickness and the bonding strength of the dielectric interface are effectively improved. The problem of mutual interference between processes is significantly alleviated, enabling stable and cyclical completion of multi-layer rewiring stacking, improving the wiring yield of embedded bonding packaging products and the long-term operational stability of devices. Attached Figure Description

[0052] Figure 1 This is a flowchart illustrating a method for multilayer rewiring with unilevel bonding in one embodiment of the present invention.

[0053] Figure 2 This is a schematic diagram of a double-level inclined shallow cavity elevation structure with first-order bonding in one embodiment of the present invention.

[0054] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0056] Reference Figure 1 The diagram below illustrates a process flow of a meta-level bonding multilayer rewiring method proposed in this invention, comprising the following steps:

[0057] S1. A temporary filling material is filled into the shallow cavity of the packaging substrate, which has a cavity wall with a double-gradient slope and a chip supported at the bottom of the cavity. The surface of the temporary filling material is then leveled until the upper surface of the temporary filling material is flush with the top surface of the packaging substrate, forming a temporary continuous plane.

[0058] S2, Prepare an extracavity section of the redistribution layer on the temporary continuous plane, and perform full-surface polishing on the extracavity section of the redistribution layer;

[0059] S3, according to the material properties of the temporary filling material, match the corresponding etching parameters to completely remove the temporary filling material in the shallow cavity. The etching parameters are set to have a higher etching rate for the temporary filling material than for the packaging substrate material and the redistribution layer metal material.

[0060] S4, an intracavity section of the redistribution layer is prepared on the surface of the double-gradient slope and the chip, and the top end of the intracavity section is physically connected and electrically interconnected with the outer cavity section at the opening edge of the shallow cavity;

[0061] S5, perform localized polishing on the area above the chip surface in the cavity section of the redistribution layer to remove the metal deposition layer in the area that exceeds the target thickness, and complete the fabrication of the single-layer redistribution structure.

[0062] As described in step S1 above, by filling the packaging substrate with a shallow cavity featuring a double-gradient slope using temporary filler material and performing surface leveling, the three-dimensional recessed structure inside the shallow cavity is temporarily transformed into a continuous planar structure flush with the top surface of the substrate. This eliminates the compatibility barrier of the shallow cavity stepped structure with subsequent planar processes. This step serves as the foundation of the entire segmented redistribution fabrication scheme. By using temporary filler material to completely cover the double-gradient slope and chip surface, it provides a uniform and consistent planar processing reference for the subsequent fabrication and polishing of the external cavity sections. This avoids the processing blind spots and edge stress concentration problems that easily occur when directly performing planar processes on a three-dimensional stepped structure, allowing conventional planar redistribution processes to be directly adapted to packaging substrates with shallow cavity structures.

[0063] As described in step S2 above, the fabrication and full-surface polishing of the external cavity section of the redistribution layer are completed based on the temporary continuous plane formed in step S1. Due to the flatness of the temporary plane, the external cavity section can be processed using mature planar redistribution fabrication technology, and the thickness uniformity and surface flatness of the external cavity section are controlled through full-surface polishing. This step completes the processing of the external cavity planar region, which is the most difficult to polish, in a temporary two-dimensional planar state, fully leveraging the processing accuracy advantages of conventional planar polishing technology, ensuring the flatness index of the wiring area on the top surface of the substrate, and avoiding process defects such as over-polishing of the cavity edge and metal collapse that are easily caused by directly polishing the entire three-dimensional structure, thus ensuring the processing yield and electrical performance of the external cavity section.

[0064] As described in step S3 above, this step is a transitional process between external and internal cavity fabrication. By matching the corresponding etching parameters according to the material properties of the temporary filler material, the temporary filler material inside the shallow cavity is completely removed while ensuring that the substrate material of the packaging substrate and the already fabricated redistribution layer external cavity section are not damaged by etching. Selective removal is achieved by controlling the difference in etching rates between different materials. While releasing the double-gradient slope ramp inside the shallow cavity and the chip surface processing area, the integrity and performance stability of the existing external cavity wiring structure are maintained, providing a clean and qualified processing substrate for the subsequent fabrication of the internal cavity section and ensuring the reliability of the connection between the two wiring structures.

[0065] As described in step S4 above, this step prepares the intracavity segment of the redistribution layer on the exposed double-slope ramp and chip surface, and achieves electrical interconnection between the intracavity segment and the outer cavity segment through physical connection at the edge of the shallow cavity opening, thereby forming a complete redistribution conductive path extending from the chip surface to the top surface of the substrate. The wiring processing of the three-dimensional ramp area is completed by segmented preparation. The wiring is prepared separately for the structural characteristics of the ramp, avoiding the problems of uneven wiring thickness and poor step coverage that are prone to occur in the step area when preparing the whole surface simultaneously. At the same time, the conductivity continuity of the redistribution structure is ensured by the precise connection of the two wiring segments, realizing the fan-out redistribution function from the chip pad to the external interface of the substrate.

[0066] As described in step S5 above, this step performs localized polishing on the area above the chip surface within the cavity section of the redistribution layer. This precisely removes the metal deposition layer exceeding the target thickness in this area, thereby completing the fabrication of a single-layer redistribution structure. By employing a limited-area polishing method, thickness control is applied only to the flat wiring area on the chip surface at the bottom of the cavity, avoiding the wiring area with a double-gradient slope. This solves the problem of excessive metal deposition thickness in the cavity bottom area and avoids damage to the sloped wiring structure caused by the polishing operation. While ensuring the flatness and thickness accuracy of the wiring on the chip surface, it provides a basic structure that meets the flatness requirements for the subsequent stacking fabrication of multi-layer redistribution structures.

[0067] In one embodiment, step S1, which involves filling a shallow cavity of a packaging substrate with a double-gradient slope cavity wall and a chip supported at the cavity bottom, with a temporary filling material, and then performing surface leveling treatment on the temporary filling material, includes:

[0068] Inject liquid temporary filling material into the shallow cavity;

[0069] Maintain a vacuum negative pressure state in the process environment until the temporary filling material completely wets the double-step variable slope and fills the shallow cavity;

[0070] The temporary filling material that has been filled is subjected to a stepped temperature pre-curing treatment;

[0071] The surface of the pre-cured temporary filler material is ground until the upper surface of the temporary filler material is flush with the top surface of the encapsulation substrate.

[0072] Reference Figure 2This is a schematic diagram of the vertical structure of a double-sloping shallow cavity with first-order bonding in one embodiment of the present invention. In a specific implementation, a liquid temporary filling material is uniformly injected along the edge of one side of the shallow cavity using a precision dispensing device. The temporary filling material is an organic polymer temporary bonding material that can be dry-etched and removed. After curing, the structure has stable strength and good compatibility with the substrate and chip surface. The dispensing rate is gradually reduced as the liquid level in the cavity rises to avoid air entrainment and the formation of internal bubbles during the dispensing process. The liquid filling material has flow characteristics that adapt to three-dimensional morphology and can initially cover the slope and transition areas of the double-sloping slope. After dispensing, the encapsulation substrate is placed in a negative pressure process cavity, and the internal air pressure is gradually reduced to a preset negative pressure value of 10Pa~100Pa and maintained for 30s~120s. The duration of negative pressure is adjusted according to the depth of the shallow cavity and the complexity of the slope. The deeper the cavity and the more transitions in the slope, the longer the maintenance time. Air trapped inside the shallow cavity and in the transition gaps of the double-slope slope is expelled by pressure differential, forcing the liquid filler material to fully saturate all slope areas and completely fill the shallow cavity space. This eliminates filling voids that easily occur at the slope transitions, ensuring the compactness of the internal structure after filling. After full filling, the encapsulation substrate undergoes a stepped temperature pre-curing treatment. The process temperature is gradually increased according to 3-4 temperature gradients, with the heating rate controlled at 5℃ / min~8℃ / min. First, the temperature is maintained in the low-temperature range for 15min~30min to allow the solvent inside the filler material to slowly and evenly evaporate. Then, the temperature is increased to the crosslinking temperature range and maintained for 20min~40min to allow the filler material to gradually polymerize and solidify. Finally, the solidification is completed and stabilized in the heat preservation range. This stepped temperature increase avoids defects caused by uneven material thickness. Differences in thermal stress can lead to problems such as cracking and peeling from the inclined interface. This ensures that the cured filler material has the structural strength and interfacial adhesion suitable for subsequent grinding processes. After pre-curing, the upper surface of the temporary filler material is ground. The top surface of the encapsulation substrate is used as the grinding termination reference. An incrementally thinning grinding method is used to remove the excess thickness of the top of the filler material. During the process, the surface flatness and thickness parameters are monitored in real time until the upper surface of the temporary filler material is completely flush with the top surface of the encapsulation substrate. The flushness is determined by optical interferometry combined with end-face morphology detection. The surface height of the passivation layer on the top surface of the substrate is used as the reference. When the height difference between the surface of the filler material and the reference surface is less than 50nm, it is considered to meet the standard, forming a temporary continuous plane with continuous morphology and flatness that meets the requirements of subsequent thin film deposition processes.

[0073] In one embodiment, step S2, the step of fabricating the extracavity segment of the redistribution layer on the temporary continuous plane, includes:

[0074] An insulating dielectric layer is deposited on a temporary continuous planar surface and then cured.

[0075] A metal seed layer is sputtered and deposited, coated with photoresist and patterned to define the external wiring pattern;

[0076] A metal layer is deposited in the wiring pattern area using an electroplating process;

[0077] Remove the photoresist and etch away the seed layer in the area not covered by the metal layer to form the cavity segment of the redistribution layer.

[0078] In practice, a spin-coating process is used to uniformly coat an insulating dielectric material onto a temporary continuous planar surface. The coating thickness is set according to the interlayer insulation requirements and process tolerances. After coating, the insulating dielectric layer undergoes a stepped thermal curing treatment. The temperature is gradually increased to the material curing temperature according to a preset heating curve and held at that temperature for a set time to allow the dielectric material to fully cross-link and cure, forming a dense and uniform insulating dielectric layer. This provides an insulating support substrate for subsequent metal wiring and ensures interfacial adhesion with the underlying temporary filling material. After curing, a titanium adhesion layer and a copper conductive layer are sequentially deposited using a magnetron sputtering process to form a continuous metal seed layer. The titanium adhesion layer enhances the interfacial adhesion between the copper layer and the insulating dielectric layer, preventing metal peeling during subsequent electroplating. The copper conductive layer provides a continuous conductive path for subsequent electroplating processes. After the seed layer is deposited, a positive photoresist is uniformly coated on the surface. After pre-baking, the surface is exposed through a photomask, and then the photoresist in the exposed areas is removed by a development process. An external wiring pattern consistent with the preset wiring scheme is defined on the top surface of the substrate. The area not covered by the photoresist is the target area for subsequent metal deposition. After patterning, the packaging substrate is placed in an electroplating tank. The metal seed layer is used as the conductive cathode and connected to an electroplating power source. Under the influence of the electric field, copper ions are continuously deposited on the exposed seed layer surface until the metal layer thickness reaches the preset process value, forming the metal conductor structure corresponding to the wiring pattern. After electroplating, a wet stripping process is used to remove the remaining photoresist mask. Then, a selective wet etching process is used to etch the substrate surface, removing only the seed layer in areas not covered by the metal layer, while retaining the seed layer structure beneath the metal conductors. During etching, the etching time and etchant concentration are controlled to avoid over-etching damage to the metal conductors and the underlying insulating dielectric layer, ultimately forming a structurally complete and precisely patterned redistribution layer's external cavity segment.

[0079] In one embodiment, the step of performing full-surface polishing on the extracavity section of the redistribution layer includes:

[0080] The surface of the external cavity section and the temporary filling material was simultaneously ground using a coarse polishing pad.

[0081] When the remaining thickness of the metal layer in the outer cavity section reaches a preset threshold after rough polishing, the process switches to fine polishing pad to perform precision planarization grinding on the ground surface.

[0082] The thickness of the metal layer in the external cavity section is detected in real time, and polishing is terminated when the metal layer thickness reaches the preset value.

[0083] In practice, the packaged substrate with the completed external cavity section is fixed on the support stage of a chemical mechanical polishing (CMP) machine. First, a hard coarse polishing pad is selected, and the corresponding polishing pressure and polishing disc speed are set to simultaneously grind the surface of the metal layer and the surface of the temporary filler material in the external cavity section. During the coarse polishing stage, a high material removal rate is used to rapidly reduce the overall thickness of the metal layer, while simultaneously grinding the surface of the temporary filler material, gradually making the top surface heights of both consistent, quickly eliminating surface undulations and thickness deviations of the metal layer after electroplating. In this embodiment, the remaining thickness of the metal layer in the external cavity section is monitored in real time. The coarse polishing pressure is set to 2 psi to 5 psi, and the polishing disc speed is set to 60 rpm to 120 rpm. When the remaining thickness of the metal layer reaches the preset coarse polishing termination threshold, the coarse polishing process is immediately stopped and switched to a soft fine polishing pad. The coarse polishing termination threshold is set to 120% to 150% of the final target thickness, leaving a 20% to 50% fine polishing allowance. Simultaneously, the polishing pressure is reduced to 0.5 psi to 2 psi, and the polishing disc speed is reduced to 30 rpm to 80 rpm, entering the precision planarization grinding stage. During the fine polishing process, an optical in-situ thickness measuring device is used to detect the thickness of the metal layer in the outer cavity section in real time. The target thickness of the metal layer in the outer cavity section is typically in the range of 1μm to 5μm, and is adjusted according to the wiring current carrying requirements. When the metal layer thickness is detected to reach the target thickness value preset by the process, the polishing process is immediately terminated and the substrate surface is cleaned to remove the abrasive and debris remaining from the polishing process, ensuring that the thickness uniformity and surface flatness of the outer cavity section meet the requirements of subsequent processes.

[0084] In one embodiment, step S3, the step of completely removing the temporary filling material within the shallow cavity, includes:

[0085] The packaging substrate is pre-treated with surface cleaning to remove polishing residue from the surface of the external cavity section.

[0086] The etching parameters are matched according to the material properties of the temporary filler material, and the main etching process is performed.

[0087] During the etching process, passivation gas is continuously introduced to form a passivation protective film on the redistribution layer metal and the substrate surface.

[0088] An etching process was performed to remove the remaining temporary filling material in the shallow cavity area after the main etching.

[0089] In practice, a wet cleaning method combined with megaphonic oscillation is used to pre-treat the surface of the packaging substrate. A low-concentration alkaline cleaning solution compatible with the redistribution layer metal and substrate substrate material is selected. With the help of low-frequency megaphonic oscillation, polishing abrasive particles, metal debris and polishing byproducts attached to the surface of the external cavity section are removed. After cleaning, deionized water is used to rinse and pre-dry the surface to avoid residual particles forming local masking during the subsequent etching process, which would lead to incomplete etching of the filling material. At the same time, it ensures the cleanliness of the external metal wiring surface and reduces the risk of abnormal corrosion during the etching process. After cleaning, the packaged substrate is placed in the dry etching chamber. Etching parameters are matched according to the material properties of the temporary filler material: if the temporary filler material is an organic polymer, an etching gas composition is matched with oxygen-based gas as the main component and fluorine-based gas as the auxiliary component. The etching selectivity between materials is controlled by adjusting the gas ratio. RF power controls the etching rate and etching anisotropy, while chamber pressure controls the uniformity of the etched surface, ensuring that the active free radicals generated during etching have a high reaction rate with the temporary filler material before the main etching process. This rapidly removes most of the temporary filler material from the shallow cavity at a high etching rate. During etching, the composition changes of the etching exhaust gas are monitored in real time using an optical endpoint detection device. When the spectral signal intensity of the characteristic etching product corresponding to the temporary filler material drops below 30% of the peak value, the main etching is considered to have reached the preset endpoint. Throughout the main etching process, a set proportion of passivating gas is continuously introduced into the etching chamber, with the passivating gas volume accounting for 5% to 15% of the total etching gas, fine-tuned according to the actual etching selectivity. After the main etching is completed, an over-etching process is performed. The over-etching time is set to 10% to 20% of the total main etching time. The etching power is appropriately reduced while the passivation gas introduction ratio is maintained. The small amount of temporary filling material remaining in the shallow cavity after the main etching is thoroughly removed. The focus is on covering the slope transition of the double-gradient slope and the corner area of ​​the cavity bottom, which are difficult to be uniformly treated during the main etching stage. This ensures that the temporary filling material in the shallow cavity is completely removed. At the same time, the protection of the passivation protective film is used to avoid the over-etching from causing additional damage to the substrate structure.

[0090] In one embodiment, the step of removing the remaining temporary filler material within the shallow cavity after the main etching includes:

[0091] The etched packaging substrate is wet-cleaned to remove etching byproducts adhering to the surface.

[0092] Plasma activation treatment was applied to the double-gradient inclined plane and the chip surface.

[0093] The activated surface is dried with nitrogen to remove the cleaning solution adhering to the surface.

[0094] In practice,

[0095] After the etching process, the packaging substrate undergoes wet cleaning. A cleaning solution compatible with the etching byproduct components is selected, and low-frequency megasonic oscillation is used to peel off and dissolve etching polymer byproducts and microparticle impurities adhering to the substrate surface, the double-slope ramp, and the chip surface. During the cleaning process, the cleaning time and solution temperature are controlled to avoid excessive corrosion of the metal wiring and chip pads. After cleaning, a multi-stage deionized water rinsing process is used to thoroughly remove residual cleaning solution components, preventing residual impurities from affecting the interface bonding quality of subsequent thin film deposition. Immediately after wet cleaning, the double-slope ramp and chip surface undergo plasma activation treatment. The packaging substrate is placed in a low-pressure plasma treatment chamber, and inert gas and a small amount of reactive gas are introduced to generate plasma. Through the physical bombardment and surface chemical modification of the plasma, trace amounts of residual organic contaminants on the surface are removed. At the same time, the surface energy and hydrophilicity of the surface are increased, improving the interface wetting effect during subsequent deposition of the insulating dielectric layer, enhancing the bonding strength between the dielectric layer and the ramp and chip surface, and preventing defects such as dielectric layer peeling and pinholes in the ramp area. Immediately after activation, high-purity heated nitrogen is used to dry the substrate surface from all directions. The cleaning solution adhering to the surface is quickly and completely evaporated by a stable nitrogen flow. During the drying process, the nitrogen temperature and purging pressure are controlled to avoid high temperature affecting the performance of the chip surface structure. At the same time, the inert atmosphere of nitrogen prevents oxidation of the metal surface, ensuring that the treated surface is clean and dry, meeting the feeding requirements of subsequent cavity segment preparation processes.

[0096] In one embodiment, step S4, the step of fabricating an intracavity segment of the redistribution layer on the surface of the double-gradient slope and the chip, includes:

[0097] An insulating dielectric layer is deposited on a double-gradient slope and the chip surface and then cured.

[0098] The insulating dielectric layer is etched to the surface of the chip pad through photolithography and etching processes to form interconnect vias;

[0099] Metal seed layers are sputtered and deposited on the surface of the insulating dielectric layer and the inner wall of the interconnect vias;

[0100] Photoresist is applied and the cavity wiring pattern is defined. A metal layer is deposited using an electroplating process to form the cavity section of the redistribution layer.

[0101] In practice, an ultrasonic atomization spraying process is used to coat insulating dielectric material on a double-slope inclined surface and the chip surface. The liquid dielectric material is atomized into micron-sized droplets and sprayed onto the three-dimensional surface at a directional angle. This effectively covers areas prone to dripping and thinning in conventional spin coating, such as slope transitions, and is adapted to the three-dimensional morphology of the double-slope inclined surface. During the coating process, the packaging substrate rotates at a constant speed of 500 rpm to 1500 rpm, and the horizontal reciprocating scanning of the spray nozzle is combined with multiple thin coatings to complete the target thickness in 3 to 5 passes. After each coating, a low-temperature pre-baking is performed to allow the surface dielectric to initially solidify before the next coating is applied. This prevents the liquid dielectric from dripping on the slope due to gravity, ensuring that the dielectric material forms a uniform thickness covering layer on slopes of different gradients, slope transitions, and the chip surface, avoiding defects such as thinning or gaps in the dielectric layer at steep slope locations. After coating, a stepped thermosetting process is performed, gradually increasing the temperature according to a preset heating curve and holding the temperature in sections to ensure full cross-linking and curing of the dielectric material, forming a dense insulating support structure. This ensures the interfacial bonding strength between the insulating dielectric layer and the slope and chip surface meets the requirements of subsequent processes. After curing, photolithography alignment and etching are performed. Using the alignment marks on the packaging substrate as a reference, the via pattern on the photomask is precisely aligned with the chip pad position. After exposure and development, a photolithography mask pattern is formed at the corresponding position of the chip pad. Then, a dry etching process is used to vertically etch the insulating dielectric layer. During the etching process, the etching endpoint is detected in real time using an optical endpoint detection system. When the characteristic spectral signal corresponding to the chip pad metal is detected, the etching is determined to have reached the endpoint and immediately terminated, forming interconnect vias with regular sidewalls and fully exposed bottom pad metal, providing a conductive path for the electrical connection between the chip pad and the redistribution layer. After the interconnect vias are fabricated, a metal seed layer is deposited using magnetron sputtering. During sputtering, the packaging substrate is rotated in a planetary motion (revolution and rotation), allowing sputtered metal particles to enter from multiple angles onto the slope of the double-gradient ramp and the inner wall of the interconnect vias, ensuring the step coverage of the seed layer on the three-dimensional surface. A titanium adhesion layer and a copper conductive layer are deposited sequentially to form a continuous conductive substrate. The titanium adhesion layer enhances the interfacial adhesion between the copper layer and the insulating dielectric layer, preventing metal peeling during subsequent electroplating. After seed layer deposition, photoresist is uniformly coated onto the three-dimensional surface using a spraying process. After baking and curing, exposure and development are performed using a photomask to define the intracavity wiring pattern covering the chip surface, the double-gradient ramp, and extending to the edge of the shallow cavity opening. The ends of the pattern precisely correspond to the ends of the extracavity sections. After patterning, a metal layer is deposited in the wiring pattern area using electroplating. After electroplating, the remaining photoresist is removed, and the seed layer in areas not covered by the metal layer is etched away, ultimately forming a continuous and precisely patterned intracavity section of the redistribution layer.

[0102] In one embodiment, the step of depositing a metal layer using an electroplating process includes:

[0103] The packaging substrate is placed in the electroplating tank, and an external auxiliary cathode structure is arranged at the station corresponding to the slope turning position of the double-step variable slope in the electroplating tank.

[0104] When the electroplating power supply is turned on, the concentrated current at the bend of the slope is diverted through the auxiliary cathode structure.

[0105] Adjust the electroplating current density and electroplating time until the metal deposition thickness at different locations on the slope is consistent.

[0106] In practice, the packaged substrate with the in-cavity wiring pattern is fixed on a special tooling fixture in the electroplating tank. A strip-shaped external metal auxiliary cathode structure parallel to the slope transition line is pre-installed at the work station corresponding to the slope transition position of the packaged substrate in the electroplating tank. The cathode material is stainless steel or titanium alloy, and the auxiliary cathode extends along the slope transition line.

[0107] In this embodiment, the horizontal distance between the auxiliary cathode and the slope transition point is set to 5mm~15mm, adjusted according to the slope difference; the greater the slope difference, the smaller the distance. The auxiliary cathode extends along the ridge line of the slope transition point and is independent of the cathode conductive structure on the substrate. After the electroplating power supply is turned on, the electric field distribution in the electroplating tank is affected by the tip effect at the slope transition point, and the current lines will concentrate at the slope transition point, resulting in a significantly higher metal deposition rate in this area than in other slope areas. After the external auxiliary cathode is connected to the cathode potential, it can attract some current lines to the auxiliary cathode structure, thereby diverting the concentrated current at the slope transition point, reducing the actual current density in this area, and weakening the impact of the tip effect on the deposition uniformity. During the electroplating process, the overall electroplating current density is adjusted based on the slope difference and slope height parameters of the double-slope inclined plane. The typical current density range is 0.5A / dm² to 2A / dm². Simultaneously, the current shunt ratio of the auxiliary cathode is adjusted, with the shunt current accounting for 10% to 25% of the total current. Thickness sampling is performed on the same batch of test pieces, with a calibration target of less than 10% difference in metal deposition thickness between the slope transition area and the flat area. The electroplating time and current parameters are fine-tuned in real-time based on the thickness measurement results at different locations on the slope. This process continues until the metal deposition thickness deviation on the upper and lower slopes, slope transition areas, and chip surface of the double-slope inclined plane is controlled within the allowable process range. This ensures the uniformity of thickness on the three-dimensional morphology surface of the cavity section, preventing stress concentration at slope transition areas due to excessive metal layer thickness or decreased conductivity due to insufficient thickness.

[0108] In one embodiment, step S5, which involves performing localized polishing on the region located above the chip surface within the cavity segment of the redistribution layer, includes:

[0109] A photoresist protective layer is coated on the surface of the double-gradient slope and the external cavity section. After photolithography and development, only the area above the chip surface in the cavity section of the redistribution layer is exposed.

[0110] Based on the chip surface size, a small polishing head of the corresponding specification is determined to perform targeted grinding on the exposed area;

[0111] The thickness of the metal layer is monitored in real time. Polishing is stopped once the target thickness is reached, and the photoresist protective layer is removed.

[0112] In practice, a spray coating process is used to uniformly coat the surface of the double-slope inclined surface and the external cavity section with a photoresist protective layer. By controlling the spraying angle and the revolution speed of the packaging substrate, the photoresist forms a uniform and complete coverage on the slope, slope transition and external cavity section surfaces at different slopes, avoiding thinning of the photoresist layer or gaps in coverage at three-dimensional morphological positions, and ensuring that all non-polished areas have complete polishing protection capabilities. After the photoresist coating is completed, it is pre-baked and cured. Photolithography alignment and exposure are completed with the alignment marks of the packaging substrate as a reference. Then, the photoresist in the corresponding area above the chip surface is removed by the development process, exposing only the area above the chip surface in the cavity section of the redistribution layer. The photoresist in the remaining areas serves as a rigid protective layer to isolate the subsequent polishing operation from the damage to the inclined surface wiring and external cavity wiring. Subsequently, based on the effective processing dimensions of the chip surface, a small polishing head with a diameter 0.2mm to 0.5mm smaller than the side length of the effective processing area on the chip surface is selected. This ensures that the effective range of the polishing head is completely limited to the exposed wiring area on the chip surface, preventing the polishing head from contacting the surrounding photoresist or sloped structures during the polishing process and ensuring precise definition of the polishing area. The polishing process adopts a low-pressure contact grinding mode, with the contact pressure set at 0.2psi to 1psi and the polishing head speed set at 20rpm to 60rpm. The small polishing head performs point-to-point reciprocating grinding on the exposed area, precisely reducing the metal layer thickness in this area with a controllable material removal rate. At the same time, the surrounding photoresist acts as a barrier to prevent the polishing abrasive from penetrating into the sloped area and causing unexpected grinding damage. Throughout the polishing process, an in-situ optical thickness measurement device is used to monitor the thickness of the metal layer on the chip surface in real time. When the metal layer thickness reaches the preset target thickness value, the polishing operation is immediately terminated. After polishing, a wet photoresist removal process is used to remove all photoresist protective layers, and deionized water is used to rinse away the polishing abrasive and debris attached to the surface, resulting in a single-layer redistribution structure with a surface flatness that meets the requirements of subsequent multi-layer stacking.

[0113] In one embodiment, the multilayer stacking fabrication step of a single-layer redistribution structure includes:

[0114] An interlayer dielectric layer is deposited on the single-layer redistribution structure, and the entire surface of the interlayer dielectric layer is polished.

[0115] Conductive vias are fabricated within the interlayer dielectric layer using photolithography and etching processes.

[0116] Repeat all the fabrication steps of the aforementioned single-layer rewiring structure to fabricate the next single-layer rewiring structure on the interlayer dielectric layer.

[0117] In practice, after the single-layer redistribution structure is prepared, an interlayer dielectric layer is deposited on the surface of the single-layer redistribution structure using a spin-coating process. The dielectric material is then fully cross-linked and cured through a stepped thermosetting process to form an insulating isolation structure between two adjacent redistribution layers, ensuring the interlayer electrical insulation performance. The interlayer dielectric layer is then polished in a step-by-step process combining rough polishing and fine polishing to control the surface flatness and thickness uniformity of the interlayer dielectric layer to a preset standard. This provides a flat and consistent processing substrate for the preparation of the next redistribution structure, avoiding surface undulations from affecting the processing accuracy of subsequent thin film deposition and patterning. After the interlayer dielectric layer is planarized, photolithographic alignment is performed using the alignment marks on the packaging substrate as a reference. The via pattern is aligned one-to-one with the interconnect node positions of the lower redistribution layer. After exposure and development, an etching mask pattern is formed. Then, a dry etching process is used to vertically etch the interlayer dielectric layer. The etching stops immediately after reaching the surface of the metal layer of the lower redistribution layer, forming conductive vias with regular sidewalls and fully exposed bottom metal. The diameter of the conductive via is set according to the thickness of the interlayer dielectric layer, and the via depth-to-width ratio is controlled within 1:1 to ensure the filling capacity and conductivity reliability of subsequent metal deposition, providing a vertical electrical connection path for the upper and lower redistribution layers. After the conductive vias are fabricated, the entire fabrication process of the single-layer redistribution structure described above is repeated. The plane is fabricated based on the interlayer dielectric layer, and the complete process flow of temporary filling leveling, external cavity section fabrication and full-surface polishing, temporary filling material removal, internal cavity section fabrication, and localized polishing is completed in sequence. The next single-layer redistribution structure is fabricated on the interlayer dielectric layer. This process is repeated to fabricate redistribution structures with the corresponding number of layers according to the wiring density and interconnection requirements. Each layer is vertically interconnected layer by layer through conductive vias, and finally a complete multi-layer redistribution structure is formed.

[0118] In summary, this invention fills a shallow cavity of a packaging substrate with a cavity wall having a double-gradient slope and a chip supported at the bottom with a temporary filler material, and performs surface leveling treatment on the temporary filler material until the upper surface of the temporary filler material is flush with the top surface of the packaging substrate, forming a temporary continuous plane; an external section of a redistribution layer is prepared on the temporary continuous plane, and the external section of the redistribution layer is subjected to full-surface polishing treatment; the temporary filler material in the shallow cavity is completely removed by matching the corresponding etching parameters according to the material properties of the temporary filler material, wherein the etching parameters are set to be applied to the temporary filler material. The etching rate of the material is higher than that of the substrate material of the packaging substrate and the metal material of the redistribution layer; an intracavity section of the redistribution layer is prepared on the surface of the double-gradient slope and the chip, and the top of the intracavity section is physically connected and electrically interconnected with the outer cavity section at the opening edge of the shallow cavity; a local polishing process is performed on the area above the chip surface in the intracavity section of the redistribution layer to remove the metal deposition layer exceeding the target thickness in the area, thereby completing the preparation of a single-layer redistribution structure, so as to achieve the purpose of stable preparation of multi-layer redistribution under a three-dimensional substrate structure, reducing circuit defects and improving the reliability of packaging interconnection.

[0119] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for multilayer rewiring using meta-level bonding, characterized in that, Includes the following steps: A temporary filling material is filled into the shallow cavity of a packaging substrate with a double-gradient slope cavity wall and a chip supported at the bottom of the cavity. The surface of the temporary filling material is then leveled until the upper surface of the temporary filling material is flush with the top surface of the packaging substrate, forming a temporary continuous plane. An extracavity section of the redistribution layer is prepared on the temporary continuous plane, and the extracavity section of the redistribution layer is subjected to full-surface polishing. According to the material properties of the temporary filling material, the corresponding etching parameters are matched to completely remove the temporary filling material in the shallow cavity. The etching parameters are set to have a higher etching rate for the temporary filling material than for the packaging substrate material and the redistribution layer metal material. An intracavity section of a redistribution layer is prepared on the surface of the double-gradient slope and the chip. The top end of the intracavity section is physically connected and electrically interconnected with the outer cavity section at the opening edge of the shallow cavity. Localized polishing is performed on the area above the chip surface in the cavity section of the redistribution layer to remove the metal deposition layer in the area that exceeds the target thickness, thus completing the fabrication of the single-layer redistribution structure.

2. The method for multilayer redistribution bonding according to claim 1, characterized in that, The step of filling a shallow cavity with temporary filling material into a packaging substrate whose cavity wall is a double-gradient slope and whose cavity bottom supports a chip, and then performing surface leveling treatment on the temporary filling material, includes: Inject liquid temporary filling material into the shallow cavity; Maintain a vacuum negative pressure state in the process environment until the temporary filling material completely wets the double-step variable slope and fills the shallow cavity; The temporary filling material that has been filled is subjected to a stepped temperature pre-curing treatment; The surface of the pre-cured temporary filler material is ground until the upper surface of the temporary filler material is flush with the top surface of the encapsulation substrate.

3. The method for multilayer redistribution bonding according to claim 1, characterized in that, The step of preparing the extracavity segment of the redistribution layer on the temporary continuous plane includes: An insulating dielectric layer is deposited on a temporary continuous planar surface and then cured. A metal seed layer is sputtered and deposited, coated with photoresist and patterned to define the external wiring pattern; A metal layer is deposited in the wiring pattern area using an electroplating process; Remove the photoresist and etch away the seed layer in the area not covered by the metal layer to form the cavity segment of the redistribution layer.

4. The method for multilayer redistribution bonding according to claim 1, characterized in that, The step of performing full-surface polishing on the external cavity section of the redistribution layer includes: The surface of the external cavity section and the temporary filling material was simultaneously ground using a coarse polishing pad. When the remaining thickness of the metal layer in the outer cavity section reaches a preset threshold after rough polishing, the process switches to fine polishing pad to perform precision planarization grinding on the ground surface. The thickness of the metal layer in the external cavity section is detected in real time, and polishing is terminated when the metal layer thickness reaches the preset value.

5. The method for multilayer rewiring with meta-level bonding according to claim 1, characterized in that, The step of completely removing the temporary filling material in the shallow cavity includes: The packaging substrate is pre-treated with surface cleaning to remove polishing residue from the surface of the external cavity section. The etching parameters are matched according to the material properties of the temporary filler material, and the main etching process is performed. During the etching process, passivation gas is continuously introduced to form a passivation protective film on the redistribution layer metal and the substrate surface. An etching process was performed to remove the remaining temporary filling material in the shallow cavity area after the main etching.

6. The method for multilayer redistribution bonding according to claim 5, characterized in that, The step of removing the remaining temporary filler material within the shallow cavity area after the main etching includes: The etched packaging substrate is wet-cleaned to remove etching byproducts adhering to the surface. Plasma activation treatment was applied to the double-gradient inclined plane and the chip surface. The activated surface is dried with nitrogen to remove the cleaning solution adhering to the surface.

7. The method for multilayer redistribution bonding according to claim 1, characterized in that, The step of fabricating the intracavity section of the redistribution layer on the double-gradient slope and the surface of the chip includes: An insulating dielectric layer is deposited on a double-gradient slope and the chip surface and then cured. The insulating dielectric layer is etched to the surface of the chip pad through photolithography and etching processes to form interconnect vias; Metal seed layers are sputtered and deposited on the surface of the insulating dielectric layer and the inner wall of the interconnect vias; Photoresist is applied and the cavity wiring pattern is defined. A metal layer is deposited using an electroplating process to form the cavity section of the redistribution layer.

8. The method for multilayer redistribution bonding according to claim 7, characterized in that, The step of depositing a metal layer using an electroplating process includes: The packaging substrate is placed in the electroplating tank, and an external auxiliary cathode structure is arranged at the station corresponding to the slope turning position of the double-step variable slope in the electroplating tank. When the electroplating power supply is turned on, the concentrated current at the bend of the slope is diverted through the auxiliary cathode structure. Adjust the electroplating current density and electroplating time until the metal deposition thickness at different locations on the slope is consistent.

9. The method for multilayer redistribution bonding according to claim 1, characterized in that, The step of performing localized polishing on the region located above the chip surface in the cavity section of the redistribution layer includes: A photoresist protective layer is coated on the surface of the double-gradient slope and the external cavity section. After photolithography and development, only the area above the chip surface in the cavity section of the redistribution layer is exposed. Based on the chip surface size, a small polishing head of the corresponding specification is determined to perform targeted grinding on the exposed area; The thickness of the metal layer is monitored in real time. Polishing is stopped once the target thickness is reached, and the photoresist protective layer is removed.

10. The method for multilayer rewiring with meta-level bonding according to claim 1, characterized in that, The fabrication steps for a multilayer stacked single-layer redistribution structure include: An interlayer dielectric layer is deposited on the single-layer redistribution structure, and the entire surface of the interlayer dielectric layer is polished. Conductive vias are fabricated within the interlayer dielectric layer using photolithography and etching processes. Repeat all the fabrication steps of the aforementioned single-layer rewiring structure to fabricate the next single-layer rewiring structure on the interlayer dielectric layer.

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